JP7112200B2 - Transmitter, receiver and chip - Google Patents

Description

The present invention relates to a transmitting device, a receiving device, and a chip that perform OFDM (Orthogonal Frequency Division Multiplexing) transmission.

ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) has been standardized as a transmission system for current digital terrestrial broadcasting in Japan (see, for example, Non-Patent Document 1). Moreover, in recent years, ultra-high-definition video called 8K Super Hi-Vision has been put to practical use, and studies are underway on next-generation terrestrial digital broadcasting transmission systems that support this.

FIG. 17 shows the main transmission parameters of ISDB-T and provisional specifications for next-generation terrestrial digital broadcasting. In the next-generation terrestrial digital broadcasting, for example, the signal bandwidth is increased from 5.57 MHz to 5.83 MHz, and the number of FFT points is expanded two to four times, thereby increasing the transmission capacity. Also, by increasing the number of segments from 13 to 35, the bit rate of each layer can be finely adjusted, and flexibility can be improved. Also, in order to improve error correction capability, an LDPC (Low Density Parity Check) code is adopted as an error correction code.

On the other hand, overseas, DVB-T (Digital Video Broadcasting-Terrestrial) and DVB-C (Digital Video Broadcasting-Cable) have been standardized as digital broadcasting transmission methods that employ LDPC codes (for example, non-patented Reference 2). LDPC codes adopted in these standards are known to be generated using a parity check matrix in which 1's are periodically arranged in the row direction (see, for example, Non-Patent Document 3). In addition, Non-Patent Document 4 describes a table indicating the element position of 1 in the parity check matrix for each coding rate of the LDPC code.

"Transmission system for digital terrestrial television broadcasting", ARIB STD-B31, Association of Radio Industries and Businesses ””DVB-C2”, [online], [searched December 16, 2016], Internet <URL: https://www.dvb.org/standards/dvb-c2> Takashi Yokokawa et al., ``Parity and column twist bit interleaver for DVB-T2 LDPC codes'', IEEE 5th International Symposium on Trurbo Codes and Related Topics, 2008, pp.123-127 "Transmission system for advanced wideband satellite digital broadcasting", ARIB STD-B-44, Association of Radio Industries and Businesses

The LDPC code can interleave data bit by bit and disperse burst errors by using bit interleaving processing together, and is expected to improve error correction capability. However, according to Non-Patent Literature 1, there is no definition of a configuration that uses an LDPC code in combination with bit interleave processing.

Also, with the DVB standard LDPC code, a table of different numbers of bits is prepared for each carrier modulation method, and bit interleave processing is performed using this table. The maximum number of bits in this table is 20 bits for DVB-C2, for example, and a common table was used for each carrier modulation method except when the coding rate was 2/3. Therefore, it was difficult to completely eliminate the regularity even with bit interleave processing.

SUMMARY OF THE INVENTION An object of the present invention, which has been made in view of such circumstances, is to provide a transmitting device, a receiving device, and a chip that combine bit interleaving processing with an LDPC code and are capable of improving the error correction capability more than conventionally. .

In order to solve the above problems, a transmission apparatus according to the present invention is a transmission apparatus that transmits an OFDM signal, and includes an LDPC encoding unit that performs LDPC encoding on transmission data to generate an LDPC code, and , a bit interleaving unit that performs interleave processing on a bit-by-bit basis using an input/output conversion table for each block of LDPC code length to generate interleaved data; a mapping unit that generates symbols; an OFDM frame construction unit that generates OFDM symbols by arranging the carrier symbols at predetermined positions; and a transmission processing unit that generates OFDM signals based on the OFDM symbols, The output conversion table is different for each coding rate of the LDPC code and the carrier modulation method, and has the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. do.

Further, in the transmitting device according to the present invention, the bit interleaving unit includes a parity interleaving unit that interleaves the parity bits of the LDPC code at a predetermined bit period, and the LDPC code processed by the parity interleaving unit for each block. a block interleaving unit that sequentially writes data into a memory from the head of each column in the column direction and then reads out the data in the row direction; and an interleaved portion.

Also, in the transmitting apparatus according to the present invention, the number of bits of the input/output conversion table is a common multiple of the modulation multilevel numbers of all carrier modulation schemes that can be used in the transmitting apparatus.

In order to solve the above problems, a receiver according to the present invention is a receiver for receiving an OFDM signal obtained by carrier-modulating and OFDM-modulating an LDPC code, estimating a propagation path characteristic and generating a carrier symbol of the OFDM signal. a noise variance calculation unit that calculates a noise variance from the carrier symbol; an LLR calculation unit that calculates a likelihood ratio using the carrier symbol and the noise variance; a bit deinterleaving unit that performs deinterleaving processing on a bit-by-bit basis using an input/output conversion table to generate deinterleaved data; and an LDPC decoding unit that performs LDPC decoding using the deinterleaved data. The conversion table differs depending on the coding rate of the LDPC code and the carrier modulation method, and has the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. .

Further, in the receiving apparatus according to the present invention, the bit deinterleaving unit performs deinterleaving processing on the likelihood ratio according to the input/output conversion table and an intra-carrier-symbol deinterleaving unit. A block deinterleaving unit that sequentially writes the likelihood ratios obtained in each block from the beginning of each row in the row direction into a memory and then reads them in the column direction, and among the likelihood ratios processed by the block deinterleaving unit, and a parity deinterleaving unit that deinterleaves the likelihood ratio corresponding to the parity bit of the code at a predetermined bit period.

Also, in the receiving apparatus according to the present invention, the same number of bits is a common multiple of modulation multilevel numbers of all carrier modulation schemes that can be used by the transmitting apparatus that transmits the OFDM signal.

In order to solve the above problems, a chip according to the present invention includes an LDPC encoder that performs LDPC encoding on transmission data to generate an LDPC code, and an input/output conversion for each block of the LDPC code length for the LDPC code. A bit interleaving unit that performs interleave processing on a bit-by-bit basis using a table to generate interleaved data, a mapping unit that maps the interleaved data to an IQ plane and generates carrier symbols that have undergone carrier modulation, and the carrier symbols. An OFDM frame structuring unit that generates OFDM symbols placed at a predetermined position, and a transmission processing unit that generates an OFDM signal based on the OFDM symbols, wherein the input/output conversion table includes the coding rate of the LDPC code. and the number of bits is different for each carrier modulation method and is the same regardless of the coding rate of the LDPC code and the carrier modulation method.

Further, in order to solve the above problems, a chip according to the present invention is a chip mounted in a receiver for receiving an OFDM signal obtained by carrier-modulating and OFDM-modulating an LDPC code, estimating a propagation path characteristic and performing the OFDM an equalization unit that generates carrier symbols of a signal; a noise variance calculation unit that calculates noise variance from the carrier symbols; an LLR calculation unit that calculates a likelihood ratio using the carrier symbols and the noise variance; A bit deinterleaving unit that performs deinterleaving processing on a bit-by-bit basis using an input/output conversion table for the degree ratio to generate deinterleaved data, and an LDPC decoding unit that performs LDPC decoding using the deinterleaved data; and the input/output conversion table differs depending on the coding rate of the LDPC code and the carrier modulation method, and is the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. characterized by being

According to the present invention, bit interleave processing can be combined with an LDPC code to improve the error correction capability more than conventionally.

1 is a diagram showing a configuration example of an OFDM transmission/reception system according to an embodiment of the present invention; FIG. FIG. 4 is a diagram showing a configuration example of an XMI packet; It is a figure which shows the structural example of the transmission apparatus which concerns on one Embodiment of this invention. It is a figure which shows the structural example of the input interface part of the transmission device which concerns on one Embodiment of this invention. FIG. 4 is a diagram showing a configuration example of a modulation section of a transmission device according to an embodiment of the present invention; It is a figure which shows the structural example of an LDPC (Low Density Parity Check) block. FIG. 3 is a diagram showing a configuration example of a bit interleaving section of the transmission device according to one embodiment of the present invention; FIG. 4 is a diagram showing an example of processing of a block interleaving unit of the transmission device according to one embodiment of the present invention; It is a figure which shows the structural example of the receiving apparatus which concerns on one Embodiment of this invention. FIG. 3 is a diagram showing a configuration example of a demodulation section of a receiving device according to an embodiment of the present invention; FIG. 4 is a diagram showing a configuration example of a bit deinterleaving section of the receiving device according to one embodiment of the present invention; It is a figure which shows the structural example of the output interface part of the receiving apparatus which concerns on one Embodiment of this invention. 4 is a flow chart showing an operation example of a transmission device according to an embodiment of the present invention; 4 is a flow chart showing an operation example of a receiving device according to an embodiment of the present invention; FIG. 10 is a first diagram showing the effect of the bit interleave processing of the present invention; FIG. 10 is a second diagram showing the effect of the bit interleave processing of the present invention; FIG. 2 is a diagram showing a comparison of main transmission parameters between ISDB-T and provisional specifications for next-generation terrestrial digital broadcasting;

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated, referring drawings.

FIG. 1 is a diagram showing a configuration example of an OFDM transmission/reception system 1 according to one embodiment of the present invention. Here, a next-generation digital terrestrial broadcasting system is shown. Hierarchical transmission is performed by allocating different segments in the frequency band of one channel in order to provide services with different image quality and noise immunity in the same channel. In hierarchical transmission, layers are called A layer, B layer, . . . in descending order of error correction. For example, A-layer transmission can provide broadcasting for mobile receiving terminals, and B-layer transmission can provide high-definition broadcasting for fixed receiving terminals. In the following description, it is assumed that two layers of data, A layer data and B layer data, are transmitted, but the number of layers is not limited to two layers.

Furthermore, in the next-generation digital terrestrial broadcasting, transmission of highly urgent data with a lower delay than that in the A and B layers is under consideration. In this specification, the channel transmitted with this low delay is called "Lch". Specifically, in the remultiplexing device 20, the processing of layers A and B constitutes a frame, so a delay of one frame or more is required. On the other hand, the Lch processing is operated in symbol cycles, and the packets input to the remultiplexer 20 are immediately assigned to the symbols to be transmitted, and transmitted quickly, thereby realizing low-delay transmission.

The OFDM transmission/reception system 1 shown in FIG. 1 includes a multiplexing device 10 (10a to 10c), a remultiplexing device 20, and a transmission device 30 on the transmission side. Moreover, the receiving side includes a receiving device 40 and a demultiplexing device 50 .

The multiplexing device 10a is provided corresponding to the A layer, multiplexes the input video/audio signal for the A layer and the subtitle signal, and converts it into a packet (for example, MMT (MPEG Media Transport)) in a predetermined format (for example, MMT (MPEG Media Transport)). MMTP (MMT Protocol) packet) and output as a package for layer A. A transmission line between the multiplexing device 10 and the re-multiplexing device 20 is an IP (Internet Protocol) transmission line, and the multiplexing device 10 stores MMTP packets in IP packets and outputs them to the re-multiplexing device 20. . Therefore, hereinafter, packets output from the multiplexing device 10 to the remultiplexing device 20 may be referred to as MMTP/IP packets.

The multiplexing device 10b and the multiplexing device 10c are provided corresponding to the B layer and the Lch, respectively, and receive video/audio signals and caption signals for the corresponding B layer or Lch. Similar to the multiplexing device 10a, the multiplexing devices 10b and 10c respectively multiplex the input video/audio signals and caption signals, packetize them into MMTP packets, and re-multiplex them as B-layer packages and Lch packages. Output to device 20 .

The re-multiplexing device 20 receives a plurality of layer package data (a layer A package and a B layer package) multiplexed by the multiplexing devices 10a and 10b, and a low-delay package multiplexed by the multiplexing device 10c. The data (package for Lch) is remultiplexed and output to the transmission device 30 . More specifically, the remultiplexer 20 generates XMI packets of a format different from the MMTP packets from the MMTP packets input from the multiplexers 10a, 10b, and 10c, remultiplexes them into one system, and transmits them. Output to device 30 . In the current ISDB-T, packets output from the remultiplexer to the transmitter are TS (Transport Stream) packets.

FIG. 2 is a diagram showing a configuration example of an XMI packet output by the remultiplexer 20. As shown in FIG. An XMI packet has a header area and a data unit area. As shown in FIG. 2, the header area of the XMI packet has an IPv4 header, a UDP header, an MMTP packet header (MMTP header), and an XMI header. A number attached to each field (region) indicates an example of the number of bits in each field.

Synchronous control information or a data unit is stored in the data unit area of the XMI packet. If the number of bits is less than the predetermined number, stuff bits are added. The Lch data is quickly (with low delay) assigned to the data unit area in symbol cycles by the remultiplexer 20 .

The IPv4 header has the same configuration as the IPv4 header defined in Part 3 of ARIB STD-B32. The UDP header has the same configuration as the UDP header defined in Part 3 of ARIB STD-B32. The MMTP header has the same structure as the MMTP header defined in ARIB STD-B60.

The payload area (MMTP payload) of the MMTP packet stores the XMI header and below. Also, the MMTP header stores information indicating the data type of data to be stored in the MMTP payload, information for identifying the type of data to be stored in the MMTP payload, and the like.

As shown in FIG. 2, the XMI header includes a logical frame number, data unit type, sequence number, CRC_32, and data unit length.

The logical frame number indicates the frame number to which the data unit stored in the XMI packet belongs.

The data unit type indicates whether or not synchronization control information is stored in the data unit area of the XMI packet, whether it is a data unit of layer A or layer B, and whether it is a stuff bit. .

The sequence number indicates the order of the XMI packets within the OFDM frame.

CRC_32 is written with a CRC (Cyclic Redundancy Check) according to ITU-T Recommendation H222.0.

The data unit length indicates the size of the data unit in the XMI packet.

The transmitter 30 constructs an OFDM frame using the XMI packets input from the remultiplexer 20 and transmits an OFDM signal. Details will be described later.

The receiver 40 receives the OFDM signal transmitted by the transmitter 30 , decodes the received OFDM signal into MMTP/IP packets, and outputs the MMTP/IP packets to the demultiplexer 50 . Details will be described later.

The demultiplexing device 50 demultiplexes the MMTP/IP packet received from the receiving device 40 into a video/audio signal and a closed caption signal and outputs them.

[Transmitter]
Next, the configuration of the transmission device according to one embodiment of the present invention will be described in detail. FIG. 3 is a block diagram showing a configuration example of a transmission device according to the first embodiment of the present invention. A transmission device 30 shown in FIG. 3 includes an input interface section 31 and a modulation section 32 .

The input interface unit 31 receives the XMI packet from the remultiplexer 20, and concatenates the layer data and the Lch data (low-delay data) to form a layer A frame, a layer B frame, and an Lch frame (low-delay frame). ) and outputs it to the modulation unit 32 .

The modulation unit 32 constructs an OFDM frame from the frame input from the input interface unit 31 based on transmission parameters included in the synchronization control information, and transmits an OFDM signal from the transmission antenna 33 .

FIG. 4 is a diagram showing a configuration example of the input interface unit 31. As shown in FIG. The input interface unit 31 shown in FIG. 4 includes an XMI packet receiving unit 311, an A layer frame generation unit 312a, a B layer frame generation unit 312b, an Lch frame generation unit 312c, and a control information/TMCC information generation unit 313. Prepare.

The XMI packet receiving unit 311 receives the XMI packets from the remultiplexer 20, outputs the A layer XMI packets to the A layer frame generation unit 312a, and outputs the B layer XMI packets to the B layer frame generation unit 312b. . The XMI packet receiver 311 also outputs the A-layer XMI packet and the B-layer XMI packet to the Lch frame generator 312c. Furthermore, XMI packet receiving section 311 outputs a synchronization control XMI packet containing synchronization control information to control information/TMCC information generating section 313 .

In the XMI header of the XMI packet, as described above, information stored in the data unit area of the XMI packet indicates whether or not synchronization control information is stored, whether or not it is a data unit of layer A or layer B, and a stuff bit. A data unit type indicating whether or not the The XMI packet receiving unit 311 can identify the type of each XMI packet by referring to the value of the data unit type and output it to an appropriate output destination.

The A-layer frame generator 312 a connects the data units included in the A-layer XMI packet input from the XMI packet receiver 311 , generates a layer-A frame, and outputs the frame to the modulator 32 .

The B-layer frame generator 312 b connects the data units included in the B-layer XMI packet input from the XMI packet receiver 311 , generates a B-layer frame, and outputs the frame to the modulator 32 .

The Lch frame generation unit 312 c connects symbols included in the XMI packet input from the XMI packet reception unit 311 to generate an Lch frame and outputs the Lch frame to the modulation unit 32 .

The control information/TMCC information generation unit 313 generates control information indicating various kinds of information for forming an OFDM frame and transmission parameters from the synchronization control information included in the synchronization control XMI packet input from the XMI packet receiving unit 311. TMCC information is generated and output to the modulation section 32 .

FIG. 5 is a diagram showing a configuration example of the modulation section 32. As shown in FIG. The modulation unit 32 shown in FIG. 5 includes FEC block transform units 321a and 321b, energy spreading units 322a and 322b, BCH encoding units 323a and 323b, LDPC encoding units 324a and 324b, and bit interleaving units 325a and 325b. , mapping units 326a and 326b, a hierarchical synthesis unit 327, a band division unit 328, a time interleaving unit 329, a frequency interleaving unit 330, a band synthesis unit 331, an error correction coding unit 332, and a DBPSK modulation unit. 333 , an OFDM frame configuration unit 334 , and a transmission processing unit 335 .

The FEC block conversion unit 321a converts each bit string of the layer A frame into an FEC block, and outputs the FEC block to the energy diffusion unit 322a. As for the size of the FEC block, three sizes are set according to the code length (Short, Middle, Long) of LDPC encoding, which will be described later.

The energy spreading unit 322a performs energy spreading processing using a pseudorandom code sequence on the FEC blocks input from the FEC block transforming unit 321a in order to prevent the same code from occurring continuously for a long period of time, Output to the BCH encoding unit 323a.

The BCH encoding unit 323a performs BCH encoding on the FEC block input from the energy spreading unit 322a using a generator polynomial to generate a BCH code (BCH block) for each block, and an LDPC encoding unit 324a. output to The generator polynomial is generated by a 14th-order primitive polynomial when the LDPC code is in Short mode, and is generated by a 16th-order primitive polynomial when the LDPC code is in Middle mode or Long mode. The number of correction bits shall be 12 bits.

The LDPC encoding unit 324a performs LDPC encoding on the BCH block (transmission data) input from the BCH encoding unit 323a to generate an LDPC code (LDPC block) having an LDPC code length, and performs bit interleaving. Output to the unit 325a. For example, there are three LDPC code lengths: 11220 bits in Short mode, 44880 bits in Middle mode, and 269280 bits in Long mode. For example, there are 11 types of coding rates. LDPC encoding section 324a generates an LDPC code using a parity check matrix that does not have a structure in which 1's are regularly arranged, in order to improve processing performance in bit interleaving section 325, which will be described later.

A codeword C of the LDPC code is determined by a parity check matrix H consisting of 0 and 1 elements. If the parity check matrix H uses the LDGM structure, CH ^T =0 holds. where T represents the transpose of the matrix. The parity check matrix H can be expressed using a parity check matrix initial value table that indicates the element position of 1 in the parity check matrix H. FIG. In this embodiment, 1 elements of parity check matrix H are arranged in the column direction at intervals of every 374 columns. The parity check matrix initial value table in this case has a row number of 1 in the column direction of the parity check matrix H (the leading value of the row number is 0) as many as the number of column weights that the column has, 1+374×0 column from the top , 1+374×1st column, 1+374×2nd column, . . . , 1+374×kth column. The value of k differs depending on the coding rate. Assuming that the code length is N and the parity length is P, the relationship of equation (1) holds between the information length (NP) and k.

NP=(k+1)×374 (1)

An example of the parity check matrix initial value table when the coding rate is 81/120 is shown in Table 3 (first half) and Table 4 (second half) below. This parity check matrix initial value table is described in Section 3.4 of Non-Patent Document 4.

An example of the parity check matrix initial value table when the coding rate is 61/120 is shown in Table 5 (first half) and Table 6 (second half) below. This parity check matrix initial value table is described in Section 3.4 of Non-Patent Document 4.
shown in

The value in the first row of the parity check matrix initial value table indicates the row position of 1 in the first column of the parity check matrix. For example, in the case of the check matrix initial value tables shown in Tables 3 and 4, the row positions of 1 in the first column of the check matrix are 4958th, 6639th, 6721st, 8238th, 9540th, 9550th, 10491st, 11742nd, 11641st, 12092nd, 13056th and 13460th. Representing these read row numbers by h _ij , h _1-1 =4958, h _1-2 =6639, h _1-3 =6721, h _1-4 =8238, h _1-5 =9540, h _1-6 =9550, h _1-7 =10491, h _1-8 =11742, h _1-9 =11641, h _1-10 =12092, h _1-11 =13056, and h _1-12 =13460. . Here, _i of h ij is the row number of the parity check matrix initial value table, and _j of h ij is the column number of the parity check matrix initial value table.

Next, using the parity check matrix row number described in the first row of the parity check matrix initial value table read from the predetermined memory area and the equation (2), the parity check matrix of the 2nd to 374th columns of the parity check matrix A row-direction element list H _qj is obtained (q=2 to 374). H _{qj indicates the row number of 1 in the q-} th column of parity check matrix H; The _j in H qj indicates the order of the number of column weight elements. Thus, for column weights of 12, j=1-12. q=1 uses the first row of the parity check matrix initial value table.

H _q−j = mod {(h _i−j +mod((q−1),374))×Q),P} (2)

Here, mod (x, y) means the remainder when x is divided by y. Q in equation (2) has a different value for each coding rate, and Q is obtained by equation (3).

Q = P/374 (3)

A value obtained by calculating the second column (q=2) of the check matrix according to Equation (2) is used as the row number of the second column of the check matrix. Similarly, for q=3 to 374, calculation is performed according to Equation (2) to obtain the row numbers of the check matrix from the 1st column to the 374th column.

Using the 2nd row to the k+1th row (last row) of the parity check matrix initial value table, all the row numbers in the column direction of the parity check matrix are calculated by the method described above. As described above, all the row numbers of 1 in the column direction of the parity check matrix H are determined, and all the element positions of 1 in the parity check matrix H are determined.

FIG. 6 is a diagram illustrating a configuration example of an LDPC block. In the Short and Middle modes, one BCH block is inserted into the LDPC block as shown in FIG. 6(a). In Long mode, a plurality of BCH blocks are inserted into an LDPC block as shown in FIG. 6(b).

In order to improve the performance of the error correction code, the bit interleaving unit 325a performs interleave processing on the LDPC code input from the LDPC encoding unit 324a on a bit-by-bit basis for each LDPC block to generate interleaved data, and performs mapping. output to the unit 326a.

FIG. 7 is a diagram showing a configuration example of the bit interleaving section 325 (325a, 325b). In the example shown in FIG. 7, the bit interleaving section 325 includes a parity interleaving section 3251, a block interleaving section 3252, and an intra-carrier symbol interleaving section 3253, but it may be configured to include only the block interleaving section 3252, or a carrier symbol. A configuration in which only the inner interleaving section 3253 is provided may be employed.

Parity interleaving section 3251 interleaves only parity bits (LDPC parity) for each LDPC block input from LDPC encoding section 324 (324a, 324b) at a predetermined bit period, and divides the parity-interleaved LDPC code into blocks. Output to interleaving section 3252 . For example, the parity interleaving unit 3251 writes parity bits in the memory in the column direction and then reads them out in the row direction. In addition, if the number of columns is the modulation multilevel number of the carrier modulation method (for example, 10 for 1024QAM), by reading each row in the row direction, the modulation multilevel number of the carrier modulation method (for example, even if it is 1024QAM) 10-bit LDPC code is output.

For each LDPC block input from parity interleaving section 3251 , block interleaving section 3252 interleaves the entire LDPC block, and outputs the block-interleaved LDPC code to intra-carrier-symbol interleaving section 3253 .

FIG. 8 is a diagram showing an example of processing by the block interleaver 3252. As shown in FIG. In this example, both the information bit and the parity bit are divided into L pieces, and the t-th (0≦t≦L−1) information bit and parity bit are used as one unit, and are arranged in the memory from the head of each column in the column direction. After sequentially writing, reading is performed in the row direction. As a result, if the LDPC code length is n bits, the memory capacity required for one interleaving process is n/L bits, and the memory capacity can be reduced. When the number of columns is the modulation multi-value number of the carrier modulation method, LDPC codes corresponding to the modulation multi-value number of the carrier modulation method are output by reading out one row at a time in the row direction. If the LDPC code length is not large, it is not necessary to divide the LDPC code with L=1.

In the DVB standard as well, when interleave processing is performed for the entire block, the LDPC code is written in the memory in the column direction and then read in the row direction. The LDPC code of the DVB standard may also generate periodicity due to the fact that it is generated using a parity check matrix having a structure of regular arrangement of 1s. start writing at different positions for each column. On the other hand, in the transmitting apparatus 30 according to the present invention, the LDPC encoding section 324a generates an LDPC code using a parity check matrix that does not have a regular arrangement structure of 1, as described above. The periodicity can be eliminated only by simple processing by the unit 3252 .

Intra-carrier-symbol interleaving section 3253 interleaves the LDPC block input from block interleaving section 3252 according to an input/output conversion table with the same number of bits M, regardless of the carrier modulation method and the coding rate of the LDPC code, and interleaves. The processed LDPC code is output to mapping section 326 . For this intra-carrier-symbol interleaving process, it is preferable to have different input/output conversion tables for each carrier modulation method and coding rate to perform different interleaving processes. Also, in the mapping units 326 and 326b, when it is possible to select whether each symbol is evenly arranged (UC: Uniform Constellation) or non-uniformly arranged (NUC: Non-Uniform Constellation) at the intersection points of the lattice on the IQ plane. , different input/output conversion tables may be used depending on which one is selected.

Here, the number of bits M of the input/output conversion table is an integral multiple of the modulation multilevel number of carrier symbols generated by the mapping section 326 . By setting the number of bits M to a common multiple of the modulation multilevel numbers of all carrier modulation schemes that can be used by the transmitting device 30, the number of bits M can be the same value regardless of the carrier modulation scheme. There is a possibility that the bit interleaving performance will improve as the number of bits M increases, but from the viewpoint of memory increase and optimization difficulty, all carrier modulation schemes that can be used in the transmission device 30 The lowest common multiple of numbers is preferred. In this embodiment, the number of bits M is set to 120, which is the least common multiple of 4, 6, 8, 10, and 12.

Table 1 shows an example of the input/output conversion table used by intra-carrier symbol interleaving section 3253 when the coding rate of the LDPC code is 81/120. When the intra-carrier-symbol interleaving section 3253 performs interleave processing according to this input/output conversion table, the 0th bit is changed to the 10th bit, the 1st bit to the 23rd bit, ... the 119th bit to 113. th bit.

Table 7 below shows an example of an input/output conversion table used by intra-carrier symbol interleaving section 3253 when the coding rate of the LDPC code is 61/120. When the intra-carrier-symbol interleaving unit 3253 performs interleave processing according to this input/output conversion table, the 0th bit becomes the 23rd bit, the 1st bit becomes the 1st bit, . . . the 119th bit becomes 114. th bit.

Mapping section 326a maps the interleaved LDPC code input from bit interleaving section 325a onto the IQ plane as m bits/symbol, and carries out carrier modulation according to the modulation scheme to obtain carrier symbols (modulation symbols). is generated and output to the hierarchical synthesizing unit 327 . The modulation scheme corresponds to, for example, QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM, and the A layer and B layer can be set independently.

As described above, the FEC block transforming unit 321a, the energy spreading unit 322a, the BCH encoding unit 323a, the LDPC encoding unit 324a, the bit interleaving unit 325a, and the mapping unit 326a perform processing for layer A. The FEC block transforming unit 321b, the energy spreading unit 322b, the BCH encoding unit 323b, the LDPC encoding unit 324b, the bit interleaving unit 325b, and the mapping unit 326b perform processing on the B layer, but the processing contents are the same as those on the A layer. Since it is the same, the explanation is omitted.

The layer combining unit 327 combines the layer A carrier symbol input from the mapping unit 326a and the layer B carrier symbol input from the mapping unit 326b to form a data segment transmitted by one OFDM symbol. , to the band division unit 328 .

Band dividing section 328 divides the data segment input from hierarchical synthesizing section 327 into a partial reception band segment and a non-partial reception band segment, and outputs the segments to time interleaving section 329 . In addition to the partial reception band and the non-partial reception band, the additional band (extension band) used in the compatibility mode may be divided into a total of three bands.

Time interleaving section 329 rearranges the order of the carrier symbols input from band dividing section 328 in the time direction, and outputs the result to frequency interleaving section 330 .

Frequency interleaving section 330 further rearranges the order of the carrier symbols input from time interleaving section 329 in the frequency direction, and outputs the result to band combining section 331 .

Band synthesizing section 331 synthesizes the partial reception band and the non-partial reception band, and outputs the result to OFDM frame construction section 334 .

The error correction coding section 332 performs error correction coding on the Lch frame and outputs it to the DBPSK modulation section 333 .

DBPSK modulation section 333 adds a differential reference bit to the head of the code input from error correction encoding section 332 , performs DBPSK modulation to generate an Lch symbol, and outputs the code to OFDM frame construction section 334 .

The OFDM frame construction section 334 arranges the carrier symbols input from the band combining section 331 and the Lch symbols input from the DBPSK modulation section 333 at predetermined positions to generate OFDM symbols. At that time, pilot symbols (SP symbols), TMCC symbols indicating control information, and AC symbols indicating additional information are inserted. Then, with all carriers as one OFDM symbol, an OFDM frame is configured with blocks of a predetermined number of OFDM symbols, and is output to transmission processing section 335 .

The transmission processing unit 335 performs IFFT (Inverse Fast Fourier Transform) processing on the OFDM symbols input from the OFDM frame construction unit 334 to generate effective symbol signals in the time domain. Then, a guard interval, which is a copy of the latter half of the effective symbol signal, is inserted at the beginning of the effective symbol signal, and the analog signal subjected to quadrature modulation processing and D/A conversion is transmitted to the outside via the transmitting antenna 33 .

Although not particularly mentioned in the embodiment, a program that causes a computer to execute each process performed by the transmission device 30 may be provided. Also, the program may be recorded on a computer-readable medium. It can be installed on a computer using a computer readable medium. Here, the computer-readable medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, but may be, for example, a recording medium such as CD-ROM or DVD-ROM.

Alternatively, a chip mounted on transmitter 30 may be provided. This chip is composed of a memory that stores a program for executing each process performed by the transmitter 30, and a processor that executes the program stored in the memory.

[Receiving device]
Next, the configuration of the receiver according to one embodiment of the present invention will be described in detail. FIG. 9 is a block diagram showing a configuration example of a receiver according to one embodiment of the present invention. The receiving device 40 receives an OFDM signal obtained by carrier-modulating and OFDM-modulating an LDPC code, which is transmitted by the transmitting device 30 described above. As shown in FIG. 9 , the receiver 40 includes a demodulator 41 and an output interface 42 .

The demodulator 41 receives the OFDM signal transmitted from the transmitter 30 via the receiving antenna 43 and demodulates it. The received OFDM signal includes carrier symbols of A layer, B layer, and Lch. The demodulator 41 performs processing to undo the processing performed by the transmitting device 30 on the carrier symbols of the A layer, the B layer, and the Lch after the Fourier transform processing.

The output interface unit 42 specifies and outputs variable-length TLV packets from the A-layer bit data, the B-layer bit data, and the Lch bit data.

FIG. 10 is a diagram showing a configuration example of the demodulator 41. As shown in FIG. As shown in FIG. 10, the demodulator 41 includes a reception processor 401, an equalizer 402, a noise variance calculator 403, a band divider 404, a frequency deinterleaver 405, and a time deinterleaver 406. , band synthesis section 407, layer division section 408, LLR (Log Likelihood Ratio) calculation sections 409a and 409b, FEC block conversion sections 410a and 410b, bit deinterleaving sections 411a and 411b, and LDPC. It includes decoding units 412a and 412b, BCH decoding units 413a and 413b, and energy despreading units 414a and 414b.

The reception processing unit 401 receives the OFDM signal transmitted from the transmission device 30 via the reception antenna 43 . Then, the received OFDM signal is subjected to orthogonal demodulation processing to generate a baseband signal, and A/D conversion is performed to generate an analog signal. Next, the effective symbol signal is extracted by removing the guard interval, and the effective symbol signal is subjected to FFT (Fast Fourier Transform) processing to generate a complex baseband signal.

Equalization section 402 extracts a pilot signal from the complex baseband signal input from reception processing section 401 and estimates channel characteristics. Then, the equalization coefficient is calculated, the complex baseband signal is subjected to equalization processing, the carrier symbol of the OFDM signal is generated, and the generated carrier symbol is output to the band dividing section 414 . Equalization uses, for example, a zero-forcing criterion.

Noise variance calculation section 403 calculates noise variance from the carrier symbols input from equalization section 402 and outputs the result to band division section 404 . The noise variance means the deviation between the symbol point on the IQ coordinates where the carrier symbol should be and the symbol point P of the actually observed carrier symbol, and is obtained by obtaining the modulation error ratio and reciprocating it. The noise variance is necessary to obtain the likelihood ratio for each bit that constitutes each carrier symbol.

Band division section 404 divides the carrier symbols input from equalization section 402 and the noise variance input from noise variance calculation section 413 into partial reception bands and non-partial reception bands, respectively, and outputs them to frequency deinterleaving section 405. do. In addition to the partial reception band and the non-partial reception band, the additional band (extension band) used in the compatibility mode may be divided into a total of three bands.

Frequency deinterleaving section 405 performs deinterleaving processing in the frequency direction (reverse processing to frequency interleaving section 330 of transmitting apparatus 30) on the carrier symbols and noise variance input from band dividing section 404, and performs time deinterleaving processing. Output to interleaving section 406 .

Time deinterleaving section 406 performs deinterleaving processing in the time direction (reverse processing to time interleaving section 329 of transmitting apparatus 30) on the carrier symbols and noise variance input from frequency deinterleaving section 405, and performs band Output to the synthesizing unit 407 .

Band synthesizing section 407 synthesizes the partial reception band and the non-partial reception band with the carrier symbols and noise variance input from time deinterleaving section 406 , and outputs the result to layer division section 408 .

Hierarchical division section 408 divides the carrier symbols and noise variance input from band combining section 407 into A and B layers, respectively. Then, the carrier symbols and noise variance of layer A are output to LLR calculation section 409a, and the carrier symbols and noise variance of layer B are output to LLR calculation section 409b.

LLR calculation section 409a calculates likelihood ratios such as LLRs (logarithmic likelihood ratios) using the carrier symbols and noise variance of layer A input from layer division section 418, and outputs the likelihood ratios to FEC block conversion section 410a.

FEC block transforming section 410a divides the likelihood ratio input from LLR calculating section 409a into blocks each having a size equal to the LDPC code length, and outputs the blocks to bit deinterleaving section 411a.

The bit deinterleaving unit 411a performs deinterleaving processing (reverse processing to the bit interleaving unit 325 of the transmitting device 30) for each block on the likelihood ratios input from the FEC block transforming unit 410a. Interleaved data is generated and output to the LDPC decoding unit 412a.

FIG. 11 is a diagram showing a configuration example of the bit deinterleaving unit 411 (411a, 411b). Bit deinterleaving section 411 includes intra-carrier symbol deinterleaving section 4111 , block deinterleaving section 4112 , and parity deinterleaving section 4113 .

Intra-carrier-symbol deinterleaving section 4111 converts the likelihood ratios input from FEC block transforming sections 410a and 410b into input data with the same number of bits M, regardless of the carrier modulation scheme of transmitting apparatus 30 and the coding rate of the LDPC code. Deinterleave processing is performed according to the output conversion table, and likelihood ratios subjected to intra-carrier-symbol deinterleaving processing are output to block deinterleaving section 4212 . This input/output conversion table is obtained by replacing the values of in and out of the input/output conversion table used in intra-carrier-symbol interleaving section 3253 of transmitting apparatus 30 . As described above, the number of bits M is preferably a common multiple or least common multiple of the modulation multilevel numbers of all carrier modulation schemes that can be used in the transmission device 30 .

Table 2 shows an example of the input/output conversion table used by intra-carrier-symbol deinterleaving section 4111 when the coding rate of the LDPC code is 81/120. When the intra-carrier-symbol deinterleaving unit 4111 performs deinterleaving according to this input/output conversion table, the 0th bit becomes the 18th bit, the 1st bit becomes the 11th bit, . . . the 119th bit. to the 97th bit.

Table 8 below shows an example of an input/output conversion table used by intra-carrier-symbol deinterleaving section 4111 when the coding rate of the LDPC code is 61/120. When the intra-carrier-symbol deinterleaving unit 4111 performs deinterleaving according to this input/output conversion table, the 0th bit becomes the 20th bit, the 1st bit becomes the 1st bit, . Permute the bits to the 96th bit.

Block deinterleaving section 4112 sequentially writes the likelihood ratios input from intra-carrier-symbol deinterleaving section 4211 into the memory in the row direction for each block from the beginning of each row, and then reads them in the column direction to read out the entire block. The deinterleaved likelihood ratio is output to parity deinterleaving section 4113 .

Parity deinterleaving section 4113 deinterleaves only the likelihood ratios corresponding to the parity bits of the LDPC code for each block of likelihood ratios input from parity deinterleaving section 4113 at a predetermined bit period, and performs parity deinterleaving. The processed likelihood ratios are output to LDPC decoding sections 412a and 412b.

LDPC decoding section 412a decodes the LDPC code using the deinterleaved data input from bit deinterleaving section 411a, and outputs a bit string to BCH decoding section 413a. The LDPC code decoding algorithm uses, for example, the Sum-product decoding method.

BCH decoding section 413a BCH-decodes the bit string input from LDPC decoding section 412a, and outputs the result to energy despreading section 414a.

The energy despreading unit 414a performs energy despreading processing (reverse processing to the energy spreading unit 322 of the transmitting device 30) on the bit string input from the BCH decoding unit 413a, and outputs layer A bit data to the output interface unit 42. output to

As described above, the LLR calculation unit 409a, the FEC block conversion unit 410a, the bit deinterleaving unit 411a, the LDPC decoding unit 412a, the BCH decoding unit 413a, and the energy despreading unit 414a perform processing for layer A. The LLR calculation unit 409b, the FEC block conversion unit 410b, the bit deinterleaving unit 411b, the LDPC decoding unit 412b, the BCH decoding unit 413b, and the energy despreading unit 414b perform processing for the B layer, but the processing content is the processing for the A layer. , so the description is omitted.

Lch demodulation section 415 extracts the Lch carrier from the complex baseband signal input from reception processing section 401, performs DBPSK demodulation, and demodulates the Lch signal. Then, error correction of the Lch signal is performed, and the decoded Lch bit data is output to the output interface unit 42 .

FIG. 12 is a diagram showing a configuration example of the output interface unit 42. As shown in FIG. The output interface unit 42 shown in FIG. 12 includes bit-to-byte conversion units 421a, 421b, and 421c, TLV (Types Length Value) packet separation units 422a, 422b, and 422c, IP header expansion units 423a, 423b, and 423c, and Eth- IF (Ethernet (registered trademark) interface) 424a and 424b.

The bit-to-byte conversion unit 421a converts the A layer bit data input from the demodulation unit 41 into byte data, and outputs the A layer byte data to the TLV packet separation unit 422a. The bit-to-byte conversion unit 421b converts the B layer bit data input from the demodulation unit 41 into byte data, and outputs the B layer byte data to the TLV packet separation unit 422b. The bit-byte conversion unit 421c converts the Lch bit data input from the demodulation unit 41 into byte data, and outputs the Lch byte data to the TLV packet separation unit 422c.

The TLV packet separation unit 422a performs error correction decoding by the demodulation unit 41 on the A-layer byte data input from the bit-byte conversion unit 421a. Identify the stored TLV packet and output it as an IPv4 packet. However, if part of the TLV packet is transmitted in an FEC block in which the syndrome is not zero, the TLV packet is discarded. Null-type TLV packets are also discarded. The TLV packet separation unit 422b performs the same processing on the B layer byte data input from the bit byte conversion unit 421b.

The TLV packet separation unit 422c combines the Lch byte data input from the bit-byte conversion unit 421c into data on the stream. Then, the TLV packet is specified from the data on the stream and output.

TLV packets transmitted in layer A, TLV packets transmitted in layer B, and TLV packets transmitted in Lch are output from the same Ethernet port (Eth-IF424a), but they are UDP destination port numbers. distinguish by When outputting from the Ethernet port, the interval of the IPv4 packets is adjusted and output so that the TLV packets transmitted in the OFDM frame are output in the OFDM frame time.

The output Ethernet performs bi-directional communication and establishes an Ethernet link, but after the link is established, bi-directional communication is not performed, and only Ethernet frames are output unilaterally, and ARP responses and flow control are not performed. Not performed. Therefore, a broadcast address (0xFFFFFFFFFFFF) is set as the destination MAC address and output. Although it is not assumed that a router is connected to the output interface unit 42, it is possible to connect a switching hub.

There are five types of TLV packets: IPv4 packets, IPv6 packets, header-compressed IP packets, transmission control signal packets, or null packets. When the TLV packet is an IPv4 packet or an IPv6 packet, the IP header expansion unit 423a extracts each IP packet from the data area of the TLV packet and outputs it to the Eth-IF 424b. If the TLV packet is a header-compressed IP packet, the compressed IP header is restored, the IP packet at the time of transmission is restored, and the IP packet is output as an IPv4 packet or an IPv6 packet to the Eth-IF 424b. Also, if the TLV packet is a transmission control signal packet or a null packet, it is discarded. When outputting these IP packets, the IP packet interval is adjusted and output so that the IP packets transmitted in the OFDM frame are output in the OFDM frame time. The IP header extension units 423b and 423c also perform similar processing.

Although not particularly mentioned in the embodiment, a program that causes a computer to execute each process performed by the receiving device 40 may be provided. Also, the program may be recorded on a computer-readable medium. It can be installed on a computer using a computer readable medium. Here, the computer-readable medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, but may be, for example, a recording medium such as CD-ROM or DVD-ROM.

Alternatively, a chip mounted on receiver 40 may be provided. This chip consists of a memory that stores a program for executing each process performed by the receiver 40, and a processor that executes the program stored in the memory.

Next, main operations of the transmitting device 30 and the receiving device 40 according to this embodiment will be described.

FIG. 13 is a flow chart showing main operations of the transmitting device 30 . The transmitting device 30 generates LDPC codes by LDPC-encoding transmission data using the LDPC encoding units 324a and 324b of the modulation unit 32 (step S11).

Then, the transmitting device 30 generates interleaved data by interleaving the LDPC code on a bit-by-bit basis using the bit interleaving units 325a and 325b of the modulating unit 32 (step S12). More specifically, for each block of LDPC code length (LDPC block), the parity bits of the LDPC code are interleaved at a predetermined bit period, then the entire block is interleaved, and further interleaved every predetermined number of bits. .

Then, the transmitting device 30 generates an Lch frame using the mapping sections 326a and 326b of the modulating section 32 (step S13).

Transmitter 30 generates OFDM symbols by arranging carrier symbols at predetermined positions by OFDM frame construction section 334 of modulation section 32, and constructs an OFDM frame (step S14).

Then, the transmission processing unit 335 of the modulation unit 32 of the transmission device 30 generates an OFDM signal based on the OFDM symbols, and transmits the OFDM signal via the transmission antenna 33 (step S14).

FIG. 14 is a flow chart showing main operations of the receiving device 40 . Receiving apparatus 40 estimates channel characteristics and generates carrier symbols of the OFDM signal by equalization section 402 of demodulation section 41 (step S21).

Receiving apparatus 40 then uses noise variance calculator 403 of demodulator 41 to calculate the noise variance from the carrier symbol (step S22).

Receiving device 40 then uses the carrier symbols and the noise variance to calculate likelihood ratios using LLR calculation sections 409a and 409b of demodulation section 41 (step S23).

Then, the receiver 40 generates deinterleaved data by performing deinterleave processing on the likelihood ratio on a bit-by-bit basis using the bit deinterleave units 411a and 411b of the demodulator 41 (step S24). More specifically, for each block of the LDPC code length, deinterleave processing is performed for each predetermined number of bits, and then the entire block is deinterleaved. Deinterleave with .

Then, the receiving device 40 performs LDPC decoding using the deinterleaved data by the LDPC decoding units 412a and 412b of the demodulation unit 41 (step S25).

FIG. 15 shows a simulation result when bit interleave processing is performed using the input/output conversion table shown in Table 1. In FIG. Here, the code length of the LDPC code is 44880 bits, the coding rate of the LDPC code is 81/120, and the modulation multilevel number is 4096 QAM. C2 (standard name: ETSI EN 302 769, see Section 6.2.2 of Non-Patent Document 2) was used. Decoding of the LDPC code was performed by the Sum-product decoding method, and the number of times of iterative decoding was set to 50 times. Also, an AWGN communication channel is assumed as the communication channel.

FIG. 16 shows simulation results when bit interleave processing is performed using the input/output conversion table shown in Table 7. In FIG. Here, the code length of the LDPC code is 44880 bits, the coding rate of the LDPC code is 61/120, and the modulation level is 4096 QAM. C2 (standard name: ETSI EN 302 769, see Section 6.2.2 of Non-Patent Document 2) was used. Decoding of the LDPC code was performed by the Sum-product decoding method, and the number of times of iterative decoding was set to 50 times. Also, an AWGN communication channel is assumed as the communication channel.

As can be seen from FIGS. 15 and 16, in the present invention, the LDPC code is subjected to bit interleave processing, the input/output conversion table is made different for each coding rate of the LDPC code and the carrier modulation method, and the carrier By using the same number of bits regardless of the modulation method, it is possible to eliminate regularity and greatly improve bit error rate (BER) characteristics, that is, improve error correction capability. .

Although the configuration and operation of the transmitting device 30 and the receiving device 40 have been described in this embodiment, the present invention is not limited to this. and a method of receiving an OFDM signal transmitted from the transmitter 30.

Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many modifications and substitutions may be made within the spirit and scope of the invention. Therefore, the present invention should not be construed as limited by the embodiments described above, and various modifications and changes are possible without departing from the scope of the appended claims.

1 OFDM transmission/reception system 10a, 10b, 10c multiplexer 20 remultiplexer 30 transmitter 31 input interface unit 32 modulator 33 transmitter antenna 40 receiver 41 demodulator 42 output interface 43 receiver antenna 50 demultiplexer 311 XMI packet Receiver 312a A-layer frame generator 312b B-layer frame generator 312c Lch frame generator 313 Control information/TMCC information generator 321a, 321b FEC block converter 322a, 322b Energy spreader 323a, 323b BCH encoder 324a, 324b LDPC encoding section 325a, 325b Bit interleaving section 326a, 326b Mapping section 327 Hierarchical combining section 328 Band dividing section 329 Time interleaving section 330 Frequency interleaving section 331 Band combining section 332 Error correction coding section 333 DBPSK modulation section 334 OFDM frame configuration section 335 transmission processing unit 401 reception processing unit 402 equalization unit 403 noise variance calculation unit 404 band division unit 405 frequency deinterleaving unit 406 time deinterleaving unit 407 band synthesis unit 408 layer division unit 409a, 409b LLR calculation unit 410a, 410b FEC block Conversion unit 411a, 411b Bit deinterleaving unit 412a, 412b LDPC decoding unit 413a, 413b BCH decoding unit 414a, 414b Energy despreading unit 415 Lch demodulation unit 421a, 421b, 421c Bit byte conversion unit 422a, 422b, 422c TLV packet separation unit 423a, 423b, 423c IP header expansion unit 424a, 424b Eth-IF
3251 parity interleaving section 3252 block interleaving section 3253 intra-carrier symbol interleaving section 4111 intra-carrier symbol de-interleaving section 4112 block de-interleaving section 4113 parity de-interleaving section

Claims (8)

A transmitter for transmitting an OFDM signal,
an LDPC encoder that LDPC-encodes transmission data to generate an LDPC code;
a bit interleaving unit that generates interleaved data by interleaving the LDPC code in units of bits using an input/output conversion table for each block of the LDPC code length;
a mapping unit that maps the interleaved data onto an IQ plane and generates carrier symbols that have undergone carrier modulation;
an OFDM frame configuration unit that arranges the carrier symbols at predetermined positions to generate an OFDM symbol;
a transmission processing unit that generates an OFDM signal based on the OFDM symbol;
The input/output conversion table differs depending on the coding rate of the LDPC code and the carrier modulation method, and has the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. A transmitting device characterized by: The bit interleaving unit
a parity interleaving unit that interleaves the parity bits of the LDPC code at a predetermined bit period;
a block interleaving unit that sequentially writes the LDPC code processed by the parity interleaving unit into a memory from the head of each column in the column direction for each block, and then reads the LDPC code in the row direction;
an intra-carrier-symbol interleaving unit that interleaves the LDPC code processed by the block interleaving unit according to the input/output conversion table;
2. The transmitting device according to claim 1, characterized by comprising: 3. The transmitting apparatus according to claim 1, wherein the number of bits of said input/output conversion table is a common multiple of modulation multilevel numbers of all carrier modulation schemes usable in said transmitting apparatus. A receiver for receiving an OFDM signal obtained by carrier-modulating and OFDM-modulating an LDPC code,
an equalizer that estimates channel characteristics and generates carrier symbols of the OFDM signal;
a noise variance calculator that calculates a noise variance from the carrier symbols;
an LLR calculator that calculates a likelihood ratio using the carrier symbols and the noise variance;
a bit deinterleaving unit that performs deinterleaving processing on the likelihood ratio on a bit-by-bit basis using an input/output conversion table to generate deinterleaved data;
An LDPC decoding unit that performs LDPC decoding using the deinterleaved data,
The input/output conversion table differs depending on the coding rate of the LDPC code and the carrier modulation method, and has the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. A receiving device characterized by: The bit deinterleaving unit
an intra-carrier-symbol deinterleaving unit that deinterleaves the likelihood ratio according to the input/output conversion table;
a block deinterleaving unit that sequentially writes the likelihood ratios processed by the intra-carrier-symbol deinterleaving unit into a memory in the row direction from the beginning of each row for each block, and then reads them out in the column direction;
a parity deinterleaving unit that deinterleaves, at a predetermined bit period, likelihood ratios corresponding to parity bits of an LDPC code among the likelihood ratios processed by the block deinterleaving unit;
5. The receiving device according to claim 4 , characterized by having: 6. The receiving apparatus according to claim 4 , wherein said same number of bits is a common multiple of modulation multilevel numbers of all carrier modulation schemes usable by a transmitting apparatus that transmits said OFDM signal. A chip mounted on a transmitter that transmits an OFDM signal,
an LDPC encoder that LDPC-encodes transmission data to generate an LDPC code;
a bit interleaving unit that generates interleaved data by interleaving the LDPC code in units of bits using an input/output conversion table for each block of the LDPC code length;
a mapping unit that maps the interleaved data onto an IQ plane and generates carrier symbols that have undergone carrier modulation;
an OFDM frame configuration unit that arranges the carrier symbols at predetermined positions to generate an OFDM symbol;
a transmission processing unit that generates an OFDM signal based on the OFDM symbol;
The input/output conversion table differs depending on the coding rate of the LDPC code and the carrier modulation method, and has the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. Characteristic chip. A chip mounted in a receiver that receives an OFDM signal obtained by carrier-modulating and OFDM-modulating an LDPC code,
an equalizer that estimates channel characteristics and generates carrier symbols of the OFDM signal;
a noise variance calculator that calculates a noise variance from the carrier symbols;
an LLR calculator that calculates a likelihood ratio using the carrier symbols and the noise variance;
a bit deinterleaving unit that performs deinterleaving processing on the likelihood ratio on a bit-by-bit basis using an input/output conversion table to generate deinterleaved data;
An LDPC decoding unit that performs LDPC decoding using the deinterleaved data,
The input/output conversion table differs depending on the coding rate of the LDPC code and the carrier modulation method, and has the same number of bits regardless of the coding rate of the LDPC code and the carrier modulation method. Characteristic chip.

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