JP7649130B2 - Encoder, decoder, transmitter and receiver, and chip - Google Patents

Description

The present invention relates to the technical fields of satellite broadcasting, terrestrial broadcasting, fixed communication, and mobile communication, and in particular to an encoder, decoder, transmitter, receiver, and chip for digital data of a low latency transmission channel (LLch: Low Latency Channel) in next-generation terrestrial broadcasting.

The current terrestrial digital broadcasting system ISDB-T allows data transmission using AC (Auxiliary Channel), and ARIB-STD B31 specifies a transmission method for emergency earthquake alerts, which require low-latency transmission using AC. ISDB-T terrestrial digital broadcasting divides the frequency bandwidth of one channel (approximately 6 MHz) into 13 segments to enable data transmission, but AC transmission achieves low-latency transmission by using the central segment (8 carriers) of the 13 segments, and uses a difference set cyclic code (273, 191) as the error-correcting code.

Figures 12(a) and 12(b) are block diagrams showing the schematic configurations of a transmitter 100 and a receiver 200 for AC transmission data in the conventional terrestrial digital broadcasting system ISDB-T.

The transmitting device 100 includes a difference set cyclic coding unit 101, a DBPSK modulation unit 102, and an OFDM modulation unit 103.

The difference set cyclic encoding unit 101 performs error correction processing on the input AC transmission data using a difference set cyclic code (273, 191), generates AC transmission data with error correction parity added, and outputs it to the DBPSK modulation unit 102.

The DBPSK modulation unit 102 generates an AC carrier by performing symbol mapping using DBPSK (Differential Phase Shift Keying) modulation on the AC transmission data to which error correction parity has been added by the difference set cyclic coding unit 101, and outputs the AC carrier to the OFDM modulation unit 103.

The OFDM modulation unit 103 orthogonally frequency-division multiplexes the AC carrier, three-layer data carrier, and a TMCC (Transmission and Multiplexing Configuration Control) carrier, which is a transmission control signal, to generate an OFDM (Orthogonal Frequency Division Multiplexing) modulated signal, which it outputs to the outside. The OFDM modulation unit 103 uses the central segment (8 carriers) of the 13 segments to transmit AC carriers with the same content using these 8 carriers.

The receiving device 200 includes an OFDM demodulation unit 201, an AC carrier extraction unit 202, a DBPSK demodulation unit 203, and a difference set cyclic code decoding unit 204.

The OFDM demodulation unit 201 receives the OFDM modulated signal transmitted from the transmitting device 100, performs OFDM demodulation processing, and outputs the OFDM demodulated signal to the AC carrier extraction unit 202.

The AC carrier extraction unit 202 extracts the AC carrier from the OFDM demodulated signal based on an external AC specification, and outputs it to the DBPSK demodulation unit 203.

The DBPSK demodulation unit 203 demodulates the AC carrier obtained through the AC carrier extraction unit 202 through symbol demapping based on DBPSK to extract the AC symbol, and outputs it to the difference set cyclic code decoding unit 204.

The difference set cyclic code decoding unit 204 reconstructs the AC transmission data to which error correction parity has been added based on the likelihood judgment from the extracted AC symbols, performs a decoding process based on the difference set cyclic code (273, 191) to restore the output bit string corresponding to the AC transmission data on the transmitting side, and outputs it to the outside.

In this way, AC transmission in the current terrestrial digital broadcasting standard ISDB-T achieves low-latency transmission by using the central segment (8 carriers) of 13 segments, and uses a difference set cyclic code (273, 191) as the error-correcting code.

The theoretical upper limit of the frequency efficiency relative to the signal-to-noise ratio is called the Shannon limit. In this specification, the communication capacity that a modulated signal can achieve is conveniently referred to as the Shannon limit. ARIB STD-B44, which specifies the transmission method for 4K/8K Super Hi-Vision satellite broadcasting, employs LDPC codes as error correction codes for digital transmission (see, for example, Non-Patent Document 1). LDPC codes are linear codes defined by a very sparse check matrix H (the elements of the check matrix consist of 0 and 1, and the number of 1s is very small).

LDPC codes are powerful error-correcting codes that, by using an appropriate check matrix, can generally obtain transmission characteristics approaching the Shannon limit as the code length increases. The use of LDPC codes as error-correcting codes for digital transmission is also being considered for the next generation of terrestrial digital broadcasting systems (see, for example, Non-Patent Document 2).

In the next-generation terrestrial digital broadcasting system, the frequency bandwidth of one channel (approximately 6 MHz) will be divided into 35 segments to enable data transmission, and three FFT point numbers are expected: 8K, 16K, and 32K. For the data carrier that forms the main signal, it is being considered to use an LDPC code as the inner code and a BCH code as the outer code.

However, in the next generation of terrestrial digital broadcasting systems, it is being considered to set up LLch for the purpose of low-latency transmission of digital data instead of AC, and to assign it as one layer to be multiplexed onto the OFDM signal. The specific configuration of the LLch error correction method is still under consideration.

"Transmission method standard for advanced wideband digital satellite broadcasting, ARIB STD-B44, version 2.1, revised March 25, 2016, Association of Radio Industries and Businesses (ARIB) Nakamura, Madoka, "Research and Development for the Realization of Next-Generation Terrestrial Broadcasting," NHK Giken R&D No. 158, August 35, 2016, [online], [Retrieved November 11, 2019], Internet: https://www.nhk.or.jp/strl/publica/rd/rd158/PDF/P28-35.pdf

As mentioned above, the current terrestrial digital broadcasting standard ISDB-T allows data transmission using AC for applications that require low-latency transmission, such as emergency earthquake alerts. However, on the transmitting device side that performs this AC transmission, the central segment (8 carriers) transmits the same data content in order to strengthen resistance to white noise, and as a result, a diversity effect is obtained on the receiving device side that receives the AC-transmitted data. However, even though this AC transmission is a low-latency transmission, it still incurs a transmission delay of one frame (231.336 ms, mode = 3, GI = 1/8), and transmission with even lower latency is required.

In addition, AC transmission in the current terrestrial digital broadcasting system ISDB-T, like TMCC transmission, uses a difference set cyclic code (273, 191) as an error correction code. This difference set cyclic code is a relatively short code and has excellent performance, but it is desirable to further improve its resistance to white noise.

In the next generation of terrestrial digital broadcasting systems, it is expected that LDPC codes will be adopted as an error correction method for LLch, instead of AC, with the aim of low-latency transmission of digital data. LDPC codes not only have excellent transmission performance, but also allow the coding rate to be variably set, making it possible to increase resistance to white noise. On the other hand, LDPC codes have the property that the longer the code length is, the closer the transmission characteristics approaching the Shannon limit can be obtained, but there is a problem in that the longer the code length is, the greater the transmission delay becomes.

For this reason, even if LDPC codes are adopted as the error correction method for LLch, it is necessary to achieve lower latency than conventional AC transmission while at the same time improving resistance to white noise.

In view of the above problems, the object of the present invention is to provide an encoder, decoder, transmitter, receiver, and chip that achieves lower latency while improving resistance to white noise for data transmission on a low-latency transmission channel (LLch) in a terrestrial digital broadcasting system.

The encoder according to the present invention is an encoder that performs error correction coding processing on transmission data of a low-delay transmission channel in a terrestrial digital broadcasting system, and includes a first LDPC encoding means that performs a first LDPC coding processing using a check matrix of a first LDPC coding rate on data to be transmitted using a first segment area that is a central partial reception band among a predetermined number of segments assigned to the low-delay transmission channel, and a second LDPC encoding means that performs a second LDPC coding processing using a check matrix of a second LDPC coding rate on data to be transmitted using a second segment area that is a non-partial reception band other than the partial reception band among the predetermined number of segments assigned to the low-delay transmission channel, and is characterized in that the code lengths of the first LDPC coding processing and the second LDPC coding processing are the same code length.

In addition, in the encoder of the present invention, the first LDPC coding rate is set to a lower coding rate than the second LDPC coding rate.

The encoder according to the present invention is also characterized in that the code length is 1224 bits.

In addition, in the encoder of the present invention, the first LDPC coding rate is greater than or equal to 0.1 and less than 0.2, and the second LDPC coding rate is greater than or equal to 0.8 and less than 1.0.

The encoder according to the present invention is also characterized in that the first LDPC coding rate is 144/1224 and the second LDPC coding rate is 1016/1224.

In the encoder according to the present invention, the first LDPC encoding means is configured to perform the first LDPC encoding process using a check matrix having a code length of 1224 bits and an initial value set to a check matrix initial value table determined in advance according to the first LDPC encoding rate, and the check matrix includes a first submatrix in which one element of a submatrix corresponding to an information length according to the first LDPC encoding rate is periodically arranged in the column direction at a first cycle number, a second submatrix in which one element is periodically arranged in the column direction at a second cycle number different from the first cycle number, and a third submatrix that has been subjected to parity interleaving by shifting in the row direction for each of the first cycle number and periodically arranging one element in the column direction at the second cycle number.

In the encoder according to the present invention, the second LDPC encoding means is configured to perform the second LDPC encoding process using a check matrix having a code length of 1224 bits and an initial value set to a check matrix initial value table determined in advance according to the second LDPC encoding rate, and the check matrix includes a submatrix in which one element of the submatrix corresponding to the information length according to the second LDPC encoding rate is periodically arranged in the column direction at a third cycle number.

In the encoder according to the present invention, the check matrix initial value table (Table 1) for the coding rate of 144/1224, which indicates the initial values when the first submatrix is submatrix A, the second submatrix is submatrix C, and the third submatrix is submatrix D, is characterized in that it is made up of the following table:

In addition, in the encoder according to the present invention, the check matrix initial value table (Table 2) for the coding rate of 1016/1224 indicating the initial values of the submatrix is characterized by comprising the following table:

The decoder according to the present invention is characterized by comprising: means for LDPC decoding data encoded by the encoder of the present invention using the first LDPC encoding process, using a check matrix of the first LDPC encoding rate; and means for LDPC decoding data encoded by the encoder using the second LDPC encoding process, using a check matrix of the second LDPC encoding rate.

The transmitting device according to the present invention is also characterized by having an encoder according to the present invention.

The receiving device according to the present invention is also characterized by having a decoder according to the present invention.

The chip according to the present invention is characterized by having any one of the encoder, decoder, transmitter, and receiver according to the present invention.

According to the present invention, the amount of delay in transmission of the low-latency transmission channel (LLch) in the next generation of terrestrial digital broadcasting can be significantly reduced compared to the AC transmission of the current terrestrial digital broadcasting system ISDB-T, and noise resistance can also be improved by using LDPC codes as error correction codes.

1 is a block diagram illustrating only the main components of a low latency transmission channel (LLch) transmission data transmission device according to an embodiment of the present invention; 1 is a block diagram illustrating only the main components of a receiving device for receiving data transmitted through a low-delay transmission channel (LLch) according to an embodiment of the present invention; 1A and 1B are diagrams showing the configuration of an error correction block with an LDPC coding rate of 144/1224 according to one embodiment of an LDPC code with a code length of 1224 bits formed for data (L0ch transmission data) transmitted using a first segment area that is a central partial reception band among a predetermined number of segments assigned to a low-latency transmission channel according to the present invention, and the configuration of an error correction block with an LDPC coding rate of 1016/1224 according to one embodiment of an LDPC code with a code length of 1224 bits formed for data (L1ch transmission data) transmitted using a second segment area that is a non-partial reception band other than the partial reception band among a predetermined number of segments assigned to a low-latency transmission channel. 1A and 1B are diagrams showing a check matrix H of an LDPC coding rate of 144/1224 for an LDPC code of a code length of 1224 bits formed for L0ch transmission data according to the present invention, and a check matrix H of an LDPC coding rate of 1016/1224 for an LDPC code of a code length of 1224 bits formed for L1ch transmission data according to the present invention, respectively. 1 is a diagram showing a submatrix B on a check matrix H for an LDPC code having a code length of 1224 bits formed for L0ch transmission data and L1ch transmission data according to the present invention. FIG. 1 is a diagram showing a submatrix I on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. 1 is a diagram showing a submatrix A on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. 1 is a diagram showing a submatrix C on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. 1 is a diagram showing a submatrix D on a check matrix H for an LDPC code having a code length of 1224 bits formed for L0 ch transmission data according to the present invention. FIG. 1 is a diagram showing a submatrix A on a check matrix H related to an LDPC code having a code length of 1224 bits formed for L1ch transmission data according to the present invention. FIG. 5A and 5B are diagrams showing C/N versus BER and FER characteristics when DBPSK modulation is applied to L0ch transmission data and L1ch transmission data according to the present invention, respectively. 1A and 1B are block diagrams showing schematic configurations of a transmitter and a receiver for AC transmission data in the conventional terrestrial digital broadcasting standard ISDB-T, respectively.

The following describes a transmitter 1 and a receiver 2 for low-delay transmission channel (LLch) data according to one embodiment of the present invention, with reference to the drawings. The transmission system according to one embodiment of the present invention is composed of a transmitter 1 shown in FIG. 1 and a receiver 2 shown in FIG. 2, which are intended for a next-generation terrestrial broadcast transmission system, and employs an LDPC code as an error correction method for low-delay transmission channel (LLch) data used in the next-generation terrestrial broadcast transmission system, and further divides the data into two types of segment areas, each of which is optimized as a forward error correction code.

First, referring to FIG. 1, a transmitter 1 according to an embodiment of the present invention will be described.

[Transmitting device]
Fig. 1 is a block diagram showing only the main components of a transmitter 1 for low-delay transmission channel (LLch) data according to an embodiment of the present invention. The transmitter 1 includes an encoder 10 (a first LDPC encoding unit 11 and a second LDPC encoding unit 12), a DBPSK modulation unit 13, and an OFDM modulation unit 16. The transmitter 1 is configured to transmit LLch transmission data divided into two types of segment areas, and performs a series of processes from generating an error correction block signal shown in Fig. 3 to generating an OFDM modulated signal. The transmitter 1 can be configured to transmit parameters related to transmission, such as the modulation method and coding rate of the LLch transmission data, by including them in the TMCC signal. In this example, the modulation method and coding rate of the LLch transmission data are predetermined between the transmitter 1 shown in Fig. 1 and the receiver 2 shown in Fig. 2, and an example will be described in which the receiver 2 demodulates and decodes the LLch transmission data without demodulating and decoding the TMCC signal.

In addition, in the next generation of terrestrial digital broadcasting systems, it is expected that LLch will be set instead of AC for the purpose of low-latency transmission of digital data, and assigned as one layer to be multiplexed onto the OFDM signal. For this reason, the transmitting device 1 shown in FIG. 1 generates an OFDM modulated signal by orthogonal frequency division multiplexing the LLch carrier that is the carrier wave of the LLch transmission data, independent of the data carrier that is the main signal and the TMCC carrier that is the transmission control signal. Therefore, the LLch carrier, like the TMCC carrier, can be transmitted to the receiving device 2 independently of the data carrier that is the main signal.

The transmitting device 1 illustrated in FIG. 1 has an encoder 10 including a first LDPC encoding unit 11 that performs a first LDPC encoding process using a check matrix H with a first LDPC encoding rate of 144/1224 on data (L0ch transmission data) to be transmitted using a first segment area (9 segments) that is a partial reception band in the center out of a predetermined number of segments (35 segments) assigned to LLch, and a second LDPC encoding unit 12 that performs a second LDPC encoding process using a check matrix with a second LDPC encoding rate of 1016/1224 on data (L1ch transmission data) to be transmitted using a second segment area (26 segments) that is a non-partial reception band other than the partial reception band. Hereinafter, each component of the transmitting device 1 illustrated in FIG. 1 will be described.

The first LDPC encoding unit 11 inputs a bit string (144 information bits) of L0ch transmission data to be transmitted using a first segment area (9 segments) that is the central partial reception band of the LLch, performs a first LDPC encoding process using a check matrix H with a first LDPC coding rate of 144/1224, constructs an error correction block having L0ch transmission data with LDPC parity added, and outputs it to the DBPSK modulation unit 13.

The first LDPC encoding unit 11 has a parity interleaving unit 11a that performs bit swapping of LDPC parity in an order that is specified in advance by a submatrix of the check matrix H, as will be described in detail later.

The second LDPC encoding unit 12 inputs a bit string (1016 information bits) of L1ch transmission data to be transmitted using a second segment area (26 segments) that is a non-partial reception band of the LLch, performs a second LDPC encoding process using a check matrix H with a second LDPC coding rate of 1016/1224, constructs an error correction block having L1ch transmission data to which LDPC parity has been added, and outputs the block to the DBPSK modulation unit 13. Note that, in this example, the second LDPC encoding unit 12 does not have a parity interleaving function that replaces the bits of the LDPC parity, but it is also possible to configure the block to have a parity interleaving unit similar to the first LDPC encoding unit 11.

Figure 3(a) is a diagram showing the configuration of an error correction block with an LDPC coding rate of 144/1224 in one embodiment of an LDPC code with a code length of 1224 bits formed for data (L0ch transmission data) transmitted using a first segment area (9 segments) that is a central partial reception band among a predetermined number of segments (35 segments) assigned to a low-latency transmission channel according to the present invention. Also, Figure 3(b) is a diagram showing the configuration of an error correction block with an LDPC coding rate of 1016/1224 in one embodiment of an LDPC code with a code length of 1224 bits formed for data (L1ch transmission data) transmitted using a second segment area (26 segments) that is a non-partial reception band other than the partial reception band among a predetermined number of segments (35 segments) assigned to a low-latency transmission channel according to the present invention.

As shown in Figures 3(a) and 3(b), the error correction block of the L0ch transmission data with the first LDPC coding rate of 144/1224 in the first LDPC encoding unit 11 and the error correction block of the L1ch transmission data with the second LDPC coding rate of 1016/1224 in the second LDPC encoding unit 12 are configured by dividing the input bit string into predetermined lengths according to the respective LDPC coding rates. For example, for the error correction block with the LDPC coding rate of 144/1224 shown in Figure 3(a), the input bit string of the L0ch transmission data is divided into 144-bit information bit lengths and output to the subsequent functional block each time.

In addition, the code length of each error correction block is 1224 bits based on the LDPC code, and the code length unit of the error correction block is common to reduce unnecessary processing load. Furthermore, it is generally known that LDPC codes have a code length of 1000 bits or more to improve performance compared to turbo codes. On the other hand, in order to achieve low-latency transmission, it is preferable to use a code length as short as possible, so the code length is set to 1224 bits. In addition, since L0ch has 9 segments, and there are 8 carriers per segment, the code length is set to a multiple of 72. In addition to 1224 bits, other options for code length that meet this condition include 1008 bits, 1080 bits, and 1152 bits, etc., in order to achieve lower latency transmission. However, 1224 bits is selected as a configuration that not only improves performance compared to difference set cyclic codes or Reed-Solomon codes, but also reliably improves performance compared to turbo codes.

The first LDPC coding rate of the L0ch transmission data is required to be receivable even at an extremely low C/N ratio when considering the transmission of emergency earthquake alerts, so it is set to 0.1 or more and less than 0.2, and therefore, as shown in FIG. 3(a), it is configured with 144 information bits. The second LDPC coding rate of the L1ch transmission data is required to be 0.8 or more and less than 1.0, and therefore, as shown in FIG. 3(b), it is configured with 1016 information bits. In this way, the transmitting device 1 according to the present invention is divided into two types of segment areas so that the LDPC coding rate according to the application can be applied, and an appropriate coding rate is selected according to the application.

The DBPSK modulation unit 13 generates LLch carriers through symbol mapping by DBPSK modulation for the error correction blocks of the L0ch transmission data and the L1ch transmission data, each of which has LDPC parity added, and outputs the LLch carriers to the OFDM modulation unit 16. Note that, in order to provide a diversity effect on the receiving device 2 side, the LLch carriers may be assigned in the symbol direction in any number of 1, 2, 4, or 8 for the error correction blocks of the same content within the first segment area (9 segments) for the L0 carrier and within the second segment area (26 segments) for the L1 carrier.

The OFDM modulation unit 16 performs orthogonal frequency division multiplexing on the LLch carrier, the three-layer data carrier, and the TMCC carrier, which is a transmission control signal, to generate an OFDM modulated signal, which is then output to the outside.

Next, referring to FIG. 2, a receiving device 2 according to one embodiment of the present invention will be described.

[Receiving device]
Fig. 2 is a block diagram showing only the main components of a receiver 2 for low-delay transmission channel (LLch) data according to an embodiment of the present invention. The receiver 2 shown in Fig. 2 includes an OFDM demodulator 21, an LLch carrier extractor 22, a DBPSK demodulator 23, and an LDPC decoder 24. In this example, the modulation method and coding rate of the LLch transmission data are determined in advance between the transmitter 1 shown in Fig. 1 and the receiver 2 shown in Fig. 2, and the receiver 2 demodulates and decodes the LLch transmission data without demodulating and decoding the TMCC signal. However, a configuration may be adopted in which transmission-related parameters such as the modulation method and coding rate of the LLch transmission data are included in the TMCC signal and transmitted, and the receiver 2 demodulates and decodes the LLch transmission data after demodulating and decoding the TMCC signal.

The OFDM demodulation unit 21 receives the OFDM modulated signal transmitted from the transmitting device 1, performs OFDM demodulation processing, and outputs the OFDM demodulated signal to the LLch carrier extraction unit 22.

The LLch carrier extraction unit 22 extracts at least one of the LLch carriers of L0ch and L1ch from the OFDM demodulated signal based on an external specification of L0ch or L1ch (or both L0ch and L1ch), and outputs it to the DBPSK demodulation unit 23.

The DBPSK demodulation unit 23 performs DBPSK demodulation on the LLch carrier obtained through the LLch carrier extraction unit 22 through symbol demapping based on DBPSK, extracts the LLch symbol of L0ch or L1ch, and outputs it to the LDPC decoding unit 24.

The LDPC decoding unit 24 reconstructs the LLch transmission data with error correction parity added for the extracted LLch symbols of L0ch or L1ch (or both L0ch and L1ch) based on a likelihood judgment using the corresponding check matrix, performs a decoding process based on the LDPC code, restores a bit string corresponding to the LLch transmission data of L0ch or L1ch (or both L0ch and L1ch) on the transmitting side, and outputs the bit string to the outside as an output bit string.

That is, the LDPC decoding unit 24 is configured as a decoder including means for LDPC decoding data encoded by a first LDPC encoding process performed by the first LDPC encoding unit 11 in the encoder 10 using a check matrix with a first LDPC encoding rate of 144/1224, and means for LDPC decoding data encoded by a second LDPC encoding process performed by the second LDPC encoding unit 12 in the encoder 10 using a check matrix with a second LDPC encoding rate of 1016/1224.

[LDPC code with a code length of 1224 bits]
First, referring to Fig. 3 and Fig. 4 to Fig. 10, the encoder 10 and the decoder (LDPC decoding unit 24) for each of the coding rates of 144/1224 and 1016/1224 in the LDPC code with a code length of 1224 bits will be described. Fig. 4(a) and (b) are diagrams showing a check matrix H with an LDPC coding rate of 144/1224 for the LDPC code with a code length of 1224 bits formed for the L0ch transmission data according to the present invention, and a check matrix H with an LDPC coding rate of 1016/1224 for the LDPC code with a code length of 1224 bits formed for the L1ch transmission data according to the present invention. Fig. 5 is a diagram showing a submatrix B on the check matrix H for the L0ch transmission data and the LDPC code with a code length of 1224 bits formed for the L1ch transmission data according to the present invention. Figs. 6 to 9 are diagrams showing submatrix I, A, C, D on the check matrix H for the LDPC code of the L0ch transmission data, respectively. FIG. 10 is a diagram showing a submatrix A on a check matrix H related to an LDPC code having a code length of 1224 bits that is formed for L1ch transmission data according to the present invention.

(Error correction block configuration with coding rates of 144/1224 and 1016/1224)
As shown in Fig. 3(a), the error correction block of the L0ch transmission data is composed of 144 information bits and a code length of 1224 bits consisting of 1080 LDPC parity bits, and the coding rate is 144/1224.Also, as shown in Fig. 3(b), the error correction block of the L1ch transmission data is composed of 1016 information bits and a code length of 1224 bits consisting of 208 LDPC parity bits, and the coding rate is 1016/1224.

Note that in the above-mentioned Figures 1 to 3, only the LDPC code is used as the error correction code, but for example, the information bits in Figures 3(a) and (b) may include the parity of the BCH code, or may be appropriately subjected to power dispersal processing.

(Encoder process at LDPC coding rate 144/1224)
As shown in Fig. 4(a), the first LDPC encoding unit 11 in the encoder 10 of this embodiment generates a check matrix H with an LDPC coding rate of 144/1224, which is divided into six regions by submatrices A, B, C, D, I, and O, and generates LDPC code parity using this check matrix H. The row length of check matrix H corresponds to LDPC code length, and LDPC code length N is set to 1224. Since the coding rate of this check matrix is 144/1224, the column length of check matrix H corresponds to LDPC parity length, and LDPC parity length P is 1080 bits.

In FIG. 4(a), submatrices A, C, and D are submatrices constructed using the check matrix initial value table shown in Table 1 above, and the LDGM structure (FIG. 5) is applied to submatrix B. The LDGM structure is a step matrix in which the row weight (the number of 1s in the row direction of the check matrix) is 1 in the first row, all the remaining row weights are 2, and the column weight is 2 for all columns. In the case of an error correction block of L0ch transmission data, the size of submatrix B is 72 bits in both the row and column directions. In addition, a diagonal matrix (FIG. 6) is applied to submatrix I. All row weights of the diagonal matrix are 1. The size of submatrix I is 1008 bits in both the row and column directions. Submatrix O corresponds to a zero matrix.

For the error correction block of L0ch transmission data, the size of submatrix A is 72 bits (rows) × 144 bits (columns), as shown in Figure 7.

Furthermore, the size of submatrix C is 1008 bits (rows) × 144 bits (columns), as shown in Figure 8.

The size of submatrix D is 1008 bits (rows) × 72 bits (columns), as shown in Figure 9.

Since the size of any of the submatrices A, C, and D is finite, the positions of 1's in the parity check matrix are calculated based on the following equation (1).
H _q−j = mod {(h _ij + mod((q−1),8)) × Q),P} (1)
Here, i of h _i-j is the row number of the check matrix initial value table, and j of h _i-j is the column number of the check matrix initial value table. _{H q-j} indicates the row number of 1 in the q-th column of the check matrix H. J of _{H q-j} indicates the order of the number of elements of column weight. Therefore, in the case of column weight 9, j=1 to 9. q=1 means to use the first row of the check matrix initial value table. Also, mod(x, y) means the remainder when x is divided by y. Q of formula (1) is the number of cycles that has a value determined for each coding rate, and Q is obtained by formula (2).

Q = row size of each submatrix / 8 (2)

Therefore, in this embodiment, with an LDPC coding rate of 144/1224, for submatrix A, Q = 9 (first cycle number Q1), and for submatrix C and submatrix D, Q = 126 (second cycle number Q2).

Below, we will explain in more detail how to generate a check matrix H divided into six regions by submatrices A, B, C, D, I, and O at an LDPC coding rate of 144/1224.

First, the submatrix A (FIG. 7) will be described. In order to form the submatrix A, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out values from a part of the check matrix initial value table shown in Table 1 above, and periodically arranges the positions of 1 in the area of the submatrix A in the check matrix H. The check matrix initial value table shown in Table 1 has 27 values in the column direction and a maximum of 15 values in the row direction. This value corresponds to the first position (initial value) of 1 in the check matrix used in the submatrices A, C, and D. That is, the numerical coordinate hi-j (numerical value) of the i-th row and j-th column in Table 1 specifies the first position of 1 in the submatrices A, C, and D in the check matrix H shown in FIG. 4(a). As an example, in FIG. 7, h1-1(6) corresponds to arranging the 1 in the first column of the submatrix A in the 6th row of the check matrix H, and h1-2(50) corresponds to arranging the 1 in the first column of the submatrix A in the 50th row of the check matrix H. Additionally, h2-1(28) corresponds to placing the 1 in the 9th column of submatrix A in the 28th row of check matrix H, and h2-2(43) corresponds to placing the 1 in the 9th column of submatrix A in the 43rd row of check matrix H.

Based on the above relationship, as shown in FIG. 7, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads all of the numerical coordinates hi-j (numerical values) of 18 rows and j columns (3 columns) for specifying the row positions where 1's are placed every 8 columns of submatrix A from the check matrix initial value table in Table 1, and initially assigns 1 to the specified positions in submatrix A, shifts 1 bit to the right in the row direction based on the position of the initially assigned 1, and assigns 1 to the position shifted downward in the column direction by the first cycle number Q1 = 9 (9 bits), repeating this process to construct submatrix A in check matrix H.

<Numeric coordinates hi-j (numeric values) for submatrix A of the check matrix initial value table in Table 1>
1st line: h1-1(6) to h1-3(67)
2nd line: h2-1 (28) to h2-3 (56)
Third line: h3-1 (0) to h3-3 (21)
...
18th line: h18-1 (51) to h18-3 (68)

In this way, by reading out the numerical values of 18 rows (each of these 18 rows corresponds to the first column of every 8 columns of submatrix A) in the numerical coordinates hi-j(numerical value) for submatrix A in Table 1 column by column (the numerical value of each column corresponds to the first row position of every 8 columns of submatrix A), and repeating the first cycle number Q1 = 9 shifts as shown in FIG. 7, it is possible to specify the position of 1 in submatrix A in the check matrix H equivalent to 8 x 18 = 144 bits (columns). In addition, the number of rows in submatrix A is 8 x Q1 = 72, and the size of submatrix A is 144 bits in the row direction and 72 bits in the column direction.

Submatrix C (FIG. 8) will now be described. In order to form submatrix C, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads values from a portion of the check matrix initial value table shown in Table 1 above, and periodically arranges the positions of 1 within the area of submatrix C in the check matrix H. The check matrix initial value table shown in Table 1 lists 27 values in the column direction and a maximum of 15 values in the row direction. Submatrix C differs from submatrix A in the read positions in the check matrix initial value table and the number of cycles.

As shown in FIG. 8, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads all of the numerical coordinates hi-j (numerical values) of 18 rows and j columns (maximum 12 columns) for specifying the row positions where 1's are placed every 8 columns of the submatrix C from the check matrix initial value table in Table 1, and first assigns 1 to the specified position in the submatrix C, shifts 1 bit to the right in the row direction based on the position of the 1 initially assigned, and then assigns 1 to the position shifted downward in the column direction by the second cycle number Q2 = 126 (126 bits), repeating this process to construct the submatrix C in the check matrix H in FIG. 4(a).

<Numeric coordinates hi-j (numeric values) for submatrix C of the check matrix initial value table in Table 1>
1st line: h1-4 (259) to h1-15 (990)
2nd line: h2-4 (140) to h2-15 (1037)
3rd line: h3-4 (105) to h3-15 (998)
4th line: h4-4 (99) to h4-15 (920)
5th line: h5-4 (101) to h5-13 (762)
...
18th line: h18-4 (142) to h18-13 (961)

In this way, by reading out the numerical values of 18 rows (each of these 18 rows corresponds to the first column of every 8 columns of submatrix C) in the numerical coordinates hi-j(numerical value) for submatrix C in Table 1 column by column (the numerical value of each column corresponds to the first row position of every 8 columns of submatrix C), and repeating the second cycle number Q2 = 126 shifts as shown in FIG. 8, it is possible to specify the position of 1 in submatrix C in the parity check matrix H equivalent to 8 x 18 = 144 bits (columns). In addition, the number of rows in submatrix C is 8 x Q2 = 1008, and the size of submatrix C is 144 bits in the row direction and 1008 bits in the column direction.

Next, the submatrix D (FIG. 9) will be described. In order to form the submatrix D, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads out values from a part of the check matrix initial value table shown in Table 1 above (rows 19 to 27 in Table 1) and periodically arranges the positions of 1 in the area of the submatrix D in the check matrix H. However, the submatrix D applies the same second cycle number Q2=126 as the submatrix C, but differs from the submatrix C in that the parity bit replacement is applied as the parity interleaving unit 11a by using a row-wise bit shift equivalent to the first cycle number Q1=9 in the read cycle in the check matrix initial value table.

As shown in FIG. 9, the first LDPC encoding unit 11 in the encoder 10 of this embodiment reads all of the numerical coordinates hi-j (numerical values) of 9 rows and j columns (8 columns) for specifying the row positions where 1's are placed every 8 columns of the submatrix D from the check matrix initial value table in Table 1, and initially assigns 1's to the positions in the specified submatrix D. Based on the position of the 1's initially assigned, the first cycle number Q1 = 9 bits are shifted to the right in the row direction, and the second cycle number Q2 = 126 (126 bits) is shifted downward in the column direction. By repeating this process, submatrix D in the check matrix H in FIG. 4(a) is constructed.

<Numeric coordinates hi-j (numeric values) for submatrix D of the check matrix initial value table in Table 1>
19th line: h19-1 (217) to h19-8 (1050)
20th line: h20-1 (86) to h20-8 (1059)
21st line: h21-1 (481) to h21-8 (1075)
Line 22: h22-1 (561) to h22-8 (1012)
23rd line: h23-1 (213) to h23-8 (1043)
...
27th line: h27-1 (90) to h27-8 (1052)

In this way, the method of reading the parity interleaving-applied check matrix initial value table is a different reading method from the submatrices A and C, and the numerical values of 9 rows (each of these 9 rows corresponds to the first 9 columns of submatrix D) in the numerical coordinate hi-j (numerical value) for submatrix D in Table 1 are read column by column (the numerical value for each column corresponds to the row position of each of the first 9 columns of submatrix D), and the reading of one row of the numerical coordinate hi-j (numerical value) for submatrix D in Table 1 is regarded as one set. Then, as shown in FIG. 9, by repeating a right shift of Q1=9 bits corresponding to the first cycle number and a downward shift of Q2=126 corresponding to the second cycle number eight times, it is possible to specify the position of 1 in the submatrix D in the check matrix H equivalent to 8×9=72 bits (columns). The number of rows of the submatrix D is 8×Q2=1008, and the size of the submatrix D is 72 bits in the row direction and 1008 bits in the column direction.

That is, the relationship between the check matrix initial value table in submatrix D shown in Table 1 and the column numbers in check matrix H is as follows:
The numerical value in the 19th row of the check matrix initial value table indicates the first position of a 1 in the 145th column of the check matrix H (i.e., the first column of the submatrix D) (the row position in the first check matrix H to be repeated with cycle numbers Q1 and Q2).
The numerical value in the 20th row of the check matrix initial value table indicates the first position of a 1 in the 146th column of the check matrix H (i.e., the second column of the submatrix D) (the row position in the first check matrix H to be repeated with cycle numbers Q1 and Q2).
The numerical value in row 21 of the check matrix initial value table indicates the first position of a 1 in column 147 of check matrix H (i.e., the third column of submatrix D) (the row position in the first check matrix H to be repeated with cycle numbers Q1 and Q2).
The numerical value in row 22 of the check matrix initial value table indicates the first position of a 1 in column 148 of check matrix H (i.e., the fourth column of submatrix D) (the row position in the first check matrix H to be repeated with cycle numbers Q1 and Q2).
The value in the 23rd row of the check matrix initial value table indicates the first position of a 1 in the 149th column of the check matrix H (i.e., the 5th column of submatrix D) (the row position in the first check matrix H to be repeated with cycle numbers Q1 and Q2).
The same applies below.

In FIG. 9, the value read from the 19th row of the check matrix initial value table is shifted by Q2=126 for every Q1=9 bits. By repeating this operation 8 times, the position of 1 in the submatrix D is determined for a total of 8 columns. Similarly, the value read from the 20th row of the check matrix initial value table is also shifted by Q2=126 for every Q1=9 bits, and the position of 1 in the submatrix D is determined for a total of 8 columns. Thereafter, by repeating the same process on the 21st to 27th rows, the position of 1 in the submatrix D equivalent to 8 columns x 9 sets = 72 bits is determined. Therefore, the size of the submatrix D is 72 bits in the row direction and 1008 bits in the column direction. In this way, by including the submatrix D to which the parity interleaving that shifts Q2 for every Q1 is applied in the check matrix H, it is possible to avoid the occurrence of cycle 4 that occurs between this submatrix D and the submatrix B that is connected to the higher order, and improve the decoding performance of the LDPC code. In other words, one of the causes of degradation in transmission characteristics in LDPC codes is the occurrence of an error floor, and it is known that the cause of this error floor is that when the arrangement of 1s contained in the check matrix H has a large number of shape arrangements with a cycle of 4, for example, the possibility of an error floor occurring increases. Therefore, as a means of solving this problem, the check matrix H is made to include a submatrix D.

The LDPC parity is calculated by the parity check equation (3) using the check matrix H, which is a set matrix of submatrices A, B, C, D, I, and O at an LDPC coding rate of 144/1224 obtained by the above process. Note that in the case of a coding rate of 144/1224, since the information bit length is 144 bits, in the parity check equation, parity calculation based on the LDGM structure is applied to the 1st to 72nd rows of the check matrix H, and parity calculation based on the diagonal structure is applied to the 73rd to 1080th rows.

H・C ^T =0 (3)

(Encoder process at LDPC coding rate 1016/1224)
On the other hand, the second LDPC encoding unit 12 in the encoder 10 of this embodiment generates a check matrix H with an LDPC coding rate of 1016/1224, which is divided into two regions by submatrix A and B, as shown in Fig. 4 (b), and generates LDPC code parity using this check matrix H. The row length of check matrix H corresponds to LDPC code length, and LDPC code length N is set to 1224. Since the coding rate of this check matrix is 1016/1224, the column length of check matrix H corresponds to LDPC parity length, and LDPC parity length P is 280 bits.

In FIG. 4(b), submatrix A is a submatrix constructed using the check matrix initial value table shown in Table 2 above, and the LDGM structure (FIG. 5) is applied to submatrix B. The LDGM structure is a step matrix in which the row weight (the number of 1s in the row direction of the check matrix) is 1 for the first row, all the remaining row weights are 2, and the column weight is 2 for all columns. The size of submatrix B is 208 bits in both the row and column directions for the error correction block of L1ch transmission data.

For the error correction block of L1ch transmission data, the size of submatrix A is 208 bits (rows) × 1016 bits (columns), as shown in Figure 10.

Since the size of submatrix A is finite, the positions of 1 in the check matrix are calculated based on the above-mentioned formula (1). Furthermore, Q in formula (1) is calculated using the above-mentioned formula (2), and as shown in FIG. 10, Q = 208/8 = 26.

Therefore, in this embodiment, with an LDPC coding rate of 1016/1224, Q of submatrix A is 26.

Below, we will explain in more detail how to generate check matrix H using submatrix A with an LDPC coding rate of 1016/1224.

In order to form submatrix A, the second LDPC encoding unit 12 in the encoder 10 of this embodiment reads out a value from a part of the parity check matrix initial value table shown in Table 2 above, and periodically arranges the position of 1 in the area of submatrix A in parity check matrix H. The parity check matrix initial value table shown in Table 2 lists 127 values in the column direction and a maximum of 5 values in the row direction. This value corresponds to the first position (initial value) of 1 in the parity check matrix used in submatrix A. That is, the first position of 1 in submatrix A in parity check matrix H shown in FIG. 4(b) is specified by the numerical coordinate h _i-j (numerical value) of the i-th row and j-th column in Table 2. As an example, in FIG. 10, h1-1(7) corresponds to arranging the 1 in the first column of submatrix A in the 7th row of parity check matrix H, and h1-2(62) corresponds to arranging the 1 in the first column of submatrix A in the 62nd row of parity check matrix H. In addition, h2-1(58) corresponds to placing the 1 in the 9th column of submatrix A in the 58th row of check matrix H, and h2-2(91) corresponds to placing the 1 in the 9th column of submatrix A in the 91st row of check matrix H.

Based on the above relationship, as shown in FIG. 10, the second LDPC encoding unit 12 in the encoder 10 of this embodiment reads all of the numerical coordinates hi-j (numerical values) of 127 rows and j columns (maximum 5 columns) for specifying the row positions where 1's are placed every 8 columns of submatrix A from the check matrix initial value table in Table 2, and initially assigns 1 to the specified position in submatrix A, shifts 1 bit to the right in the row direction based on the position of the initially assigned 1, and assigns 1 to the position shifted downward in the column direction by the number of cycles Q = 26 (26 bits), repeating this process to construct submatrix A in check matrix H.

<Numeric coordinates hi-j (numeric values) for submatrix A of the check matrix initial value table in Table 2>
1st line: h1-1 (7) to h1-5 (193)
2nd line: h2-1 (58) to h2-5 (153)
Third line: h3-1 (2) to h3-5 (200)
...
8th line: h8-1 (15) to h8-5 (203)
9th line: h9-1 (61) to h9-3 (176)
...
Line 127: h127-1 (2) to h127-3 (198)

In this way, by reading out the numerical values of 127 rows (each of these 127 rows corresponds to the first column of every 8 columns of submatrix A) in the numerical coordinates hi-j(numerical value) for submatrix A in Table 2 column by column (the numerical value of each column corresponds to the first row position of every 8 columns of submatrix A), and repeating the cycle number Q=26 shifts as shown in FIG. 10, it is possible to specify the position of 1 in submatrix A in the parity check matrix H equivalent to 8×127=1016 bits (columns). The number of rows in submatrix A is 8×Q1=208, and the size of submatrix A is 1016 bits in the row direction and 208 bits in the column direction.

The LDPC parity is calculated by the above-mentioned parity check equation (3) using the check matrix H, which is the aggregate matrix of submatrices A and B at the LDPC coding rate of 1016/1224 obtained by the above process. Note that in the case of a coding rate of 1016/1224, since the information bit length is 1016 bits, the parity calculation based on the LDGM structure is applied in the parity check equation.

The check matrix initial value table for the check matrix used in the LDPC coding can be transmitted as auxiliary information from the transmitting device 1 to the receiving device 2, or can be held in advance by the receiving device 2. Alternatively, the check matrix itself can be transmitted from the transmitting device 1 to the receiving device 2, or can be held in advance by the receiving device 2.

Next, we will explain the processing steps of the decoder (LDPC decoding unit 24) in this embodiment.

(Decoder process for LDPC coding rates of 144/1224 and 1016/1224)
The decoder (LDPC decoding unit 24) of this embodiment performs LDPC code decoding processing by using the check matrix H shown in Fig. 4(a) for decoding coded data (L0ch transmission data) with an LDPC coding rate of 144/1224, and by using the check matrix H shown in Fig. 4(b) for decoding coded data (L1ch transmission data) with an LDPC coding rate of 1016/1224. The modulation method of each carrier of L0ch and L1ch of these coded data is transmitted by DBPSK.

The decoder (LDPC decoder 24) of this embodiment first calculates a log-likelihood ratio λ _n (n=1 to 1224) based on the transmitted symbol x _n and the received symbol y _n . The log-likelihood ratio λ _n is the natural logarithm of the ratio of the likelihood of sending bits 0 and 1, and is expressed by equation (4) using the transmitted symbol x _n and the received symbol y _n .

λ _n = ln {P(y _n |x _n =0)/P(y _n |x _n =1)} (4)

The log-likelihood ratio obtained by formula (4) and the check matrix H (corresponding to Figures 4(a) and (b)) corresponding to each of the above-mentioned coding rates are used to perform LDPC decoding using sum-product decoding or the like. The number of iterative decoding can be any value. In addition to sum-product decoding, various methods have been proposed for LDPC decoding, such as min-sum decoding, and various methods for maximizing the likelihood ratio using a check matrix can be applied to the LDPC decoding of the present invention.

Figures 11(a) and (b) show the C/N vs. BER (Bit Error Rate) and FER (Frame Error Rate) characteristics (computer simulation) when DBPSK modulation is applied to L0ch transmission data and L1ch transmission data according to the present invention. Note that BER indicates the bit error rate, and FER indicates the frame error rate, with one error correction block being a frame. For the L0ch transmission data shown in Figure 11(a), the required C/N to satisfy BER = 1.0E-7 is approximately -1.6 dB, and for the L1ch transmission data shown in Figure 11(b), the required C/N to satisfy BER = 1.0E-7 is approximately 5.7 dB. On the other hand, for AC transmission data in the conventional terrestrial digital broadcasting system ISDB-T, the required C/N ratio to satisfy BER = 1.0E-7 is too large to be shown in Figure 11, at approximately 10 dB or more, so it was confirmed that the transmission performance of the L0ch transmission data and L1ch transmission data of the present invention both have enhanced resistance to noise.

In addition, in the next generation terrestrial digital broadcasting system, the code length of the LDPC code used for the data carrier forming the main signal is being considered to be 69120 bits (high quality transmission) or 17280 bits (simple transmission), but since the code length of the L0ch transmission data and L1ch transmission data of the present invention is 1224 bits, it is understood that extremely low delay transmission for the main signal is realized. Also, a significantly lower delay is realized compared to the current terrestrial digital broadcasting system ISDB-T. For example, the current terrestrial digital broadcasting system ISDB-T has a transmission delay of about 230 ms, but it has been confirmed that the transmission delay time of the L0ch transmission data of the present invention at BER = 1.0E-7 is about 25 ms after improving the S/N ratio compared to ISDB-T, and even if 4 carriers are combined to further improve the S/N ratio, it will be about 100 ms, so a significantly lower delay and lower noise is realized.

With respect to the above-described embodiment, the encoder 10 and the decoder (LDPC decoding unit 24), as well as the transmitter 1 and the receiver 2, can each be configured with one or more chips.

In addition, with respect to the above-mentioned embodiment, a computer that functions as the encoder 10 and the decoder (LDPC decoding unit 24), as well as the transmitter 1 and the receiver 2, can be configured, and a program for making each of the means of the encoder 10 and the decoder (LDPC decoding unit 24), as well as the transmitter 1 and the receiver 2 function can be suitably used. Specifically, a control unit for controlling each of the means can be configured with a central processing unit (CPU) in a computer, and a storage unit for appropriately storing a program required for operating each of the means can be configured with at least one memory. That is, the function of each of the above-mentioned means can be realized by having the CPU execute the program on such a computer. Furthermore, a program for realizing the function of each of the means can be stored in a predetermined area of the above-mentioned storage unit (memory). Such a storage unit can be configured with a RAM or ROM inside the device, or can be configured with an external storage device (for example, a hard disk). Also, such a program can be configured as part of the software on the OS used by the computer (stored in the ROM or an external storage device). Furthermore, the program for causing such a computer to function as each of the means can be recorded on a computer-readable recording medium. Also, each of the above-mentioned means can be configured as part of hardware or software, and can be realized by combining each of them.

The above-mentioned embodiments have been described as representative examples, but it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. For example, in addition to BCH coding, other error correction coding to be combined with LDPC coding may be block coding such as Reed-Solomon coding, or convolutional coding, or other LDPC coding may be combined. Therefore, the present invention should not be construed as being limited by the above-mentioned embodiments, but is limited only by the scope of the claims.

The encoder and decoder, as well as the transmitter and receiver, of the present invention are useful in OFDM transmission systems that require low-latency transmission.

REFERENCE SIGNS LIST 1 transmitter 10 encoder 11 first LDPC encoder 11a parity interleaving unit 12 second LDPC encoder 13 DBPSK modulator 16 OFDM modulator 21 OFDM demodulator 22 LLch carrier extractor 23 DBPSK demodulator 24 LDPC decoder (decoder)
REFERENCE SIGNS LIST 100 Conventional transmitting device 101 Difference set cyclic encoding unit 102 DBPSK modulation unit 103 OFDM modulation unit 200 Conventional receiving device 201 OFDM demodulation unit 202 AC carrier extraction unit 203 DBPSK demodulation unit 204 Difference set cyclic code decoding unit

Claims (13)

An encoder that performs error correction encoding processing on transmission data of a low-delay transmission channel in a terrestrial digital broadcasting system,
a first LDPC encoding means for performing a first LDPC encoding process on data to be transmitted using a first segment area, which is a central partial reception band, among a predetermined number of segments assigned to the low latency transmission channel, by using a parity check matrix of a first LDPC coding rate;
and a second LDPC encoding means for performing a second LDPC encoding process on data to be transmitted using a second segment area that is a non-partial reception band other than the partial reception band among a predetermined number of segments assigned to the low latency transmission channel, using a parity check matrix of a second LDPC coding rate,
The encoder according to claim 1, wherein the first LDPC encoding process and the second LDPC encoding process have the same code length. The encoder of claim 1, characterized in that the first LDPC coding rate is set to a lower coding rate than the second LDPC coding rate. The encoder according to claim 1 or 2, characterized in that the code length is 1224 bits. The encoder according to any one of claims 1 to 3, characterized in that the first LDPC coding rate is greater than or equal to 0.1 and less than 0.2, and the second LDPC coding rate is greater than or equal to 0.8 and less than 1.0. The encoder according to any one of claims 1 to 4, characterized in that the first LDPC coding rate is configured as 144/1224 and the second LDPC coding rate is configured as 1016/1224. the first LDPC encoding means is configured to perform the first LDPC encoding process using a check matrix having a code length of 1224 bits and an initial value set to a check matrix initial value table that is predetermined according to the first LDPC coding rate;
6. The encoder according to claim 1, wherein the check matrix includes a first submatrix in which one element of a submatrix corresponding to an information length according to the first LDPC coding rate is arranged in the column direction periodically at a first cycle number, a second submatrix in which one element is arranged in the column direction periodically at a second cycle number different from the first cycle number, and a third submatrix obtained by performing parity interleaving by shifting in the row direction for each of the first cycle number and arranging one element in the column direction periodically at the second cycle number. the second LDPC encoding means is configured to perform the second LDPC encoding process using a check matrix having a code length of 1224 bits and an initial value set to a check matrix initial value table that is predetermined according to the second LDPC coding rate;
7. The encoder according to claim 1, wherein the check matrix includes a submatrix in which one element of a submatrix corresponding to an information length according to the second LDPC coding rate is arranged in a column direction periodically at a third cycle number. The check matrix initial value table for the coding rate of 144/1224 indicating initial values when the first submatrix is submatrix A, the second submatrix is submatrix C, and the third submatrix is submatrix D is given as follows:

7. An encoder as claimed in claim 6, comprising: The check matrix initial value table for the coding rate of 1016/1224 indicating the initial values of the submatrices is

8. An encoder as claimed in claim 7, comprising: A decoder comprising: means for LDPC decoding data encoded by the encoder according to any one of claims 1 to 9 using a check matrix of the first LDPC coding rate; and means for LDPC decoding data encoded by the encoder using the second LDPC coding rate using a check matrix of the second LDPC coding rate. A transmitting device comprising an encoder according to any one of claims 1 to 9. A receiving device comprising the decoder according to claim 10. A chip comprising any one of the encoder according to any one of claims 1 to 9, the decoder according to claim 10, the transmitter according to claim 11, and the receiver according to claim 12.