JP7123271B2 - Hermetically sealed semiconductor device - Google Patents

Description

The present application relates to a hermetically sealed semiconductor device.

2. Description of the Related Art As a power semiconductor device, there is a hermetically sealed semiconductor device in which a semiconductor chip is housed in an airtight container. Many of these hermetically sealed semiconductor devices have a pressure contact structure for conducting electricity to the semiconductor chip. In a semiconductor device having a pressure contact structure, a pressure contact member is pressed against an electrode pad of a semiconductor chip, so that the surface of the electrode pad may be scraped to generate metallic foreign matter. When this metallic foreign matter reaches the end portion of the semiconductor chip, which is responsible for electrical insulation, it causes insulation failure.

As a conventional semiconductor device, a structure is disclosed in which the end portion of a semiconductor chip is covered with an insulating material (see, for example, Patent Document 1). In a semiconductor device having such a structure, since the end portion of the semiconductor chip is covered with an insulating material, it is possible to avoid insulation failure caused by metallic foreign matter.

Japanese translation of PCT publication No. 2017-103279

However, in a hermetically sealed semiconductor device, if the end portion of the semiconductor chip is covered with an insulating material, dielectric loss occurs in signals transmitted through the end portion of the semiconductor chip, and stray capacitance is generated due to the insulating material. occur. As a result, the electrical characteristics of the hermetically sealed semiconductor device fluctuate. Therefore, in a hermetically sealed semiconductor device having a pressure contact structure, the conventional technology cannot realize a semiconductor device in which insulation failure caused by metallic foreign matter can be avoided and electrical characteristics do not vary.

The present application has been made to solve the above-described problems, and is a hermetically sealed semiconductor device having a pressure contact structure, in which insulation failure caused by metallic foreign matter can be avoided and electrical characteristics are stabilized. It is intended to

The airtightly sealed semiconductor device of the present application includes a cylindrical frame, a cover plate that closes one opening of the frame, a base plate that closes the other opening of the frame, and a cover plate for the base plate. a semiconductor chip arranged on a surface opposite to the semiconductor chip; ing. The current-carrying member includes a conductive cover member that covers the outer circumference of the contact surface with the electrode pad.

In the airtightly sealed semiconductor device of the present application, since the current-carrying member includes the conductive covering member covering the outer periphery of the contact surface with the electrode pad, it is possible to avoid insulation failure caused by metallic foreign matter and prevent electrical damage. Characteristics can be stabilized.

1 is a schematic cross-sectional view of a hermetically sealed semiconductor device according to a first embodiment; FIG. 1 is a schematic plan view of a hermetically sealed semiconductor device according to a first embodiment; FIG. 4 is a side view of the current-carrying member of the first embodiment; FIG. 4 is a cross-sectional view of the current-carrying member of the first embodiment; FIG. FIG. 4 is an assembly drawing of the current-carrying member according to the first embodiment; 4 is a cross-sectional view of the current-carrying member of the first embodiment; FIG. 4 is a characteristic diagram showing electric field intensity distribution around the electrode pad in Embodiment 1. FIG. 4 is a characteristic diagram showing electric field intensity distribution around the electrode pad in Embodiment 1. FIG. FIG. 8 is a cross-sectional view of a current-carrying member according to Embodiment 2; FIG. 12 is a top view of a semiconductor chip according to a third embodiment; FIG. 12 is a top view of a semiconductor chip according to a third embodiment; FIG. 11 is a schematic cross-sectional view of a hermetically sealed semiconductor device according to a third embodiment; FIG. 11 is a side view of a current-carrying member according to Embodiment 3; FIG. 14 is a top view of a semiconductor chip of Embodiment 4; FIG. 11 is a cross-sectional view of a current-carrying member according to Embodiment 4; FIG. 11 is a perspective view of a current-carrying member according to a fourth embodiment; FIG. 11 is a cross-sectional view of a current-carrying member according to Embodiment 5; FIG. 12 is a cross-sectional view of a current-carrying member according to Embodiment 6;

Hereinafter, hermetically sealed semiconductor devices according to embodiments for carrying out the present application will be described in detail with reference to the drawings. In each figure, the same reference numerals denote the same or corresponding parts.

Embodiment 1.
FIG. 1 is a schematic cross-sectional view of the hermetically sealed semiconductor device according to the first embodiment. A hermetically sealed semiconductor device 1 of this embodiment includes a rectangular cylindrical frame 2 made of an insulating material, a plate-like cover plate 3 as a first main electrode, and a second main electrode. A plate-shaped base plate 4 is provided. The cover plate 3 is closely connected to one opening of the frame 2 , and the base plate 4 is closely connected to the other opening of the frame 2 . The inside of the container composed of the frame 2, the cover plate 3 and the base plate 4 is kept airtight, and an inert gas such as nitrogen gas is sealed in the container. Both the cover plate 3 and the base plate 4 are made of a metal material with low electric resistivity such as copper. The hermetically sealed semiconductor device 1 is incorporated inside, for example, a power conversion device.

A plurality of semiconductor chips 5 are provided on the surface of the base plate 4 facing the cover plate 3 . The semiconductor chip 5 is, for example, a switching element such as a diode element, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or an IGBT (Insulated Gate Bipolar Transistor). The semiconductor chip 5 has electrode pads 5a on its upper surface. A conductive member 6 is provided between the semiconductor chip 5 and the cover plate 3 . The conducting member 6 electrically connects the electrode pad 5 a and the cover plate 3 .

FIG. 2 is a schematic plan view of the hermetically sealed semiconductor device 1 of this embodiment. FIG. 2 is a schematic plan view of the airtightly sealed semiconductor device 1 viewed from the cover plate side, excluding the cover plate. FIG. 1 is a schematic cross-sectional view taken along line AA of FIG. In the airtightly sealed semiconductor device 1 of the present embodiment, nine semiconductor chips 5 are arranged vertically and horizontally. A conductive member 6 is arranged on each semiconductor chip 5 .

FIG. 3 is a side view of one conducting member in this embodiment. The conducting member 6 connects an upper pressing member 61 whose upper surface contacts the cover plate 3, a lower pressing member 62 whose lower surface contacts the electrode pad 5a, and side surfaces of the upper pressing member 61 and the lower pressing member 62. A plurality of connection plates 63 are provided. The connection plate 63 is fixed to the upper pressing member 61 and the lower pressing member 62 with screws 64 . Further, the conducting member 6 has a cover member 65 surrounding the lower pressure contact member 62 at the portion where the lower pressure contact member 62 contacts the electrode pad 5a. The upper pressing member 61 and the lower pressing member 62 are prismatic members made of metal. The connection plate 63 is a plate-like member of low resistivity such as copper. The cover member 65 is a thin plate-like member made of metal.

FIG. 4 is a cross-sectional view of the conducting member 6 of this embodiment. As shown in FIG. 4, the upper pressing member 61 and the lower pressing member 62 have a prismatic shape with a hollow central portion, and are structured to be fitted to each other. A spring member 66 is inserted into the hollow portion of the upper pressing member 61 . As the spring member 66, for example, a disc spring made of metal can be used. With such a structure, the conducting member 6 has elasticity in the vertical direction. The lower pressing member 62 has a projecting portion 62a at a portion that contacts the electrode pad 5a. The protruding portion 62a has a smaller outer diameter than the other portion of the lower pressing member 62. As shown in FIG. The covering member 65 surrounds the entire periphery of the protruding portion 62a and covers the outer periphery of the contact surface between the electrode pad 5a and the lower pressure contact member 62. As shown in FIG. Moreover, the cover member 65 covers up to the outer edge of the electrode pad 5a. As shown in FIG. 4, the cover member 65 is a thin plate-like member made of metal, and both ends thereof are bent inward. With such a structure, the covering member 65 has elasticity, and is fitted between the lower pressing member 62 and the electrode pad 5a surrounding the projecting portion 62a.

FIG. 5 is an assembly drawing of the current-carrying member of the present embodiment. As shown in FIG. 5, the spring member 66 is inserted into the hollow portion of the upper pressing member 61 and the upper pressing member 61 is inserted into the hollow portion of the lower pressing member 62 . Next, the connecting plate 63 connects the side surface of the upper pressing member 61 and the side surface of the lower pressing member 62 . Also, the covering member 65 is inserted from below the lower pressing member 62 . Finally, the connecting plate 63 is fixed to the upper pressing member 61 and the lower pressing member 62 with screws 64 . Thus, the current-carrying member 6 can be assembled. In addition, in FIG. 5, only the cover member 65 is shown in cross section for easy understanding.

As shown in FIG. 1, the current-carrying member 6 is sandwiched between the cover plate 3 and the base plate 4 and pressurized in the vertical direction when the hermetically sealed semiconductor device 1 is assembled. Since the conducting member 6 has a spring member 66 inside, it has elasticity in the vertical direction. Therefore, the conducting member 6 can press the lower pressing member 62 against the electrode pad 5a side by vertical pressure. As a result, the electrical connection between the conducting member 6 and the electrode pad 5a can be reliably maintained. Since the conducting member 6 is configured to expand and contract by the spring material 66 contained therein, the relative positions of the upper pressing member 61 and the lower pressing member 62 change by the amount of displacement of the spring material 66 . Therefore, as shown in FIG. 5, a bent portion 63a is formed so that the connection plate 63 is also deformed by the amount of displacement. Since the connecting plate 63 can also be vertically deformed by the bent portion 63a, the connecting plate 63 can always electrically connect the upper pressing member 61 and the lower pressing member 62 together.

In the present embodiment, the upper pressing member 61 and the lower pressing member 62 are made of prismatic members made of metal, but may be members of other shapes such as columnar or polygonal columnar shapes. Moreover, although the connection plate 63 is fixed to the upper pressing member 61 and the lower pressing member 62 with screws 64, it may be fixed by other methods such as soldering and welding. Further, the spring member 66 may be a spring such as a plate spring other than the metal disc spring.

FIG. 6 is an enlarged cross-sectional view of the lower pressure contact member portion of the current-carrying member of the present embodiment. Since the electrode pad 5a is pressed by the lower pressing member 62, the contact surface of the electrode pad 5a with the lower pressing member 62 may be scraped. At this time, the electrode pad 5a is scraped to generate metallic foreign matter. This metallic foreign object can move in the surrounding electric field. If the metal foreign matter moves to the end portion 5b of the semiconductor chip 5, it causes insulation failure. Here, the end portion of the semiconductor chip is a region surrounding electrode pads and the like on the surface of the semiconductor chip. The airtightly sealed semiconductor device of this embodiment includes a covering member 65 surrounding the outer circumference of the portion where the lower pressure contact member 62 and the electrode pad 5a are in contact with each other. The covering member 65 surrounds the entire periphery of the protruding portion 62a and covers the outer periphery of the contact surface between the electrode pad 5a and the lower pressure contact member 62. As shown in FIG. The covering member 65 can prevent the metal foreign matter from moving to the end portion 5b of the semiconductor chip 5 even if the contact surface between the electrode pad 5a and the lower press-contact member 62 is scraped and metallic foreign matter is generated.

The cover member 65 is made of a thin plate-shaped metal material, and both ends thereof are bent inward. With such a structure, the cover member 65 surrounds the projecting portion 62a and is fixed in a state of being fitted between the lower pressing member 62 and the electrode pad 5a. Note that the cover member 65 may be fixed to the lower pressing member 62 by another fixing method using screws, adhesive, solder, brazing, or the like.

The airtightly sealed semiconductor device configured in this manner includes a cover member surrounding the outer periphery of the portion where the conductive member and the electrode pad are in contact. Foreign matter can be prevented from moving to the end portion of the semiconductor chip. As a result, it is possible to avoid insulation failure caused by metallic foreign matter. In addition, since the end portion of the semiconductor chip is exposed to the insulating gas and is not covered with the insulating material, dielectric loss of signals and stray capacitance caused by the insulating material do not occur. As a result, electrical properties are stabilized.

Furthermore, in the airtightly sealed semiconductor device of the present embodiment, since the current-carrying member includes the covering member, an electric field relaxation effect for suppressing the occurrence of discharge can be obtained. The reason is explained below. 7 and 8 are characteristic diagrams showing the electric field intensity distribution around the electrode pads in this embodiment. FIG. 7 shows the electric field strength distribution without the covering member, and FIG. 8 shows the electric field strength distribution with the covering member. 7 and 8 are characteristic diagrams obtained by simulation. As simulation conditions, the thickness of the electrode pad 5a was 10 μm, the distance between the end of the electrode pad 5a and the cover member 65 was 0.1 mm, a voltage of 1 kV was applied to the semiconductor chip 5, and the electrode pad 5a was The potential and the potential of the cover member 65 are assumed to be the same. 7 and 8, dashed lines indicate equipotential surfaces, and hatching indicates electric field strength. The darker the hatching, the higher the electric field strength.

As shown in FIG. 7, in the absence of the covering member, the equipotential surfaces on the top of the electrode pads 5a extend laterally along the surfaces of the electrode pads 5a. On the other hand, as shown in FIG. 8, when the cover member is provided, the equipotential surface on the upper portion of the electrode pad 5a extends upward along the cover member 65. As shown in FIG. Therefore, when the covering member is provided, the density of the equipotential surfaces around the electrode pads 5a is lower than when the covering member is not provided. When a discharge occurs in the semiconductor chip 5, the electrode pad 5a becomes the starting point of the discharge. By providing the cover member, the density of the equipotential surfaces around the electrode pads 5a is reduced, so that the occurrence of discharge can be suppressed.

Embodiment 2.
FIG. 9 is an enlarged cross-sectional view of a lower pressure contact member portion of a current-carrying member in the airtightly sealed semiconductor device of the second embodiment. The conducting member of this embodiment includes a ring-shaped buffer member 67 between the cover member 65 and the electrode pad 5a. The elastic modulus of the cushioning member 67 is smaller than that of the covering member 65 . As the material of the buffer member 67, for example, a heat-resistant resin such as polyimide or silicone rubber can be used. As a method of attaching the buffer member 67, there is a method of sandwiching the buffer member 67 when the current-carrying member is pressed against the electrode pad 5a, a method of curing the liquid resin on the surface of the electrode pad 5a to form the buffer member, and a method of forming the buffer member by curing the liquid resin on the surface of the electrode pad 5a. may be cured on the surface of the covering member 65 to form the cushioning member.

In the airtightly sealed semiconductor device configured in this manner, the metallic cover member 65 does not come into direct contact with the electrode pads 5a, so the generation of metallic foreign matter can be suppressed. It should be noted that the electric field relaxation effect described in the first embodiment is lost if the buffer member 67 is too thick. Therefore, it is preferable that the thickness of the buffer member 67 is smaller than the distance between the end of the electrode pad 5a and the cover member 65 . Specifically, by setting the thickness of the buffer member 67 to 0.05 mm or less, an electric field relaxation effect can be obtained.

Embodiment 3.
When the semiconductor chip is a switching element such as a MOSFET or IGBT, the surface of the semiconductor chip may be provided with a gate electrode pad for control in addition to the electrode pad. By applying a control signal to this gate electrode pad, the current flowing through the semiconductor chip can be controlled. The hermetically sealed semiconductor device of the third embodiment is mounted with a semiconductor chip having a gate electrode pad.

10 and 11 are top views of the semiconductor chip of this embodiment. As shown in FIGS. 10 and 11, semiconductor chip 5 of the present embodiment includes gate electrode pad 5c on the same surface as electrode pad 5a. The gate electrode pad 5c is electrically insulated from the electrode pad 5a and is formed at the end of the semiconductor chip 5. As shown in FIG.

FIG. 12 is a schematic cross-sectional view of a hermetically sealed semiconductor device according to this embodiment. In the hermetically sealed semiconductor device 1 of the present embodiment, one semiconductor chip 5 has gate electrode pads 5c on the same surface as the electrode pads 5a. A conducting member 6 corresponding to a semiconductor chip 5 having a gate electrode pad 5c has a gate pin 7 for supplying power to the gate electrode pad 5c. One end of gate pin 7 is electrically connected to gate electrode pad 5c. The other end of gate pin 7 is electrically connected to gate wiring 8 . The gate wiring 8 is led to the outside of the airtightly sealed semiconductor device 1 from between the cover plate 3 and the frame 2 . Gate wiring 8 is electrically insulated from cover plate 3 . The gate wiring 8 transmits a control signal for controlling the current flowing through the semiconductor chip 5 to the gate electrode pad 5c.

FIG. 13 is a side view of one conducting member of this embodiment. A conducting member 6 shown in FIG. 13 is a conducting member corresponding to a semiconductor chip 5 having a gate electrode pad 5c. One connection plate 63 among the plurality of connection plates 63 has an arm portion 63b for fixing the gate pin 7 . The gate pin 7 is fixed to this arm portion 63b. The surface of the gate pin 7 is covered with an insulating member 7a, and the gate pin 7 is electrically insulated from the arm portion 63b of the connection plate 63. As shown in FIG. Both ends of gate pin 7 are spring pins 7b, which are electrically connected to gate electrode pad 5c and gate wiring. The cover member 65 is formed with a hole through which the gate pin 7 is passed, and the cover member 65 and the gate pin 7 are electrically insulated. In addition, in FIG. 13, only the cover member 65 is shown in cross section for easy understanding.

The airtightly-sealed semiconductor device configured in this way includes a covering member surrounding the outer periphery of the portion where the conducting member contacts the electrode pad and the portion where the gate pin contacts the gate electrode pad. It is possible to suppress migration of metallic foreign matter generated at the portion where the electrode pad contacts and the portion where the gate pin and the gate electrode pad contact to the end portion of the semiconductor chip. As a result, it is possible to avoid insulation failure caused by metallic foreign matter.

Embodiment 4.
FIG. 14 is a top view of the semiconductor chip of Embodiment 4. FIG. The semiconductor chip 5 of this embodiment has a gate electrode pad 5c on the same surface as the electrode pad 5a. The gate electrode pad 5c is electrically insulated from the electrode pad 5a and formed at the central position of the semiconductor chip 5. As shown in FIG.

FIG. 15 is a cross-sectional view of the current-carrying member of this embodiment. Moreover, FIG. 16 is a perspective view of the current-carrying member of this embodiment. In FIG. 16, the covering member 65 is omitted. As shown in FIGS. 15 and 16, the current-carrying member 6 of the present embodiment has a through-hole 68 for the gate pin 7 to pass through in the central portion. The gate pin 7 is arranged through the through hole 68 . The surface of the gate pin 7 is covered with an insulating member 7a, and both ends of the gate pin 7 are spring pins 7b. One end of gate pin 7 is electrically connected to gate electrode pad 5c. The other end of gate pin 7 is electrically connected to the gate wiring. Gate pin 7 is electrically insulated from conducting member 6 and cover member 65 .

The airtightly-sealed semiconductor device configured in this way includes a covering member surrounding the outer periphery of the portion where the conducting member contacts the electrode pad and the portion where the gate pin contacts the gate electrode pad. It is possible to suppress migration of metallic foreign matter generated at the portion where the electrode pad contacts and the portion where the gate pin and the gate electrode pad contact to the end portion of the semiconductor chip. As a result, it is possible to avoid insulation failure caused by metallic foreign matter.

Embodiment 5.
FIG. 17 is a cross-sectional view of a current-carrying member according to Embodiment 5. FIG. In the conductive member 6 of the present embodiment, the space between the cover member 65 and the projecting portion 62a of the lower pressing member 62 is filled with an elastic filler 69. As shown in FIG. The filler 69 has electrical insulation, and the material of the filler 69 is, for example, silicone rubber.

In the airtightly-sealed semiconductor device configured in this manner, the filler blocks movement of foreign metal particles generated at the portion where the current-carrying member and the electrode pad are in contact with each other, so that the foreign metal particles move to the end portion of the semiconductor chip. can be further suppressed. As a result, the effect of avoiding insulation failure caused by metallic foreign matter is improved.

In the present embodiment, the filling area of the filling material is the entire space between the cover member and the projecting portion of the lower pressing member, but it may be a part of the space.

In the airtightly sealed semiconductor device having the gate pin shown in the third and fourth embodiments, the space between the cover member and the lower pressing member may be filled with an elastic filler. In this case, the filler must have a through-hole for the gate pin to pass through.

Embodiment 6.
FIG. 18 is a cross-sectional view of a current-carrying member according to Embodiment 6. FIG. In the current-carrying member 6 of the present embodiment, the covering member 65 is made of a flexible conductive member. The covering member 65 made of this conductive material covers the entire periphery of the protruding portion 62a and further covers the entire periphery of the contact surface between the electrode pad 5a and the lower pressure contact member 62. As shown in FIG. Also, the cover member 65 covers up to the outer edge of the electrode pad 5a. The covering member 65 made of this conductive material can be formed around the projecting portion 62a of the lower pressing member 62 in advance when assembling the airtightly sealed semiconductor device.

In the airtightly-sealed semiconductor device constructed in this manner, the cover member 65 blocks the movement of metallic foreign matter generated at the portion where the current-carrying member and the electrode pad are in contact with each other. can be further suppressed. As a result, the effect of avoiding insulation failure caused by metallic foreign matter is improved.

Moreover, in the airtightly sealed semiconductor device having the gate pin shown in the third and fourth embodiments, the covering member made of the conductive member described in the present embodiment may be used. In this case, the conductive member needs a through hole through which the gate pin passes so that the conductive member does not short-circuit the electrode pad 5a and the gate electrode pad 5c.

Although this application describes various exemplary embodiments, the various features, aspects, and functions described in one or more embodiments may be limited to the application of particular embodiments. can be applied to the embodiments alone or in various combinations.
Therefore, countless modifications not illustrated are envisioned within the scope of the technology disclosed in the present application. For example, modification, addition or omission of at least one component, extraction of at least one component, and combination with components of other embodiments shall be included.

1 hermetically sealed semiconductor device, 2 frame, 3 cover plate, 4 base plate, 5 semiconductor chip, 5a electrode pad, 5b termination portion, 5c gate electrode pad, 6 conducting member, 7 gate pin, 7a insulating member, 7b spring pin , 8 gate wiring, 61 upper pressure contact member, 62 lower pressure contact member, 63 connection plate, 63a bent portion, 63b arm portion, 64 screw, 65 cover member, 66 spring member, 67 buffer member, 68 through hole, 69 filler.

Claims (7)

a cylindrical frame;
a cover plate that closes one opening of the frame;
a base plate that closes the other opening of the frame;
a semiconductor chip arranged on a surface of the base plate facing the cover plate;
The airtightly sealed semiconductor device includes a current-carrying member disposed in pressure contact with the electrode pad of the semiconductor chip and the cover plate and electrically connecting the electrode pad and the cover plate. hand,
The airtightly sealed semiconductor device, wherein the current-carrying member includes a conductive cover member covering the outer periphery of the contact surface with the electrode pad. 2. The hermetically sealed semiconductor device according to claim 1, wherein said cover member is made of a metal plate. 3. The hermetically sealed semiconductor device according to claim 1, further comprising a cushioning member having an elastic modulus smaller than that of said covering member, provided between said covering member and said electrode pad. 4. The hermetically sealed semiconductor device according to claim 1, wherein a space surrounded by said covering member is filled with an insulating filler. 2. The hermetically sealed semiconductor device according to claim 1, wherein said covering member is made of a flexible conductive member. 6. The hermetically sealed semiconductor device according to claim 1, wherein said cover member covers up to an outer edge of said electrode pad. The semiconductor chip has a gate electrode pad formed on the same surface as the electrode pad, and the current-carrying member has one end electrically connected to the gate electrode pad and the other end 7. The hermetically sealed type according to any one of claims 1 to 6, further comprising a gate pin electrically connected to the gate wiring, wherein the gate pin and the current-carrying member are electrically insulated. semiconductor device.

Images