JP7140482B2 - Switching power supply circuit and liquid crystal display device - Google Patents

Description

The present invention relates to a switching power supply circuit and a liquid crystal display device.

2. Description of the Related Art Conventionally, a switching power supply circuit having a pulse skip function is known. For example, in the switching power supply circuit described in Patent Document 1, even though the PWM signal with the minimum duty ratio is output from the PWM control unit, the error indicated by the error signal is large when the output voltage is higher than the target voltage. Control is executed to thin out the pulses of the PWM signal so that the number of pulses per unit time is reduced.

JP 2009-296763 A

However, when pulse skipping occurs, the switching frequency may be reduced to the audio frequency band. In such a case, noise may be generated from the components that make up the switching power supply circuit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a switching power supply circuit capable of preventing the generation of noise, and a liquid crystal display device having such a switching power supply circuit.

A switching power supply circuit of the present invention includes a capacitor charged by a DC power supply, a first switching element for switching charging from the DC power supply to the capacitor, and a second switching element for discharging electric charges accumulated in the capacitor. When the feedback voltage of the output voltage of the DC-DC converter and the DC-DC converter does not exceed the threshold voltage, the first switching element is operated based on the difference voltage between the feedback voltage and the reference voltage at regular intervals. A driver control unit that drives and skips the driving of the first switching element when the feedback voltage exceeds the threshold voltage, and turns on the second switching element while the first switching element is off. and a first discharge control unit.

Preferably, the driver control section turns on and off the first switching element in each period of the internal clock when the feedback voltage does not exceed the threshold voltage. The first discharge control section turns on and off the second switching element every cycle of the internal clock regardless of whether the feedback voltage exceeds the threshold voltage.

Preferably, the driver control section turns on the first switching element during any period when the internal clock is off when the feedback voltage does not exceed the threshold voltage. The first discharge control section turns on the second switching element while the internal clock is on.

Preferably, the first switching element is a PMOS transistor and the second switching element is an NMOS transistor.

Preferably, the DC-DC converter includes: a first switching element arranged between an input terminal for receiving an input voltage and a first node; a diode arranged between the first node and ground; and a second node to which the output terminal is connected, a choke coil disposed between the second node and the ground, and a capacitor disposed between the second node and the third node and a second switching element disposed between the third node and ground.

Preferably, the DC-DC converter further comprises a second NMOS transistor arranged between the third node and ground in parallel with the second switching element. The switching power supply circuit includes a second discharge control section that turns on the second NMOS transistor to discharge the capacitor when the shutdown signal is received.

Preferably, the first discharge control unit detects a switching frequency of the first switching element, and when the detected switching frequency is within a predetermined range and the first switching element is off, the second switching Turn on the device to discharge the charge on the capacitor.

A liquid crystal display device of the present invention includes a liquid crystal panel, a plurality of source drivers for driving data lines of the liquid crystal panel, a plurality of gate drivers for driving scanning lines of the liquid crystal panel, a timing controller, and a switching power supply circuit. . A voltage output from the output terminal of the switching power supply circuit is supplied to the timing controller.

According to the present invention, it is possible to prevent the occurrence of ringing.

It is a figure showing the structure of a liquid crystal display device. 3 is a diagram showing the configuration of a first voltage generator (voltage regulator) 300. FIG. 3 is a diagram showing a detailed configuration of error amplifier 12. FIG. 3 is a diagram showing the configuration of a current limiting circuit 13a of a reference example; FIG. FIG. 10 is a diagram showing the configuration of a current limiting circuit 13a according to a second embodiment; FIG. 4 is a diagram showing the configuration of a gate driver drive circuit 400 of a reference example; FIG. 4 is a diagram showing transitions of control signal FLK, voltage VX of node NX, and output voltage VGG in gate driver driving circuit 400 of the reference example; FIG. FIG. 13 is a diagram showing the configuration of a gate driver driving circuit 400 of a third embodiment; FIG. FIG. 10 is a diagram showing transitions of the control signal FLK, the voltage VX of the node NX, and the output voltage VGG of the gate driver drive circuit 400 of the third embodiment; 4 is a diagram showing characteristics of a Schmitt trigger circuit 29; FIG. 3 is a diagram showing the configuration of a switching power supply circuit 500 of a reference example; FIG. 3 is a diagram showing the configuration of a driver control unit 31; FIG. FIG. 13 is a diagram showing the configuration of a switching power supply circuit 500 according to a fourth embodiment; FIG. FIG. 4 is a diagram showing timings of a switching signal SW and an ON signal ON within one cycle during normal operation; FIG. 4 is a diagram showing timings of a switching signal SW and an ON signal ON during normal operation; FIG. 4 is a diagram showing timings of a switching signal SW and an ON signal ON under light load; FIG. 4 is a diagram showing timings of a switching signal SW and an ON signal ON when there is no load; FIG. 4 is a diagram showing timings of a switching signal SW and an ON signal ON during shutdown; FIG. 13 is a diagram showing the configuration of a third voltage generator 500 of a modification of the fourth embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First embodiment]
FIG. 1 is a diagram showing the configuration of a liquid crystal display device.

The liquid crystal display device includes a liquid crystal module 140 and a drive circuit 120 mounted on the drive substrate 100 . Liquid crystal module 140 includes liquid crystal panel 700 , source circuit 900 , and gate circuit 800 . The drive circuit 120 has a timing controller 600 and a power management IC 200 .

Liquid crystal panel 700 is, for example, an active matrix driven panel. The liquid crystal panel 700 includes a panel composed of a plurality of pixels filled with a liquid crystal material and a glass substrate placed on the back of the panel. On this glass substrate, a plurality of scanning lines (for example, G1 to G4) are arranged in the vertical direction and extend in the horizontal direction, and a plurality of data lines are arranged in the horizontal direction and extend in the vertical direction (for example, S1 to S4) are arranged. Pixels (for example, 2-a to 2-d) are provided in a matrix through TFTs (Thin Film Transistors) (for example, 1-a to 1-d) corresponding to intersections of scanning lines and data lines. It is

Gate circuit 800 comprises a plurality of gate drivers (eg, 0-1 to 90-4). Gate driver 90-i is connected to scanning line Gi.

The source circuit 900 includes a plurality of source drivers (91 to 91-4, for example) and a control circuit 92. FIG. The source driver 91-i is connected to the data line Si.

The power management IC 200 receives the input voltage VIN and operates to generate various voltages. The power management IC 200 includes a first voltage generator (voltage regulator circuit) 300 , a second voltage generator (gate driver drive circuit) 400 , and a third voltage generator (switching power supply circuit) 500 .

The first voltage generator 300 generates a gate driver driving voltage VGG and supplies it to the gate drivers 90-1 to 90-4.

The second voltage generator 400 generates an analog power supply voltage AVDD and supplies it to the source drivers 91-1 to 91-4.

The third voltage generator 500 generates a logic system power supply voltage VDD and supplies it to the timing controller 600 and the control circuit 92 .

The timing controller 600 operates by being supplied with the logic system power supply voltage VDD. Timing controller 600 controls vertical synchronization of gate drivers (eg 90-1 to 90-4) and source drivers (eg 91-1 to 91-4) based on commands and data input from a host device (not shown). horizontal synchronization control, etc.

Gate drivers 90-i (eg, i=1 to 4) are supplied with voltage VGG and operate based on the vertical synchronization signal. For example, gate driver 90-i receives voltage VGG. The gate driver 90-i uses the voltage VGG as a power supply voltage to generate a gate voltage GX and supply it to the scanning line Gi.

The source drivers 91-i (eg, i=1 to 4) are supplied with the analog system power supply voltage AVDD and operate based on the horizontal synchronizing signal. For example, the source driver 91-i drives the source amplifier using the analog power supply voltage AVDD, thereby corresponding to the gradation value (for example, 0 to 255 gradation) of the digital video signal input from the host device. A source voltage SSi is generated and supplied to the pixels of the liquid crystal panel 700 through the data line Si.

The control circuit 92 operates by being supplied with the logic system power supply voltage VDD. Control circuit 92 controls source drivers 91-i (eg, i=1 to 4).

[Second embodiment]
The second embodiment relates to the detailed configuration and operation of the first voltage generator (voltage regulator circuit) 300. FIG. Specifically, a voltage regulator with current limiting is described.

FIG. 2 is a diagram showing the configuration of the first voltage generator (voltage regulator) 300. As shown in FIG.
The first voltage generating section 300 includes a reference voltage generating section 11, an error amplifier 12, current limiting circuits 13a and 13b, a PMOS transistor M1, an NMOS transistor M2, and a feedback section 68.

The reference voltage generation unit 11 generates a reference voltage VREF from the input voltage VIN input to the input terminal A1 and outputs the reference voltage VREF to the error amplifier 12 .

PMOS transistor M1 is arranged between input terminal A1 and node ND1 connected to output terminal P1.

The feedback section 68 consists of a resistor R1 and a resistor R2. The voltage of node ND2 between resistors R1 and R2 is supplied to error amplifier 12 as feedback voltage VF. The feedback voltage VF is R1/(R1+R2) of the output voltage AVDD output from the output terminal P1. As a result, the magnitude of the output voltage AVDD and the magnitude of the feedback voltage VF are adjusted to the magnitude of the reference voltage VREF.

NMOS transistor M2 is arranged between node ND1 and ground GND. By turning on the NMOS transistor M2, the current input from the terminal P1 flows to the ground.

The error amplifier 12 controls on and off of the PMOS transistor M1 and the NMOS transistor M2.

The current limiting circuit 13a suppresses an increase in current flowing through the PMOS transistor M1. The current limiting circuit 13b suppresses an increase in current flowing through the NMOS transistor M2.

FIG. 3 is a diagram showing a detailed configuration of error amplifier 12. Referring to FIG.
The error amplifier 12 includes an input differential amplifier circuit 14 and an output differential amplifier circuit 15 .

The input differential amplifier circuit 14 includes resistors R61 and R62, NMOS transistors N61 and N62, and a constant current source IS1.

Resistor R61 is arranged between terminal A1 receiving input voltage VIN and node ND2. Resistor R62 is arranged between terminal A1 receiving input voltage VIN and node ND3.

NMOS transistor N61 is arranged between node ND2 and node ND61. The gate of NMOS transistor N61 receives feedback voltage FB. NMOS transistor N62 is arranged between node ND3 and node ND61. The gate of NMOS transistor N62 receives reference voltage VREF. Constant current source IS1 is arranged between node ND61 and ground GND.

The output differential amplifier circuit 15 includes PMOS transistors P61, P62, P63 and NMOS transistors N63, N65, N66.

PMOS transistor P61 is arranged between node ND2 and node ND9. The gate of PMOS transistor P61 receives voltage BIAS.

PMOS transistor P62 is arranged between node ND3 and node ND4. The gate of PMOS transistor P62 receives voltage BIAS.

PMOS transistor P63 is arranged between node ND4 and node ND565. The gate of PMOS transistor P63 receives voltage BIAS2.

PMOS transistor P64 is arranged between node ND4 and node ND565. The gate of PMOS transistor P64 receives voltage BIAS3.

NMOS transistor N65 is arranged between node ND9 and ground GND. NMOS transistor N66 is arranged between node ND65 and ground GND. The gate and drain of NMOS transistor N65 and the gate of NMOS transistor N66 are connected.

Node ND4 is connected to the gate of PMOS transistor M1, and node ND65 is connected to the gate of PMOS transistor M2.

(Reference example current limiting circuit)
FIG. 4 is a diagram showing the configuration of the current limiting circuit 13a of the reference example.

The current limiting circuit 13a of the reference example includes a PMOS transistor M3, a resistor RA, and a PNP transistor Q.

Resistor RA is arranged between input terminal A1 receiving input voltage VIN and node ND10. PMOS transistor M3 is arranged between node ND10 and node ND1. A gate of the PMOS transistor M1 and a gate of the PMOS transistor M3 are connected to the node ND4. PNP transistor Q1 is arranged between input terminal A1 receiving input voltage VIN and node ND4. The base of PNP transistor Q1 is connected to node ND10.

(Operation of the current limiting circuit in the reference example)
The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M3, and the drain of the PMOS transistor M1 is connected to the drain of the PMOS transistor M3. The current also increases. If the size of the PMOS transistor M3 is K times the size of the PMOS transistor M1, the current I2 flowing through the PMOS transistor M3 is expected to be K×I1 when the current flowing through the PMOS transistor M1 is I1.

Therefore, when I1 increases, the potential of node ND10 decreases. The base-emitter voltage of the PNP transistor Q1 increases, and the ON resistance of the PNP transistor Q1 decreases. As a result, a decrease in the voltage of the node ND4, which is the gate voltage of the PMOS transistor M1, is suppressed, thereby suppressing an increase in the current of the PMOS transistor M1.

(Problems with the current limiting circuit in the reference example)
Due to the current I2 flowing through the resistor RA, the source potential of the PMOS transistor M3 (the potential of the node ND10) becomes lower than the source potential of the PMOS transistor M1. As a result, the current I2 may deviate from K×I1, and the PMOS transistor M3 cannot properly monitor the current I1 flowing through the PMOS transistor M1. This is especially problematic when the resistance RA is large.

(Current limiting circuit of the second embodiment)
FIG. 5 is a diagram showing the configuration of the current limiting circuit 13a of the second embodiment.

The current limiting circuit 13a of the second embodiment includes a PMOS transistor M30, a PNP transistor Q2, a variable resistor RB, PMOS transistors M4 and M5, NMOS transistors M6 and M7, and a constant current source IS2.

The size of the PMOS transistor M30 is K1 times the size of the PMOS transistor M1. The size of the PMOS transistor M5 is K1 times the size of the PMOS transistor M5. The size of the NMOS transistor M7 is K2 times the size of the NMOS transistor M6.

PMOS transistor M30 is arranged between input terminal A1 receiving input voltage VIN and node ND11.

Resistor RB is arranged between input terminal A1 receiving input voltage VIN and node ND12.

PNP transistor Q2 is arranged between input terminal A1 receiving input voltage VIN and node ND4. The base of PNP transistor Q2 is connected to node ND12.

NMOS transistor M7 is arranged between node ND12 and ground GND.
A PMOS transistor M5 and an NMOS transistor M6 are connected in series between the node ND11 and the ground GND.

A PMOS transistor M4 and a constant current source IS2 are connected in series between the node ND1 and the ground GND.

The gate of the PMOS transistor M4 and the gate of the PMOS transistor M5 are connected, and the gate and drain of the PMOS transistor M4 are connected. The PMOS transistor M4 and the PMOS transistor M5 form a current mirror circuit CM1.

The current mirror circuit CM1 duplicates the current I1 flowing through the PMOS transistor M4, whereby the duplicated current I2 flows through the PMOS transistor M5. Current I2 is K1×I1.

The gate of the NMOS transistor M6 and the gate of the NMOS transistor M7 are connected, and the gate and drain of the NMOS transistor M6 are connected. The NMOS transistor M6 and the NMOS transistor M7 constitute a current mirror circuit CM2.

The current mirror circuit CM2 duplicates the current I2 flowing through the PMOS transistor M30, the PMOS transistor M4, and the NMOS transistor M6, whereby the duplicated current I3 flows through the PMOS transistor M7. Current I3 is K2*I2.

(Operation of Current Limiting Circuit of Second Embodiment)
The gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M3, and the source of the PMOS transistor M1 is connected to the source of the PMOS transistor M3. The current also increases. Since the size of the PMOS transistor M3 is K1 times the size of the PMOS transistor M1, the current I2 flowing through the PMOS transistor M30 is expected to be K1×I1 when the current flowing through the PMOS transistor M1 is I1.

Since the size of the PMOS transistor M7 is K2 times the size of the PMOS transistor M6, the current I3 flowing through the PMOS transistor M7 is K2×I2 (=K2×K1×I1) by the current mirror circuit CM2.

As current I1 increases, current I2 increases, and as current I2 increases, current I3 increases. As the current I3 increases, the potential of the node ND12 decreases. The base-emitter voltage of the PNP transistor Q2 increases, and the ON resistance of the PNP transistor Q2 decreases. As a result, a decrease in the voltage of the node ND4, which is the gate voltage of the PMOS transistor M1, is suppressed, thereby suppressing an increase in the current of the PMOS transistor M1.

In this embodiment, since the drain of the PMOS transistor M1 and the drain of the PMOS transistor M3 are not connected, the potential of the drain of the PMOS transistor M1 and the potential of the drain of the PMOS transistor M3 are not equal, and the current I2 It may not be K×I1. Due to the current mirror circuit CM1, the potential of the drain of the PMOS transistor M1 and the potential of the drain of the PMOS transistor M30 become the same, and the current I2=K1×I1 can be determined.

Also, by adjusting the resistance value of the variable resistor RB, the upper limit value of the current I1 flowing through the PMOS transistor M1 can be adjusted. The magnitudes of resistors R1 and R2 are adjustable by a signal from timing controller 600. FIG.

A resistor with a fixed resistance value may be used instead of the variable resistor RB.
Even without the current mirror circuit CM1, the current mirror circuit CM1 can be omitted if the difference between the drain potential of the PMOS transistor M1 and the drain potential of the PMOS transistor M3 is small and does not pose a problem.

As described above, according to the present embodiment, it is possible to correctly monitor the current flowing through the PMOS transistor M1 and limit the rush current flowing to the load.

[Third Embodiment]
This embodiment relates to the detailed configuration and operation of the second voltage generator 400 (gate driver driving circuit). Specifically, a gate driver control circuit having a gate shading function will be described.

(Gate driver drive circuit of reference example)
FIG. 6 is a diagram showing the configuration of a gate driver drive circuit 400 of a reference example.

The gate driver drive circuit 400 of the reference example includes a predriver PD, a PMOS transistor M11, and a capacitor CA.

Input terminal A2 receives control signal FLK, which has a steep rising portion and a steep falling portion and changes periodically. This control signal FLK is, for example, a signal generated by the timing controller 600 and synchronized with the vertical synchronization signal.

The predriver PD outputs a voltage VX to the node NDX in response to the control signal FLK in order to drive the PMOS transistor M11.

PMOS transistor M11 has node NDW connected to power supply terminal A3 that receives power supply voltage VCC generated by power management IC 200, and node NDZ connected to output terminal P2 connected to gate drivers 90-1 to 90-4. is placed between

The gate of PMOS transistor M11 is connected to node NDX and receives voltage VX. When the magnitude of the voltage VX decreases, the PMOS transistor M11 is turned on and the magnitude of the output voltage VGG at the node NDZ increases.

Capacitor CA is arranged between node NDX and node NDW.
FIG. 7 is a diagram showing transitions of control signal FLK, voltage VX of node NX, and output voltage VGG in gate driver driving circuit 400 of the reference example.

In FIG. 7, voltages VX and VGG when the drivability of predriver PD is high are indicated by solid lines, and voltages VX and VGG when drivability of predriver PD is low are indicated by broken lines.

First, the operation when the driving capability of the pre-driver PD is high will be described.
At time t0, when control signal FLK falls to a low level, predriver PD lowers voltage VX on node NDX. Since the pre-driver PD cannot drop the voltage VX abruptly, the voltage VX drops to the threshold voltage Vth of the PMOS transistor M11 with a slope of K1X.

At time t1, the voltage VX drops to the threshold voltage Vth of the PMOS transistor M11. At this timing, the PMOS transistor M11 is turned on, and the output voltage VGG starts to decrease.

After that, the voltage VX maintains the threshold voltage Vth for a certain period of time due to the action of the capacitor CA. During this time, the output voltage VGG decreases with a slope K1O.

At the timing of time t3, the voltage VX begins to drop again with a slope of K1X by the predriver PD. At this timing, the output voltage VGG reaches the minimum value.

At time t4, voltage VX reaches its minimum value.
As described above, the output voltage VGG decreases at a constant slope K1O after the time ΔT1 (=t1−t0) has elapsed from the timing of the fall of the control signal FLK.

The voltage VGG is supplied to gate drivers 90-1 to 90-4.
For example, gate driver 90-1 receives voltage VGG. The gate driver 90-i uses the voltage VGG as a power supply voltage to generate a gate voltage GX and supply it to the scanning line G-1. The outline of the gate voltage GX is the same as that of the voltage VGG.

Assume that the voltage supplied to the gate of the TFT1-a is Va at a certain time. Assume that voltages Vb, Vc, and Vd are applied to the gates of the TFTs 1-b, 1-c, and 1-d in an ideal state in which there is no parasitic capacitance on the scanning line G-1. Here, Vb=2*Va, Vc=3*Va, and Vd=4*Va. The distances between the gate driver 90-1 and the TFTs 1-a, 1-b, 1-c, and 1-d are D1, D2 (=2×D1), D3 (=3×D1), D4 (=4× D1).

It is assumed that the parasitic capacitance of the scanning line G-1 causes the voltages applied to TFT1-b, TFT1-c, and TFT1-d to be 1/2, 1/3, and 1/4 of the ideal state. As a result, the gates of the TFTs 1-a to 1-d receive the voltage of the same magnitude at a certain time and can be turned on. As a result, in the scanning line direction of the liquid crystal panel 700 , the timing at which the TFTs are turned on does not deviate.

As described above, unevenness in brightness can be prevented by generating the voltage VGG that decreases at a constant slope with the fall of the control signal FLK as a trigger. Therefore, the gate driver drive circuit 400 of the reference example also has a gate shading function.

However, since the output voltage VGG starts to decrease with a delay from the timing of the fall of the control signal FLK, the TFTs of the liquid crystal panel 700 are not turned on immediately after the fall of the control signal FLK, and the display of the liquid crystal panel 700 is not performed. will be late.

Next, the operation when the driving capability of the pre-driver PD is low will be described.
At time t0, when control signal FLK falls to a low level, predriver PD lowers voltage VX on node NDX. The pre-driver PD causes the voltage VX to drop to the threshold voltage Vth of the PMOS transistor M11 with a slope of K2X.

At time t2, the voltage VX drops to the threshold voltage Vth of the PMOS transistor M11. At this timing, the PMOS transistor M11 is turned on, and the output voltage VGG starts to decrease.

After that, the voltage VX maintains the threshold voltage Vth for a certain period of time due to the action of the capacitor CA. During this time, the output voltage VGG decreases with a slope of K2O.

At the timing of time t4, the pre-driver PD starts to decrease the voltage VX again with a slope of K2X. At this timing, the output voltage VGG reaches the minimum value.

At time t5, voltage VX reaches its minimum value.
As described above, the output voltage VGG decreases at a constant slope K2O after the time ΔT2 (=t2−t0) has elapsed from the falling timing of the control signal FLK.

By lowering the driving capability of the pre-driver PD, it is possible to generate the voltage VGG that decreases with a smaller slope, triggered by the fall of the control signal FLK. However, the time delay at which the output voltage VGG starts to decrease also increases. Therefore, when the driving capability of the pre-driver PD is lowered, the display delay of the liquid crystal panel 700 increases.

(Gate driver driving circuit of the third embodiment)
FIG. 8 is a diagram showing the configuration of the gate driver drive circuit 400 of the third embodiment.

The gate driver driving circuit 400 includes a predriver PD, a PMOS transistor M11, a capacitor CA, an NMOS transistor M13, and a control circuit 78.

Input terminal A2 receives a control signal FLK that has a steep rising portion and a steep falling portion and periodically changes, as in the reference example.

Pre-driver PD responds to control signal FLK and outputs voltage VX to node NDX in order to drive PMOS transistor M11, as in the reference example.

As in the reference example, the PMOS transistor M11 has a node NDW connected to the power supply terminal A3 receiving the power supply voltage VCC, and a node NDZ connected to the output terminal P2 connected to the gate drivers 90-1 to 90-4. is placed between

The gate of PMOS transistor M11 is connected to node NDX and receives voltage VX. When the magnitude of the voltage VX decreases, the PMOS transistor M11 is turned on and the magnitude of the output voltage VGG at the node NDZ increases.

Capacitor CA is arranged between node NDX and node NDW.
The NMOS transistor M13 is arranged between the node NDX and the ground GND. A control circuit 78 controls the gate of the NMOS transistor M13.

The control circuit 78 applies a high-level voltage to the gate of the NMOS transistor M13 to turn on the NMOS transistor M13 when the voltage of the node NDX is higher than the threshold voltage Vth that turns on the PMOS transistor M11. As a result, the voltage of the node NDX can be rapidly lowered. The control circuit 78 applies a low-level voltage to the gate of the NMOS transistor M13 to turn off the NMOS transistor M13 when the voltage of the node NDX drops to the threshold voltage Vrh that turns on the PMOS transistor M11. This completes control of the voltage of the node NDX via the NMOS transistor M13, and control of the voltage of the node NDX is performed by the predriver PD.

The control circuit 78 includes a NOR circuit NOR, a PMOS transistor M12, a resistor Rd, and a Schmitt trigger circuit 29.

NOR circuit NOR has an input terminal IN1 for receiving control signal FLK, an input terminal IN2 for receiving the output of Schmitt trigger circuit 29, and an output terminal OUT connected to NMOS transistor M13.

PMOS transistor M12 is arranged between node NDZ and node NDY. A gate of the PMOS transistor M12 is connected to the node NDX.

Resistance Rd is arranged between node NDY and ground GND.
Assume that the threshold voltage of the PMOS transistor M11 and the threshold voltage of the PMOS transistor M12 are both Vth.

Schmitt trigger circuit 29 receives voltage VA at node NDY and outputs voltage VB to input terminal IN2 of NOR circuit NOR.

FIG. 9 is a diagram showing transitions of the control signal FLK, the voltage VX of the node NX, and the output voltage VGG of the gate driver driving circuit 400 of the third embodiment.

At time t0, control signal FLK falls to low level. At this timing, the control signal FLK input to the NOR circuit NOR is at a low level, and the output of the Schmitt trigger circuit 29 is at a low level, so the output of the NOR circuit NOR is at a high level. Therefore, the NMOS transistor M13 is turned on, and the voltage VX of the node NDX rapidly drops to the threshold voltage Vth of the PMOS transistor M11. In this state, as in the reference example, the pre-driver PD also tries to gently lower the voltage VX of the node NDX, but the contribution of the NMOS transistor M13 is dominant. Also, at this timing, the PMOS transistor M11 is turned on, and the output voltage VGG starts to decrease.

When the voltage of the node NDX drops to the threshold voltage Vth, the PMOS transistor M12 is also turned on and the voltage of the node NDY rises. As a result, the output of the Schmitt trigger circuit 29 changes to high level, the output of the NOR circuit NOR changes to low level, and the NMOS transistor M13 is turned off.

Thereafter, voltage VX maintains threshold voltage Vth for a certain period of time due to the actions of predriver PD and capacitor CA. During this time, the output voltage VGG decreases with a slope of K3O.

At the timing of time t6, the pre-driver PD starts to decrease the voltage VX again with a slope of K3X. At this timing, the output voltage VGG reaches the minimum value.

In the present embodiment, the output voltage VGG decreases at a constant slope K3O without delay from the falling timing of the control signal FLK.

As in the reference example, the voltage VGG is supplied to gate drivers 90-1 to 90-4.
It is assumed that the parasitic capacitance of the scanning line G-1 causes the voltages applied to TFT1-b, TFT1-c, and TFT1-d to be 1/2, 1/3, and 1/4 of the ideal state. As a result, the gates of the TFTs 1-a to 1-d receive the same voltage at a certain time and are turned on. As a result, in the scanning line direction of the liquid crystal panel 700, the timing at which the TFTs are turned on does not deviate.

Furthermore, in the present embodiment, since the output voltage VGG starts decreasing without delay from the timing of the fall of the control signal FLK, the TFTs of the liquid crystal panel 700 are turned on immediately after the fall of the control signal FLK. The display on the liquid crystal panel 700 can be prevented from being delayed.

FIG. 10 is a diagram showing characteristics of the Schmitt trigger circuit 29. As shown in FIG.
When the voltage VA of the node NDY rises and exceeds the threshold value VH, the output voltage VB becomes high level. When the voltage VA of the node NDY decreases, the output voltage VB becomes low level when it becomes smaller than the threshold VL. As a result, it is possible to eliminate noise-induced fluctuations in the voltage VA of the node NDY, thereby preventing malfunction.

As described above, according to the present embodiment, by providing the NMOS transistor M13 and the control circuit 78, the gate driver applies a voltage that does not cause flickering on the liquid crystal panel and delay the display of the liquid crystal panel. It can be supplied to the drive circuit.

[Fourth embodiment]
The present embodiment relates to the detailed configuration and operation of the third voltage generator (switching power supply circuit) 500. FIG. Specifically, a switching power supply circuit having a function of preventing component noise will be described.

(Reference example switching power supply circuit)
FIG. 11 is a diagram showing the configuration of a switching power supply circuit 500 of a reference example.

A switching power supply circuit 500 of the reference example includes an asynchronous rectification DC-DC circuit 35 , a driver control section 31 and a discharge control section 32 .

The asynchronous rectification DC-DC circuit 35 includes a PMOS transistor M21 as a first switching element, a resistor RC, an NMOS transistor M22, a choke coil LA, a diode DA, and a smoothing capacitor CB.

PMOS transistor M21 is arranged between input terminal A4 receiving input voltage VIN and node NX. A gate of the PMOS transistor 21 is connected to the driver control section 31 . The gate of PMOS transistor M21 receives switching signal SW from driver control section 31 .

Choke coil LA is arranged between node NX and node NY connected to output terminal P3. The output terminal P3 is connected to the load LD. The load LD is specifically the timing controller 600 and the control circuit 92 .

Capacitor CB is arranged between node NY and ground GND.
Diode DA is arranged between node NX and ground GND. The anode of diode DA is connected to ground GND, and the cathode of diode DA is connected to node NX.

A resistor RC is arranged between the node NX and the node NZ.
The NMOS transistor M22 is arranged between the node NZ and the ground GND. A gate of the NMOS transistor M22 is connected to the discharge control section 32 . A gate of the NMOS transistor M22 receives a discharge signal DSC from the discharge control section 32 .

When the PMOS transistor M21, which is a switching element, is in the ON state, energy is stored in the choke coil LA by the current flowing from the input terminal A4 to the output terminal P3. When the PMOS transistor M21 changes from the ON state to the OFF state, the choke coil LA releases the stored energy, generates an electromotive force in a direction that hinders the current change, and causes an induced current to flow, thereby obtaining a DC current. . This DC current is smoothed by the capacitor CB and output to the output terminal P3.

When the power is turned off, the discharge control unit 32 receives the shutdown signal SDW and turns on the NMOS transistor M22 by setting the discharge signal DSC to high level. This discharges the charge stored in the capacitor CB. A large-sized NMOS transistor M22 is used because it draws current.

FIG. 12 is a diagram showing the configuration of the driver control section 31. As shown in FIG.
The driver control unit 31 includes voltage dividing resistors R11 and R12, a reference voltage generation unit 34, an overvoltage threshold control unit 38, an error amplifier 36, an overvoltage detector 37, and a PWM (Pulse Width Modulation) signal generation circuit 39. Prepare.

The voltage dividing resistor R11 and the voltage dividing resistor R10 divide the voltage VDD of the node NY to generate the feedback voltage VB.

Reference voltage generator 34 generates reference voltage VREF from input voltage VIN and outputs it to error amplifier 36 and overvoltage detector 37 .

The error amplifier 36 outputs an error voltage VEA obtained by amplifying the difference between the feedback voltage VB and the reference voltage VREF.

The overvoltage threshold controller 38 receives the reference voltage VREF and outputs a threshold voltage VREF2 that is higher than the reference voltage VREF by ΔV.

The overvoltage detector 37 outputs a low-level skip signal SK when the feedback voltage VB is equal to or less than the threshold voltage VREF2, and outputs a high-level skip signal SK when the feedback voltage VB exceeds the threshold voltage VREF2.

Normally, the feedback voltage VB does not exceed the threshold voltage VREF2, so the skip signal SK output from the overvoltage detector 37 is at low level.

The PWM signal generation circuit 39 drives the PMOS transistor M21, which is a switching element, at regular intervals when the skip signal SK is at low level. That is, the PWM signal generation circuit 39 maintains the ON time at the minimum ON time until the error voltage VEA reaches the set voltage TH from 0. When the error voltage VEA exceeds the set voltage TH, the PWM signal generation circuit 39 increases the ON time in direct proportion to the increase in the error voltage VEA. The PWM signal generation circuit 39 generates the switching signal SW based on the ON time. The PWM signal generation circuit 39 generates the switching signal SW with the minimum pulse width when the ON time is set to the minimum ON time. When the on-time exceeds the minimum on-time, the PWM signal generation circuit 39 increases the pulse width of the switching signal SW as the on-time increases.

The output voltage VDD rises during light load and no load. As the output voltage VDD rises, the feedback voltage VB also rises and exceeds the threshold voltage VREF2. As a result, the skip signal SK output from the overvoltage detector 37 becomes high level. The PWM signal generation circuit 39 skips the switching operation while the skip signal SK is at high level. That is, the pulse of the switching signal SW is skipped. As a result, it is possible to reduce the switching loss and prevent an increase in the output voltage VDD.

When the switching frequency of the PMOS transistor M21, which is the frequency of the switching signal SW, drops to the audible range (20 Hz to 20 KHz) as a result of pulse skipping under light load and no load, the components forming the switching power supply circuit 500 become audible. A ringing phenomenon occurs. The switching power supply circuit 500 of the reference example has such a problem of noise.

(Switching power supply circuit of the fourth embodiment)
FIG. 13 is a diagram showing the configuration of a switching power supply circuit 500 according to the fourth embodiment.

A switching power supply circuit 500 of the fourth embodiment includes an NMOS transistor M23 as a second switching element and a discharge control section 33 in addition to the components of the reference example.

The NNOS transistor M23 is arranged in parallel with the NMOS transistor M22 between the node NZ and the ground GND.

The discharge control unit 33 outputs an on-signal ON for turning on the NMOS transistor M23 while the PMOS transistor M21 is off. When the ON signal ON becomes high level and the NMOS transistor M23 is turned ON, the charge accumulated in the capacitor CB is discharged. This suppresses an increase in the output voltage VDD and prevents pulse skipping.

However, the size of the NMOS transistor M23 is smaller than the size of the NMOS transistor M22 so that only a small amount of current flows through the NMOS transistor M23.

FIG. 14 is a diagram showing the timings of the switching signal SW and the ON signal ON within one cycle during normal operation.

As shown in FIG. 14, the driver control unit 31 sets the switching signal SW to a low level in order to turn on the PMOS transistor M21, which is the first switching element, during any period during which the internal clock CLK of the cycle T is off. to activate.

The discharge control unit 33 activates the ON signal ON to a high level in order to turn ON the NMOS transistor M23, which is the second switching element, during the ON period of the internal clock CLK of period T.

FIG. 15 is a diagram showing timings of the switching signal SW and the ON signal ON during normal operation.

Normally, since the feedback voltage VB does not exceed the threshold voltage VREF2, pulse skipping does not occur. The driver control unit 31 changes the switching signal SW so that the PMOS transistor M21, which is the first switching element, is turned on and off for each period of the internal clock CLK.

The discharge control unit 33 changes the on-signal ON so that the NMOS transistor M23, which is the second switching element, is turned on and off for each period of the internal clock CLK.

FIG. 16 is a diagram showing the timings of the switching signal SW and the ON signal ON when the load is light.

When the load is light, the pulse width of the switching signal SW becomes smaller because the error voltage VEA becomes smaller. Further, when the load is light, the feedback voltage VB exceeds the threshold voltage VREF2, so pulse skipping occurs. As a result, the switching cycle becomes longer.

However, the charge accumulated in the capacitor CB is discharged by the NMOS transistor M23. This prevents the switching frequency of the PMOS transistor M21, which is the frequency of the switching signal SW, from dropping to the audible range (20 Hz to 20 KHz). can do.

FIG. 17 is a diagram showing timings of the switching signal SW and the ON signal ON when there is no load.

Even at no load, as in light load, the feedback voltage VB exceeds the threshold voltage VREF2, so pulse skipping occurs. However, even when there is no load, the pulse may not disappear completely due to the influence of current leakage components. In such a case, the switching period becomes longer as in the case of light load. However, even in such a case, the charge accumulated in the capacitor CB is discharged by the NMOS transistor M23, so that the components constituting the switching power supply circuit 500 can be prevented from generating noise.

FIG. 18 is a diagram showing timings of the switching signal SW and the ON signal ON at the time of shutdown.

The driver control section 31, the discharge control section 32, and the discharge control section 22 receive a shutdown signal SDW from the timing controller 600 when the power is turned off.

The driver control unit 31 terminates switching of the PMOS transistor M21 when the shutdown signal SDW is activated to a high level.

The discharge controller 33 terminates switching of the NMOS transistor M23 when the shutdown signal SDW is activated to a high level.

When the shutdown signal SDW is activated to high level, the discharge control section 32 activates the discharge signal DSC to the gate of the NMOS transistor M22 to high level. The NMOS transistor M22 is turned on when the discharge signal DSC is activated to a high level, and the charge accumulated in the capacitor CB is discharged through the NMOS transistor M22.

As described above, according to the present embodiment, the pulse skip function reduces the switching loss and prevents the switching frequency from decreasing to the audible frequency band. can be prevented from occurring.

[Modification 1 of the fourth embodiment]
In the fourth embodiment, the ON signal is activated every cycle regardless of the switching frequency of the PMOS transistor M21 to discharge the capacitor CB through the NMOS transistor M23, but this is not restrictive. do not have.

For example, the capacitor CB may be discharged through the NMOS transistor M23 only when the switching frequency of the PMOS transistor M21 drops to the audible frequency band.

The discharge control section 33 detects the switching frequency of the PMOS transistor M21. For example, the discharge controller 33 detects the switching frequency of the PMOS transistor M21 by monitoring pulse skipping by the driver controller 31 . When the detected switching frequency of the PMOS transistor M21 is within a predetermined range, the discharge control unit 33 switches the NMOS transistor, which is the second switching element, during the OFF period of the PMOS transistor M21, which is the first switching element. M23 is turned on to discharge the capacitor CB.

[Modification 2 of the fourth embodiment]
FIG. 19 is a diagram showing the configuration of the third voltage generator 500 of the modification of the fourth embodiment.

In the fourth embodiment, the switching power supply circuit includes the NMOS transistor M22 for discharging the capacitor CB during shutdown and the discharge control unit 32 for controlling the NMOS transistor M22, but the present invention is limited to this. not a thing

As shown in FIG. 19, the switching power supply circuit 500 may not include the NMOS transistor M22 and the discharge control section 32. FIG.

It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and range of equivalents of the scope of the claims.

1-a to 1-d TFT, 2-a to 2-d pixel, 11, 34 reference voltage generator, 12 differential amplifier, 13a, 13b current limiting circuit, 14 input differential amplifier circuit, 15 output difference Dynamic amplifier circuit, 29 Schmitt trigger circuit, 31 driver control unit, 32, 33 discharge control unit, 35, 45, 55 asynchronous rectification circuit, 36 error amplifier, 37 overvoltage detector, 38 voltage threshold control unit, 39 PWM signal generation circuit , 68 feedback part, 90-1 to 90-4 gate driver, 91-1 to 91-4 source driver, 78, 92 control circuit, 100 drive substrate, 120 drive circuit, 140 liquid crystal module, 200 power circuit IC, 300 third 1 voltage generator (voltage regulator circuit), 400 second voltage generator (gate driver drive circuit), 500 third voltage generator (switching power supply circuit), 600 timing controller, 700 liquid crystal panel, 800 gate circuit, 900 source circuit, DA diode, CM1, CM2 current mirror circuit, R1, R2, R10, R11, R61, R62, RA, RB, RC, Rd resistor, CA, CB capacitor, LD load, A1, A2, A3, A4 , P1, P2, P3 terminals, M1, M4, M5, M11, M12, M21, M3, P61, P62, P63 PMOS transistors, M2, M6, M7, M13, M22, M23, N61, N62, N63, N65, N66 NMOS transistor, IS1, IS2 constant current source, Q1, Q2 PNP transistor, PD pre-driver, NOR NOR circuit.

Claims (4)

A switching power supply circuit,
a DC-DC converter including a capacitor charged by a DC power supply, a first switching element switching charging from the DC power supply to the capacitor, and a second switching element discharging the charge accumulated in the capacitor; ,
When the feedback voltage of the output voltage of the DC-DC converter does not exceed the threshold voltage, the first switching element is driven based on the difference voltage between the feedback voltage and the reference voltage at regular intervals. a driver control unit that skips driving the first switching element when the feedback voltage exceeds the threshold voltage;
a first discharge control unit that turns on the second switching element while the first switching element is off;
The first discharge control unit detects a switching frequency of the first switching element, and controls the second discharge control unit when the detected switching frequency is within a predetermined range and when the first switching element is off. turning on the switching element of to discharge the capacitor ,
the first switching element is a PMOS transistor,
the second switching element is a first NMOS transistor;
The DC-DC converter is
the first switching element arranged between an input terminal that receives an input voltage and a first node;
a diode positioned between the first node and ground;
a choke coil arranged between the diode and a second node to which the output terminal is connected;
the capacitor positioned between the second node and ground;
a resistor disposed between the second node and the third node;
the second switching element arranged between the third node and ground;
a second NMOS transistor arranged between the third node and ground in parallel with the second switching element;
The switching power supply circuit
a second discharge controller that turns on the second NMOS transistor to discharge the capacitor when a shutdown signal is received;
The switching power supply circuit , wherein the size of the second NMOS transistor is larger than the size of the first NMOS transistor . The driver control unit turns on and off the first switching element for each period of an internal clock when the feedback voltage does not exceed the threshold voltage,
2. The first discharge control unit according to claim 1, wherein said first discharge control unit turns on and off said second switching element for each cycle of said internal clock regardless of whether said feedback voltage exceeds said threshold voltage. switching power supply circuit. The driver control unit turns on the first switching element during any period in which the internal clock is off when the feedback voltage does not exceed the threshold voltage,
3. The switching power supply circuit according to claim 2, wherein said first discharge control section turns on said second switching element while said internal clock is on. LCD panel and
a plurality of source drivers for driving the data lines of the liquid crystal panel;
a plurality of gate drivers for driving scanning lines of the liquid crystal panel;
a timing controller;
A switching power supply circuit according to claim 1,
A liquid crystal display device, wherein a voltage output from an output terminal of the switching power supply circuit is supplied to the timing controller.

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