JP7145607B2 - DMA TRANSFER DEVICE, DMA TRANSFER CONTROL METHOD, AND COMMUNICATION DEVICE - Google Patents

Description

The present invention relates to a DMA transfer device capable of performing checksum calculation.

TCP/IP and UDP/IP are the most widely used communication protocols for data communication on the Internet and intranets. TCP/IP is a communication protocol that defines order assurance of communication packets and retransmission control when packets are lost. On the other hand, UDP/IP is a communication protocol that does not prescribe the order guarantee of communication packets or recovery processing for loss. Note that TCP/IP indicates Transmission Control Protocol/Internet Protocol. Also, UDP/IP indicates User Datagram Protocol/Internet Protocol.

These communication protocols utilize checksums to verify the integrity of communication packets. A checksum is simply the sum of data strings calculated on the transmission side. The transmitting side attaches the checksum to the transmission data and transmits it, and the receiving side calculates the sum of the received data string, and determines an error if the sum does not match the attached checksum.

In each of the above communication protocols, an Internet checksum is used as a checksum, which is calculated using specific fields of the IP header and TCP/UDP header, and the payload. Internet checksum calculations in PCs (Personal Computers) and embedded devices are realized by software processing by CPUs (Central Processing Units) and hardware such as NICs (Network Interface Cards) and in-chip communication units.

Since the checksum calculation has a large processing load, there is a possibility that the communication speed will decrease if the checksum calculation is performed by an embedded device with a low CPU processing capability. Therefore, it has been proposed that an NPU (Network Processing Unit) dedicated to communication processing or a hardware computing unit computes the checksum. This reduces the processing load on the CPU and speeds up the arithmetic processing. Also, in a PC, a checksum has been calculated by hardware such as a NIC for the purpose of reducing the load on the CPU. For example, Patent Document 1 proposes a method of reducing the load on a processor in a system by calculating a checksum when transferring a network packet from a storage device to a packet buffer in a network adapter.

A technique has also been proposed that combines a checksum calculator and a DMA (Direct Memory Access) transfer device to calculate a checksum during DMA data transfer, thereby speeding up communication processing throughout the entire system inside the device. For example, Patent Literature 2 proposes a method of calculating two checksums when performing DMA transfer between a buffer storing datagrams from the application layer and a buffer of a communication unit. Here the two checksums are the IP header checksum and the UDP or TCP checksum.

JP-A-6-78024 JP 2006-303765 A

During DMA transfer of datagrams (payload) from the application layer, by calculating the sum of the payloads (payload sum), it is possible to calculate the Internet checksum using the payload sum, so that the communication speed can be increased. However, if the payload length is changed during DMA transfer, the payload sum cannot be used when computing the Internet checksum, resulting in a decrease in communication speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to prevent a decrease in communication speed when a checksum is calculated during DMA data transfer.

In order to achieve the above object, a DMA transfer device according to one aspect of the present invention has the following configuration. That is, provided in a communication device having at least one processor capable of executing a protocol stack and control hardware capable of performing concatenation processing for concatenating first data and second data from an application. A DMA (Direct Memory Access) transfer device,
first computing means for computing a first checksum for each of the first data and the second data when a transfer instruction is received from the processor executing the protocol stack ;
when a transfer command is received from the control hardware, a second checksum operation different from the first checksum calculation is performed on the first data and the second data on which the concatenation processing is performed, and a communication header; a second computing means for computing a checksum of 2;
transfer means for transferring checksum data obtained through calculation by the first calculation means or the second calculation means to a memory area corresponding to a transfer destination address;
has
When the processor determines that the first data and the second data need to be linked, the calculation by the second calculation means is performed by combining the first data and the It is characterized in that the control hardware transmits a transfer command for transferring the second data to the DMA transfer device.

It is possible to prevent a decrease in communication speed when calculating a checksum during DMA data transfer.

1 is a schematic configuration diagram of a communication device 100; FIG. An example of DMA transfer when the first checksum calculator 112 is used is shown. An example of DMA transfer when the second checksum calculator 113 is used is shown. 4 is a processing flowchart of the CPU 101 in the first embodiment; 4 is a processing flowchart of a DMA transfer unit 110 according to the first embodiment; FIG. 4 shows a sequence chart of each processing block when the payload length is not changed in the first embodiment; FIG. FIG. 4 shows a sequence chart of each processing block when the payload length is changed in the first embodiment; FIG. It is a processing flowchart of CPU101 in a 2nd embodiment. FIG. 10 is a sequence chart of each processing block when payload change is present in the second embodiment; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail based on an example of its embodiment with reference to the accompanying drawings. Note that the configurations shown in the following embodiments are merely examples, and the present invention is not limited to the illustrated configurations.

[First embodiment]
(Configuration of communication device 100)
FIG. 1 shows a schematic configuration diagram of a communication device 100 in the embodiment described below. The CPU 101 controls each functional block, each software, and each hardware included in the communication device 100 . In this embodiment, the CPU 101 controls two pieces of software, an application and a protocol stack. The application is software that operates when data of a captured image or moving image is uploaded to the Internet or a media server when a camera or a camcorder is assumed as the communication device 100 . A protocol stack is software that performs communication protocol processing such as TCP (UDP)/IP. Specifically, the protocol stack performs retransmission control in TCP (UDP)/IP communication, guarantees the order of packets, and checks consistency of communication packets using checksums. Also, the protocol stack generates a TCP (UDP) header and an IP header, which are communication headers for realizing these functions.

The memory 106 is a memory area used by applications. The memory 106 stores data such as moving images output from applications, for example. On the other hand, memory 107 is a memory area used by the protocol stack. The memory 107 is used, for example, as a temporary data copy area for the protocol stack to generate packets from moving image data, or as an area for generating communication headers. Note that although the memory 106 and the memory 107 are configured separately in FIG. 1, these memories may be configured by the same memory, and the areas used by each software may be managed by memory addresses.

Data used or output by an application is input/output to/from memory 106 via system bus 102 . Data exchange (data transfer/copy) between storage areas (memory 106, memory 107, internal memory 105 in sequencer 103, transmission buffer 109 in communication unit 108) is performed via system bus 102 by: It is executed by the CPU 101 or the DMA controller 111 in the DMA transfer unit 110 . Also, it is assumed that data is exchanged between each hardware block in the communication device 100 via the system bus 102 .

The DMA transfer section 110 is composed of a first checksum calculation section 112 , a second checksum calculation section 113 and a DMA controller 111 . The first checksum calculator 112 calculates the sum of datagrams (hereafter referred to as payload sum). Also, the second checksum calculator 113 calculates an Internet checksum. The amount of computation involved in computing the payload sum is less than the amount of computation involved in computing the Internet checksum. Specifically, the payload sum is the one's complement sum of each 16-bit word of the input datagram. The Internet checksum is the 1's complement of the 1's complement sum for each 16-bit word in RFC (Request for Comments) 791, RFC793, RFC2460 and RFC1071 defined by the Internet Engineering Task Force (IETF). More specifically, the Internet checksum in this embodiment is the inverse (16-bit one's complement ). Here, the pseudo-header contains the SRC (source) address, DST (destination) address, protocol number. (number), which can be constructed from the TCP length.

With such a configuration, the DMA transfer unit 110 can calculate the payload sum and Internet checksum during DMA transfer. Also, the DMA transfer unit 110 can simply operate as a DMA transfer device without performing checksum calculation.

The DMA transfer unit 110 selects either the first checksum calculation unit 112 or the second checksum calculation unit 113 based on the register values set by the CPU 101 or the sequencer 103 . Also, the DMA transfer unit 110 reads a descriptor from a memory area specified by the value of the register, and performs DMA transfer or DMA transfer involving checksum calculation based on the descriptor. In the following description, a register setting for DMA transfer is referred to as a transfer instruction, and a DMA transfer involving checksum calculation is referred to as an arithmetic transfer instruction. A memory area is designated as a register value set in the DMA transfer unit 110 . The DMA transfer unit 110 operates according to the descriptor stored in the specified memory area. A descriptor is information necessary for DMA transfer in the DMA transfer unit 110, and includes at least a transfer source address, a transfer destination address, and a data length. That is, the DMA transfer unit acquires information including the transfer source address and the transfer destination address based on the received operation transfer command or transfer command.

As will be described later, the sequencer 103 is control hardware capable of performing data concatenation or data division in response to receiving a request for substitution of an operation transfer instruction and a predetermined instruction. For example, the sequencer 103 divides the datagram into MSS (Maximum Segment Size) when it receives an instruction to divide the data together with a request to substitute the operation transfer instruction. Note that the MSS is the maximum data size when dividing a datagram output by an application into a size that can be transmitted on a communication protocol when packetizing the datagram for communication. Subsequently, header generation logic 104 within sequencer 103 generates a communication header for each piece of split/concatenated data. After generating a communication header for each piece of divided/concatenated data, the sequencer 103 generates a descriptor for DMA-transferring each piece of divided/concatenated data and the generated communication header to the transmission buffer 109 and forming a communication packet. The generated descriptor is stored in memory 106 . After storing the descriptor in memory 106 , sequencer 103 issues a transfer command to DMA transfer unit 110 .

A communication unit 108 communicates with an external device. Specifically, the communication unit 108 performs processing of a MAC (Media Access Control) layer and a PHY layer necessary for communication.

(DMA transfer operation when using the first checksum calculator 112)
FIG. 2 shows an example of DMA transfer when using the first checksum calculator 112 in this embodiment. Hereinafter, when the DMA transfer unit 110 DMA-transfers the datagram output by the application to the memory 106 to the memory 107 used by the protocol stack, the first checksum calculation unit 112 is used to calculate the payload sum. will be described.

In the CPU 101, after the application outputs the datagram 201 to the memory 106, the task is switched to the protocol stack. The protocol stack generates descriptors 202 for DMA transfer of datagrams 201 stored in memory 106 . If the datagram is smaller than the MSS, the protocol stack generates a descriptor 202 with a transfer length the same size as the datagram 201 and a descriptor with a transfer length of 2 bytes for the payload sum. The protocol stack stores the generated descriptor 202 in memory 106 .

On the other hand, if the datagram 201 is larger than the MSS, the protocol stack divides the datagram by MSS because it is necessary to calculate the payload sum for each MSS. Subsequently, the protocol stack generates, as descriptors 202, a plurality of descriptors whose transfer length is MSS, a descriptor whose transfer length is the data size remaining after division by MSS, and a descriptor for the payload sum of each divided data. The protocol stack stores the generated descriptor 202 in memory 106 .

Note that the protocol stack may generate the read descriptor 202 and the write descriptor 202 separately. For example, the protocol stack may generate a descriptor for the divided data as the descriptor 202 for reading. Also, the protocol stack may generate the descriptor for division and the descriptor for the payload sum as the write descriptor 202 . Here, the protocol stack may add the transfer lengths of the descriptor for divided data and the descriptor for payload sum as the descriptor 202 for writing, and combine them into one descriptor.

After generating the descriptor 202 , the protocol stack issues an operation transfer instruction to the DMA transfer unit 110 . That is, the protocol stack sets a value indicating the use of the first checksum calculation unit 112 and the memory area for storing the descriptor in the register of the DMA transfer unit 110 . The DMA transfer section 110 determines to use the first checksum calculation section 112 according to the value set in the register. Note that the DMA transfer unit 110 may decide to use the first checksum calculation unit 112 by a method other than determining the value set in the register. For example, the DMA transfer unit 110 detects that it is an operation transfer instruction from the protocol stack from the transaction ID on the system bus 102, the address of the register access source, etc., and uses the first checksum operation unit 112. may be determined. Also, the DMA transfer unit 110 may determine to use the first checksum calculation unit 112 from the combination of the transfer source address and the transfer destination address of the descriptor 202 .

In the DMA transfer unit 110 that receives an operation transfer command from the CPU 101 (protocol stack), the internal DMA controller 111 reads the descriptor 202 stored in the memory 106 from the value set in the register. Subsequently, the DMA controller 111 reads the divided data 203 of the transfer length written in the descriptor 202 from the memory 106 . The first checksum calculator 112 calculates the payload sum 204 of the read divided data. A payload sum 204 is added to the end of the divided data 203, and the DMA transfer unit 110 writes it to the memory 107 according to the descriptor 202. FIG.

The protocol stack then calculates the internet checksum from the payload sum 204 stored in memory 107 . The protocol stack then generates a communication header 205 containing an internet checksum corresponding to each piece of data 203 and stores it in memory 107 . Furthermore, the protocol stack generates descriptors for DMA transferring the divided data 203 and the communication header 205 from the memory 107 to the transmission buffer 109 . After generating the descriptor, the protocol stack issues a transfer command to the DMA transfer unit 110 . In response, the DMA transfer unit 110 transfers the divided data 203 and the communication header 205 to the transmission buffer 109 of the communication unit 108 .

The communication unit 108 transmits the communication packet 121 composed of the divided data 203 and the communication header 205 written in the transmission buffer 109 to the external device.

(DMA transfer operation when using the second checksum calculator 113)
FIG. 3 shows an example of DMA transfer when using the second checksum calculator 113 in this embodiment. Here, it is assumed that the protocol stack (CPU 101) determines to change the payload length after the datagram from the application is DMA-transferred from the memory 106 to the memory 107 with payload sum calculation. In this case, the payload sum cannot be used to calculate the Internet checksum. The case where the payload length is changed is, for example, the case where datagrams are concatenated or the case where the MSS is changed. In such a case, the operation of the DMA transfer unit 110 using the second checksum calculation unit 113 to calculate the Internet checksum will be described.

First, after the datagram from the application is DMA-transferred from the memory 106 to the memory 107, the protocol stack notifies the sequencer 103 of substitution of the operation transfer instruction when determining to change the payload length. The protocol stack notifies the sequencer 103 of instructions regarding data division/concatenation together with a request for substitution of the operation transfer instruction. For example, when the datagram from the application is smaller than the MSS, the protocol stack determines whether it can be concatenated with the next data. When judging that connection is possible, the protocol stack notifies the sequencer 103 of a data connection instruction together with a request for substitution of the operation transfer instruction. Also, when the MSS is changed from the time the datagram is transferred from the application, the protocol stack instructs the sequencer 103 to divide the data according to the new MSS as a proxy for the operation transfer instruction. Notify with request.

The sequencer 103 performs data concatenation or data division according to notification from the protocol stack. Subsequently, the sequencer 103 generates the communication header 120 in which the Internet checksum 303 field has not been calculated in the header generation logic 104 and stores it in the internal memory 105 . The sequencer 103 further generates a descriptor 301 for DMA-transferring the communication header 120, the payload 302 stored in the memory 107, and the Internet checksum 303 (generated by the second checksum calculation unit 113) to the transmission buffer. do. Here, the transfer destination address for the Internet checksum 303 refers to the checksum field in the communication header after DMA transfer, and is set so that the communication packet 121 is completed when the transfer to the transmission buffer 109 of the communication unit 108 is completed. .

After generating the descriptor 301 , the protocol stack issues an operation transfer instruction to the DMA transfer unit 110 . That is, the protocol stack sets a value indicating the use of the second checksum calculation unit 113 and the memory area for storing the descriptor 301 in the register of the DMA transfer unit 110 . The DMA transfer unit 110 determines to use the second checksum calculation unit 113 according to the value set in the register. Here, similarly to when the first checksum calculation unit 112 is used, the DMA transfer unit 110 detects that it is an operation transfer instruction from the sequencer 103 by means of the transaction ID on the system bus, the address of the register access source, and the like. Then, it may be determined to use the second checksum calculator 113 . Also, the DMA transfer unit 110 may determine to use the second checksum calculation unit 113 based on the combination of the transfer source address and the transfer destination address of the descriptor 301 .

The communication unit 108 transmits the communication header 120 including the Internet checksum 303 written in the transmission buffer 109 and the communication packet 121 composed of the payload 302 to the external device.

(Operation of CPU 101)
FIG. 4 shows a processing flowchart of the CPU 101 (protocol stack) in this embodiment. Here, a flowchart for switching the operation depending on whether or not to change the payload length after the datagram from the application is DMA-transferred from the memory 106 to the memory 107 with payload sum calculation will be described.

In S400, the protocol stack sends an operation transfer instruction to the DMA transfer unit 110 to transfer (copy) the datagram from the application from the memory 106 to the memory 107 used by the protocol stack with the payload sum operation. issue. At the time of datagram transfer, if the data size is greater than or equal to the MSS, the datagram is divided by MSS and DMA transferred. That is, the payload sum is calculated for each piece of divided data divided by MSS. If the data size is less than the MSS, the transfer is performed with the datagram size notified from the application.

In S401, the protocol stack waits for the completion of the operation transfer from the DMA transfer unit 110 in response to the operation transfer instruction issued in S400. For example, the protocol stack waits for an interrupt from DMA transfer section 110 . Note that the protocol stack may determine the completion of operation transfer by polling the registers of the DMA controller 111 .

In S402, the protocol stack compares the length of the datagram from the application with the MSS, and if the length of the datagram is less than or equal to the MSS, it determines whether it can be concatenated with the next datagram from the application. If the MSS is equal to or less than the MSS even after concatenation with the next datagram, the protocol stack determines that concatenation is possible (Yes in S402), and proceeds to the processing of S406. If the length of the datagram is equal to the MSS, or if the length of the datagram is less than the MSS but will be greater than the MSS when concatenated with the next datagram, the protocol stack determines that concatenation is not possible (S402 No), the process proceeds to S403.

In S403, the protocol stack determines whether or not there is a change in the MSS from before datagram transfer from the application due to a change in communication conditions. For example, the protocol stack determines whether there is an MSS change in TCP in the received SYN (synchronization) packet. If the MSS has been changed (Yes in S403), the process proceeds to S407, and if the MSS has not been changed (No in S403), the process proceeds to S404.

In S404, as described in FIG. 2, the protocol stack uses the payload sum calculated by the first checksum calculator 112 when transferring data from the memory 106 to refer to each field value on the communication header. to calculate the internet checksum. The protocol stack also writes back the checksum field of the communication header after computing the Internet checksum. At S<b>405 , the protocol stack issues a transfer command to the DMA transfer unit 110 . Subsequently, in S408, the protocol stack waits for a transfer completion notification from the DMA transfer unit 110 for the transfer command. Here, the protocol stack may detect transfer completion either by interrupt or polling.

On the other hand, if it is determined in S402 that the datagrams can be concatenated (Yes in S402), and if there is a change in the MSS (Yes in S403), the protocol stack uses the calculated Payload sum not available. In these cases, the protocol stack notifies the sequencer 103 of the proxy (S406, S407). That is, the protocol stack requests the sequencer 103 to act as a substitute for the operation transfer instruction, and uses the second checksum calculation unit 113 to calculate the Internet checksum. In S408 from S406 or S407, the protocol stack waits for the completion of the operation transfer from the DMA transfer unit 110 in response to the transfer operation instruction from the sequencer 103. FIG. Here, the protocol stack may detect the completion of operation transfer by interrupt or polling.

(Operation of DMA Transfer Unit 110)
FIG. 5 shows a processing flowchart of the DMA transfer unit 110 in this embodiment. FIG. 5 is a flowchart showing processing when the DMA transfer unit 110 receives an operation transfer command or a transfer command from the CPU 101 (protocol stack) or sequencer 103 .

In S500, the DMA transfer unit 110 determines whether the received instruction is an operation transfer instruction or a transfer instruction. For example, the DMA transfer unit 110 has a register that bypasses the first checksum calculation unit 112 and the second checksum calculation unit 113, and determines whether it is a transfer instruction or an arithmetic transfer instruction from the setting value set in the register. do. Here, the DMA transfer unit 110 may determine that a read descriptor and a write descriptor have transfer lengths different from each other by 2 bytes as an arithmetic transfer instruction, and that transfer lengths are the same as a transfer instruction. Further, the DMA transfer unit 110 may determine that the instruction is a transfer command when the operation size set for the first checksum operation unit 112 and the second checksum operation unit 113 is 0. .

In the case of a transfer command (No in S500), the DMA transfer unit 110 transfers data between each memory area (memory 106, memory 107, internal memory 105 in sequencer 103, transmission buffer 109 in communication unit 108) based on the descriptor. DMA transfer is performed (S501). On the other hand, in the case of the operation transfer instruction (Yes in S500), in S502, the DMA transfer unit 110 determines whether the operation transfer instruction is from the protocol stack or the sequencer 103 (that is, the operation transfer instruction issuer). to decide. The DMA transfer unit 110 determines the issuing source of the operation transfer instruction, for example, from a combination of the register setting value, the transaction ID on the system bus, the address of the register access source, the transfer source of the descriptor, and the transfer destination address. If the sequencer 103 is the source of the operation transfer instruction (No in S502), the DMA transfer unit 110 uses the second checksum calculation unit 113 to calculate the Internet checksum in S503. Subsequently, in S<b>504 , the DMA transfer unit 110 transfers the communication header, payload, and calculated Internet checksum to the transmission buffer 109 . On the other hand, if the protocol stack is the source of the operation transfer instruction (Yes in S502), the DMA transfer unit 110 uses the first checksum operation unit 112 to calculate the payload sum in S505. In subsequent S506, the DMA transfer unit 110 transfers the payload and payload sum to the memory 107 used by the protocol stack. In S507, the DMA transfer unit 110 notifies the transfer instruction or operation transfer instruction issuer of transfer completion or operation transfer completion.

(Sequence chart of each processing block (when payload length is not changed))
FIG. 6 shows a sequence chart of each processing block when the payload length is not changed. In S600, the protocol stack operating on the CPU 101 generates a descriptor for transferring data from the application. In S<b>601 , the descriptor generated by the CPU 101 is stored in the memory 106 . In S<b>602 , the protocol stack operating on the CPU 101 issues an operation transfer instruction to the DMA transfer unit 110 . In S603, the DMA transfer unit 110 receives the operation transfer instruction, and in subsequent S604, the descriptor is read from the memory 106. FIG. Next, the DMA transfer unit 110 analyzes the read descriptor and reads data from an address in the memory 106 that matches the transfer source address. Subsequently, the first checksum calculator 112 of the DMA transfer unit 110 calculates the payload sum using the read data. When the calculation of the payload sum is completed, in S605, the DMA transfer unit 110 writes the data and payload sum to the address in the memory 107 that matches the transfer destination address in the descriptor. When the data transfer is completed, in S606, the DMA transfer unit 110 notifies the CPU 101 of the completion of the computation data transfer for the computation transfer command.

At S607, the protocol stack confirms that the payload length does not change. That is, the protocol stack determines that the payload sum is available for computing the Internet checksum, and reads the payload sum from memory 107 at S607, S608. In S609, the protocol stack calculates the Internet checksum by referring to each field value on the communication header from the read payload sum. Subsequently, the protocol stack inserts the calculated Internet checksum into the checksum field of the communication header at S610 and writes the communication packet to memory 107 at S611. Further, the protocol stack generates a descriptor for transferring the communication packet to the transmission buffer 109 of the communication unit 108 and stores it in the memory 106 in S612. After generating the descriptor, the protocol stack issues a transfer command to the DMA transfer unit 110 in S614. The DMA transfer unit 110 having received the transfer command in S615 reads the descriptor from the memory 106 in S616. Subsequently, the DMA transfer unit 110 reads the communication packet from the memory 107 according to the descriptor in S617, and writes the communication packet to the transmission buffer 109 in the communication unit 108 in S618. Finally, in S619, the DMA transfer unit 110 notifies the CPU 101 (protocol stack) of transfer completion.

(Sequence chart of each processing block (when payload length is changed))
FIG. 7 shows a sequence chart of each processing block when the payload length is changed. The processing sequence of S700 to S706 is the same as that of S600 to S606 in FIG. 6, so the description is omitted. That is, in S700 to S706, the first checksum calculator 112 calculates the payload sum.

At S707, the protocol stack determines whether multiple datagrams from the application can be concatenated. If multiple datagrams can be concatenated, the protocol stack notifies the sequencer 103 of a data concatenation instruction in S708 together with a request for substitution of the operation transfer instruction. In step S<b>709 , the sequencer 103 receives the proxy computation notification including the data concatenation instruction, and generates a communication header in the internal memory 105 . Subsequently, in S710, the sequencer 103 generates a descriptor for DMA transfer while calculating an internet checksum from the generated communication header and the payload stored in the memory 107 in S705. In S<b>711 , the sequencer 103 stores the generated descriptor in the memory 106 .

In S<b>712 , the sequencer 103 issues an operation transfer instruction to the DMA transfer unit 110 . In S713, the DMA transfer unit 110 is instructed to start the checksum calculation, the address of the descriptor stored in the memory 106, and the DMA transfer by the calculation transfer instruction. The DMA transfer unit 110 accesses the memory 106 in S714, and reads the descriptor from the memory 106 in S715. In S715, the DMA transfer unit 110 starts DMA transfer according to the read descriptor. The DMA transfer unit 110 reads the communication header stored in the internal memory 105 of the sequencer 103 in S717, and reads the data stored in the memory 107 in S716. The DMA transfer unit 110 calculates an internet checksum from the read communication header and data.

In S718, the DMA transfer unit 110 writes the communication header, data (payload), and Internet checksum to the transmission buffer 109 in the communication unit 108 as a communication packet. At this time, the DMA transfer unit 110 may write the Internet checksum to the transmission buffer 109 after inserting it into the checksum field in the communication header. Alternatively, the DMA transfer unit 110 may overwrite the checksum field with the Internet checksum after the communication header is written on the transmission buffer 109 .

After the write processing in S718 is completed, the DMA transfer unit 110 notifies the sequencer 103 of the completion of operation transfer, and the sequencer 103 receives the notification in S719. Furthermore, the sequencer 103 notifies the CPU 101 of the completion of the substitution of the operation transfer instruction upon receiving the notification of the operation transfer completion. Finally, in S720, the CPU 101 receives notification of completion of substitution of the operation transfer instruction.

As described above, according to the present embodiment, even when the payload length is changed, the Internet checksum calculation can be performed by hardware, thereby preventing a decrease in communication speed during DMA transfer. It becomes possible.

[Second embodiment]
In the first embodiment, it was explained that the sequencer 103 performs Internet checksum calculation instead of the CPU 101 when the payload length is changed during protocol stack processing. In the second embodiment, a case will be described in which the payload length can be changed during retransmission of communication packets in addition to the case where the payload length is changed during protocol stack processing. Differences from the first embodiment will be described below.

(Operation of CPU 101)
FIG. 8 shows a processing flowchart of the CPU 101 (protocol stack) in this embodiment. At S800, the protocol stack determines whether or not there is a payload change when retransmitting a communication packet after transmitting the communication packet. When a payload change occurs, the part of the payload at the time of transmission was correctly received, and a resent packet (a communication packet containing part of the communication packet that was first sent) is generated from the middle of the payload at the time of transmission. is. In this case, since the payload changes, the payload sum calculated at the time of transmission is no longer available. Here, it is possible to confirm to what extent the retransmission was correctly received by analyzing the ACK number of the acknowledgment packet from the transmission destination.

In S800, if there is a change in the payload (Yes in S800), the process proceeds to S801. In S<b>801 , the protocol stack notifies the sequencer 103 of the substitution of the calculation transfer instruction, and causes the second checksum calculation unit 113 in the DMA transfer unit 110 to calculate the Internet checksum. On the other hand, if a communication packet including the same payload as that at the time of transmission is to be transmitted at the time of retransmission (No in S800), the payload sum can be used. to calculate In subsequent S405, the protocol stack issues a transfer command for DMA-transferring the communication packet to the transmission buffer 109. FIG.

(Sequence chart of each processing block (with payload change))
FIG. 9 shows a sequence chart of each processing block when there is a payload change. S900 is the communication packet transmission sequence shown in FIGS. 6 and 7 described in the first embodiment. After the communication sequence, in S901, the communication unit 108 receives an acknowledgment packet for the transmission packet. In S<b>902 , the protocol stack operating on the CPU 101 analyzes the acknowledgment packet received by the communication unit 108 . Then, the protocol stack detects that the communication partner has not correctly received the data included in the transmission packet from the middle, and determines to perform retransmission that causes a payload change. Subsequently, in S903, the protocol stack determines the data start position for retransmission from the ACK number of the acknowledgment packet. After determining the data start position for retransmission, in S904, the protocol stack requests the sequencer 103 to substitute the operation transfer instruction. At this time, the protocol stack notifies the sequencer 103 of the start position of the data that could not be correctly received by the communication partner. In S<b>905 , the sequencer 103 receives the proxy computation notification and generates a communication header in the internal memory 105 . Subsequently, in S906, the sequencer 103 calculates an internet checksum from the generated communication header and the payload stored in the memory 107, and generates a descriptor for DMA transfer. In S<b>907 , the sequencer 103 stores the generated descriptor in the memory 106 . Here, the address in the memory 106 that matches the data start position notified from the CPU 101 is described in the transfer source address in the descriptor. After storing the descriptor, the sequencer 103 issues an operation transfer instruction to the DMA transfer unit 110 in S908.

The DMA transfer unit 110 receives the operation transfer command in S908. The DMA transfer unit 110 accesses the memory 106 in S910, and reads the descriptor from the memory 106 in S911. DMA transfer unit 110 in S912. DMA transfer is started according to the read descriptor. The DMA transfer unit 110 reads the communication header stored in the internal memory 105 of the sequencer 103 in S912, and reads the payload into the memory 107 in S913. Here, the address at which reading of the payload specified by the descriptor is started is the start address of the data in the middle that could not be correctly received at the communication partner. The second checksum calculation unit 113 of the DMA transfer unit 110 calculates the Internet checksum from the read communication header and payload according to the register setting at the time of issuing the calculation transfer instruction.

In S913, the DMA transfer unit 110 writes the communication header, data (payload), and Internet checksum to the transmission buffer 109 in the communication unit 108 as a communication packet. After the write processing in S913 is completed, the DMA transfer unit 110 notifies the sequencer 103 of the completion of the operation transfer instruction, and the sequencer 103 receives the notification in S914. Furthermore, upon receiving the notification of the operation transfer instruction, the sequencer 103 notifies the CPU 101 of completion of the substitution of the operation transfer instruction. Finally, in S<b>915 , the CPU 101 receives notification of completion of substitution of the operation transfer instruction.

Thus, in this embodiment, when the payload is changed during retransmission, the DMA transfer unit 110 calculates the Internet checksum and generates a retransmission packet, thereby preventing a decrease in communication speed during DMA transfer. becomes possible. Instead of the DMA transfer unit 110, it is also possible to configure the protocol stack to calculate the Internet checksum and generate a retransmission packet.

[Third Embodiment]
In the description of the first embodiment, it is assumed that the payload sum is calculated when data is DMA-transferred from the memory 106 to the memory 107 . However, in the UDP protocol that does not involve retransmission, when the DMA transfer unit 110 performs DMA transfer from the memory 106 to the transmission buffer 109, the second checksum calculation unit 113 is used to calculate the Internet checksum, and the communication is performed. Packets may be generated. In addition, in the TCP protocol, if data for retransmission can be managed in the memory 106 by managing the memory area between the application and the protocol stack, a communication packet is configured without transferring (copying) to the memory 107. good too. Also, depending on the type of application that requires data transfer, a communication packet is generated in the transmission buffer 109 (first embodiment), or the communication packet is generated without copying the data to the memory 107 as described above. You can switch whether to generate or not.

[Other embodiments]
The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus reads and executes the program. It can also be realized by processing to It can also be implemented by a circuit (for example, ASIC) that implements one or more functions.

100 communication device, 101 CPU, 102 system bus, 103 sequencer, 104 header generation logic, 105 internal memory, 106 memory, 107 memory, 108 communication unit, 109 transmission buffer

Claims (11)

A DMA provided in a communication device having at least one processor capable of executing a protocol stack and control hardware capable of performing concatenation processing for concatenating first data and second data from an application. Direct Memory Access) transfer device,
first computing means for computing a first checksum for each of the first data and the second data when a transfer instruction is received from the processor executing the protocol stack ;
when a transfer command is received from the control hardware, a second checksum operation different from the first checksum calculation is performed on the first data and the second data on which the concatenation processing is performed, and a communication header; a second computing means for computing a checksum of 2;
transfer means for transferring checksum data obtained through calculation by the first calculation means or the second calculation means to a memory area corresponding to a transfer destination address;
has
When the processor determines that the first data and the second data need to be linked, the calculation by the second calculation means is performed by combining the first data and the A DMA transfer device, wherein the control hardware transmits a transfer command for transferring the second data to the DMA transfer device. In calculating the second checksum, if the processor determines that concatenation of the first data and the second data is unnecessary, the processor reads the first checksum from a memory, 2. The DMA transfer device according to claim 1, wherein the transfer is performed by said processor using said read first checksum. acquisition means for acquiring information including the transfer source address and the transfer destination address based on the received transfer command;
further comprising selection means for selecting the first calculation means or the second calculation means,
The first computing means performs the first checksum computation on data from a memory area corresponding to the transfer source address,
3. The DMA transfer according to claim 1, wherein said second computing means computes said second checksum for data from a memory area corresponding to said transfer source address. Device. 4. The DMA transfer apparatus according to claim 3, wherein said selection means selects said first arithmetic means or said second arithmetic means based on the issuer of said transfer instruction. 5. The DMA transfer device according to claim 3 , wherein the calculation of said first checksum has a smaller amount of calculation than the calculation of said second checksum. wherein the first checksum operation is a 1's complement sum for each 16-bit word and the second checksum operation is a 1's complement sum for the 1's complement sum for each 16-bit word 6. The DMA transfer device according to any one of claims 3 to 5 , wherein: A communication device comprising the DMA transfer device according to any one of claims 1 to 6 , the at least one processor, and the control hardware,
When the processor determines that concatenation of the first data and the second data is unnecessary , the processor issues the transfer instruction to the DMA transfer device, and the processor and said second data , said control hardware issues said transfer command to said DMA transfer device. A communication device comprising the DMA transfer device according to any one of claims 1 to 6 , the at least one processor, and the control hardware,
When the processor determines that the maximum data size that can be transmitted by packetizing the data from the application has not been changed, the processor issues the transfer command to the DMA transfer device, and the processor A communication device, wherein the control hardware issues the transfer command to the DMA transfer device when it is determined that the maximum data size has been changed. A communication device comprising the DMA transfer device according to any one of claims 1 to 6 , the at least one processor, and the control hardware,
After transmitting a communication packet in which data from the application is packetized,
If the processor determines to resend the communication packet, the processor issues the transfer instruction to the DMA transfer device; and if the processor determines to resend part of the communication packet, the control A communication device, wherein hardware issues the transfer command to the DMA transfer device. A communication device comprising the DMA transfer device according to any one of claims 1 to 6 , the at least one processor, and the control hardware,
When the transfer means needs to copy data from the application to a memory area corresponding to the transfer destination address, the processor issues the transfer instruction to the DMA transfer device, is absent, the control hardware issues the transfer command to the DMA transfer device. A DMA (DMA) provided in a communication device having at least one processor capable of executing a protocol stack and control hardware capable of performing concatenation processing for concatenating first data and second data from an application. Direct Memory Access) transfer device control method,
a first computing step of computing a first checksum for each of the first data and the second data when a transfer instruction is received from the processor executing the protocol stack ;
when a transfer command is received from the control hardware, a second checksum operation different from the first checksum calculation is performed on the first data and the second data on which the concatenation processing is performed, and a communication header; a second computing step of computing two checksums;
a transfer step of transferring the checksum data obtained through the calculation in the first calculation step or the second calculation step to a memory area corresponding to a transfer destination address;
has
When the processor determines that the first data and the second data need to be linked, the calculation by the second calculation step is performed by combining the first data and the A control method for a DMA transfer device, wherein the control hardware transmits a transfer command for transferring the second data to the DMA transfer device.

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