JP7192599B2 - Clock domain crossing circuit, method and program - Google Patents

Description

TECHNICAL FIELD The present disclosure relates to a clock domain crossing circuit, method and program, and more particularly to a clock domain crossing circuit, method and program capable of reducing circuit scale.

As one of the clock transfer methods, a circuit is known in which data is stored in a two-port RAM (Random Access Memory) to divide the time for write processing and read processing, thereby avoiding read data errors due to processing conflicts. In addition, as one method of rearranging a plurality of data in units of frames, a two-port RAM is used in a two-sided configuration, and the RAM accessed by the writing side and the RAM accessed by the reading side are separated. A circuit is known in which address control is performed independently without contention between writing and reading.

Patent Document 1 discloses a 2-port RAM in which a write address control unit that controls a write address to which input data is written, a blank address detection unit that detects a blank address in which input data is not written in the write address, and a 2-port RAM. In the RAM, a two-port RAM is disclosed that includes a read address conversion unit that converts write addresses other than blank addresses into read addresses from which output data is read.

JP 2012-238992 A

In the above-described clock domain switching circuit, for example, as shown in Patent Document 1, an address conversion section is required, and there is a problem that it is difficult to reduce the circuit scale.

An object of the present disclosure is to provide a clock domain crossing circuit, method, and program that solve the above-described problems.

A clock domain crossing circuit according to the present disclosure includes:
first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; a write control unit that alternately writes to the second memory and the fourth memory each time;
a read control unit that reads the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
an output switching unit that outputs the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
with
The reading speed for reading the predetermined number of bits is a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the number of column data.

A clock domain crossing circuit according to the present disclosure includes:
first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; a write control unit that alternately writes to the second memory and the fourth memory each time;
a read control unit that reads the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
an output switching unit that outputs the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
with
The reading speed for reading the predetermined number of bits is a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the ratio of the effective number of bits to the predetermined number of bits of all column data. is.

A method according to the present disclosure includes:
first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; alternately writing to the second memory and the fourth memory every
reading the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
outputting the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
setting the reading speed for reading the predetermined number of bits to a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the number of column data;
Prepare.

The program according to the present disclosure is
first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; alternately writing to the second memory and the fourth memory every
reading the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
outputting the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
setting the reading speed for reading the predetermined number of bits to a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the number of column data;
run on the computer.

According to the present disclosure, it is possible to provide a clock domain crossing circuit, method, and program capable of reducing circuit scale.

1 is a block diagram illustrating a clock domain switching circuit according to an embodiment; FIG. 1 is a block diagram illustrating a clock domain switching circuit according to an embodiment; FIG. 4 is a timing chart illustrating a write operation of the clock domain crossing circuit according to the embodiment; 4 is a timing chart illustrating the read operation of the clock domain switching circuit according to the embodiment; 9 is a timing chart illustrating phase adjustment processing of the clock transfer circuit according to the embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same or corresponding elements, and redundant description will be omitted as necessary for clarity of description.

[Embodiment]
First, the outline of the clock domain switching circuit according to the embodiment will be described.
FIG. 1 is a block diagram illustrating a clock domain crossing circuit according to an embodiment.

As shown in FIG. 1 , the clock transfer circuit 11 includes a storage section 111 , a write control section 112 , a read control section 113 and an output switching section 114 . The storage unit 111 has a first memory 1111 , a second memory 1112 , a third memory 1113 and a fourth memory 1114 .

The write control unit 112 alternately writes the first column data including a plurality of data in the first memory 1111 and the third memory 1113 every predetermined number of bits. In parallel with this, the write control unit 112 alternately writes the second column data containing a plurality of different data into the second memory 1112 and the fourth memory 1114 for every predetermined number of bits.

Specifically, the write control unit 112 writes data of the first predetermined number of bits of the first column data to the first memory 1111, and writes data of the next predetermined number of bits of the first column data to the third memory. Write to 1113. In parallel with this, the write control unit 112 writes the first predetermined number of bits of the second column data to the second memory 1112, and writes the next predetermined number of bits of data to the fourth column data. Write to memory 1114 .

A temporal width of data of a predetermined number of bits is called a frame. Therefore, the write control unit 112 alternately writes the first column data into the first memory 1111 and the third memory 1113 on a frame-by-frame basis.

The read control unit 113 reads a predetermined number of bits from each of the first memory 1111, second memory 1112, third memory 1113, and fourth memory 1114. FIG.

The output switching unit 114 outputs the data read by the read control unit 113 as output data in the order of the first memory 1111, the second memory 1112, the third memory 1113, and the fourth memory 1114. FIG. At this time, the read speed at which the read control unit 113 reads the predetermined number of bits is the speed obtained by multiplying the write speed at which the write control unit 112 writes the predetermined number of bits by the number of column data.

For example, if the write speed is 100 MHz, the read speed is 200 MHz.

Next, the details of the clock domain switching circuit according to the embodiment will be described.
FIG. 2 is a block diagram illustrating the clock domain crossing circuit according to the embodiment.

As shown in FIG. 2 , the clock transfer circuit 11 includes a pulse timing comparator 115 , a phase signal generator 116 , a phase signal detector 117 and a phase comparator 118 . A write enable generator 1121 and a write address counter 1122 are included in the write controller 112 . Also, read address counter 1131 is included in read control unit 113 .

The clock transfer circuit 11 uses the first memory 1111 to the fourth memory 1114 to transfer the column data input in two columns, that is, the first column data and the second column data, from the write clock to the read clock.

Note that each of the first memory 1111, the second memory 1112, the third memory 1113, and the fourth memory 1114 uses, for example, a 2-port RAM (Random Access Memory).

In addition, the clock transfer circuit 11 sets the initial phase within a range in which the addresses of the two-port RAM do not overlap during write processing and read processing during operation.

The write address counter 1122 generates a value twice as large as (the depth of the 2-port RAM) and outputs a signal excluding the most significant bit as a write address signal WA from the first memory 1111 to the fourth memory 1114. .

The write enable signals (WE1 to WE4) of the first memory 1111 and the second memory 1112 or the third memory 1113 and the fourth memory 1114 are switched by the signal of the most significant bit.

The write enable generator 1121 generates the write enable signal WE4 from the write enable signal WE1 of each memory based on the value of the write address counter 1122 .

The read address counter 1131 generates a value four times (the depth of the 2-port RAM) and connects the signal excluding the upper two bits to the first memory 1111 to the fourth memory 1114 as the read address signal RA.

The output switching unit 114 switches from the first path to the fourth path based on the value of the read address counter 1131 for output.

The pulse timing comparator 115 compares the phase of the input frame pulse and the phase of the write address counter 1122 and generates an initialization signal S1 for initializing the write address counter 1122 and the read address counter 1131 .

The value of the write address counter 1122 is output to the phase comparator 118 as phase signal information S2 after the synchronization clock is changed from the write clock to the read clock in the phase signal generator 116 and the phase signal detector 117. .

A phase comparator 118 monitors the phase relationship between the write address signal WA and the read address signal RA. The phase comparator 118 outputs an initialization signal S3 when the phase relationship exceeds the allowable range.

Next, the operation of the clock domain switching circuit according to the embodiment will be described.
In this example, two columns (first column data and second column data) of K pieces of multi-bit data are input in one frame, and the first column data and the second column data are input in one frame by clock switching. Explain to output. However, let K be a natural number. In this example, the write clock (write speed) will be 100 MHz and the read clock (read speed) will be 200 MHz.

FIG. 3 is a timing chart illustrating the write operation of the clock domain crossing circuit according to the embodiment. FIG. 3 shows data processing on the input side (write side).
FIG. 4 is a timing chart illustrating the read operation of the clock domain switching circuit according to the embodiment. FIG. 4 shows data processing on the output side (read side).
FIG. 5 is a timing chart illustrating phase adjustment processing of the clock domain transfer circuit according to the embodiment.

As shown in FIGS. 3 and 5, when the pulse timing comparator 115 detects the first input frame pulse after activation, the pulse timing comparator 115 outputs an initialization signal S1 for initializing the write address counter 1122 and the read address counter 1131. to output The read address counter 1131 is initialized based on the phase signal information S2 of the write address counter 1122 .

The phase comparison unit 118 compares the value of the write address counter 1122 and the value of the read address counter 1131, and if the set range is exceeded, generates an initialization signal S3 for initializing the read address counter 1131, Output to read address counter 1131 .

The write enable generator 1121 asserts the write enable signal WE1 and the write enable signal WE3 when the most significant bit of the write address counter 1122 is "0". Then, the clock domain switching circuit 11 writes the first column data to the first memory 1111 and the third memory 1113 .

Write enable generator 1121 asserts write enable signal WE2 and write enable signal WE4 when the most significant bit of write address counter 1122 is "1". Then, the clock domain switching circuit 11 writes the second column data to the second memory 1112 and the fourth memory 1114 .

The clock transfer circuit 11 detects the first input frame pulse after activation and then starts writing the first column data and the second column data.

As shown in FIGS. 4 and 5, the output switching unit 114 generates a selection signal for selecting one of the first memory 1111 to the fourth memory 1114 from the value of the upper two bits of the read address counter 1131 . . The output switching unit 114 selects data read from the first memory 1111, the second memory 1112, the third memory 1113, and the fourth memory 1114 based on the selection signal, and outputs the selected data as output data.

The clock transfer circuit 11 according to the embodiment rearranges a plurality of input data on a frame-by-frame basis (frame by frame) and writes the data into a memory, performs clock transfer processing, and reads and outputs data at the post-transfer speed. . As a result, the circuit scale of the clock transfer circuit 11 can be reduced.

In addition, since the circuit scale of the clock transfer circuit 11 is reduced and the processing time is shortened, the processing delay can be reduced.

In the embodiment, the number of input column data is two, but the number is not limited to this. In the embodiment, the number of input column data may be three or more columns.

Also, the ratio of the clock frequencies before and after clock switching is not limited to 1:2. The read speed at which the clock domain switching circuit 11 reads out a predetermined number of bits is obtained by multiplying the write speed at which the predetermined number of bits is written by the ratio of the effective number of bits to the predetermined number of bits of all column data. speed.

Specifically, when N pieces of the first column data and (N/2) pieces of the first half of the second column data shown in FIG. The clock frequency may be set to 150 megahertz and only valid data may be transferred. However, N is a multiple of 2.

Although the present invention has been described as a hardware configuration in the above embodiment, the present invention is not limited to this. The present invention can also be implemented by causing a CPU (Central Processing Unit) to execute a computer program to process each component.

In the above embodiments, the programs can be stored and delivered to computers using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (specifically flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (specifically magneto-optical discs), CD-ROMs (Read Only Memory ), CD-R, CD-R/W, semiconductor memory (specifically, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM)), flash ROM, and RAM (Random Access Memory). The program may also be delivered to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired channels, such as wires and optical fibers, or wireless channels.

It should be noted that the present invention is not limited to the above embodiments, and can be modified as appropriate without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 11... Clock transfer circuit 111... Storage part 1111... 1st memory 1112... 2nd memory 1113... 3rd memory 1114... 4th memory 112... Write control part 1121... Write enable generation part 1122... Write address counter 113 ... read control section 1131 ... read address counter 114 ... output switching section 115 ... pulse timing comparison section 116 ... phase signal generation section 117 ... phase signal detection section 118 ... phase comparison section WA ... write address signals WE1, WE2, WE3, WE4 ... write enable signal RA ... read address signal S1, S3 ... initialization signal S2 ... phase signal information

Claims (7)

first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; a write control unit that alternately writes to the second memory and the fourth memory each time;
a read control unit that reads the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
an output switching unit that outputs the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
with
The reading speed for reading the predetermined number of bits is a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the number of column data,
Clock transfer circuit. The write control unit
writing data of the first predetermined number of bits of the first column data to the first memory, writing data of the predetermined number of bits subsequent to the first column data to the third memory;
writing the first data of the predetermined number of bits of the second column data to the second memory, and writing the data of the predetermined number of bits subsequent to the second column data to the fourth memory;
2. The clock domain crossing circuit of claim 1. Each of the first memory, the second memory, the third memory, and the fourth memory is a 2-port RAM (Random Access Memory),
3. A clock domain crossing circuit as claimed in claim 1 or 2. the write speed is 100 megahertz and the read speed is 200 megahertz;
4. A clock domain crossing circuit as claimed in any one of claims 1 to 3. first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; a write control unit that alternately writes to the second memory and the fourth memory each time;
a read control unit that reads the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
an output switching unit that outputs the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
with
The reading speed for reading the predetermined number of bits is a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the ratio of the effective number of bits to the predetermined number of bits of all column data. is
Clock transfer circuit. first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; alternately writing to the second memory and the fourth memory every
reading the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
outputting the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
setting the reading speed for reading the predetermined number of bits to a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the number of column data;
How to prepare. first column data containing a plurality of data are alternately written into the first memory and the third memory for each predetermined number of bits; alternately writing to the second memory and the fourth memory every
reading the predetermined number of bits from each of the first memory, the second memory, the third memory, and the fourth memory;
outputting the read data in the order of the first memory, the second memory, the third memory, and the fourth memory;
setting the reading speed for reading the predetermined number of bits to a speed obtained by multiplying the writing speed for writing the predetermined number of bits by the number of column data;
A program that makes a computer run

Images