JP7202990B2 - DRAM diagnosis method - Google Patents

Description

The present application relates to a method for diagnosing a DRAM.

2. Description of the Related Art A DRAM (Dynamic Random Access Memory), which is one type of semiconductor memory, is used as a main memory device of electronic equipment such as a computer. Data stored in the DRAM may have unintended errors due to DRAM failure, manufacturing failure, cosmic rays, or the like. Diagnostics are required to periodically verify that the data stored in the DRAM is error-free and normal. As a method of diagnosing the presence or absence of errors in a DRAM, there is a method in which a microprocessor executes a memory diagnostic program for all areas of the DRAM when the system is started. In some cases, the diagnostic program for the memory is executed during online operation after startup. will decline.

As means for preventing the deterioration of DRAM access performance, a method of simultaneously performing a refresh operation and a DRAM diagnostic operation has been disclosed (see, for example, Patent Document 1). However, even when DRAM refresh and memory diagnosis are performed simultaneously by memory read access, which is a DRAM refresh means, access performance to the DRAM is lowered because access requests to the DRAM from other devices are made to wait. I had a problem to make it work.

In order to solve this problem, the DRAM is divided into a plurality of banks, and when an access request is received for each bank, the memory control section of the bank performs access from the memory bus, and the refresh control section triggers this access. Then, refresh is performed by performing read access, which is a refresh means, to the bank having the highest DRAM refresh priority among the banks that are not being accessed, and data diagnosis is also performed using the data read by the read access. Thus, it is disclosed that the access performance to the DRAM is prevented from deteriorating (see, for example, Patent Document 2).

JP-A-4-266143 JP-A-9-213072

In Patent Document 2, in order to solve the problem of Patent Document 1, the DRAM is divided into a plurality of banks, and when the DRAM is accessed, the bank other than the accessed bank has the highest refresh request. It is possible to issue a refresh request to the However, when the refresh request of the accessed bank itself is high, there is a problem that the access is made to wait.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a method of performing a diagnostic operation of a DRAM without degrading access performance to the DRAM, even when any area of the DRAM is accessed. intended to

The DRAM diagnostic method disclosed in the present application is a DRAM diagnostic method executed by a memory controller that controls access from a microprocessor to a DRAM. The data stored in the DRAM address is stored in the diagnostic data buffer of the memory controller, and when the microprocessor requests access for read operation to the DRAM, the DRAM address stored in the diagnostic data buffer and the requested read operation are read. When the addresses match, the data stored in the diagnostic data buffer is output to the microprocessor.

According to the DRAM diagnostic method disclosed in the present application, the DRAM diagnostic operation can be performed without lowering the access performance to the DRAM.

1 is a configuration diagram of a microprocessor and a memory device according to Embodiment 1; FIG. 4 is a diagram showing a period of DRAM diagnostic operation for a specific address according to Embodiment 1; FIG. 4 is a diagram showing diagnostic addresses generated by a refresh counter according to the first embodiment; FIG. 4 is a processing flow diagram relating to a read operation from the microprocessor to the DRAM and a DRAM diagnostic operation according to the first embodiment; FIG. 4 is a processing flow diagram when a request for a read operation to the DRAM is issued from the microprocessor according to the first embodiment; FIG. FIG. 10 is a diagram showing diagnostic addresses generated by a refresh counter according to the second embodiment; FIG. FIG. 10 is a diagram showing a period of DRAM diagnostic operation for a specific address according to the third embodiment; FIG. 11 is a processing flow diagram of a read operation from a microprocessor to a DRAM and a DRAM diagnostic operation according to a fourth embodiment;

Hereinafter, the DRAM diagnostic method of the embodiment will be described with reference to the drawings. In each drawing, the same or corresponding members and portions are denoted by the same reference numerals.

Embodiment 1.
FIG. 1 is a configuration diagram of a microprocessor 1 and a memory device 100 according to the first embodiment. The memory device 100 is composed of a memory controller 3 (a portion surrounded by a dashed line in FIG. 1) that controls access from the microprocessor 1 to the DRAM 2 and the DRAM 2 . The memory controller 3 that executes the DRAM diagnostic method includes a timing control unit 4, an error correction and detection unit (hereinafter referred to as an error correction/detection unit 5), a diagnostic data buffer 6, a refresh counter 7, an address selector 8, and a data selector. 9. In FIG. 1, each component is connected by a single line or a branched line, but each line is provided separately for each signal flowing through each line.

Basic operations of the microprocessor 1 and the memory device 100 will be described. Microprocessor 1 requests access to DRAM 2 for read or write operations. In a read operation, microprocessor address signal 11 and microprocessor control signal 12 are input from microprocessor 1 to timing control section 4 . After the signals are input, the timing control unit 4 performs timing control for outputting the address selector selection signal 16 , the data selector selection signal 17 and the DRAM control signal 22 to the address selector 8 , data selector 9 and DRAM 2 . Also, in a write operation, microprocessor data signal 13 is input from microprocessor 1 to data selector 9 .

FIG. 2 is a diagram showing the period of the DRAM diagnostic operation for a specific address. The memory controller 3 periodically performs a refresh operation of the DRAM 2 and a DRAM diagnostic operation. The DRAM diagnostic operation is performed in a refresh operation cycle (hereinafter referred to as refresh cycle) based on the diagnostic address signal 14 generated by the refresh counter 7 . That is, diagnosis is performed at points A, B, and C in FIG. The refresh operation of the DRAM 2 is also performed by the read operation.

A DRAM diagnosis operation will be described. First, the path through which the DRAM address (diagnostic address) to be diagnosed is output to the DRAM 2 will be described. FIG. 3 is a diagram showing diagnostic addresses generated by the refresh counter 7. As shown in FIG. A diagnostic address signal 14 generated by the refresh counter 7 is input to the address selector 8 and the timing controller 4 . Based on the input diagnostic address signal 14, the address selector 8 selects a diagnostic address. A DRAM address signal 21 of the selected diagnostic address is input to the DRAM2. A DRAM control signal 22 is input from the timing control unit 4 to the DRAM 2, and the data stored at the diagnostic address based on the DRAM address signal 21 is read out to the error correction/detection unit 5 along with the DRAM address at the timing based on the DRAM control signal 22. .

The read operation includes an operation related to diagnosis in the error correction/detection unit 5. In the DRAM diagnosis operation and the read operation, the error correction/detection unit 5 checks whether there is an error (DRAM error) in the read data. to detect DRAM errors are detected and corrected by adding an ECC (error check and correction) code generated from the data to the data as check data for error detection and error correction. . For example, by adding a 7-bit ECC code to 32-bit data, 1-bit error correction and 2-bit error detection can be performed. An ECC code is generated from the data based on a Hamming code, and error correction and error detection are performed using the data and the ECC code. A detected DRAM error is notified to microprocessor 1 via timing control unit 4 and microprocessor control signal 12 . The error correction/detection unit 5 stores the DRAM address read from the DRAM 2 and the data stored in the DRAM address in the diagnostic data buffer 6 as the DRAM data signal 23 . The data stored in the diagnostic data buffer 6 are corrected data. Note that if the detected DRAM error is corrected, there is no problem in continuing the operation of the memory device 100, but the microprocessor 1 checks the number of error corrections and the frequency of the error, so that there is a possibility that the error will occur in the future. Preventive maintenance against DRAM failures can be performed. If the error is not corrected, the operation of the memory device 100 may not be able to continue. Therefore, the microprocessor 1 logs the detection of the error and then stops operation for fail-safe or returns the error state. In order to reset, the memory device 100 is restarted to restore the state.

FIG. 4 is a processing flow chart of the read operation from the microprocessor 1 to the DRAM 2 and the DRAM diagnostic operation. A processing flow of the read operation and the DRAM diagnostic operation will be described with reference to FIG. When the microprocessor 1 issues an access request for a read or write operation to the DRAM 2 (step S11), the timing control unit 4 determines whether a DRAM diagnosis operation is requested (step S12), and executes the DRAM diagnosis. If no operation is requested, microprocessor 1 accesses DRAM 2 for read or write operation (step S13).

If the DRAM diagnostic operation is requested, it is determined whether the access request from the microprocessor 1 to the DRAM 2 is for a read operation (step S14). ), and then the write operation is executed (step S16).

If the access request from the microprocessor 1 to the DRAM 2 is a read operation, it is checked whether the DRAM address (diagnostic address) generated by the DRAM diagnostic operation matches the address at which the microprocessor 1 requests the DRAM 2 to perform the read operation. If they do not match, the DRAM diagnosis operation is continued (step S18), and then the read operation is executed (step S19).

If the DRAM address (diagnostic address) generated by the DRAM diagnostic operation matches the address at which the microprocessor 1 requests the DRAM 2 to perform the read operation, the read operation is performed (step S20). Since the read operation includes an operation related to diagnosis in the error correction/detection unit 5, the processing flow ends at step S20 without executing the DRAM diagnosis operation separately.

The fact that the provision of the diagnostic data buffer 6 suppresses deterioration of access performance of the diagnostic operation to the DRAM 2 during execution of the read operation will be described in detail below. The operation when a read operation is requested from the microprocessor 1 to the DRAM 2 will be described. FIG. 5 is a processing flow chart when a read operation request from the microprocessor 1 to the DRAM 2 is issued. At the access request for the read operation (step S21), the address requested by the read operation is output from the microprocessor 1 as the microprocessor address signal 11. FIG. Microprocessor address signal 11 is input to diagnostic data buffer 6 . The diagnostic data buffer 6 checks whether the DRAM address of the data stored in the diagnostic data buffer 6 matches the address requested in the read operation (step S22). As a result of collation, if the DRAM address matches the address requested in the read operation, the diagnostic data buffer 6 outputs a diagnostic data buffer storage notification signal 18 to the timing control section 4 . Further, the diagnostic data buffer 6 outputs to the data selector 9 as a diagnostic data signal 15 the data whose DRAM address matches the address requested in the read operation. The data selector 9 outputs the diagnostic data signal 15 to the microprocessor 1 as the microprocessor data signal 13 (step S23). In this way, when the DRAM address and the address requested in the read operation match, the timing control section 4 does not perform the read operation of the DRAM 2 . Therefore, the deterioration of the access performance of the periodically executed diagnostic operation to the DRAM 2 is suppressed. If the DRAM address and the address requested by the read operation do not match, the timing control section 4 executes the read operation to the DRAM 2 (step S24).

The data stored in the diagnostic data buffer 6 is discarded when the microprocessor 1 writes to the DRAM 2 (write operation).

As described above, in this DRAM diagnostic method, the DRAM address read from the DRAM 2 and the data stored at that DRAM address are stored in the diagnostic data buffer 6, and then stored from the diagnostic data buffer 6 by the read operation. Since the data is read out, the read operation to the DRAM 2 is not performed. Therefore, the DRAM diagnostic operation of the DRAM 2 can be performed without lowering the access performance of the diagnostic operation to the DRAM 2. FIG. Further, when the DRAM address generated by the memory controller 3 in the DRAM diagnostic operation and the address requesting the read operation access from the microprocessor 1 to the DRAM 2 match, the read operation access from the microprocessor 1 to the DRAM 2 is executed, Since an operation related to diagnosis in the error correction/detection unit 5 is also executed in the read operation, the diagnosis of the DRAM 2 can be performed without lowering the access performance to the DRAM 2 .

Embodiment 2.
A DRAM diagnostic method according to the second embodiment will be described. FIG. 6 is a diagram showing diagnostic addresses generated by the refresh counter 7. As shown in FIG. In the first embodiment, the diagnostic address generated by the refresh counter 7 consists only of the row address used for the refresh operation with the column address fixed as shown on the right side of FIG. As shown on the left side of FIG. 6, it consists of a row address and a column address. Other configurations are the same as those described in the first embodiment, so the same reference numerals are given and descriptions thereof are omitted.

The diagnostic address consists of both a row address and a column address, as shown on the left side of FIG. 6, and access to the DRAM 2 is performed by designating the row address and column address in a time division manner. In FIG. 6, the row address consists of 12 bits (0 to 4095 in decimal) and the column address consists of 8 bits (0 to 255 in decimal). I don't mind.

Next, the DRAM diagnostic operation of the DRAM 2 using the diagnostic addresses shown in FIG. 6 will be described. In a normal refresh operation, all row addresses are refreshed within a predetermined time. The diagnostic address of the conventional method is constructed such that the column address is fixed and only the row address is incremented to generate all row addresses, as shown on the right side of FIG. On the other hand, in the second embodiment, as shown on the left side of FIG. 6, all diagnostic addresses are generated by not only incrementing the row address but also making the column address variable. The row address and column address are handled in the DRAM diagnostic operation by first fixing the column address and sequentially incrementing the row address. After the row address makes a round, the column address is incremented, and the row address is incremented to make a round. By performing these operations in sequence, diagnostic operations can be performed for all addresses of the DRAM 2 without duplication.

As described above, in this DRAM diagnostic method, the diagnostic address generated by the DRAM diagnostic operation includes the column address in addition to the row address required for the refresh operation. diagnostic operation can be performed without degrading the In addition to row address defects, column address defects can also be detected.

Embodiment 3.
A DRAM diagnostic method according to the third embodiment will be described. FIG. 7 is a diagram showing the period of the DRAM diagnostic operation for a specific address. In the first embodiment, the period of the DRAM diagnostic operation is the same as that of the refresh cycle, but in the third embodiment, the period of the DRAM diagnostic operation is half the refresh cycle. When the access request and the DRAM diagnostic operation conflict with the same address, the DRAM diagnostic operation is skipped. Other configurations are the same as those described in the first embodiment, so the same reference numerals are given and descriptions thereof are omitted.

FIG. 7 is a diagram showing the cycle of the DRAM diagnostic operation in the horizontal direction. showing execution. Diagnosis is performed at points A, C, and E in the upper stage, and diagnosis is performed at points A, B, C, D, and E in the lower stage. In the normal case where the access request from the microprocessor 1 to the DRAM 2 and the DRAM diagnosis operation do not conflict for the same address, diagnosis is performed in a cycle of points A, B, C, D and E.

Next, the operation when the access request from the microprocessor 1 to the DRAM 2 and the DRAM diagnostic operation conflict with respect to the same address will be described. When there is contention, the access request from the microprocessor 1 is preferentially executed and the DRAM diagnostic operation is skipped. As shown at point C in FIG. 3, when the DRAM diagnostic operation is skipped, the diagnostic skip flag is set. The diagnosis skip flag indicates that the DRAM diagnosis has been skipped. If the diagnostic skip flag is set, the diagnostic operation is executed without skipping the DRAM diagnosis in the next diagnostic cycle. Here, since the diagnosis skip flag is set at point D, which is the next diagnosis cycle, the diagnostic operation of the DRAM 2 is executed at point D without skipping the DRAM diagnosis. Since the DRAM diagnostic operation has been executed, the set diagnostic skip flag is cleared.

As described above, in this DRAM diagnosis method, since the period of the DRAM diagnosis operation is half the period of the refresh cycle, the DRAM diagnosis operation is skipped when the access from the microprocessor 1 to the DRAM 2 conflicts with the DRAM diagnosis operation. Even so, by executing the DRAM diagnostic operation in the next period, the DRAM diagnostic operation can be executed within the normal refresh cycle required for the DRAM 2 without lowering the access performance to the DRAM 2. FIG.

Embodiment 4.
A DRAM diagnostic method according to the fourth embodiment will be described. FIG. 8 is a processing flow chart of the read operation from the microprocessor 1 to the DRAM 2 and the DRAM diagnostic operation. In the first embodiment, when the access request for the read operation and the DRAM diagnosis operation conflict and the addresses of both match, the read operation is executed. When the request and the DRAM diagnostic operation conflict and the addresses of both match, the DRAM diagnostic operation is executed and the read data is output to the microprocessor 1. FIG. Other configurations are the same as those described in the first embodiment, so the same reference numerals are given and descriptions thereof are omitted.

The operation when a read access request from the microprocessor 1 to the DRAM 2 conflicts with the DRAM diagnostic operation will be described. In FIG. 8, the processing from step S41 to step S49 is the same as the processing from step S11 to step S19 in FIG. 4, so description thereof will be omitted. In step S47, if the DRAM address (diagnostic address) generated by the DRAM diagnostic operation and the address requesting the read operation from the microprocessor 1 to the DRAM 2 match, the DRAM diagnostic operation is continued, and the read by the DRAM diagnostic operation is continued. Data is output to the microprocessor 1 (step S50). Since the data read by the DRAM diagnostic operation is regarded as the data read by the read operation, the process flow ends at step S50 without executing the read operation separately.

As described above, in this DRAM diagnostic method, when the DRAM address generated by the memory controller 3 in the DRAM diagnostic operation matches the address requested by the microprocessor 1 to access the DRAM 2 for read operation, the DRAM diagnostic operation is continued. Since the data read by the DRAM diagnostic operation is output to the microprocessor 1 and the data read by the DRAM diagnostic operation is regarded as the data read by the read operation, access performance to the DRAM 2 is not lowered. A diagnostic operation for the DRAM 2 can be performed.

While this application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments may not apply to particular embodiments. can be applied to the embodiments singly or in various combinations.
Accordingly, numerous variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, modification, addition or omission of at least one component, extraction of at least one component, and combination with components of other embodiments shall be included.

1 microprocessor, 2 DRAM, 3 memory controller, 4 timing control section, 5 error correction/detection section, 6 diagnostic data buffer, 7 refresh counter, 8 address selector, 9 data selector, 11 microprocessor address signal, 12 microprocessor control 13 microprocessor data signal 14 diagnostic address signal 15 diagnostic data signal 16 address selector selection signal 17 data selector selection signal 18 diagnostic data buffer storage notification signal 21 DRAM address signal 22 DRAM control signal 23 DRAM data signal, 100 memory device

Claims (5)

A DRAM diagnostic method performed by a memory controller controlling access to a DRAM from a microprocessor, comprising:
storing a DRAM address read from the DRAM and data stored at the DRAM address in a diagnostic data buffer of the memory controller in a DRAM diagnostic operation and a read operation;
When the microprocessor requests to access the DRAM for a read operation,
DRAM diagnosis, wherein the data stored in the diagnostic data buffer is output to the microprocessor when the DRAM address stored in the diagnostic data buffer and the address requested in the read operation match. Method. The DRAM address generated by the memory controller in the DRAM diagnostic operation includes a column address in addition to a row address used for refresh operation,
2. The method of diagnosing a DRAM as claimed in claim 1, wherein all addresses of said DRAM are diagnosed. executing the DRAM diagnostic operation at a period shorter than the periodic refresh operation period of the DRAM;
When a request for access to the DRAM from the microprocessor conflicts with the DRAM diagnostic operation,
2. The DRAM diagnostic method of claim 1, wherein the DRAM diagnostic operation is skipped. When the DRAM address generated by the memory controller in the DRAM diagnostic operation matches the address requested by the microprocessor to access the DRAM for read operation,
2. The method of diagnosing a DRAM as claimed in claim 1, wherein access of a read operation from said microprocessor to said DRAM is executed. When the DRAM address generated by the memory controller in the DRAM diagnostic operation matches the address requested by the microprocessor to access the DRAM for read operation,
2. The DRAM diagnostic method according to claim 1, wherein said DRAM diagnostic operation is executed, and data read by said DRAM diagnostic operation is output to said microprocessor.

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