JP7203511B2 - Aluminum nitride template and device - Google Patents

Description

The present invention relates to nitride semiconductor templates and devices manufactured therewith.

A nitride semiconductor template (hereinafter simply referred to as template) in which an aluminum (Al)-containing nitride semiconductor layer is laminated on a different substrate is used as a member for manufacturing various devices (aluminum nitride (AlN) See, for example, Patent Document 1 for an example of template preparation). The template is used, for example, as a base for ultraviolet light emitting diodes (LEDs), and as a material for SAW (Surface Acoustic Wave) filters, BAW (Bulk Acoustic Wave) filters, FBAR (Film Bulk Acoustic Resonator) filters, and the like. there is

A high-quality Al-containing nitride semiconductor layer can be grown on a substrate by using any one of a sapphire substrate, a silicon carbide substrate, and a nitride semiconductor substrate as a template substrate. There is also a need for a template with

For example, for ultraviolet LED applications, an Al-containing nitride semiconductor layer is formed on a silicon (Si) substrate. Further, for example, in filter applications, an Al-containing nitride semiconductor layer is formed on a Si substrate, a glass substrate, or the like via a metal layer serving as a lower electrode. However, it is difficult to grow a high-quality Al-containing nitride semiconductor layer on these substrates, and the X-ray diffraction half width of the Al-containing nitride semiconductor layer is several thousand seconds.

JP 2015-173273 A

SUMMARY OF THE INVENTION It is an object of the present invention to provide a novel nitride semiconductor template having a high quality Al-containing nitride semiconductor layer and a device manufactured using the same.

According to a first aspect of the invention,
a substrate;
a nitride semiconductor layer laminated on the substrate, made of an aluminum-containing nitride semiconductor, and having a half width of (0002) diffraction of 1,000 seconds or less by X-ray rocking curve measurement;
has
The nitride semiconductor layer is directly bonded to the substrate,
The substrate is made of a material that is neither sapphire, silicon carbide nor a nitride semiconductor.
A nitride semiconductor template is provided.

According to a second aspect of the invention,
a substrate;
a nitride semiconductor layer laminated on the substrate, made of an aluminum-containing nitride semiconductor, and having a half width of (0002) diffraction of 1,000 seconds or less by X-ray rocking curve measurement;
has
The nitride semiconductor layer is bonded to the substrate via an intermediate layer,
wherein the intermediate layer is made of a material that is neither sapphire, silicon carbide nor nitride semiconductor;
A nitride semiconductor template is provided.

According to the third aspect of the invention,
A device manufactured using the nitride semiconductor template of the first aspect or the second aspect is provided.

A novel nitride semiconductor template having a high quality Al-containing nitride semiconductor layer and devices fabricated using the same are provided.

FIG. 1 is a schematic cross-sectional view showing the structure of templates according to first and second embodiments of the present invention. 2(a) to 2(c) are schematic cross-sectional views showing steps of manufacturing the template according to the first embodiment. 3(a) to 3(d) are schematic cross-sectional views showing steps of manufacturing the template according to the first embodiment. 4(a) and 4(b) are schematic cross-sectional views showing steps of manufacturing a template according to the second embodiment. FIG. 5 is a schematic cross-sectional view showing the structure of templates according to the third and fourth embodiments. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the template according to the third embodiment. FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the template according to the fourth embodiment. FIG. 8 is a schematic cross-sectional view showing the structure of the growth substrate in the sixth embodiment. FIG. 9 is a schematic cross-sectional view showing an ultraviolet LED as an application.

<First embodiment>
A nitride semiconductor template 100 (hereinafter also referred to as template 100) according to the first embodiment of the present invention will be described. First, the structure of the template 100 will be described. FIG. 1 is a schematic cross-sectional view showing the structure of a template 100 according to the first embodiment. The template 100 has a support substrate 40 (hereinafter also referred to as substrate 40 ) and a nitride semiconductor layer 20 (hereinafter also referred to as layer 20 ) laminated on the substrate 40 .

Layer 20 is composed of an aluminum (Al)-containing nitride semiconductor. As an Al-containing nitride semiconductor, aluminum nitride (AlN) is exemplified below. The half width of (0002) diffraction (hereinafter also simply referred to as (0002) diffraction) by X-ray rocking curve measurement of the layer 20 is 1,000 seconds or less. The layer 20 has crystallinity such that at least the (0002) diffraction half width is 1,000 seconds or less, and such crystallinity is hereinafter also referred to as "high crystallinity". The half width of (0002) diffraction of layer 20 is preferably 300 seconds or less, more preferably 200 seconds or less. In addition, the half width of (10-12) diffraction (hereinafter simply referred to as (10-12) diffraction) by X-ray rocking curve measurement of the layer 20 is preferably 1,000 seconds or less, more preferably 500 seconds. seconds or less.

The substrate 40 is made of a material that is not suitable as a base for growing AlN with high crystallinity. Hereinafter, such a material is also referred to as "underlying material with low AlN crystallinity". Underlying materials on which AlN is grown with high crystallinity include sapphire, silicon carbide (SiC), and nitride semiconductors. The substrate 40 is made of a material other than sapphire, SiC, and nitride semiconductors. The substrate 40 is, for example, a crystalline substrate, and examples of materials constituting the crystalline substrate include magnesium oxide (MgO) and silicon (Si). The substrate 40 is also, for example, an amorphous substrate, and examples of materials constituting the amorphous substrate include glass and polymeric materials such as polyethylene terephthalate (PET).

In the first embodiment, the layer 20 is laminated to the substrate 40 by being directly bonded to the substrate 40 without any other layer interposed therebetween. As described above, the template 100 is characterized in that the layer 20 composed of AlN having high crystallinity is laminated on the substrate 40 composed of a base material having low crystallinity AlN.

In a conventional technique, a nitride semiconductor template ( hereinafter, also referred to as a template according to a comparative example). In the template according to the comparative example, the (0002) diffraction half width of the nitride semiconductor layer is as large as several thousand seconds, and the crystallinity of the nitride semiconductor layer is low.

In contrast, in the template 100 according to the present embodiment, the layer 20 is made of AlN having high crystallinity, that is, having high quality, even if the substrate 40 is made of a base material with low AlN crystallinity. Therefore, a device manufactured using the template 100 according to the present embodiment can obtain higher performance than a device manufactured using the template according to the comparative example. Moreover, in the template 100 according to the present embodiment, the degree of freedom in selecting the material for the substrate 40 can be increased while imparting high crystallinity to the layer 20 . Therefore, it is possible to obtain the template 100 in which the substrate 40 has various characteristics.

Next, a method for manufacturing the template 100 will be described. FIGS. 2(a) to 2(c) and FIGS. 3(a) to 3(d) are schematic cross-sectional views showing manufacturing steps of the template 100 according to the first embodiment. Please refer to FIG. First, a growth substrate 10 (hereinafter also referred to as substrate 10) is prepared. In the first embodiment (and second to fourth embodiments described later), either a sapphire substrate or a SiC substrate is preferably used as the substrate 10, and the sapphire substrate is exemplified below. In addition, in fifth and sixth embodiments described later, as the substrate 10, a substrate having at least a surface layer made of a nitride semiconductor is preferably used. Substrate 10 is capable of withstanding temperature conditions of 1000-1300° C. during growth of layer 20 as described below, and temperatures of 1600-1800° C. during annealing of layer 20 as described below. It is preferably resistant to temperature conditions.

A peelable film 11 (hereinafter also referred to as film 11) is formed on a substrate 10. As shown in FIG. A hexagonal boron nitride (hBN) film is preferably used as the film 11 . The film 11 is formed of hBN by metalorganic vapor phase epitaxy (MOVPE) using, for example, triethyl boron (TEB) gas as a boron (B) source gas and ammonia (NH ₃ ) gas as a nitrogen (N) source gas. It is formed by growing. hBN is a nitride semiconductor having a layered structure. Since the layers of hBN are weakly bonded by the van der Waals force, the layers of hBN can be separated from each other in the middle of the thickness direction of the film 11 . Note that there is a possibility that a graphene film can be used as the film 11 .

Please refer to FIG. Layer 20 is formed on film 11 by growing AlN. The layer 20 is formed by hydride vapor phase epitaxy (HVPE) using, for example, aluminum monochloride (AlCl) gas or aluminum trichloride (AlCl ₃ ) gas as an aluminum (Al) source gas and NH ₃ gas as an N source gas. is formed by growing AlN by These raw material gases may be mixed with a carrier gas composed of hydrogen gas (H2 gas), nitrogen gas _{( N2} gas), or a mixture thereof and supplied.

The growth temperature is exemplified as 1,000 to 1,300° C., and the growth rate is exemplified as 0.5 to 500 nm/min. The V/III ratio, which is the supply amount ratio of the N source gas to the Al source gas, is 0.2 to 200, for example. In order to prevent AlN from adhering to the nozzle of the gas supply pipe for introducing various gases into the growth chamber of the HVPE apparatus, hydrogen chloride (HCl) gas may be supplied. Alternatively, an amount that provides a ratio of 0.1 to 100 with respect to AlCl ₃ gas is exemplified.

From the viewpoint of forming the layer 20 as a continuous film, the thickness of the layer 20 is preferably 50 nm or more, more preferably 100 nm or more, and even more preferably 200 nm or more. In addition, from the viewpoint of suppressing the occurrence of cracks in the layer 20, the thickness of the layer 20 is preferably 800 nm or less. The layer 20 has a group III polar surface (Al polar surface in this example) on the growth side, and an N polar surface on the substrate 10 side, which is the opposite side. Hereinafter, the growth-side surface of the layer 20 may be referred to as the "upper surface", and the surface of the layer 20 on the substrate 10 side may be referred to as the "lower surface".

In this way, the crystallinity of the layer 20 can be improved by forming the layer 20 by growing AlN on the substrate 10, which is, for example, a sapphire substrate through the film 11, which is, for example, an hBN film. As a result, the half width of (0002) diffraction of the layer 20 can be set to 1,000 seconds or less.

By setting the thickness of the layer 20 to 800 nm or less in order to suppress the generation of cracks in the layer 20, there is concern that the dislocation density of AlN in the layer 20 will increase. Therefore, it is preferable to perform annealing (hereinafter simply referred to as annealing) to reduce the dislocation density of the layer 20 . Annealing is performed, for example, as follows. After the layer 20 is grown to the desired thickness, stop the supply of Al source gas, _N source gas and H2 gas into the growth chamber of the HVPE apparatus and supply _N2 gas from all gas supply pipes. , the atmosphere in the growth chamber is replaced with _N2 gas. Annealing is performed by heating layer 20 to the desired annealing temperature in a _N2 gas atmosphere in the growth chamber of the HVPE apparatus. The annealing temperature is preferably 1,600 to 1,800° C., and the annealing time is preferably 30 to 1,800 minutes. Annealing under such conditions reduces the dislocation density of AlN constituting the layer 20, thereby making it possible to reduce the half width of (0002) diffraction to 300 seconds or less, more preferably 200 seconds or less. 10-12) The half width of diffraction can be 1,000 seconds or less, preferably 500 seconds or less.

Refer to FIG. 2(c). A transfer substrate 30 is bonded onto the layer 20 . As the transfer substrate 30, for example, a Si substrate, a gallium arsenide (GaAs) substrate, a sapphire substrate, or the like is used. Here, as the transfer substrate 30, a Si substrate or a GaAs substrate that can be etched with an acid or alkaline solution is exemplified. A method for joining the layer 20 and the transfer substrate 30 is not particularly limited. For example, the surface of the layer 20 and the bonding surface of the transfer substrate 30 can be cleaned and activated by plasma irradiation or the like to directly adhere to each other (so-called surface activation method). . In this manner, the transfer substrate 30 is joined to the layer 20 .

Please refer to FIG. The layer 20 is separated from the substrate 10 with the membrane 11 as the boundary. The layer 20 is separated from the substrate 10 by separating the film 11 into the film 11a on the substrate 10 side and the film 11b on the layer 20 side in the middle of its thickness.

Please refer to FIG. After peeling the layer 20 from the substrate 10, the film 11b remaining on the lower surface of the layer 20 is removed.

See FIG. 3(c). On the underside of layer 20 is bonded a substrate 40 which provides the final support for layer 20 . In a first embodiment, layer 20 is bonded directly to substrate 40 . A method for bonding the layer 20 and the substrate 40 is not particularly limited, and for example, a surface activation method can be used.

See FIG. 3(d). The transfer substrate 30 is removed by etching the transfer substrate 30 using an acid or alkaline solution as an etchant. Note that when the substrate 40 is made of a material that is easily etched by the etching solution, the side and back surfaces of the template 100 in which the substrate 40 and the layer 20 are laminated are made of a material that is difficult to be etched by the etching solution. It is preferable to prevent etching of the substrate 40 by covering it with a protective film (for example, a silicon oxide film, a resist film, or the like). Since the layer 20 made of AlN is not easily dissolved in acids and alkalis, the layer 20 itself acts as a so-called etch stop layer. Etching of layer 20 is thus prevented. In the first embodiment, the template 100 is manufactured with a structure in which the Al polar face of the layer 20 is arranged as the surface of the template 100 and the N polar face of the layer 20 is arranged as the bonding surface with the substrate 40 . Hereinafter, the template 100 having such a structure is also referred to as an Al-polar template 100 . As described above, the template 100 according to the first embodiment is manufactured.

<Modified Example of First Embodiment>
Next, a modified example of the first embodiment will be described. This modification differs from the first embodiment in the method of annealing the layer 20, and otherwise is the same as the first embodiment. First, in the same manner as in the first embodiment, a layered body (hereinafter also referred to as a layered body having layer 20 formed thereon) having layer 20 formed on substrate 10 with film 11 interposed therebetween is obtained (see FIG. 2B). ). In the first embodiment, the case where the layer 20 is annealed in the HVPE apparatus after the layer 20 is formed has been exemplified. In this modified example, the case where the layer 20 is annealed by another annealing apparatus installed outside the HVPE apparatus is illustrated.

In this modification, annealing is performed in a state in which two laminates having layers 20 formed thereon are superposed so that the layers 20 face each other. The annealing temperature is preferably 1,600 to 1,800° C., and the annealing time is preferably 30 to 1,800 minutes. The process after annealing is completed is the same as in the first embodiment. As described above, the template 100 according to the modified example of the first embodiment is manufactured.

In the first embodiment, although annealing improves the crystallinity of the layer 20, the surface of the layer 20 tends to be roughened. In this modified example, thermal decomposition of AlN can be suppressed by performing annealing in a state in which the laminated body having the layer 20 formed thereon is superimposed, so roughening of the surface of the layer 20 can be suppressed. The root-mean-square (RMS) surface roughness of the layer 20 in the template 100 of this modification is, for example, 10 nm or less, preferably 5 nm or less. Here, the RMS is a value obtained by observing a 5 μm square region on the surface of the layer 20 in the template 100 with an atomic force microscope (AFM). Annealing in second to fourth embodiments described later may be performed in the same manner as in this modified example.

<Second embodiment>
Next, the template 100 according to the second embodiment will be described. The second embodiment exemplifies a template 100 in which the layer 20 is bonded directly to the substrate 40, as in the first embodiment (see FIG. 1). However, while the first embodiment exemplified the Al-polarity template 100, the second embodiment exemplifies the N-polarity template 100 as described later.

In the method of manufacturing the template 100 according to the second embodiment, first, in the same manner as in the first embodiment, the steps of forming the layer 20 by growing AlN and annealing the layer 20 are performed (see FIG. 2B). ).

The next step will be described with reference to FIGS. 4(a) and 4(b). 4(a) and 4(b) are schematic cross-sectional views showing the manufacturing process of the template 100 according to the second embodiment. Please refer to FIG. Bonded onto layer 20 (on top of layer 20) is substrate 40, which will ultimately support layer 20. FIG. As described in the first embodiment, the method of joining the layer 20 and the substrate 40 is not particularly limited.

Please refer to FIG. As in the process described with reference to FIG. 3A in the first embodiment, the layer 20 is separated from the substrate 10 with the film 11 as the boundary. After peeling the layer 20 from the substrate 10, the film 11b remaining on the lower surface of the layer 20 is removed. In the second embodiment, the template 100 is manufactured with a structure in which the N-polar surface of the layer 20 is arranged as the surface of the template 100 and the Al-polar surface of the layer 20 is arranged as the bonding surface with the substrate 40 . Hereinafter, the template 100 having such a structure is also referred to as an N-polar template 100 . As described above, the template 100 according to the second embodiment is manufactured.

<Third Embodiment>
Next, the template 100 according to the third embodiment will be described. While the first and second embodiments exemplify the template 100 in which the layer 20 is directly bonded to the substrate 40, the third embodiment has the layer 20 bonded to the substrate 40 via the intermediate layer 50. A template 100 is illustrated. The third embodiment, like the first embodiment, exemplifies an Al-polar template 100 .

FIG. 5 is a schematic cross-sectional view showing the structure of the template 100 according to the third embodiment. Template 100 has substrate 40 , layer 20 laminated to substrate 40 , and intermediate layer 50 interposed between substrate 40 and layer 20 . That is, the layer 20 is laminated to the substrate 40 by being bonded to the substrate 40 via the intermediate layer 50 , in other words, by being directly bonded to the intermediate layer 50 .

As a material for forming the intermediate layer 50, a material that serves as an adhesive layer between the substrate 40 and the layer 20 and can impart desired functions to the intermediate layer 50 can be appropriately selected and used. Metal, which is a conductive material, is exemplified below as the material of the intermediate layer 50 . Since the intermediate layer 50 is made of metal, the intermediate layer 50 can function as a conductive layer.

As a material for forming the intermediate layer 50, an underlying material of AlN with low crystallinity, that is, a material other than sapphire, SiC, and nitride semiconductor is used. Note that when the template 100 has the intermediate layer 50, that is, when the layer 20 is not directly bonded to the substrate 40, the material constituting the crystalline substrate 40 is not limited to a base material such as AlN having low crystallinity. Any of sapphire, SiC and nitride semiconductors may be used.

In the method of manufacturing the template 100 according to the third embodiment, first, in the same manner as in the first embodiment, the transfer substrate 30 is bonded onto the upper surface of the layer 20, and the laminate from which the substrate 10 is peeled off is obtained. A process is performed (refer FIG.3(b)).

The next step will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the template 100 according to the third embodiment. On the bottom surface of layer 20, a metal layer 50a is formed. Also, a metal layer 50b is formed on the bonding surface of the substrate 40 with the layer 20 . As each of the metal layers 50a and 50b, for example, a Pt or Au single layer film is used. A film formed with a two-layer structure of an underlying layer and an upper layer such as Au or Pt is used. Then, the layer 20 and the substrate 40 are arranged such that the metal layers 50a and 50b or their upper layers (Au or Pt) face each other, and the metal layers 50a and 50b are fused together. The layer 20 and the substrate 40 are joined by forming the intermediate layer 50 as an integrated metal layer in which the metal layer 50a and the metal layer 50b are fused together. After the bonding between the layer 20 and the substrate 40 is completed, the transfer substrate 30 is removed by etching in the same manner as the process described with reference to FIG. 3(d) in the first embodiment. In this embodiment, in order to prevent the intermediate layer 50 from being etched, it is preferable to perform the etching while at least the side surfaces of the intermediate layer 50 are covered with a protective film. As described above, the template 100 according to the third embodiment is manufactured.

<Fourth Embodiment>
Next, the template 100 according to the fourth embodiment will be described. The fourth embodiment exemplifies a template 100 in which a layer 20 is bonded to a substrate 40 via an intermediate layer 50, as in the third embodiment (see FIG. 5). However, while the third embodiment exemplifies the Al-polarity template 100, the fourth embodiment exemplifies the N-polarity template 100 similarly to the second embodiment.

In the method of manufacturing the template 100 according to the fourth embodiment, first, in the same manner as in the second embodiment, the steps of forming the layer 20 by growing AlN and annealing the layer 20 are performed (see FIG. 2B). ).

The next step will be described with reference to FIG. FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the template 100 according to the fourth embodiment. On top of layer 20, a metal layer 50a is formed. Also, a metal layer 50b is formed on the bonding surface of the substrate 40 with the layer 20 . Then, the layer 20 and the substrate 40 are arranged so that the metal layers 50a and 50b face each other, and the metal layers 50a and 50b are fused to each other. The layer 20 and the substrate 40 are joined by forming the intermediate layer 50 as an integrated metal layer in which the metal layer 50a and the metal layer 50b are fused together. After the bonding between the layer 20 and the substrate 40 is completed, the layer 20 is peeled off from the substrate 10 with the film 11 as the boundary in the same manner as the process described with reference to FIG. 4B in the second embodiment. . After peeling the layer 20 from the substrate 10, the film 11b remaining on the lower surface of the layer 20 is removed. As described above, the template 100 according to the fourth embodiment is manufactured.

<Fifth Embodiment>
Next, the template 100 according to the fifth embodiment will be described. The fifth embodiment is the same as the first embodiment except for the substrate 10 used for growing the layer 20, which is different from the first embodiment. In the first embodiment, a sapphire substrate or a SiC substrate is exemplified as the substrate 10, whereas in the fifth embodiment, a nitride semiconductor substrate is exemplified as the substrate 10. FIG. Like the layer 20, the substrate 10 of the fifth embodiment is preferably made of an Al-containing nitride semiconductor. As the substrate 10, an AlN single crystal substrate is exemplified below. As the AlN single crystal substrate, it is preferable to use a low dislocation substrate having a dislocation density of 1×10 ⁶ /cm ² or less, which is formed by sublimation, for example.

A method of manufacturing the template 100 according to the fifth embodiment is the same as that of the first embodiment. However, the annealing of layer 20 may be omitted. In the fifth embodiment, since the substrate 10 is made of AlN single crystal, the crystallinity of the layer 20 formed by growing AlN after forming the film 11 such as hBN thereon can be further enhanced. can. Therefore, it is possible to obtain a high-quality layer 20 as described below without performing annealing. In the fifth embodiment, the (0002) diffraction half width of the layer 20 is 100 seconds or less, and the (10-12) diffraction half width of the layer 20 is 200 seconds or less. In addition, in the second to fourth embodiments, the crystallinity of the layer 20 may be further improved by using a nitride semiconductor substrate as the substrate 10 as in the fifth embodiment.

<Sixth Embodiment>
Next, the template 100 according to the sixth embodiment will be described. The sixth embodiment is the same as the first embodiment except for the substrate 10 used for growing the layer 20 from the first embodiment. In the first embodiment, a sapphire substrate or a SiC substrate was exemplified as the substrate 10. In the fifth embodiment, as shown in FIG. 1 illustrates a template substrate on which a nitride semiconductor layer 10b (hereinafter also referred to as layer 10b) is grown. Like the layer 20, the layer 10b is preferably composed of an Al-containing nitride semiconductor, and an AlN layer is exemplified below as the layer 10b.

A substrate 10, which is a template substrate, is prepared by growing a layer 10b directly on a substrate 10a and annealing the layer 10b. The growth and annealing of layer 10b can be performed in the same manner as the growth and annealing of layer 20;

A method of manufacturing the template 100 according to the sixth embodiment is the same as that of the first embodiment. However, the annealing of layer 20 may be omitted. In the sixth embodiment, the substrate 10 is a template substrate whose surface layer is made of AlN. can be higher. Therefore, it is possible to obtain a high-quality layer 20 as described below without performing annealing. In the sixth embodiment, the half width of (0002) diffraction of layer 20 is 200 seconds or less, and the half width of (10-12) diffraction of layer 20 is 300 seconds or less. In the second to fourth embodiments, the crystallinity of the layer 20 may be further enhanced by using the substrate 10 as a template substrate, as in the sixth embodiment.

By using an AlN single crystal substrate as the substrate 10 as in the fifth embodiment, the crystallinity of the layer 20 can be improved more than in the case of using the substrate 10 as a template substrate as in the sixth embodiment. However, currently available AlN single crystal substrates are small in size, with a diameter of 1 inch or less. On the other hand, template substrates using sapphire substrates or SiC substrates can currently be realized up to a maximum diameter of 6 inches. Therefore, the sixth embodiment can be preferably used as a technique for forming the layer 20 having a large area although the crystallinity is slightly lower than that of the fifth embodiment.

As described above, in the template 100 of the first to sixth embodiments, the substrate 40 or the intermediate layer 50, which is a member to which the layer 20 is directly bonded, is made of an underlying material of AlN having low crystallinity. Even though the layer 20 has a high crystallinity. Thereby, the performance of devices manufactured using the template 100 can be enhanced. Moreover, since the degree of freedom in material selection for the substrate 40 and the intermediate layer 50 is high, the template 100 having various properties can be obtained.

<Other embodiments>
The present invention is not limited to the above-described embodiments and modifications, and various modifications may be made without departing from the scope of the invention. Also, various embodiments and modifications may be combined as appropriate.

In the first and third embodiments described above, when manufacturing the Al polarity template 100, the process of bonding the layer 20 to the substrate 40 using the transfer substrate 30 was exemplified. Bonding may be performed without using the transfer substrate 30 if grown. In such a case, after the layer 20 is grown, the layer 20 can be separated from the substrate 10 without bonding the transfer substrate 30, and the film 11b can be removed to obtain the self-supporting layer 20. Then, by joining the lower surface of the layer 20 to the substrate 40 directly or via the intermediate layer 50, an Al-polar template 100 can be obtained. By using the transfer substrate 30, the bonding of the layer 20 to the substrate 40 can be performed even if the thickness of the layer 20 is such that the layer 20 cannot stand on its own. Note that when the layer 20 can stand on its own, the transfer substrate 30 may be used to bond the layer 20 to the substrate 40 .

When bonding the layer 20 and the transfer substrate 30, the layer 20 and the transfer substrate 30 may be bonded via a temporary adhesive layer. Bonding using a temporary adhesive layer is, for example, as follows. A metal layer whose outermost surface layer is a gold layer is formed on each of the layer 20 and the transfer substrate 30 by a vacuum deposition method or a sputtering method, and the layer 20 and the transfer substrate 30 are bonded by pressing while the gold layers are in contact with each other. A transfer substrate 30 can be bonded. When the temporary adhesive layer is used, the transfer substrate 30 can be separated from the layer 20 by removing the temporary adhesive layer by etching using, for example, an acid or alkaline solution, without removing the transfer substrate 30 itself by etching. good too.

In the second and fourth embodiments described above, when manufacturing the N-polar template 100, the process of peeling off the layer 20 from the substrate 10 after bonding the layer 20 and the substrate 40 is illustrated. Layer 20 may be stripped from substrate 10 prior to bonding with substrate 40 if the layer 20 can be grown to a thickness that allows it to stand on its own. In such a case, after the layer 20 is grown, the layer 20 can be separated from the substrate 10 and the film 11b removed to obtain the free-standing layer 20 . Then, by bonding the top surface of layer 20 directly or via intermediate layer 50 to substrate 40, N-polar template 100 can be obtained.

The layer 20 may optionally be doped with impurities such as conductivity determining impurities. Moreover, the layer 20 may be configured with a laminated structure, for example, with a laminated structure of layers of different conductivity types, if necessary.

<Application example>
The template 100 is distributed as a member for manufacturing various devices, and is used as a member for manufacturing various devices. An ultraviolet light emitting diode (LED) will be described as an example of an application device manufactured using the template 100 with reference to FIG. FIG. 9 is a schematic cross-sectional view showing an ultraviolet LED 200 of an application. In this example, substrate 40 is a conductive substrate. Working layer 210 includes layer 20 and includes an n-type AlN layer and a p-type AlN layer stacked on the n-type AlN layer. An n-side electrode 220 is provided on the lower surface of the substrate 40 and a p-side electrode 230 is provided on the upper surface of the operating layer 210 . The template 100 is not limited to the base member of the ultraviolet LED 200, but also the base member of the ultraviolet light receiving element, SAW (Surface Acoustic Wave) filter, BAW (Bulk Acoustic Wave) filter, FBAR (Film Bulk Acoustic Resonator) filter, and other filters are manufactured. It may be used as a member or the like for

<Preferred embodiment of the present invention>
Preferred embodiments of the present invention are described below.

(Appendix 1)
a substrate;
a nitride semiconductor layer laminated on the substrate, made of an aluminum-containing nitride semiconductor, and having a half width of (0002) diffraction of 1,000 seconds or less by X-ray rocking curve measurement;
has
The nitride semiconductor layer is directly bonded to the substrate,
The substrate is made of a material that is neither sapphire, silicon carbide nor a nitride semiconductor.
Nitride semiconductor template.

(Appendix 2)
The nitride semiconductor template according to appendix 1, comprising the substrate and the nitride semiconductor layer.

(Appendix 3)
a substrate;
a nitride semiconductor layer laminated on the substrate, made of an aluminum-containing nitride semiconductor, and having a half width of (0002) diffraction of 1,000 seconds or less by X-ray rocking curve measurement;
has
The nitride semiconductor layer is bonded to the substrate via an intermediate layer,
wherein the intermediate layer is made of a material that is neither sapphire, silicon carbide nor nitride semiconductor;
Nitride semiconductor template.

(Appendix 4)
3. The nitride semiconductor template according to appendix 3, comprising the substrate, the intermediate layer, and the nitride semiconductor layer.

(Appendix 5)
5. The nitride semiconductor template according to any one of Appendices 1 to 4, wherein the nitride semiconductor layer has a (0002) diffraction full width at half maximum measured by X-ray rocking curve measurement of 300 seconds or less.

(Appendix 6)
6. The nitride semiconductor template according to any one of Appendices 1 to 5, wherein the nitride semiconductor layer has a (0002) diffraction full width at half maximum measured by X-ray rocking curve measurement of 200 seconds or less.

(Appendix 7)
7. The nitride semiconductor template according to any one of Appendices 1 to 6, wherein the nitride semiconductor layer has a (0002) diffraction full width at half maximum measured by X-ray rocking curve measurement of 100 seconds or less.

(Appendix 8)
8. The nitride semiconductor template according to any one of appendices 1 to 7, wherein the nitride semiconductor layer has a (10-12) diffraction full width at half maximum measured by X-ray rocking curve measurement of 1,000 seconds or less.

(Appendix 9)
9. The nitride semiconductor template according to any one of Appendices 1 to 8, wherein the nitride semiconductor layer has a (10-12) diffraction full width at half maximum measured by X-ray rocking curve measurement of 500 seconds or less.

(Appendix 10)
10. The nitride semiconductor template according to any one of Appendices 1 to 9, wherein the nitride semiconductor layer has a (10-12) diffraction full width at half maximum measured by X-ray rocking curve measurement of 300 seconds or less.

(Appendix 11)
11. The nitride semiconductor template according to any one of Appendices 1 to 10, wherein the nitride semiconductor layer has a (10-12) diffraction full width at half maximum measured by X-ray rocking curve measurement of 200 seconds or less.

(Appendix 12)
12. The nitride semiconductor template according to any one of appendices 1 to 11, wherein the nitride semiconductor layer has an RMS surface roughness of 10 nm or less, preferably 5 nm or less.

(Appendix 13)
Appendices 1 to 1, wherein the group III polar plane of the nitride semiconductor layer is arranged as the surface of the template, and the nitrogen polar plane of the nitride semiconductor layer is arranged as the bonding surface between the nitride semiconductor layer and the substrate. 13. The nitride semiconductor template according to any one of 12.

(Appendix 14)
Appendices 1 to 1, wherein the nitrogen polar plane of the nitride semiconductor layer is arranged as the surface of the template, and the Group III polar plane of the nitride semiconductor layer is arranged as the bonding surface between the nitride semiconductor layer and the substrate. 13. The nitride semiconductor template according to any one of 12.

(Appendix 15)
15. The nitride semiconductor template according to any one of Appendices 1 to 14, wherein the substrate is a crystalline substrate or an amorphous substrate.

(Appendix 16)
5. The nitride semiconductor template according to appendix 3 or 4, wherein the intermediate layer is made of a conductive material.

(Appendix 17)
17. The nitride semiconductor template according to any one of Appendices 1 to 16, distributed as a member for manufacturing a device.

(Appendix 18)
growing a nitride semiconductor layer composed of an aluminum-containing nitride semiconductor on a first substrate composed of any one of sapphire, silicon carbide, and nitride semiconductor via a peelable film;
separating the nitride semiconductor layer from the first substrate with the peelable film as a boundary;
bonding the nitride semiconductor layer to a second substrate made of a material other than sapphire, silicon carbide, or a nitride semiconductor;
A method for manufacturing a nitride semiconductor template, comprising:

(Appendix 19)
19. The method of manufacturing a nitride semiconductor template according to appendix 18, wherein in the step of bonding the nitride semiconductor layer, the nitride semiconductor layer is directly bonded to the second substrate.

(Appendix 20)
19. The method of manufacturing a nitride semiconductor template according to appendix 18, wherein in the step of bonding the nitride semiconductor layer, the nitride semiconductor layer is bonded to the second substrate via an intermediate layer.

(Appendix 21)
The intermediate layer is made of metal,
21. The method of manufacturing a nitride semiconductor template according to appendix 20, wherein in the step of joining the nitride semiconductor layers, the nitride semiconductor layers are joined by fusion bonding of the metal.

(Appendix 22)
Between the step of growing the nitride semiconductor layer and the step of peeling off the nitride semiconductor layer,
An annealing step of reducing the dislocation density of the nitride semiconductor layer,
A method for manufacturing a nitride semiconductor template according to any one of Appendices 18 to 21.

(Appendix 23)
The annealing step is performed in a state in which two laminates obtained by growing the nitride semiconductor layer on the first substrate are superimposed so that the nitride semiconductor layers face each other.
A method for manufacturing a nitride semiconductor template according to appendix 22.

(Appendix 24)
A device manufactured using the nitride semiconductor template according to any one of Appendices 1 to 17 or by the method for manufacturing a nitride semiconductor template according to any one of Appendices 18 to 23.

REFERENCE SIGNS LIST 10 growth substrate 11 peelable film 20 nitride semiconductor layer 30 transfer substrate 40 support substrate 50 intermediate layer 100 nitride semiconductor template 200 ultraviolet LED
210 operating layer 220 n-side electrode 230 p-side electrode

Claims (11)

a substrate;
It is laminated on the substrate, is made of aluminum nitride, has a thickness of 50 nm or more and 800 nm or less, has a half width of (0002) diffraction of 300 seconds or less by X-ray rocking curve measurement, and has a half width of (10-12) diffraction. an aluminum nitride layer having a value width of 1,000 seconds or less;
has
the aluminum nitride layer is directly bonded to the substrate;
The substrate is made of a material that is neither sapphire, silicon carbide nor a nitride semiconductor.
Aluminum nitride template. a substrate;
It is laminated on the substrate, is made of aluminum nitride, has a thickness of 50 nm or more and 800 nm or less, has a half width of (0002) diffraction of 300 seconds or less by X-ray rocking curve measurement, and has a half width of (10-12) diffraction. an aluminum nitride layer having a value width of 1,000 seconds or less;
has
The aluminum nitride layer is bonded to the substrate via an intermediate layer,
wherein the intermediate layer is made of a material that is neither sapphire, silicon carbide nor nitride semiconductor;
Aluminum nitride template. 3. The aluminum nitride template according to claim 1, wherein the RMS surface roughness obtained by observing a 5 μm square region on the surface of said aluminum nitride layer with an atomic force microscope is 10 nm or less. Aluminum nitride template according to any one of claims 1 to 3, wherein the substrate is a crystalline or amorphous substrate. 3. The aluminum nitride template of claim 2, wherein said intermediate layer is composed of a conductive material. 2. The aluminum nitride template of claim 1, wherein a nitrogen polar plane of said aluminum nitride layer is positioned as a bonding plane between said aluminum nitride layer and said substrate. 2. The aluminum nitride template of claim 1, wherein an aluminum polar face of said aluminum nitride layer is positioned as a bonding face between said aluminum nitride layer and said substrate. 3. The aluminum nitride template according to claim 2, wherein a nitrogen polar plane of said aluminum nitride layer is arranged as a bonding plane between said aluminum nitride layer and said intermediate layer. 3. The aluminum nitride template of claim 2, wherein an aluminum polar face of said aluminum nitride layer is positioned as a bonding face between said aluminum nitride layer and said intermediate layer. The aluminum nitride template according to any one of claims 1 to 9, which is distributed as a member for manufacturing devices. A device having as part of its structure an aluminum nitride template according to any one of claims 1-10.

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