JP7239094B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a multi-chip semiconductor device, and more particularly to a semiconductor device in which a high voltage is applied to lead terminals.

In a hybrid vehicle or an electric vehicle, a battery for driving the vehicle is configured to output a predetermined driving voltage, and it is necessary to constantly monitor the output voltage of the battery. For example, a vehicle drive battery for a hybrid vehicle has an output voltage of about 200V, which is further boosted to be used at about 500V. Therefore, a voltage monitoring circuit is required to monitor the abnormal voltage. Also, in recent years, there is a demand for a high voltage monitoring circuit that monitors abnormal voltage exceeding 1000V.

FIG. 14 shows an example of a motor drive device. The motor drive device 100 boosts a DC high voltage (eg, 200 V) output from a high-voltage battery B insulated from the vehicle body by a boost converter 101 (boosted to 600 V, for example), and the boosted voltage is passed through a smoothing capacitor 102. The inverter circuit 103 converts the AC voltage into a three-phase AC voltage for driving the motor and supplies it to the motor M for driving the vehicle. A motor drive device of this type is described in, for example, Japanese Unexamined Patent Application Publication No. 2002-200011.

This type of motor drive device includes a voltage detection circuit 104 to monitor the boosted voltage, and detects voltages at a node N1 connected to the positive side of the battery B and a node N2 connected to the negative side of the battery B, Based on the detection result, a control circuit (not shown) outputs a control signal to the boost converter 101 and the inverter circuit 103 to control the motor drive.

A voltage detection circuit 104 for detecting high voltage can be composed of an operational amplifier and a resistor. FIG. 15 shows an example in which the voltage detection circuit 104 shown in FIG. 14 is composed of operational amplifiers and resistance elements. In voltage detection circuit 200 shown in FIG. 15, resistor 202a having a sufficiently large resistance value is an element for reducing the high voltage on the positive side of battery B, and terminal N11 is connected to the positive side of battery B shown in FIG. connected to the node N1 that The other end of the resistor 202a is connected to the non-inverting input terminal of the operational amplifier 201 and to one end of the resistor 202d. The resistor 202d is an element for applying a reduced voltage to the non-inverting input terminal of the operational amplifier, and is composed of an element having a small resistance value with respect to the resistor 202a having a large resistance value.

On the other hand, resistor 202b having a sufficiently large resistance value is an element for reducing the high voltage on the negative side of battery B, and terminal N12 is connected to node N2 connected to the negative side of battery B shown in FIG. The other end of resistor 202 b is connected to the inverting input terminal of operational amplifier 201 .

The resistor 202c is an element (feedback resistor) for determining the amplification gain of the operational amplifier 201. One end of the resistor 202c is connected to the inverting input terminal of the operational amplifier 201, and the other end is connected to the output terminal OUT of the operational amplifier 201. . A detection signal output from the voltage detection circuit 200 is input to a control circuit (not shown), and a control signal for controlling the operation of the boost converter 101 and the inverter circuit 103 is output from the control circuit to control the driving of the motor M. Become. The applicant of the present application has proposed a semiconductor device that configures this type of voltage detection circuit (Patent Document 2).

The applicant of the present application has also proposed a similar semiconductor device for monitoring high voltages of about 1000 V or more (Patent Document 3). This type of voltage detection circuit is used, for example, in the high voltage block 300 of a laser printer as shown in FIG. In the example shown in FIG. 16, a high voltage obtained by boosting by a booster circuit that constitutes a power supply circuit 301 is supplied via a constant voltage circuit 302 to a charging section, a developing section, or a transfer section. The voltage of the node N3 is detected by the voltage detection circuit 303 in order to monitor the variation of this supply voltage and control it to a predetermined constant voltage. A detection signal from the voltage detection circuit 303 is output to the differential amplifier circuit 304 , and the differential amplifier circuit 304 outputs the difference from the reference voltage to the arithmetic circuit 305 . Arithmetic circuit 305 controls constant voltage circuit 302 by outputting a control signal to constant voltage circuit 302 so that the voltage of node N3 is constant.

Such a voltage detection circuit 303 can also be configured with an operational amplifier and a resistance element. FIG. 17 shows an example in which the voltage detection circuit 303 shown in FIG. 16 is composed of operational amplifiers and resistance elements. A voltage detection circuit 400 shown in FIG. 17 has resistors 402a and 402b connected in series, which are elements for dividing the high voltage applied to a terminal N13. , the other end is connected to a reference voltage. A series connection point of the resistors 402 a and 402 b is connected to the inverting input terminal of the operational amplifier 401 , and the non-inverting input terminal of the operational amplifier 401 is applied with a reference voltage.

The resistor 402c is an element (feedback resistor) for determining the amplification gain of the operational amplifier 401. One end of the resistor 402c is connected to the inverting input terminal of the operational amplifier 401, and the other end is connected to the output terminal OUT of the operational amplifier 401. .

Japanese Patent Application Laid-Open No. 2009-201192 JP 2016-136608 A JP 2017-195242 A

By the way, the semiconductor device previously proposed by the applicant of the present application can be used under high voltage conditions without discharge between lead terminals. The common mode rejection ratio (CMRR) is low, and improvement in characteristics has been desired. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device that can be used under high voltage conditions and that has improved characteristics.

In order to achieve the above object, the invention according to claim 1 of the present application comprises a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip. , a semiconductor device mounted on a die pad, wire-connected between chip electrodes and lead terminals for external extraction, and sealed with a sealing resin, wherein the lead terminals sandwich the die pad. forming a first lead row and a second lead row each composed of a plurality of lead terminals arranged opposite to each other; and the first chip having a resistive element as a main component; The second chip has an operational amplifier and a capacitor as main components, and the lead terminal of the first lead line is composed of two lead terminals, and the lead terminal of the first lead line is rectangular. connected to two resistor chip electrodes formed on the first chip and arranged on one side of the first chip on the side of the first lead row; Another resistor chip electrode arranged on another side opposite to the one side from the electrode is an operational amplifier formed on the rectangular second chip and arranged on one side of the first chip. connected to a chip electrode or a lead terminal of the second lead line; another operational amplifier chip electrode connected to a lead terminal of the second lead line; and connecting the capacitor between at least two electrodes of the operational amplifier chip electrode. The voltage applied to the lead terminals of the first lead line is reduced by the resistor element formed on the first chip, and the inverting input terminal of the operational amplifier formed on the second chip or the non outputting to one of the inverting input terminals and outputting the output signal processed by the second chip from the lead terminal of the second lead line; and two lead terminals of the first lead line, The lead terminals are arranged apart from each other by a dimension that withstands the voltage applied to the lead terminals, and the sealing resin is filled between at least two lead terminals of the first lead row. do.

In the invention according to claim 2 of the present application, a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, In a semiconductor device in which wire connections are made between chip electrodes and between chip electrodes and lead terminals for external extraction, and the lead terminals are sealed with a sealing resin, the lead terminals are arranged to face each other with the die pad interposed therebetween. a first lead row and a second lead row each comprising a plurality of lead terminals; a resistor, a second resistor, a third resistor, and a fourth resistor; and the second chip has an operational amplifier and a capacitor as main components, and the capacitor is , a first capacitor, and a second capacitor; the lead terminal of the first lead string is composed of two lead terminals; one lead terminal of the first lead string is A resistor chip electrode formed on the square first chip and one resistor chip electrode of two resistor chip electrodes arranged on one side of the first chip on the side of the first lead row. and the other lead terminal of the first lead string is connected to another resistor tip of the two resistor tip electrodes. A separate resistor connected to a resistor chip electrode connected to the second resistor element for reducing the voltage applied to the electrode, and arranged on a side opposite to the one side from the two resistor chip electrodes. of the resistor chip electrodes, a resistor chip electrode for outputting a first reduced voltage by the first resistor element and a resistor chip electrode for outputting a second reduced voltage by the second resistor element are arranged in a rectangular shape Among the operational amplifier chip electrodes arranged on one side of the first chip formed on the second chip, the operational amplifier chip electrodes that become either the inverting input terminal or the non-inverting input terminal of the operational amplifier are respectively of the operational amplifier chip electrodes arranged on one side of the first chip formed on the second chip, the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the inverting input terminal. The third resistance element formed on the first chip and the first capacitor formed on the second chip are connected in parallel between the operational amplifier chip electrode and the operational amplifier chip electrode. A resistance chip electrode connected to one end of the fourth resistance element and one end of the second capacitor are connected to the operational amplifier chip electrode serving as the non-inverting input terminal, and a resistor connected to the other end of the fourth resistance element. A chip electrode, an operational amplifier chip electrode connected to the other end of the second capacitor, and the other operational amplifier chip electrode are connected to lead terminals of the second lead string, and a voltage is applied to the resistor chip electrode. The voltage applied to the lead terminals of the first lead row serving as input terminals is reduced by the first resistance element and the second resistance element formed on the first chip, and the second outputting to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the chip, and outputting the signal processed by the second chip from the lead terminal of the second lead line; two lead terminals of one lead row are arranged apart from each other by a dimension that withstands the voltage applied to the lead terminals;
A space between at least two lead terminals of the first lead row is filled with the sealing resin.

In the invention according to claim 3 of the present application, a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad . In a semiconductor device mounted, wire-connected between chip electrodes and between chip electrodes and lead terminals for external extraction, and sealed with a sealing resin, the lead terminals are opposed to each other with the die pad interposed therebetween. a first lead row and a second lead row each comprising a plurality of arranged lead terminals; the first chip having a resistive element as a main component; The chip has an operational amplifier and a capacitor as main components, and one of the resistor chip electrodes formed on the first chip serves as an input terminal. It is connected to one lead terminal of one lead row, and the resistor chip electrodes excluding the resistor chip electrode serving as the input terminal among the resistor chip electrodes are an operational amplifier chip formed on the second chip. Other of the operational amplifier chip electrodes that are connected to the operational amplifier chip electrodes of the electrodes or the lead terminals of the second lead row and that are not connected to the resistor chip electrodes are connected to the second lead. a voltage applied to one lead terminal of the first lead string connected to the lead terminals of the first lead string connected to the lead terminals of the first lead string, connecting the capacitor between at least two electrodes of the operational amplifier chip electrodes, and connecting the input terminal to the input terminal; The voltage is reduced by a resistive element formed on one chip, output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip, and signal-processed by the second chip. A signal is output from the lead terminal of the second lead row.

In the invention according to claim 4 of the present application, a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, In a semiconductor device in which wire connections are made between chip electrodes and between chip electrodes and lead terminals for external extraction, and the lead terminals are sealed with a sealing resin, the lead terminals are arranged to face each other with the die pad interposed therebetween. a first lead row and a second lead row each comprising a plurality of lead terminals; and the first chip has a resistive element as a main component, and the resistive element serves as a fifth resistor. element, a sixth resistance element, and a seventh resistance element; the second chip includes an operational amplifier and a third capacitor as main components; One resistor chip electrode connected to one end of the fifth resistor formed on the chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to one lead terminal of the first lead row. one end of the sixth resistor element is connected to the other end of the fifth resistor element, and the resistor chip electrode connected to the other end of the sixth resistor element is connected to the non-inverting input terminal of the operational amplifier. The resistor chip electrode connected to the operational amplifier chip electrode and connected to the common connection point between the other end of the fifth resistor element and one end of the sixth resistor element is connected to the operational amplifier chip electrode connected to the inverting input terminal of the operational amplifier. and the seventh resistor formed on the first chip and the second chip between the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the operational amplifier chip electrode serving as the inverting input terminal. The third capacitor formed in the second lead line is connected in parallel, and the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the other operational amplifier chip electrode are connected to the lead terminal of the second lead line, and the input The voltage applied to the lead terminals of the first lead row connected to the terminals is reduced by the fifth resistance element or the fifth and sixth resistance elements formed on the first chip. and outputting to the inverting input terminal of the operational amplifier formed on the second chip, and outputting the output signal processed by the second chip from the lead terminal of the second lead line.

In the invention according to claim 5 of the present application, a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, In a semiconductor device in which wire connections are made between chip electrodes and between chip electrodes and lead terminals for external extraction, and the lead terminals are sealed with a sealing resin, the lead terminals are arranged to face each other with the die pad interposed therebetween. a first lead row and a second lead row each comprising a plurality of lead terminals; and the first chip has a resistive element as a main component, and the resistive element serves as an eighth resistor. a ninth resistance element, a tenth resistance element, and an eleventh resistance element; and the second chip has an operational amplifier and a fourth capacitor as main components. One resistor chip electrode connected to one end of the eighth resistor element formed on the first chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to the first lead line. , one end of the ninth resistor element is connected to the other end of the eighth resistor element, and the other end of the eighth resistor element and one end of the ninth resistor element are connected to connected to the operational amplifier chip electrode connected to the non-inverting input terminal of the operational amplifier, and connected to one end of the tenth resistance element and the operational amplifier chip electrode serving as the output terminal of the operational amplifier The other end of the tenth resistance element is connected to one end of the eleventh resistance element, and the resistance chip electrode connected to the other end of the eleventh resistance element is set at a low power supply potential. , and an operational amplifier chip electrode connected to the inverting input terminal of the operational amplifier is connected to a common connection point between the other end of the tenth resistance element and one end of the eleventh resistance element, and the output terminal of the operational amplifier and the tenth resistance element formed on the first chip and the fourth capacitor formed on the second chip between the operational amplifier chip electrode serving as the inverting input terminal and the operational amplifier chip electrode serving as the inverting input terminal; are connected in parallel, an operational amplifier chip electrode serving as an output terminal of the operational amplifier, another operational amplifier chip electrode, a resistance chip electrode connected to the other end of the ninth resistance element, and one end of the tenth resistance element is connected to the lead terminal of the second lead line, and the voltage applied to the lead terminal of the first lead line connected to the input terminal is formed on the first chip. Said eighth and the ninth resistance element, output to the non-inverting input terminal of the operational amplifier formed on the second chip, and the eleventh resistance element formed on the first chip and An amplification gain is determined by the tenth resistance element, output to an inverting input terminal of the operational amplifier formed on the second chip, and an output signal processed by the second chip is supplied to the second lead line. is output from the lead terminal of the

In the invention according to claim 6 of the present application, a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, In a semiconductor device in which wire connections are made between chip electrodes and between chip electrodes and lead terminals for external extraction, and the lead terminals are sealed with a sealing resin, the lead terminals are arranged to face each other with the die pad interposed therebetween. a first lead row and a second lead row each comprising a plurality of lead terminals; a thirteenth resistance element, a fourteenth resistance element, and a fifteenth resistance element; and the second chip has an operational amplifier and a fifth capacitor as main components. One resistor chip electrode connected to one end of the twelfth resistor formed on the first chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to the first lead line. , one end of the 13th resistor element is connected to the other end of the 12th resistor element, and the other end of the 12th resistor element and one end of the 13th resistor element are connected to The resistor chip electrode connected to the common connection point of is connected to the operational amplifier chip electrode connected to the inverting input terminal of the operational amplifier, and connected to the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the other end of the thirteenth resistor element. and a resistor chip electrode connected to a common connection point between one end of the fourteenth resistor element and the other end of the fifteenth resistor element is connected to the non-inverting input terminal of the operational amplifier. connecting a resistor chip electrode connected to an electrode and connected to the other end of the fourteenth resistor element to a reference voltage, and connecting a resistor chip electrode connected to one end of the fifteenth resistor element to a low power supply potential; the thirteenth resistance element formed on the first chip between the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the operational amplifier chip electrode serving as the inverting input terminal; The fifth capacitor formed is connected in parallel, an operational amplifier chip electrode serving as an output terminal of the operational amplifier, another operational amplifier chip electrode, and a resistor chip electrode connected to the other end of the thirteenth resistor element; A resistance chip electrode connected to the other end of the fourteenth resistance element is connected to a lead terminal of the second lead row, and the twelfth resistance element formed on the first chip. and the thirteenth resistance element to determine an amplification gain, output to the inverting input terminal of the operational amplifier formed on the second chip, and apply the low-level power supply potential to the first resistor formed on the first chip. The pressure is reduced by the 15 resistance elements and the 14th resistance element, the voltage is output to the non-inverting input terminal of the operational amplifier formed on the second chip, and the output signal processed by the second chip is processed by the second chip. is output from the lead terminal of the lead row.

The invention according to claim 7 of the present application is the semiconductor device according to any one of claims 1 to 6, wherein the first chip and the second lead string connected to a potential lower than the voltage input to the first chip are connected to each other. A plate-shaped dielectric member is arranged between the lead terminals of the first chip and the capacitance of the dielectric member is connected in series with the capacitance of the first chip.

According to claim 8 of the present application, in the semiconductor device according to claim 1 or 2, a A plate-shaped dielectric member is arranged, and the capacitance of the first chip and the capacitance of the dielectric member are connected in series.

The invention according to claim 9 of the present application is directed to the semiconductor device according to any one of claims 1 to 6, wherein the lead terminals of the second lead row to which part of the chip electrodes formed on the second chip are connected are A plate-shaped dielectric member is placed on the die pad, the second chip is placed on the dielectric member, and the capacitance of the first chip is equal to the capacitance of the first chip. The capacitance of the dielectric member and the capacitance of the second chip are connected in series.

According to claim 10 of the present application, in the semiconductor device according to any one of claims 1 to 9, the back side of the die pad is resin-sealed with the sealing resin.

The invention according to claim 11 of the present application is directed to the semiconductor device according to any one of claims 1 to 10, wherein a connection between any lead terminal of the second lead row and a resistor chip electrode formed on the first chip is provided. Alternatively, the connection between any one of the lead terminals of the second lead row and the operational amplifier chip electrodes formed on the second chip is made through auxiliary wiring formed on the first chip or the second chip. Alternatively, they are connected via a relay chip mounted on the die pad.

The invention according to claim 12 of the present application is directed to the semiconductor device according to any one of claims 1 to 11, wherein one of the lead terminals of the second lead row is a relay including an ESD protection element mounted on the die pad. The resistor chip electrode formed on the first chip and the operational amplifier chip electrode formed on the second chip are connected via the chip.

The semiconductor device of the present invention was able to improve oscillation stability and transient CMRR characteristics. In particular, in the present invention, by forming the capacitor on the second chip on which the operational amplifier is formed, even when a high voltage exceeding 1000 V is applied, the resistance element formed on the first chip is Due to the pressure reducing function, the resistance elements formed on the first chip and the operational amplifiers and capacitors formed on the second chip that performs the main signal processing will not be damaged, and discharge between the lead terminals will not occur, resulting in stable operation. signal processing is possible.

In the semiconductor device of the present invention, the lead terminals and the suspension leads of the die pad are arranged only in the first lead row and the second lead row. They are arranged at sufficiently distant positions so that a high voltage can be applied to the lead rows of the first lead row, and the operational amplifiers and capacitors are arranged so as not to be affected by the high voltages, enabling stable signal processing.

The semiconductor device of the present invention employs a predetermined connection structure to connect the lead terminals of the first lead row and the second lead row, even when a package structure that is generally used is adopted. Stable signal processing becomes possible by arranging operational amplifiers and capacitors so as not to be affected by high voltage while preventing discharge from occurring between lead terminals.

The semiconductor device of the present invention has a structure in which the capacitance of the plate-shaped dielectric member is connected in series with the capacitance of the first chip to which a high voltage is input, thereby increasing the voltage that can be applied to the first chip. Can be set.

In the semiconductor device of the present invention, since the back side of the die pad is resin-sealed with a sealing resin, there is also an advantage that discharge between the lead terminals and the die pad can be suppressed.

In the semiconductor device of the present invention, two chips are mounted on a die pad, and the chip electrodes of each chip are connected to lead terminals at predetermined positions. As a result, even if the resistor chip electrode or operational amplifier chip electrode and the lead terminal are wire-connected, the dimension between the wires can be secured, and the wire is deformed due to contact with the wire bonding jig during wire bonding. Also, it is possible to prevent problems such as contact of wires due to the pressure of the injected sealing resin during resin sealing.

The semiconductor device of the present invention also has the advantage that it is possible to add an ESD protection element to the relay chip and that the chip electrodes connected to the ESD protection element can be effectively protected from electrostatic breakdown.

1 is a diagram illustrating a voltage detection circuit according to a first embodiment of the invention; FIG. FIG. 4 is an explanatory diagram of a connection structure when the voltage detection circuit of the first embodiment of the present invention is mounted on a lead frame; FIG. 5 is an explanatory diagram of another connection structure when the voltage detection circuit of the first embodiment of the present invention is mounted on a lead frame; FIG. 5 is an explanatory diagram of another connection structure when the voltage detection circuit of the first embodiment of the present invention is mounted on a lead frame; FIG. 5 is a diagram illustrating a voltage detection circuit according to a second embodiment of the present invention; FIG. FIG. 9 is an explanatory diagram of a connection structure when the voltage detection circuit of the second embodiment of the present invention is mounted on a lead frame; FIG. 10 is a diagram illustrating a voltage detection circuit according to a third embodiment of the present invention; FIG. FIG. 10 is an explanatory diagram of a connection structure when the voltage detection circuit of the third embodiment of the present invention is mounted on a lead frame; It is a figure explaining the voltage detection circuit of the 4th Example of this invention. FIG. 10 is an explanatory diagram of a connection structure when the voltage detection circuit of the fourth embodiment of the present invention is mounted on a lead frame; FIG. 11 is an explanatory diagram of a connection structure when the voltage detection circuit of the fifth embodiment of the present invention is mounted on a lead frame; FIG. 11 is an explanatory diagram of a connection structure when the voltage detection circuit of the sixth embodiment of the present invention is mounted on a lead frame; FIG. 11 is an explanatory diagram of a connection structure when the voltage detection circuit of the seventh embodiment of the present invention is mounted on a lead frame; 1 is an explanatory diagram of a general motor drive circuit; FIG. 1 is an explanatory diagram of a general voltage detection circuit; FIG. 1 is an explanatory diagram of a general high voltage block; FIG. 1 is an explanatory diagram of a general voltage detection circuit; FIG.

A semiconductor device according to the present invention is a semiconductor device to which a high voltage can be applied and which has high oscillation stability and transient CMRR. Specifically, a semiconductor device to which a high voltage of about 1000 V can be applied has been realized. Therefore, in the present invention, the chip is divided into a first chip that decompresses (steps down) the directly applied high voltage signal and a second chip that processes the signal depressurized (stepped down) via the first chip. By adopting a multi-chip structure and placing circuit elements for improving oscillation stability or improving transient CMRR characteristics on the second chip, signal processing can be performed while maintaining characteristics that can be applied to high voltages. Therefore, the characteristics of the circuit elements have been improved. Examples of the present invention will be described in detail below.

A first embodiment of the present invention will be described by taking a voltage detection circuit for detecting a high voltage exceeding 1000V as an example. FIG. 1 is an explanatory diagram of a voltage detection circuit according to a first embodiment of the present invention. As shown in FIG. 1, the circuit configuration itself of the voltage detection circuit of the present invention is not greatly different from the circuit configuration of known voltage detection circuits.

Specifically, a resistor 2a (equivalent to a first resistor element) having a sufficiently large resistance value (for example, about 30 MΩ) is an element for reducing the high voltage on the positive side of battery B, and terminal B1 is connected to FIG. is connected to the node N1 connected to the positive electrode side of the battery B shown in FIG. The other end of the resistor 2a is connected to the non-inverting input terminal of the operational amplifier 1 and to one end of the resistor 2d (corresponding to a fourth resistance element). Here, in the present invention, since the first chip 10 in which the resistance element is formed and the second chip 20 in which the operational amplifier 1 is formed are formed of separate chips, A wire 3 is connected to the non-inverting input terminal of the operational amplifier 1 . The other end of the resistor 2d is connected to a reference voltage that determines the voltage of the output terminal OUT of the operational amplifier 1 when there is no signal.

On the other hand, a resistor 2b (equivalent to a second resistor element) having a sufficiently large resistance value (for example, about 30 MΩ) is an element for reducing the high voltage on the negative side of the battery B, and the terminal B2 is connected to the battery shown in FIG. It is connected to the node N2 connected to the negative electrode side of B. The other end of resistor 2 b is connected to the inverting input terminal of operational amplifier 1 . A wire 3 connects the other end of the resistor 2 b to the inverting input terminal of the operational amplifier 1 .

A resistor 2c (corresponding to a third resistor) is an element (feedback resistor) for determining the amplification gain of the operational amplifier 1. One end of the resistor 2c is connected to the inverting input terminal of the operational amplifier 1, and the other end is connected to the operational amplifier 1. are connected by wires 3 to the output terminals of . The output terminal OUT of the operational amplifier 1 is connected to a control circuit (not shown), and the control circuit outputs a control signal for controlling the operation of the boost converter 101 and the inverter circuit 103 shown in FIG. It will be.

In the present invention, a capacitor 4 a (corresponding to a first capacitor) and a capacitor 4 b (corresponding to a second capacitor) are formed on a second chip 20 . The capacitor 4a has one end connected to the output terminal of the operational amplifier 1 and the other end connected to the inverting input terminal of the operational amplifier 1, thereby being connected in parallel with the resistor 2c, thereby improving the oscillation stability of the operational amplifier 1.

One end of the capacitor 4b is connected to the non-inverting input terminal of the operational amplifier 1, and the other end is connected to the low-level power supply voltage V- to ensure impedance matching of the input terminal of the operational amplifier 1 and to prevent transient CMRR. have improved.

In the example shown in FIG. 1, the auxiliary wiring 5 is formed on the first chip 10, and the auxiliary wiring 5 is connected to the output terminal OUT. This configuration is provided so as to be suitable for forming wire connections when mounted on a lead frame as will be described later, and is not necessarily essential.

FIG. 2 shows a connection state when the voltage detection circuit described in FIG. 1 is mounted on a lead frame for forming the voltage detection circuit using the first chip 10 composed of a resistive element and the second chip 20 composed of an operational amplifier and a capacitor. Schematically. A resistor chip electrode is formed on the first chip 10, and an operational amplifier chip electrode is formed on the second chip. In the following explanation, the connection between the chip electrodes will be explained as the connection of terminals between constituent elements. do.

As shown in FIG. 2, a first chip 10 formed with a resistance element and a second chip 20 formed with an operational amplifier and a capacitor are mounted on the die pad 6 . This lead frame has two lead terminals L1 and L2 (corresponding to the first lead row) on the left side of the drawing, and seven lead terminals L4 to L10 and suspension leads L3 and L11 (second lead row) of the die pad 6 on the right side of the drawing. equivalent to a lead row).

A node B1 connected to the positive electrode side of the battery B is connected to the lead terminal L1, and a node B2 connected to the negative electrode side of the battery B is connected to the lead terminal L2. One end of the resistor 2a is connected to the lead terminal L1, and the other end of the resistor 2a is connected to the non-inverting input terminal of the operational amplifier 1 formed on the second chip 20 using the wire 3. FIG. The other end of resistor 2a is connected to one end of resistor 2d, and the other end of resistor 2d is connected to a desired reference voltage from lead L10. One end of the resistor 2b is connected to the lead terminal L2, and the other end of the resistor 2b is connected to the inverting input terminal of the operational amplifier 1 formed on the second chip 20 using the wire 3. FIG.

The output terminal of the operational amplifier 1 formed on the second chip 20 is connected by a wire 3 to one end of the resistor 2c formed on the first chip 10. The other end of this resistor 2c is connected to the second chip 20. The resistor 2c becomes a feedback resistor of the operational amplifier 1 by being connected to the inverting input terminal of the operational amplifier 1 formed in . The output terminal of the operational amplifier 1 is connected to one end of the capacitor 4a formed on the second chip 20, and the other end of the capacitor 4a is connected to the inverting input terminal of the operational amplifier 1. FIG. As a result, the resistor 2c and the capacitor 4a are connected in parallel between the output terminal and the inverting input terminal of the operational amplifier 1, thereby improving the oscillation stability. The connection between the capacitor 4a and the operational amplifier 1 can be formed by internal wiring.

The power supply terminals of the operational amplifier 1 are formed on the second chip 20. The power supply terminal V+ to which the high power supply voltage is applied is the lead terminal L5, and the power supply terminal V- to which the low power supply voltage is applied is the lead terminal. Each lead terminal is connected to a terminal L9, and a power supply voltage is supplied from each lead terminal. The power supply terminal V- becomes the ground potential.

Also, the capacitor 4b is connected between the non-inverting input terminal of the operational amplifier 1 and the power supply terminal V- to ensure the impedance matching of the input terminal of the operational amplifier 1 and improve the transient CMRR. The connection between the capacitor 4b and the operational amplifier 1 and the connection between the capacitor 4b and the power supply terminal V- can also be formed by internal wiring.

The output terminal of the operational amplifier 1 can be directly connected to the lead terminal L4, which serves as the output terminal, by the wire 3. However, in the example shown in FIG. In order to avoid contact, it is also possible to connect to lead terminal L4 by wire 3 via auxiliary wiring 5 separately formed on the first chip.

For the same purpose, as shown in FIG. 3, it is possible to provide a relay chip 8 on which auxiliary wiring 5 is formed. Furthermore, an ESD protection element (indicated as ESD) can be formed on the relay chip 8 to protect the operational amplifier from surge damage such as static electricity.

As shown in FIGS. 2 and 3, the lead terminals L1 and L2 to which a high voltage is applied are spaced apart by a predetermined distance according to the voltage applied to each lead terminal in order to secure a predetermined creepage distance. ing. It can be seen that in this embodiment, the interval between the lead terminal L1 and the lead terminal L2 of the first lead row is wider than the interval between the lead terminals of the second lead row.

Further, the lead terminal L1 not only maintains a creeping distance from the lead terminal L2, but is also arranged at a position apart from the other lead terminals L4 to L10 by a predetermined distance. The lead terminal L2 and the other lead terminals L4 to L10 are similarly arranged at positions separated by a predetermined dimension. Similarly, in order to maintain the creepage distance, the suspension leads L3 and L11 of the die pad 6 are also arranged on the right side of the drawing (the side of the second lead row).

Furthermore, in order to prevent discharge between the lead terminals L1 and L2 extending outside from the resin-encapsulated semiconductor device, a resin layer 7 corresponding to the thickness of the lead terminals is provided between the lead terminals. filled. In FIG. 3, only the resin layer 7 filled in the lead terminals exposed from the semiconductor device body in which the first chip 10, the second chip 20, and the wires 3 are sealed with the sealing resin is shown. . Since the formation of the resin layer 7 is performed simultaneously with the resin sealing of the semiconductor device body, the resin layer 7 is also formed between the lead terminals of the second lead row.

When a higher voltage is applied, it is preferable to adopt a structure in which the die pad 6 is not exposed from the semiconductor device main body in this resin sealing process. FIG. 4 schematically shows a cross-sectional structure of a semiconductor device suitable for application of a higher voltage. As shown in FIG. 4, the die pad 6 can be sealed in the semiconductor device body 9 by bending the suspension leads so that the back surface of the die pad 6 is not exposed from the sealing resin.

In this embodiment, since the capacitor added for improving the characteristics is formed on the second chip, the capacitor is not adversely affected even during operation in which a high voltage is applied. As a result, a semiconductor device to which a high voltage can be applied and which can perform stable signal processing can be realized.

Although the lead terminals L6 to L8 are not connected in FIGS. 2 and 3, they may be used to realize connection without using the auxiliary wiring 5 or the relay chip 8. FIG. Also, if it is not necessary for connection, there is no problem even if the lead frame structure does not have L6 to L8.

Next, the second embodiment will be described by taking as an example a case of configuring a voltage detection circuit that detects a high voltage exceeding 1000 V by adopting a package structure that is generally used in a general semiconductor device manufacturing process. . FIG. 5 is an explanatory diagram of a voltage detection circuit according to a second embodiment of the present invention. As shown in FIG. 5, the voltage detection circuit configuration itself of the present invention is not greatly different from the circuit configuration of known voltage detection circuits.

Specifically, a resistor 2e (corresponding to a fifth resistive element) and a resistor 2f (corresponding to a sixth resistive element), which are connected in series and have a sufficiently large resistance value, are connected to the high voltage applied to the terminal N13. The terminal N13 is connected to the node N3 shown in FIG. 16, and the other end is connected to the reference voltage REF. A common connection point between the resistors 2e and 2f is connected to an inverting input terminal of the operational amplifier 21, and a non-inverting input terminal of the operational amplifier 21 is connected to a common connection point between the reference voltage REF and the resistor 2f. Since the first chip 10a in which the resistance element is formed and the second chip 20a in which the operational amplifier is formed are composed of separate chips, wires 23 are used to connect the chips.

A resistor 2g (corresponding to a seventh resistor) is an element (feedback resistor) for determining the amplification gain of the operational amplifier 21. One end of the resistor 2g is connected to the inverting input terminal of the operational amplifier 21, and the other end is connected to the operational amplifier 21. is connected to the output terminal OUT together with the output terminal of . The output terminal OUT of this operational amplifier 21 is connected to the differential amplifier circuit 304 shown in FIG. Arithmetic circuit 305 outputs a control signal to constant voltage circuit 302 so that the voltage of node N3 is constant.

In the present invention, a capacitor 4c (corresponding to a third capacitor) is formed on the second chip 20a. One end of the capacitor 4c is connected to the output terminal of the operational amplifier 21, and the other end is connected to the inverting input terminal of the operational amplifier 21, thereby being connected in parallel with the resistor 2g to improve oscillation stability.

Note that this embodiment does not include the capacitor 4b described in the first embodiment. In the first embodiment, the circuit configuration detects the potential difference between the positive electrode side and the negative electrode side of the battery. This is because there is no need for a capacitor corresponding to the capacitor 4b intended to improve CMRR characteristics.

FIG. 6 schematically shows a connection structure when the voltage detection circuit described in FIG. 5 is mounted on a lead frame in order to form the voltage detection circuit using the first chip 10a made up of a resistive element and the second chip 20a made up of an operational amplifier and a capacitor. clearly shown.

As shown in FIG. 6, a first chip 10a having a resistive element and a second chip 20a having an operational amplifier and a capacitor are mounted on a die pad 26. As shown in FIG. This lead frame has four lead terminals L21 to L24 (corresponding to a first lead row) on the left side of the drawing, four lead terminals L25 to L28 (corresponding to a second lead row) on the right side of the drawing, and a die pad. Twenty-six suspension leads L29, L30 extend therebetween. This type of lead frame is generally used as a lead frame for semiconductor devices.

Lead terminal L21 is connected to node N3 shown in FIG. 16 to which a high voltage is applied. A series circuit of resistors 2e and 2f has the other end connected to lead terminal L28, which is connected to a reference voltage. A common connection point of the resistors 2e and 2f is connected through a wire 23 to an inverting input terminal of an operational amplifier 21 formed on the second chip 20a. Similarly, the other end of the resistor 2f is connected through a wire 23 to the non-inverting input terminal of an operational amplifier 21 formed on the second chip 20a.

The output terminal of the operational amplifier 21 formed on the second chip 20a is connected to the lead terminal L27 by the wire 23. As shown in FIG. One end of the resistor 2g is also connected to the lead terminal L27 using the wire 23. FIG. The other end of the resistor 2g is connected to the inverting input terminal of the operational amplifier 21 formed on the second chip 20a, so that the resistor 2g functions as a feedback resistor of the operational amplifier 21. FIG. The output terminal of the operational amplifier 21 is connected to one end of the capacitor 4c formed on the second chip 20a, and the other end of the capacitor 4c is connected to the inverting input terminal of the operational amplifier 21. FIG. As a result, the resistor 2g and the capacitor 4c are connected in parallel between the output terminal and the inverting input terminal of the operational amplifier 21, thereby improving the oscillation stability. The connection between the capacitor 4c and the operational amplifier 21 can be formed by internal wiring.

The power supply terminals of the operational amplifier 21 are formed on the second chip 20a. voltage is supplied.

In the example shown in FIG. 6, the lead terminal L27 and the output terminal of the operational amplifier 21 are directly connected by the wire 23, and one end of the resistor 2g is also directly connected by the wire 23. FIG. In such a case, an auxiliary wiring or a relay chip can be added as appropriate to avoid contact between wires. Furthermore, it is possible to form an ESD protection element on the relay chip.

The lead terminal L21 to which a high voltage is applied needs to be arranged apart from other terminals by a predetermined distance. Therefore, other lead terminals L22, L23, and L24 of the first lead row are not connected.

When a higher voltage is applied to the lead terminal L21, it is preferable to adopt a structure in which the die pad 26 is not exposed from the semiconductor device body by resin sealing as described in the first embodiment.

Also in this embodiment, since the capacitor added to the operational amplifier for improving the characteristics is formed on the second chip, the capacitor is not adversely affected even during operation in which a high voltage is applied. As a result, a semiconductor device to which a high voltage can be applied and which can perform stable signal processing can be realized.

A third embodiment will now be described. The semiconductor device described in the second embodiment can obtain the same effect even if the circuit configuration is changed. FIG. 7 is an explanatory diagram of a voltage detection circuit according to a third embodiment of the present invention.

As shown in FIG. 7, a resistor 2h (corresponding to an eighth resistive element) and a resistor 2i (corresponding to a ninth resistive element) having sufficiently large resistance values connected in series are applied to a terminal N13. It is an element for reducing a high voltage, and the terminal N13 is connected to the node N3 shown in FIG. 16, and the other end is connected to the reference voltage REF (not shown). The common connection point of the resistors 2h and 2i is connected to the non-inverting input terminal of the operational amplifier 21, and the inverting input terminal of the operational amplifier 21 is connected to the resistor 2k (corresponding to the eleventh resistive element) for determining the amplification gain and the resistor 2j. (corresponding to the tenth resistance element) are connected. Since the first chip 10a in which the resistance element is formed and the second chip 20a in which the operational amplifier is formed are composed of separate chips, wires 23 are used to connect the chips.

The resistor 2j is an element (feedback resistor) for determining the amplification gain of the operational amplifier 21. One end of the resistor 2j is connected to the inverting input terminal of the operational amplifier 21, and the other end is connected to the output terminal of the operational amplifier 21 and the output terminal OUT. It is The output terminal OUT of this operational amplifier 21 is connected to the differential amplifier circuit 304 shown in FIG. Arithmetic circuit 305 outputs a control signal to constant voltage circuit 302 so that the voltage of node N3 is constant.

In the present invention, a capacitor 4d (corresponding to a fourth capacitor) is formed on the second chip 20a. The capacitor 4d has one end connected to the output terminal of the operational amplifier 21 and the other end connected to the inverting input terminal of the operational amplifier 21, thereby being connected in parallel with the resistor 2j to improve the oscillation stability. As in the second embodiment, no capacitor corresponding to the capacitor 4b is provided.

FIG. 8 schematically shows a connection structure when the voltage detection circuit described in FIG. 7 is mounted on a lead frame in order to form the voltage detection circuit by using the first chip 10a made up of a resistive element and the second chip 20a made up of an operational amplifier and a capacitor. clearly shown.

As shown in FIG. 8, a first chip 10a having a resistive element and a second chip 20a having an operational amplifier and a capacitor are mounted on a die pad 26. As shown in FIG. This lead frame has four lead terminals L21 to L24 (corresponding to the first lead row) on the left side of the drawing and four lead terminals L25 to L28 (corresponding to the second lead row) on the right side of the drawing. Twenty-six suspension leads L29, L30 extend therebetween. This type of lead frame is generally used as a lead frame for semiconductor devices.

Lead terminal L21 is connected to node N3 shown in FIG. 16 to which a high voltage is applied. A series circuit of resistors 2h and 2i has the other end connected to lead terminal L28, which is connected to a reference voltage. A common connection point of the resistors 2h and 2i is connected through a wire 23 to a non-inverting input terminal of an operational amplifier 21 formed on the second chip 20a. A common connection point of the resistors 2j and 2k is connected to an inverting input terminal of an operational amplifier 21 using a wire 23. FIG. The other terminal of the resistor 2j is connected to the lead terminal L27 together with the output terminal of the operational amplifier 21, and the other terminal of the resistor 2k is connected to the lead terminal L25 to which the lower power supply potential of the operational amplifier is connected. .

The output terminal of the operational amplifier 21 formed on the second chip 20a is connected to the lead terminal L27 by the wire 23. As shown in FIG. One end of the resistor 2j is also connected to the lead terminal L27 using the wire 23. FIG. The other end of the resistor 2j is connected to the inverting input terminal of the operational amplifier 21 formed on the second chip 20a, so that the resistor 2j functions as a feedback resistor of the operational amplifier 21. FIG. The output terminal of the operational amplifier 21 is connected to one end of the capacitor 4d formed on the second chip 20a, and the other end of the capacitor 4d is connected to the inverting input terminal of the operational amplifier 21. FIG. As a result, the resistor 2j and the capacitor 4d are connected in parallel between the output terminal and the inverting input terminal of the operational amplifier 21, and the oscillation stability of the operational amplifier 21 is improved. The connection between the capacitor 4c and the operational amplifier 21 can be formed by internal wiring. Among the power supply terminals of the operational amplifier 21, the higher power supply voltage V+ is supplied from the lead terminal L26.

In the example shown in FIG. 8, the lead terminal L27 and the output terminal of the operational amplifier 21 are directly connected by the wire 23, and one end of the resistor 2j is also directly connected by the wire 23. FIG. In such a case, an auxiliary wiring or a relay chip can be added as appropriate to avoid contact between wires. Furthermore, it is possible to form an ESD protection element on the relay chip.

The lead terminal L21 to which a high voltage is applied needs to be arranged apart from other terminals by a predetermined distance. Therefore, other lead terminals L22, L23, and L24 of the first lead row are not connected.

When a higher voltage is applied to the lead terminal L21, it is preferable to adopt a structure in which the die pad 26 is not exposed from the semiconductor device body by resin sealing as described in the first embodiment.

Also in this embodiment, since the capacitor added to the operational amplifier for improving the characteristics is formed on the second chip, the capacitor is not adversely affected even during operation in which a high voltage is applied. As a result, a semiconductor device to which a high voltage can be applied and which can perform stable signal processing can be realized.

A fourth embodiment will now be described. The semiconductor devices described in the second and third embodiments can obtain the same effect even if the circuit configuration is further changed. FIG. 9 is an explanatory diagram of a voltage detection circuit according to a fourth embodiment of the present invention.

As shown in FIG. 9, a resistor 2l (corresponding to a twelfth resistor) having a sufficiently large resistance value is an element for reducing the high voltage applied to the terminal N13, and the terminal N13 connects to the node N3 shown in FIG. connect to. The other end of the resistor 2l is connected to the inverting input terminal of the operational amplifier 21 and also to the resistor 2m (corresponding to the thirteenth resistance element). A non-inverting input terminal of the operational amplifier 21 is connected to a common connection point of the resistor 2n (corresponding to the 14th resistive element) and the resistor 2o (corresponding to the 15th resistive element). A reference voltage REF is applied to the other end of the resistor 2n, and a low power supply voltage is applied to the other end of the resistor 2o. Since the first chip 10a in which the resistance element is formed and the second chip 20a in which the operational amplifier is formed are composed of separate chips, wires 23 are used to connect the chips.

The resistor 2m is an element (feedback resistor) for determining the amplification gain of the operational amplifier 21. One end of the resistor 2m is connected to the inverting input terminal of the operational amplifier 21, and the other end is connected to the output terminal of the operational amplifier 21 and the output terminal OUT. It is connected to the. The output terminal OUT of this operational amplifier 21 is connected to the differential amplifier circuit 304 shown in FIG. Arithmetic circuit 305 outputs a control signal to constant voltage circuit 302 so that the voltage of node N3 is constant.

In the present invention, a capacitor 4e (corresponding to a fifth capacitor) is formed on the second chip 20a. One end of the capacitor 4e is connected to the output terminal of the operational amplifier 21, and the other end is connected to the inverting input terminal of the operational amplifier 21, so that the capacitor 4e is connected in parallel with the resistor 2m to improve the oscillation stability. Also in this embodiment, like the second embodiment, a capacitor corresponding to the capacitor 4b is not provided.

FIG. 10 schematically shows a connection structure when the voltage detection circuit described in FIG. 9 is mounted on a lead frame in order to form the voltage detection circuit using a first chip 10a consisting of a resistive element and a second chip 20a consisting of an operational amplifier and a capacitor. clearly shown.

As shown in FIG. 10, a first chip 10a having a resistive element and a second chip 20a having an operational amplifier and a capacitor are mounted on a die pad 26. As shown in FIG. This lead frame has four lead terminals L21 to L24 (corresponding to the first lead row) on the left side of the drawing and four lead terminals L25 to L28 (corresponding to the second lead row) on the right side of the drawing. Twenty-six suspension leads L29, L30 extend therebetween. This type of lead frame is generally used as a lead frame for semiconductor devices.

Lead terminal L21 is connected to node N3 shown in FIG. 16 to which a high voltage is applied. The other end of the series circuit of resistors 2l and 2m is connected to lead terminal L27, and lead terminal L27 serves as an output terminal. A common connection point of the resistors 2l and 2m is connected through a wire 23 to an inverting input terminal of an operational amplifier 21 formed on the second chip 20a. A common connection point of the resistors 2n and 2o is connected to a non-inverting input terminal of an operational amplifier 21 using a wire 23. FIG. The other terminal of the resistor 2n is connected to the reference voltage, and the other terminal of the resistor 2o is connected to the lead terminal L25 to which the lower power supply potential of the operational amplifier is connected.

The output terminal of the operational amplifier 21 is connected to one end of the capacitor 4 d formed on the second chip 20 a, and the other end of the capacitor 4 e is connected to the inverting input terminal of the operational amplifier 21 . As a result, the resistor 2m and the capacitor 4e are connected in parallel between the output terminal and the inverting input terminal of the operational amplifier 21, thereby improving the oscillation stability. The connection between the capacitor 4e and the operational amplifier 21 can be formed by internal wiring. Among the power supply terminals of the operational amplifier 21, the higher power supply voltage V+ is supplied from the lead terminal L26.

In the example shown in FIG. 10, the lead terminal L27 and the output terminal of the operational amplifier 21 are directly connected by the wire 23, and one end of the resistor 2m is also directly connected by the wire 23. FIG. In such a case, an auxiliary wiring or a relay chip can be added as appropriate to avoid contact between wires. Furthermore, it is possible to form an ESD protection element on the relay chip.

The lead terminal L21 to which a high voltage is applied needs to be arranged apart from other terminals by a predetermined distance. Therefore, other lead terminals L22, L23, and L24 of the first lead row are not connected.

When a higher voltage is applied to the lead terminal L21, it is preferable to adopt a structure in which the die pad 26 is not exposed from the semiconductor device body by resin sealing as described in the first embodiment.

Also in this embodiment, since the capacitor added to the operational amplifier for improving the characteristics is formed on the second chip, the capacitor is not adversely affected even during operation in which a high voltage is applied. As a result, a semiconductor device to which a high voltage can be applied and which can perform stable signal processing can be realized.

Next, a fifth embodiment will be described. It is possible to further increase the breakdown voltage of the semiconductor devices described in the first to fourth embodiments. FIG. 11 shows an explanatory diagram of the fifth embodiment. The semiconductor device described in the first embodiment will be described below as an example.

A major feature of this embodiment is that a plate-like dielectric member 30 is laminated under the first chip 10 . For the dielectric member 30, for example, a flat substrate made of ceramics and having a thickness of about 200 μm can be used. FIG. 11 schematically shows a cross-sectional view passing between the lead terminal L1 and the lead terminal L10 of the semiconductor device shown in FIG. Here, the lead terminal L1 is a lead terminal to which a high voltage is applied. The lead terminal L10 corresponds to a lead terminal connected to a potential lower than the voltage input to the lead terminal L1.

As shown in FIG. 11, a capacitance C10 of the first chip 10, a capacitance C30 of the dielectric member 30, and a capacitance C20 of the second chip 20 are connected in series between the lead terminal L1 and the lead terminal L10. It is configured. Here, the capacitance of the first chip 10 is the capacitance formed by the electrode pads of the resistance element, the resistance pattern, etc. formed on the semiconductor substrate with an insulating film (such as an oxide film) interposed therebetween. Similarly, the capacitance of the second chip C20 is the capacitance of the electrode pad of the operational amplifier, the impurity region, and the like, and the capacitance of the capacitor formed on the semiconductor substrate. The capacitance C30 of the dielectric member is a capacitance value determined by the thickness, size, and dielectric constant of the material of the flat substrate. The capacitance C30 of the flat plate-shaped dielectric member can be set to a size that allows the capacitive voltage dividing effect to be obtained by appropriately setting the thickness inside the dielectric portion to a desired thickness.

As a result, when a high voltage is applied to the first chip 10, the voltage applied to the capacitance of the first chip 10 is reduced by voltage division, and a high withstand voltage of the semiconductor device can be realized.

Such an arrangement of dielectric members can also be applied to the semiconductor device described in the second embodiment.

Next, a sixth embodiment will be described. Also in this embodiment, it is possible to increase the breakdown voltage of the semiconductor device described in the first to fourth embodiments. FIG. 12 is an explanatory diagram of a modification of the fifth embodiment. Since the capacitance C10 of the first chip 10, the capacitance C30 of the dielectric member 30, and the capacitance C20 of the second chip 20 are connected in series between the lead terminal L1 and the lead terminal L10, as shown in FIG. Alternatively, a plate-like dielectric member 30 may be laminated under the second chip 20 . In this case, the thickness of the first chip C1 is 400 μm, and the thickness of the second chip C2 is 200 μm.

Also in this embodiment, when a high voltage is applied to the first chip 10 by adding the flat plate-shaped dielectric member 30, the voltage applied to the capacitance of the first chip 10 is reduced by voltage division, and the semiconductor It becomes possible to realize a high breakdown voltage of the device. Such an arrangement of dielectric members can also be applied to the semiconductor device described in the second embodiment.

Next, a seventh embodiment will be described. In the fifth and sixth embodiments described above, the case where the die pad 6 is brought into a floating state and is brought to a low potential through the second chip 20 has been explained. However, the arrangement of the lead terminals in the first embodiment is such that the suspension leads L3 and L11 of the die pad 6 extend to the second lead row. creepage distance can be maintained.

FIG. 13 schematically shows a cross-sectional view passing between the lead terminal L1 and the lead terminal L11. Also in this case, the capacitance C10 of the first chip 10 and the capacitance C30 of the dielectric member 30 are connected in series between the lead terminal L1 and the lead terminal L11. By configuring in this way, similarly to the above, when a high voltage is applied to the first chip C10, the voltage applied to the capacitance of the first chip C10 is reduced by voltage division, and a high withstand voltage of the semiconductor device is realized. It becomes possible to

It should be noted that, in the present embodiment, it is difficult to apply the present embodiment because the hanging lead terminal L29 cannot have a sufficient distance from the lead terminal L1 in the examples described in the second to fifth embodiments.

Instead of the dielectric member 30, an insulating resin layer is integrally formed on the back surface of the first chip 10 or the second chip 20, and this resin layer is used as a flat dielectric member. is also possible.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments. For example, when connecting the capacitor and the operational amplifier, an example of connecting by internal wiring has been described, but it is also possible to connect by wire or other connection method.

1, 21: operational amplifier, 2, 22: resistor, 3, 23: wire, 4, 24: capacitor, 5, 25: auxiliary wiring, 6, 26: die pad, 7, 27: resin layer, 8, 28: relay chip , 9, 29: semiconductor device body, 10, 10a: first chip, 20, 20a: second chip, 30: dielectric member, 100: motor tube control circuit, 101: step-up inverter, 102: smoothing capacitor, 103: Inverter circuit, 104: Voltage detection circuit, 200: Voltage detection circuit, 201: Operational amplifier, 202: Resistor, 300: High voltage block, 301: Power supply circuit, 400: Voltage detection circuit

Claims (12)

A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, between chip electrodes and between chip electrodes. In a semiconductor device in which a lead terminal for external extraction is wire-connected and sealed with a sealing resin,
the lead terminals constitute a first lead row and a second lead row each composed of a plurality of lead terminals arranged facing each other with the die pad interposed therebetween;
the first chip has a resistive element as a main component;
the second chip has an operational amplifier and a capacitor as main components;
The lead terminal of the first lead row is composed of two lead terminals, and the lead terminal of the first lead row is a resistor chip electrode formed on the rectangular first chip and is the first lead terminal. are connected to two resistor chip electrodes arranged on one side of the chip on the first lead row side of the chip, and another resistor chip electrode arranged on another side opposite to the one side from the resistor chip electrode. The resistor chip electrodes are connected to the operational amplifier chip electrodes formed on the rectangular second chip and arranged on one side of the first chip or to the lead terminals of the second lead row, and connected to the other operational amplifier. A chip electrode is connected to the lead terminal of the second lead line, the capacitor is connected between at least two electrodes of the operational amplifier chip electrode, and the voltage applied to the lead terminal of the first lead line is the voltage applied to the lead terminal of the first lead line. The pressure is reduced by a resistive element formed on the first chip, the voltage is output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip, and the signal is processed by the second chip. outputting an output signal from the lead terminal of the second lead row;
the two lead terminals of the first lead row are arranged apart from each other by a dimension that withstands the voltage applied to the lead terminals;
A semiconductor device, wherein the sealing resin is filled between at least two lead terminals of the first lead row. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, between chip electrodes and between chip electrodes. In a semiconductor device in which a lead terminal for external extraction is wire-connected and sealed with a sealing resin,
the lead terminals constitute a first lead row and a second lead row each composed of a plurality of lead terminals arranged facing each other with the die pad interposed therebetween;
The first chip has a resistive element as a main component, and the resistive element includes a first resistive element, a second resistive element, a third resistive element, and a fourth resistive element. being and
the second chip includes an operational amplifier and a capacitor as main components, the capacitor including a first capacitor and a second capacitor;
The lead terminal of the first lead row is composed of two lead terminals, and one lead terminal of the first lead row is a resistor chip electrode formed on the rectangular first chip, One of two resistor chip electrodes arranged on one side of the first chip on the first lead line side is connected to the first resistor element for reducing the voltage applied to one of the resistor chip electrodes. The other lead terminal of the first lead string is connected to the second resistive element for reducing the voltage applied to the other of the two resistor tip electrodes. The first reduced voltage is applied by the first resistance element of another resistor chip electrode connected to the resistor chip electrode connected to the resistor chip electrode and arranged on the other side opposite to the one side from the two resistor chip electrodes. and a resistor chip electrode for outputting a second reduced voltage by the second resistor element are arranged on one side of the first chip formed on the rectangular second chip. of the operational amplifier chip electrodes arranged on the first chip side formed on the second chip, respectively connected to the operational amplifier chip electrodes that become either the inverting input terminal or the non-inverting input terminal of the operational amplifier; Of the operational amplifier chip electrodes arranged on one side, the operational amplifier chip electrode formed on the first chip between the operational amplifier chip electrode that becomes the output terminal of the operational amplifier and the operational amplifier chip electrode that becomes the inverting input terminal. 3 and the first capacitor formed on the second chip are connected in parallel, and one end of the fourth resistor is connected to the operational amplifier chip electrode serving as the non-inverting input terminal of the operational amplifier. a resistor chip electrode that connects one end of the second capacitor to the resistor chip electrode to be connected and the other end of the fourth resistor element, and an operational amplifier chip electrode that connects to the other end of the second capacitor; The other operational amplifier chip electrode is connected to the lead terminal of the second lead line, and receives the voltage applied to the lead terminal of the first lead line, which is the terminal for inputting the voltage applied to the resistor chip electrode. The pressure is reduced by the first resistance element and the second resistance element formed on the first chip, and the voltage is applied to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip. and outputting the signal processed by the second chip from the lead terminals of the second lead string; the lead terminals are spaced apart from each other by a dimension that withstands the voltage applied to the lead terminals;
A semiconductor device, wherein the sealing resin is filled between at least two lead terminals of the first lead row. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad , and are arranged between chip electrodes and between chip electrodes. In a semiconductor device in which chip electrodes and lead terminals for external extraction are wire-connected and sealed with a sealing resin,
the lead terminals constitute a first lead row and a second lead row each composed of a plurality of lead terminals arranged facing each other with the die pad interposed therebetween;
the first chip has a resistive element as a main component;
the second chip has an operational amplifier and a capacitor as main components;
One of the resistor chip electrodes formed on the first chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to one lead terminal of the first lead row. and,
Of the resistor chip electrodes, the resistor chip electrodes other than the resistor chip electrodes serving as the input terminals are part of the operational amplifier chip electrodes formed on the second chip or the leads of the second lead line. another of the operational amplifier chip electrodes connected to a terminal and not connected to the resistor chip electrode is connected to a lead terminal of the second lead row and is connected to at least two electrodes of the operational amplifier chip electrode; The voltage applied to one lead terminal of the first lead row connected to the input terminal is reduced by a resistive element formed on the first chip, and the second The output signal is output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the chip, and the output signal processed by the second chip is output from the lead terminal of the second lead line. and semiconductor devices. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, between chip electrodes and between chip electrodes. In a semiconductor device in which a lead terminal for external extraction is wire-connected and sealed with a sealing resin,
the lead terminals constitute a first lead row and a second lead row each composed of a plurality of lead terminals arranged facing each other with the die pad interposed therebetween;
the first chip has a resistive element as a main component, the resistive element including a fifth resistive element, a sixth resistive element, and a seventh resistive element;
the second chip has an operational amplifier and a third capacitor as main components;
One resistor chip electrode connected to one end of the fifth resistor formed on the first chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to one end of the first lead row. one end of the sixth resistance element is connected to the other end of the fifth resistance element; A resistor chip electrode connected to a common connection point between the other end of the fifth resistor element and one end of the sixth resistor element is connected to the inverting input terminal of the operational amplifier. The seventh resistance element connected to the operational amplifier chip electrode and formed on the first chip between the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the operational amplifier chip electrode serving as the inverting input terminal; The third capacitors formed on two chips are connected in parallel, and the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the other operational amplifier chip electrode are connected to the lead terminals of the second lead string. death,
The voltage applied to the lead terminal of the first lead row connected to the input terminal is controlled by the fifth resistance element or the fifth and sixth resistance elements formed on the first chip. depressurized, output to the inverting input terminal of the operational amplifier formed on the second chip, and the output signal processed by the second chip is output from the lead terminal of the second lead string. semiconductor device. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, between chip electrodes and between chip electrodes. In a semiconductor device in which a lead terminal for external extraction is wire-connected and sealed with a sealing resin,
the lead terminals constitute a first lead row and a second lead row each composed of a plurality of lead terminals arranged facing each other with the die pad interposed therebetween;
The first chip has resistance elements as main components, and the resistance elements include an eighth resistance element, a ninth resistance element, a tenth resistance element, and an eleventh resistance element. being and
the second chip has an operational amplifier and a fourth capacitor as main components;
One resistor chip electrode connected to one end of the eighth resistor element formed on the first chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to one end of the first lead line. one end of the ninth resistor element is connected to the other end of the eighth resistor element; and the other end of the eighth resistor element and one end of the ninth resistor element are connected in common. The resistor chip electrode connected to the point is connected to the operational amplifier chip electrode connected to the non-inverting input terminal of the operational amplifier, and the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the resistor chip electrode connected to one end of the tenth resistor element. , the other end of the tenth resistance element is connected to one end of the eleventh resistance element, and the resistance chip electrode connected to the other end of the eleventh resistance element is connected to a low power supply potential. , an operational amplifier chip electrode connected to an inverting input terminal of the operational amplifier is connected to a common connection point between the other end of the tenth resistance element and one end of the eleventh resistance element, and the operational amplifier chip serves as an output terminal of the operational amplifier. The tenth resistance element formed on the first chip and the fourth capacitor formed on the second chip are connected in parallel between the electrode and the operational amplifier chip electrode serving as the inverting input terminal. , an operational amplifier chip electrode serving as an output terminal of the operational amplifier, another operational amplifier chip electrode, a resistor chip electrode connected to the other end of the ninth resistor element, and one end of the tenth resistor element. a resistor tip electrode connected to a lead terminal of the second lead row;
The voltage applied to the lead terminals of the first lead row connected to the input terminal is reduced by the eighth resistance element and the ninth resistance element formed on the first chip, and the second Output to the non-inverting input terminal of the operational amplifier formed on the chip, determine the amplification gain by the eleventh resistance element and the tenth resistance element formed on the first chip, and output to the second chip , and the output signal processed by the second chip is output from the lead terminal of the second lead line. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, between chip electrodes and between chip electrodes. In a semiconductor device in which a lead terminal for external extraction is wire-connected and sealed with a sealing resin,
the lead terminals constitute a first lead row and a second lead row each composed of a plurality of lead terminals arranged facing each other with the die pad interposed therebetween;
The first chip has resistance elements as main components, and the resistance elements include a 12th resistance element, a 13th resistance element, a 14th resistance element, and a 15th resistance element. being and
the second chip has an operational amplifier and a fifth capacitor as main components;
One resistor chip electrode connected to one end of the twelfth resistor formed on the first chip serves as an input terminal, and the resistor chip electrode serving as the input terminal is connected to one end of the first lead line. one end of the thirteenth resistor element is connected to the other end of the twelfth resistor element; and the other end of the twelfth resistor element and one end of the thirteenth resistor element are connected in common. The resistor chip electrode connected to the point is connected to the operational amplifier chip electrode connected to the inverting input terminal of the operational amplifier, and the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the resistor chip electrode connected to the other end of the thirteenth resistor element. and the resistor chip electrode connected to the common connection point between one end of the fourteenth resistor element and the other end of the fifteenth resistor element is connected to the operational amplifier chip electrode connected to the non-inverting input terminal of the operational amplifier. a resistor chip electrode connected to the other end of the fourteenth resistor element is connected to a reference voltage; a resistor chip electrode connected to one end of the fifteenth resistor element is connected to a low power supply potential; The thirteenth resistance element formed on the first chip between the operational amplifier chip electrode serving as the output terminal and the operational amplifier chip electrode serving as the inverting input terminal, and the resistance element formed on the second chip The fifth capacitor is connected in parallel, an operational amplifier chip electrode serving as an output terminal of the operational amplifier, another operational amplifier chip electrode, a resistance chip electrode connected to the other end of the thirteenth resistance element, and the fourteenth capacitor. the resistor chip electrode connected to the other end of the resistor element is connected to the lead terminal of the second lead row,
An amplification gain is determined by the twelfth resistance element and the thirteenth resistance element formed on the first chip, is output to the inverting input terminal of the operational amplifier formed on the second chip, and is output to the low-level gain. is reduced by the fifteenth resistance element and the fourteenth resistance element formed on the first chip, and output to the non-inverting input terminal of the operational amplifier formed on the second chip, A semiconductor device, wherein an output signal processed by said second chip is output from a lead terminal of said second lead row. The semiconductor device according to any one of claims 1 to 6,
A plate-like dielectric member is arranged between the first chip and the lead terminal of the second lead line connected to a potential lower than the voltage input to the first chip, thereby 1. A semiconductor device, wherein a capacitance of a chip and a capacitance of said dielectric member are connected in series. 3. The semiconductor device according to claim 1, wherein
A plate-like dielectric member is arranged between the first chip and the die pad connected to a voltage lower than the voltage input to the first chip, so that the capacitance of the first chip and the dielectric 1. A semiconductor device characterized by connecting a capacitance of an electrical member in series. The semiconductor device according to any one of claims 1 to 6,
A lead terminal of the second lead row to which a part of the chip electrode formed on the second chip is connected is connected to a potential lower than the input voltage, and a plate-shaped dielectric member is provided on the die pad. placing the second chip on the dielectric member, and connecting the capacitance of the first chip, the capacitance of the dielectric member, and the capacitance of the second chip in series; A semiconductor device characterized by: The semiconductor device according to any one of claims 1 to 9,
A semiconductor device, wherein the back side of the die pad is resin-sealed with the sealing resin. The semiconductor device according to any one of claims 1 to 9,
Connection between any lead terminal of the second lead row and the resistor chip electrode formed on the first chip, or connection between any lead terminal of the second lead row and the second chip The connection with the operational amplifier chip electrode is connected via an auxiliary wiring formed on the first chip or the second chip, or a relay chip mounted on the die pad. A semiconductor device characterized by: The semiconductor device according to any one of claims 1 to 11,
Any one of the lead terminals of the second lead row is connected to a resistor chip electrode formed on the first chip via a relay chip equipped with an ESD protection element mounted on the die pad, and a resistor chip electrode formed on the second chip. A semiconductor device, characterized by being connected to an operational amplifier chip electrode formed on a chip.

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