JP7243765B2 - Imaging element and imaging device - Google Patents

Description

The present invention relates to an imaging device and an imaging device.

The imaging apparatus described in Patent Document 1 outputs imaging signals read out from the pixel unit a plurality of times within one frame period in N channels in parallel. A frame memory accumulates the imaging signals for a plurality of frames. The frame addition circuit adds signals of a plurality of frames read out from the frame memory to create a standard one-frame signal.

JP 2009-239398 A

However, in the method of adding pixel data converted into digital values, the addition is performed including the conversion error generated when the image signal is A/D converted.

The imaging device of the present invention comprises: a plurality of pixels; a first holding unit that holds a first pixel signal from a first pixel among the plurality of pixels; a first holding circuit having a second holding unit for holding a second pixel signal from a second pixel arranged at a position on the side of the pixel; and converting a first output signal output from the first holding circuit into a digital signal. and a first connecting portion electrically connecting between the first holding circuit and the first comparator.
Further, the imaging device of the present invention includes: a plurality of pixels; a first holding unit that holds a first pixel signal from a first pixel of the plurality of pixels; a first holding circuit having a second holding section for holding a second pixel signal from a second pixel arranged at a position on the column direction side; and amplifying a first output signal output from the first holding circuit. and a first connecting portion electrically connecting the first holding circuit and the first amplifying portion.

Further, an imaging apparatus of the present invention includes any one of the imaging elements described above.

1 is a diagram showing the configuration of an A/D conversion circuit (ADC) according to a first embodiment of the invention; FIG. FIG. 10 is a time chart for explaining the operation without weighted addition operation; FIG. FIG. 10 is a time chart for explaining the operation when there is a weighted addition operation; FIG. It is a figure which shows the structure of the A/D-conversion circuit concerning the 2nd Embodiment of this invention. 5 is a time chart for explaining the operation (operation with weighted addition) of the ADC 12A shown in FIG. 4; 5 is a time chart for explaining the operation (operation without weighted addition) of the ADC 12A shown in FIG. 4; It is a figure which shows the structure of the A/D-conversion circuit concerning the 3rd Embodiment of this invention. 8 is a time chart for explaining the operation of ADC 12B shown in FIG. 7; FIG. It is a figure which shows the example of a solid-state imaging device. 3 is a diagram showing the configuration of a pixel circuit; FIG. 1 is a diagram showing a configuration of a normal A/D conversion circuit; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[First embodiment]
(Description of the pixel circuit)
First, the pixel PX forming the pixel portion in the CMOS solid-state imaging device will be briefly described. FIG. 10 is a diagram showing the configuration of a pixel circuit, and is a circuit diagram showing one pixel PX, vertical signal line VL, and constant current source TD.
The pixel circuit shown in FIG. 10 includes a photodiode PD as a photoelectric conversion unit, a floating diffusion FD as a charge-voltage conversion unit that receives charge and converts the charge into voltage, and a reset transistor RST that resets the potential of the floating diffusion FD. , a selection transistor SEL that supplies a signal corresponding to the potential of the floating diffusion FD to the vertical signal line VL, a transfer transistor TX as a charge transfer unit that transfers charges from the photodiode PD to the floating diffusion FD, and the floating diffusion FD. and an amplification transistor SF as an amplification section that outputs a signal corresponding to the potential.

In FIG. 10, VDD is the power supply potential. Note that the transistors SF, TX, RST, and SEL of the pixel PX are all nMOS transistors. Gates of the transfer transistors TX are connected in common for each row, and a control signal φTX for controlling the transfer transistors TX is supplied from the vertical scanning circuit 3 to the gates. Gates of the reset transistors RST are connected in common for each row, and a control signal φRST for controlling the reset transistors RST is supplied thereto from the vertical scanning circuit 3 (see FIG. 9). Gates of the selection transistors SEL are connected in common for each row, and a control signal φSEL for controlling the selection transistors SEL is supplied thereto from the vertical scanning circuit 3 .

The photodiode PD of each pixel PX generates signal charges according to the amount of incident light (object light). The transfer transistor TX of each pixel PX turns on during the high level period of the control signal φTX to transfer the charge of the photodiode PD to the floating diffusion FD.
The reset transistor RST is turned on during the high level period of the control signal φRST (during the power supply potential VDD) to reset the floating diffusion FD.

The amplification transistor SF has a drain connected to the power supply potential VDD, a gate connected to the floating diffusion FD, and a source connected to the drain of the selection transistor SEL. The source of the select transistor SEL is connected to the vertical signal line VL. The constant current source TD allows current to flow through the vertical signal line VL when the selection transistor SEL of the pixel PX corresponding to the vertical signal line VL is turned on.

The amplification transistor SF of each pixel PX outputs a voltage to the vertical signal line VL via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the control signal φSEL, and connects the source of the amplification transistor SF to the vertical signal line VL.

(Description of the overview of the A/D conversion circuit of the first embodiment)
First, the outline of the A/D conversion circuit (ADC12) of the first embodiment will be described.
FIG. 1 is a diagram showing the configuration of an A/D conversion circuit according to an embodiment of the invention. The circuit shown in FIG. 1 is configured by connecting an integrating ADC 12C to the rear stage of the PGA 11. The PGA 11 and the ADC 12 are connected to each vertical signal line VL of each column in the solid-state imaging device 1 shown in FIG. It is provided in

The operations of the PGA 11 and ADC 12 are controlled by the control unit 21 . This control unit 21 controls the ON/OFF (connection/disconnection) of each switch in the PGA 11 and ADC 12 (that is, switching between a conducting state and a non-conducting state), and also controls each signal used in the ADC 12 ( VRT, VRB, VRAMP, etc.). The control unit 21 includes a coarse conversion control unit 22 that controls coarse conversion processing operations performed in the ADC 12, and a fine conversion control unit 23 that controls fine conversion processing operations.

The control unit 21 also includes a counter 24 that is used when performing coarse conversion and fine conversion processing, a register that holds digital data of A/D conversion results, and the like. Note that the counter 24 includes a 3-bit counter 24A for counting the upper 3-bit value used in coarse conversion and a lower 12-bit counter 24A for use in fine conversion when converting the pixel signal into a digital value with a resolution of 14 bits. and a 12-bit counter 24B for counting bit values (coarse conversion and fine conversion will be described later).

The ADC 12 shown in FIG. 1 differs in configuration from the normal ADC 12C shown in FIG. 11 in that switches S9, S10, S11, S12 and S13 are newly added to the capacitors C1 to C4. Also, the configuration is different in that a switch S13 is added to the node Vcm so that the node Vcm and the node Vcm' can be selectively connected. Other configurations are the same as those of the ADC 12C shown in FIG. For this reason, the same reference numerals are attached to the corresponding structures.
In the ADC 12 shown in FIG. 1, when all the switches S9, S10, S11, S12, and S13 are constantly turned on (connected), the ADC 12 shown in FIG. 1 and the normal ADC 12C shown in FIG. result in a similar configuration (an ADC configuration without weighted addition), and the operation is also similar.

The switch S9 is a switch for holding the pixel signal Sig1 in the capacitor C1, the switches S10 and S11 are switches for holding the pixel signal Sig2 in the capacitors C2 and C3, and the switch S12 is a switch for holding the pixel signal Sig3. to the capacitor C4. For example, when the pixel signal Sig1 is input to the node Vcm and the switch S9 is turned on (switches S10, S11, S12, and S13 are in the off (open) state), the pixel signal Sig1 passes through the switch S9 to the capacitor C1. is charged, and the pixel signal Sig1 is held in this capacitor C1.

After the capacitors C1, C2, C3 and C4 are charged in order by the signals Sig1, Sig2 and Sig3 respectively, the switches S9 to S12 are simultaneously turned on (but the switch S13 is off) to generate a potential on the node Vcm. weighted addition of the signals Sig1, Sig2 and Sig3 is performed. The weighting ratio at this time is determined by the capacitance ratio of capacitor C1, capacitor C2+C3, and capacitor C4.

Here, the capacitances of the capacitors C1, C2, C3 and C4 are C1, C2, C3 and C4, and the voltage levels of the signals Sig1, Sig2 and Sig3 are Sig1, Sig2 and Sig3. Then, in this example, the charge Q1 held in the capacitor C1 with respect to the signal Sig1 is
Q1=C1×Sig1.
With respect to the signal Sig2, the charge Q2 held in the capacitors C2 and C3 is
Q2=(C2+C3)*Sig2.
For signal Sig3, the charge Q3 held in capacitor C4 is
Q3=C4*Sig2.

Therefore, the total charge Qtotal held in the capacitors C1, C2, C3, C4 is
Qtotal=C1*Sig1+(C2+C3)*Sig2+C4*Sig3,
becomes.
Also, the total capacitance Ctotal of the capacitors C1, C2, C3 and C4 is as follows because the capacitors C1, C2, C3 and C4 are connected in parallel
Ctotal=C1+(C2+C3)+C4.

Therefore, when the switches S9, S10, S11, and S12 are simultaneously turned on and the switch S13 is turned off, the potential of the node Vcm is represented by Vcm.
Vcm=Qtotal/(C1+C2+C3+C4).

Here, if C1=C2=C3=C4=C,
Qtotal=C*Sig1+2*C*Sig2+C*Sig3.
Therefore, since Vcm=Qtotal/Ctotal,
Vcm={C×Sig1+2×C×Sig2+C×Sig3}/(4×C),

Therefore, Vcm={Sig1+2*Sig2+Sig3}/4.
In this manner, weighted addition of "1:2:1" can be performed on the signals Sig1, Sig2, and Sig3.

As described above, in the ADC 12 shown in FIG. 1, the pixel signal output from the PGA 11 is weighted and added as an analog signal to generate a potential at the node Vcm, and the potential generated at the node Vcm is A/D conversion is performed. Therefore, when weighted addition is performed on the pixel signals output from the PGA 11, analog weighted addition can be performed without conversion errors in the ADC 12 (for example, errors due to noise and quantization errors). can be done.
Further, since the weighted addition is performed using the capacitors C1 to C4 for coarse conversion provided in the ADC 12, analog weighted addition can be performed without increasing the layout area.

In the above example, weighting is performed by assigning one capacitor C1, two capacitors C2 and C3, and one capacitor C4 to each of the three pixel signals Sig1, Sig2, and Sig3. An example in which the ratio of addition is "1:2:1" has been shown, but it is not limited to this. For example, it can be set to a desired ratio such as "1:3:1", "1:5:1", or "2:3:3" (however, the capacitors C1 to There is a limit due to the number of C8). Furthermore, by setting the weighting ratio to "1:1:1", it is possible to average the three pixel signals Sig1, Sig2 and Sig3.
Further, the number of pixel signals to be subjected to weighted addition is not limited to three, and weighted addition can be performed to five pixel signals or seven pixel signals (basically an odd number) (however, There is a limit due to the number of capacitors C1 to C8 prepared for course conversion).

(Explanation of configuration of ADC 12 having weighted addition function)
Next, the configuration of ADC 12 shown in FIG. 1 will be described in detail. The ADC 12 is an integrating A/D conversion circuit having a weighted addition function. The ADC 12 reads pixel signals output from the vertical signal lines VL of the solid-state imaging device through the PGA 11, and converts the pixel signals into A/D conversion is performed by

PGA11 includes a differential amplifier (AM1), switch PGA_AZ, capacitor C11, and variable capacitor C12. The reference voltage VREF is connected to the positive (+) input of the differential amplifier AM1, and the pixel signal input is connected to the negative (-) input through the capacitor C11. The output of the differential amplifier AM1 is connected to the negative feedback variable capacitor C12 and the switch PGA_AZ, as well as to the switch SPL in the ADC12. Also, the gain of the PGA 11 can be changed by the variable capacitor C12. Note that the maximum value of the signal output from the PGA 11 is, for example, +1V.

ADC 12 includes switches SPL and TSW. ADC 12 also includes capacitors C1-C8, switches S1a, S1b-S8a, S8b, S9-S13, SX, and comparator CP1. The switches SPL and TSW, and the switches S1a, S1b to S8a, S8b, S9 to S13, and SX are indicated by symbols of contact type switches, but in reality, they are composed of, for example, MOS transistors and semiconductor switches. It is what is done.
The amplified pixel signal output from PGA11 is connected to the positive (+) input of comparator CP1 via switch SPL and switch S13. The output of the comparator CP1 is connected to the negative (-) input of the comparator CP1 via a switch ADC_AZ, and a capacitor C10 for holding pixel dark state information (dark potential Vdark) is connected.

Capacitors C1-C8 are equal capacitance capacitors. The capacitors C1-C8 are capacitively coupled with node Vcm or node Vcm'. Then, in the coarse conversion described later, by sequentially switching the switches S1a, S1b to S8a, S8b connected to these capacitors (for example, the switch S1a is turned off and the switch S1b is turned on), the capacitors C1 to C8 The voltage of the counter electrode is switched between signals VRT and VRB to determine where the potential of node Vcm falls within eight ranges. Note that the signal VRT is, for example, a +2 V signal, and the signal VRT is, for example, a +1 V signal (note that the voltage of the signal VRT is denoted by the same symbol VRT, and the voltage of the signal VRB is denoted by the same symbol VRB). there is). Based on the signals VRT and VRB, a signal (VRT-VRB) with an amplitude of 1 V is generated as described later (corresponding to the output voltage of 1 V from the PGA 11). Note that the aforementioned potential Vdark is approximately 0V.

Then, as shown in FIG. 1, one end of the capacitor C1 is connected to the node Vcm (the potential of the node Vcm may be denoted by the same symbol Vcm) via the switch S9. The other end of the capacitor C1 is connected to the signal line VRT (the signal line for the signal VRT) through the switch S1a, and the other end of the capacitor C1 is connected to the signal line VRB (the signal line for the signal VRB) through the switch S1b. connected to
One end of capacitor C2 is connected to node Vcm through switch S10, and the other end of capacitor C2 is connected to signal line VRT through switch S2a and to signal line VRB through switch S2b. .

One end of the capacitor C3 is connected to the node Vcm via the switch S11, and the other end of the capacitor C3 is connected to the signal line VRT via the switch S3a and to the signal line VRB via the switch S3b. . Note that the switch S11 and the switch S10 are switches that are both turned on or turned off at the same time.
One end of capacitor C4 is connected to node Vcm through switch S12, and the other end of capacitor C4 is connected to signal line VRT through switch S4a and to signal line VRB through switch S4b. .

One end of the capacitor C5 is connected to the node Vcm', and the other end of the capacitor C5 is connected to the signal line VRT through the switch S5a and to the signal line VRB through the switch S5b.
One end of capacitor C6 is connected to node Vcm', and the other end of capacitor C6 is connected to signal line VRT through switch S6a and to signal line VRB through switch S6b.
One end of the capacitor C7 is connected to the node Vcm', and the other end of the capacitor C7 is connected to the signal line VRT through the switch S7a and to the signal line VRB through the switch S7b.
One end of the capacitor C8 is connected to the node Vcm', and the other end of the capacitor C8 is connected to the signal line VRT through the switch S8a and to the signal line VRB through the switch S8b. Furthermore, the other end of the capacitor C8 is connected to the signal line VRAMP through the switch SX.
The node Vcm and the node Vcm' are connected by the switch S13, and the node Vcm and the node Vcm' are selectively brought into a connected state or an open (disconnected) state through this step S13.

The ADC 12 shown in FIG. 1 operates as a normal A/D conversion circuit (ADC 13C without weighted addition shown in FIG. 11) by keeping the switches S9 to S13 constantly on, and the switches S9 to By controlling the on/off of S13, it operates as an A/D conversion circuit having a weighted addition function.

(Explanation of operation of ADC 12 without weighted addition)
First, in the case where the ADC 12 shown in FIG. 1 is operated as a normal A/D conversion circuit (an A/D conversion circuit without weighted addition) by keeping the switches S9 to S13 in the ON state constantly. An example of

FIG. 2 is a time chart for explaining the operation of ADC 12 when weighted addition is not performed. Note that the processing shown in FIG. 2 is the same processing as normal integration type A/D conversion processing (A/D conversion processing performed in the solid-state imaging device described in Patent Document 1). The flow of the processing will be briefly described below with reference to the time chart shown in FIG. 2 (for details, refer to the imaging apparatus described in Patent Document 1).

The A/D conversion operation in this ADC 12 is performed by two stages of A/D conversion operations of coarse conversion and fine conversion. Further, the switches S9 to S13 remain on during the operation of this A/D conversion process. As for the switches S1 to S8 connected to the capacitors C1 to C8, the switches S1a to S8a are initially in the ON state, and the switches S1b to S8b are in the OFF state.

Then, when the A/D conversion process in the ADC 12 is started by the control command from the control unit 21, the dark capture is started at time T1, and the switch PGA_AZ for the PGA auto-zero signal, the switch ADC_AZ for the auto-zero signal, and the sampling signal switch SPL is turned on. As a result, the comparator CP1 holds information about the dark state of the pixel as a potential (dark potential Vdark) at the positive potential of the capacitor C10. Then, when the dark capture started at time T1 is completed, switch PGA_AZ, switch ADC_AZ, and switch SPL are turned off.
After that, at time T2, signal acquisition (reading of pixel signals) is started, and when the switch SPL is turned on again, the pixel signal output from the PGA 11 is held at the node Vcm as the potential Vcm. Then, when this dark capturing is completed, the switch SPL is turned off.

Then, the course conversion control section 22 in the control section 21 starts course conversion from time T3. At time T3, the switch S8a connected to the capacitor C8 is turned off, and the switch S8b connected to the capacitor C8 is turned on. As a result, the voltage of the opposite electrode of the capacitor C8 capacitively coupled with the node Vcm′ (more precisely, the node Vcm and the node Vcm′ because the switch S13 is on) changes from VRT (2.0 V) to VRB (1.0 V). change to At this time, the potential of the node Vcm drops by "(VRT-VRB)/8". Also, the value of the 3-bit counter 24A for coarse conversion becomes "001".

Also, at time T4, the switch S1a connected to the capacitor C1 is turned off, and the switch S1b similarly connected to the capacitor C1 is turned on. As a result, the counter electrode of the capacitor C1 capacitively coupled with the node Vcm changes from VRT (2.0V) to VRB (1.0V). At this time, the potential of the node Vcm further drops by "(VRT-VRB)/8". Also, the value of the 3-bit counter 24A becomes "010".

Similar operations are performed at times T5 to T9, and when the potential at node Vcm further drops by "(VRT-VRB)/8" at time T10, the potential at node Vcm falls below potential Vdark (approximately 0 V). At this time, the count value ("111" in this example) of the 3-bit counter 24A determines the high-order 3 bits of the digital value after A/D conversion of the pixel signal.

When the coarse conversion ends, fine conversion is started by the fine conversion control section 23 after time T11, and determination of the lower 12 bits is started. Therefore, at time T11, the switch SX is turned on, and the signal VRAMP, which is the counter electrode potential of the capacitor C8, is raised to a level corresponding to VRT. Also, the potential of the node Vcm is raised to a level corresponding to one timing before the end of the coarse conversion. That is, it is raised by "(VRT-VRB)/8" (see Patent Document 1 for details).

After time T11, the potential of the node Vcm is lowered in a slope by changing (decreasing) the signal VRAMP in a slope, and the potential of the node Vcm becomes lower than the dark potential Vdark (approximately 0 V). is counted by a clock signal (not shown). The clock signal is counted by a 12-bit counter 24B, and the lower 12-bit digital value of the pixel signal is determined by the count value of the 12-bit counter 24B.

In this manner, the ADC 12 determines the upper bits (upper 3 bits) of pixel information in coarse conversion, and the lower bits (lower 12 bits) of pixel information in fine conversion. can be performed at high speed.

(Explanation of operation of ADC 12 when performing weighted addition)
Next, an example in which the ADC 12 shown in FIG. 1 operates as an A/D conversion circuit with weighted addition will be described with reference to the time chart of FIG.

Compared to the time chart shown in FIG. 2, the flowchart shown in FIG. 3 is different from the time chart shown in FIG. The difference is that a new processing period is added for each of the acquisition of Sig3 and the weighted addition of signals Sig1, Sig2, and Sig3 starting at time T2d. Another difference is that signal acquisition started at time T2 in FIG. 2 is changed to weighted signal acquisition started at time T2e in FIG. Others are the same as the time chart shown in FIG.

As shown in the time chart of FIG. 3, the dark capturing that starts at time T1 ends, and at time T2a, the switch S9 is turned on, and the signal Sig1 input via the PGA 11 is captured in the capacitor C1. (Capacitor C1 is charged). At time T2b, switches S10 and S11 are turned on, and signal Sig2 input through PGA11 is taken into capacitors C2 and C3 (capacitors C2 and C3 are charged). At time T2c, the switch S12 is turned on, and the signal Sig3 input through the PGA11 is taken into the capacitor C4 (the capacitor C4 is charged). This completes the loading of the signals Sig1, Sig2, and Sig3 to be weighted and added into the ADC 12. FIG.

After that, at time T2d, the four switches S9, S10, S11, and S12 are turned on all at once, and the charges accumulated in the capacitors C1, C2, C3, and C4 are released to the node Vcm. , signals Sig1, Sig2, and Sig3 are weighted and added to generate a voltage signal. The weighting ratio for the signals Sig1, Sig2, and Sig3 is "1:2:1" from the number of capacitors that hold the respective signals.

Then, at time T2d, when a voltage signal obtained by weighted addition of signals Sig1, Sig2, and Sig3 is generated at node Vcm, at time T2e, switch S13 is turned on to connect node Vcm and node Vcm'. and take in the weighted-and-added signal on the node Vcm'.
A waveform Vcm after time T2e indicates a voltage waveform at node Vcm' (node Vcm' to which capacitors C5 to C8 are connected). However, from time T2e to time T2f, the switch S13 is turned on to explain that the charges in the capacitors C1, C2, and C3 are redistributed among the capacitors C1 to C8. It schematically shows the charging potential (voltage level L1) of the capacitors C1, C2, and C3 before they are turned on.
That is, between the time T2e and the time T2f, when the switch S13 is turned on to connect the node Vcm and the node Vcm', the potential of the node Vcm (voltage level L1) changes from the charges charged in the capacitors C1, C2 and C3 to is redistributed between capacitors C1-C8, thereby dropping to voltage level L2 at time T2f.

After that, coarse conversion starts at time T3, and fine conversion starts at time T11. This coarse conversion and fine conversion are basically the same as the time chart shown in FIG.
However, the time chart shown in FIG. 3 differs from the time chart shown in FIG. 2 in that the four switches S5, S6, S7, and S8 are used for the course conversion operation. In contrast, the high-order bits of the A/D conversion value are determined by performing the coarse conversion operation in eight steps using the eight switches S1 to S8, whereas the time chart shown in FIG. The high-order bits of the A/D conversion value are determined by performing the operation in four stages using four switches S5 to S8.
This is because, during the coarse conversion operation after time T3, the switch S13 is turned off, the capacitors C1, C2, C3, and C4 are disconnected from the node Vcm′, and the switches S1 to S4 connected to the capacitors C1 to C4, respectively. cannot be used for course conversion.
After the time T2d, by keeping the switches S9 to S13 ON, it is also possible to perform the course conversion operation in eight stages using the eight switches S1 to S8.

As described above, in the A/D conversion circuit (ADC 12) of the present embodiment, weighted addition of pixel signals in the vertical direction is performed at the analog signal stage before A/D conversion. Weighted addition of pixel signals can be performed without being affected by noise components and quantization errors that occur when performing.

[Second embodiment]
In the ADC 12 of the first embodiment described above, the coarse conversion process determines the upper bits of the digital value of the pixel signal, and the fine conversion process determines the lower bits of the digital value of the pixel signal. We are trying to speed up the conversion. However, the circuit configuration becomes complicated accordingly. In the A/D conversion circuit of the present invention, it is not always necessary to perform coarse conversion processing, and it is also possible to adopt a configuration in which only fine conversion processing is performed without performing coarse conversion processing. Thereby, the circuit configuration of the A/D conversion circuit can be simplified. As a second embodiment of the present invention, an example in which only fine conversion is performed in the A/D conversion circuit will be described.

FIG. 4 is a diagram showing the configuration of an A/D conversion circuit according to the second embodiment of the present invention. The A/D conversion circuit (ADC 12A) shown in FIG. 4 is different from the A/D conversion circuit (ADC 12) shown in FIG. different. That is, it differs from the ADC 12 shown in FIG. 1 in that the capacitors C5 to C7 are eliminated and the switches S1a, S1b to S8a, S8b and SX are eliminated. Other configurations are the same as those of the ADC 12 shown in FIG. For this reason, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

FIG. 5 is a time chart for explaining the operation of ADC 12A shown in FIG. Compared to the time chart with weighted addition shown in FIG. 3, the time chart shown in FIG. The operation is the same, except that the fine conversion process starts at time T3 (in the time chart of FIG. 3, the coarse conversion process starts at time T3).

Thus, after the weighted addition of the signals Sig1, Sig2 and Sig3 is performed using the capacitors C1, C2, C3 and C4, the coarse conversion process can be omitted and the fine conversion can be started immediately. Therefore, in an A/D conversion circuit with a low number of bits (resolution), weighted addition using analog signals can be performed, and the circuit configuration can be simplified.

FIG. 6 is a time chart showing the operation of the ADC 12A shown in FIG. 5 when weighted addition is not performed. In this ADC 12A, when weighted addition is not performed, switches S9 to S13 are all left on, and after completion of dark acquisition starting from time T1 and signal acquisition starting from time T2, time Fine conversion processing is started from T3.

[Third embodiment]
In the first and second embodiments, all the capacitors C1 to C8 connected to the node Vcm have the same capacitance, and each signal is held according to the weighting of the pixel signals Sig1, Sig2, and Sig3. Allocates the number of capacitors. For example, in the example shown in FIG. 1, one capacitor C1 is assigned to the pixel signal Sig1, two capacitors C2 and C3 are assigned to the pixel signal Sig2, and one capacitor C4 is assigned to the pixel signal Sig3.
In contrast, in the third embodiment of the present invention, one capacitor is assigned to each of the pixel signals Sig1, Sig2, and Sig3, and weighting is performed by changing the capacitance of each capacitor.

FIG. 7 is a diagram showing the configuration of an A/D conversion circuit according to the third embodiment of the invention. ADC 12B shown in FIG. 7 is different from ADC 12 shown in FIG. 1 in that the capacitor for holding signal Sig2 is only one capacitor C2 (in ADC 12 in FIG. 1, signal Sig2 is held by two capacitors C2 and C3). ) are different. In addition, the magnitude of the capacitance of each of the capacitors C1, C2, and C3 is changed according to the magnitude of weighting for each of the signals Sig1, Sig2, and Sig3 (that is, the magnitude of each capacitance is setting or making the magnitude of each capacitance different).
For example, the capacitance ratio of the capacitors C1, C2, and C3 is set to "1:2:1". Other configurations are the same as those of the ADC 12 shown in FIG. For this reason, the same reference numerals are given to the same configurations.

In the example shown in FIG. 7, the capacitances of the capacitors C1, C2 and C3 are changed according to the weighting of the signals Sig1, Sig2 and Sig3. Therefore, the capacitances of the capacitors C1, C2, and C3 are different from the capacitances of the capacitors C4 to C8. That is, the capacitors C1 to C8 have different capacitances (the capacitors C1 to C8 all have the same capacitance in the ADC 12 shown in FIG. 1).

Therefore, the capacitors C1, C2 and C3 are used only when performing the weighted addition of the signals Sig1, Sig2 and Sig3. After performing the weighted addition, the switches S9, S10 and S11 remain off and the capacitor C1, C2 and C3 are not used for the coarse conversion performed by ADC 12B. That is, the ADC 12B performs coarse conversion processing using five capacitors C4, C5, C6, C7, and C8.

FIG. 8 is a time chart for explaining the operation of the ADC 12B shown in FIG. 7, and is a time chart showing the operation with weighted addition. Compared with the time chart in the ADC 12 of the first embodiment shown in FIG. 3, the time chart shown in FIG. So it's the same. Then, at time T2b shown in FIG. 8, the switch S10 is turned on, and the signal Sig2 input through the PGA11 is captured in the capacitor C2 (the capacitor C2 is charged). Further, at time T2c, the switch S11 is turned on, and the signal Sig3 input through the PGA11 is taken into the capacitor C3 (the capacitor C3 is charged). This completes the loading of the signals Sig1, Sig2, and Sig3 to be weighted and added to the ADC 12B.

After that, at time T2d, the three switches S9, S10 and S11 are turned on all at once to discharge the charges accumulated in the capacitors C1, C2 and C3 to the node Vcm. Then, at time T2d, when a voltage signal obtained by weighted addition of signals Sig1, Sig2, and Sig3 is generated at node Vcm, at time T2e, switch S13 is turned on to connect node Vcm and node Vcm'. and take in the weighted-and-added signal on the node Vcm'. As a result, a voltage signal obtained by weighting and adding the signals Sig1, Sig2, and Sig3 is generated at the node Vcm'.

Then, course conversion is started at time T3. In the time chart shown in FIG. 8, five switches S4, S5, S6, S7, and S8 are used to perform the coarse conversion operation, and the upper bits of the A/D conversion value are determined as shown in FIG. Different from the time chart.
That is, in the time chart shown in FIG. 3, the coarse conversion operation is performed in four stages using four switches S5 to S8 to determine the upper bits of the A/D conversion value, whereas in FIG. In the time chart shown, the high-order bits of the A/D conversion value are determined by performing the coarse conversion operation in five stages using five switches S4 to S8.
This is because during the course conversion operation after time T3, the switch S13 is turned off, the capacitors C1, C2, and C3 are disconnected from the node Vcm′, and the switches S1, S2, and S3 connected to the capacitors C1, C2, and C3 are switched off. can not be used for the course conversion operation, and the remaining switches S4 to S8 are used for course conversion.
When this coarse conversion is completed, fine conversion processing is started at time T9, and this fine conversion processing is the same as the cases shown in FIGS.

Thus, in the third embodiment, by changing the capacities of the capacitors C1, C2 and C3, the weighting of the signals Sig1, Sig2 and Sig3 can be finely set.

The embodiments of the present invention have been described above, and the corresponding relationships between the present invention and the above-described embodiments will be additionally described here.
The solid-state imaging device according to the present invention corresponds to the solid-state imaging device 1 shown in FIG. 9, and the A/D conversion circuit according to the present invention corresponds to the ADC 12 shown in FIG. Further, the pixel signal in the present invention corresponds to the pixel signal (for example, signals Sig1, Sig2, Sig3) generated by the pixel PX shown in FIG. 9 and input to the ADC (A/D conversion circuit) via the vertical signal line VL. do. A node in the present invention corresponds to a node Vcm (sometimes includes both a node Vcm and a node Vcm'). The predetermined potential in the present invention is the potential (Vdark) of the pixel signal in the dark state, more precisely, the voltage (dark potential Vdark) held in the capacitor C10 connected to the comparator CP1.
The control section 21 corresponds to the control means in the present invention, the coarse conversion control section 22 corresponds to the coarse conversion means in the present invention, and the fine conversion control section 23 corresponds to the fine conversion means in the present invention. The first group of capacitors in the present invention corresponds to the capacitors C1 to C4, the second group of capacitors in the present invention corresponds to the capacitors C5 to C8, and the first group of switches in the present invention corresponds to the switch S9. to S12, and the switch S13 corresponds to the second group of switches in the present invention.

(1) In the above embodiment, the ADC 12 includes a plurality of capacitors C1 to C8 capacitively coupled to a node Vcm to which the pixel signals Sig1, Sig2, and Sig3 are input via the vertical signal line VL of the solid-state imaging device; Pixel signal holding means ( Capacitors C1 to C4 and switches S9 to S11), and node potential generating means (capacitors C1 to C4 and switch S9 , S11), and by changing the voltages of the counter electrodes of the plurality of capacitors C1 to C8, the potential of the node Vcm is changed, and the potential of the node Vcm is compared with a predetermined potential (dark potential Vdark) to generate a pixel signal. and control means (control unit 21) for generating a digital value.

In the ADC 12 having such a configuration, each of the plurality of pixel signals Sig1, Sig2, and Sig3 input via the vertical signal line VL of the solid-state imaging device is applied to some of the plurality of capacitors C1 to C8 in the ADC 12. Pre-hold using C1-C4. Then, the pixel signals Sig1, Sig2, and Sig3 held in the capacitors C1 to C4 are synthesized to generate the potential of the node Vcm. After that, by changing the voltage of the opposite electrodes of the capacitors C1 to C8, the potential of the node Vcm is changed, and the potential of the node Vcm is compared with a predetermined potential (dark potential Vdark) to generate a digital value of the pixel signal. .
As a result, in the ADC 12 of this embodiment, weighted addition of the pixel signals Sig1, Sig2, and Sig3 in the vertical direction is performed at the analog signal stage, thereby reducing errors and quantization caused by noise components superimposed during A/D conversion. Weighted addition can be performed without error. Further, since the weighted addition is performed using the capacitors C1 to C4 in the ADC 12, the layout area of the solid-state imaging device (chip) is not increased.

(2) In the above embodiment, the ADC 12 has the plurality of capacitors C1 to C8 each having the same capacitance, and when performing weighted addition of the pixel signals Sig1, Sig2, and Sig3, the control unit 21: When each pixel signal is held in the capacitors C1 to C4, one or a plurality of capacitors are assigned from a plurality of capacitors C1 to C8 according to the weighting of each pixel signal, and the assigned capacitor is charged. to hold the pixel signal, and after the input of all the pixel signals to be subjected to weighted addition is completed, the pixel signals Sig1, Sig2, and Sig3 are weighted by adding the charges held in the capacitors C1 to C4. A potential is generated at the node Vcm by the weighted addition pixel signal.
As a result, the pixel signals Sig1, Sig2, and Sig3 can be easily weighted and added at the analog signal stage by using the capacitors C1 to C4 in the ADC 12. FIG. Further, since the weighted addition is performed using the capacitors C1 to C4 in the ADC 12, the layout area is not increased.

(3) In the above embodiment, the control unit 21 changes the potential of the node Vcm stepwise by sequentially switching the voltages of the opposite electrodes of the plurality of capacitors C1 to C8, and the potential of the node Vcm and the predetermined potential ( dark potential Vdark) to determine the upper bit of a predetermined number of bits of the digital value, and after the coarse conversion, the voltage of the opposite electrode of a predetermined capacitor C8 among the capacitors C1 to C8. A fine conversion control unit that changes the potential of the node Vcm along the slope by changing VRAMP in a sloped manner, compares the potential of the node Vcm with a predetermined potential (dark potential Vdark), and determines the lower bits of the digital value. 23 and.
As a result, weighted addition can be performed without including errors due to noise components superimposed during A/D conversion and quantization errors. A/D conversion speed can be increased.

(4) In the above embodiment, the control unit 21 changes the voltage VRAMP of the opposite electrode of a predetermined capacitor C8 among the capacitors C1 to C8 in a sloped manner, thereby changing the potential of the node Vcm in a sloped manner. A fine conversion control unit 23 that compares the potential of the node Vcm with a predetermined potential (Vdark) to generate a digital value.
Thereby, it is also possible to adopt a configuration in which only the fine conversion process is performed without performing the coarse conversion process. Thereby, the circuit configuration of the A/D conversion circuit can be simplified.

(5) In the above embodiment, the number of the plurality of capacitors C1 to C8 is n (n=8), and the number of capacitors C1 to C4 in the first group for holding pixel signals in advance is m (m =4), a first group of m switches S9-S12 selectively connecting between the respective capacitors C1-C4 of the first group and the node Vcm, and a plurality of capacitors C1-C8. (n−m) (four) second group capacitors C5 to C8 excluding the first group capacitors in the second group selectively connecting together and the node Vcm The control unit 21 selects the first group of switches S9 to S9 for each input pixel signal according to the number of pixel signals to be subjected to weighted addition and the weighting of each pixel signal. One or a plurality of switches are allocated in advance from among S12, and when pixel signals sequentially input through the vertical signal line VL are weighted and added, first, the first group of switches S9 to S12 and the second group of switches S9 to S12 are added. By turning off the group of switches S13 and each time a pixel signal is input, the switch assigned to the pixel signal in the first group of switches S9 to S12 is turned on, and the capacitor connected to the switch is charged. After holding the pixel signal, the switch is turned off, and after the input of all the pixel signals Sig1, Sig2, and Sig3 to be subjected to weighted addition is completed, the switches S9 to S12 of the first group are turned on collectively, and the switch is turned on. The pixel signals are weighted and added by adding the charges held in the capacitors C1 to C4 connected to the first group of switches S9 to S12, and the weighted and added pixel signals generate a potential at the node Vcm.
As a result, the pixel signals Sig1, Sig2, and Sig3 can be weighted and added in the analog signal stage, and the weighted addition can be performed using the capacitors C1 to C4 in the ADC 12. FIG.

(6) In the above embodiment, the control unit 21 controls the switches S9 to S12 of the first group and the switch S13 of the second group to be always on, thereby weighting and adding the input pixel signals. No A/D conversion is performed.
As a result, A/D conversion with weighted addition and A/D conversion without weighted addition can be selected and executed.

(7) In the above-described embodiment, the solid-state imaging device 1 includes the ADC 12 described above, and a plurality of pixels PX including photoelectric conversion elements that convert optical signals into electrical signals are arranged in a matrix. and an image pickup means (pixel unit 2) for sequentially scanning each pixel PX row by row and outputting the signal of each pixel PX in a selected row via a plurality of vertical signal lines VL wired for each column; are provided corresponding to each of the plurality of vertical signal lines VL, and convert pixel signals (for example, signals Sig1, Sig2, and Sig3) output from the vertical signal lines VL from analog signals to digital values.
As a result, in the solid-state imaging device 1 of the present invention, when pixel signals (for example, signals Sig1, Sig2, and Sig3) output from the vertical signal line VL are weighted and added and output as a digital value (digital data), this Weighted addition of pixel signals can be performed at the analog signal stage. Therefore, it is possible to output weighted-and-added digital data without including errors due to noise components and the like that are superimposed when pixel signals are A/D converted. Further, since the weighted addition is performed using the capacitors C1 to C4 in the ADC 12, the layout area is not increased.

Although the embodiments of the present invention have been described above, the A/D conversion circuit of the present invention is not limited to the above illustrated examples, and various modifications can be made without departing from the scope of the present invention. Of course you can get it.

1 solid-state imaging device 2 pixel unit 3 vertical scanning circuit 4 horizontal scanning circuit 11 PGA
12 ADC (A/D conversion circuit)
21 control unit 22 coarse conversion control unit 23 fine conversion control unit 24 counters C1 to C8 capacitors C10, C11, C12 capacitor CP1 comparator PX pixels S1a, S4b to S8a, S8b, SX switch S9, S10, S11, S12, S13 switch Sig1 , Sig2, Sig3 Pixel signal Vcm Node

Claims (45)

a plurality of pixels;
a first holding unit that holds a first pixel signal from a first pixel among the plurality of pixels; a first holding circuit having a second holding unit that holds a second pixel signal;
a first comparator used to convert the first output signal output from the first holding circuit into a digital signal;
a first connecting portion electrically connecting between the first holding circuit and the first comparator;
An image sensor. In the imaging device according to claim 1,
The first holding circuit includes a first switch that electrically connects the first pixel and the first holding section, and a second switch that electrically connects the second pixel and the second holding section. An image sensor having In the imaging device according to claim 1 or claim 2,
The second holding unit is an imaging device that holds the second pixel signal when the first pixel signal is held in the first holding unit. In the imaging device according to any one of claims 1 to 3,
a first control line outputting a first control signal for controlling the first pixel;
a second control line outputting a second control signal for controlling the second pixel;
An image sensor. In the imaging device according to claim 4,
The first pixel includes a first photoelectric conversion unit that converts light into electric charge, and a first transfer unit that is connected to the first control line and transfers the electric charge of the first photoelectric conversion unit,
The second pixel is an imaging device having a second photoelectric conversion section that converts light into electric charge, and a second transfer section that is connected to the second control line and transfers the electric charge of the second photoelectric conversion section. In the imaging device according to claim 4 or claim 5,
The imaging device in which the second control signal is output to the second control line at a timing different from the timing at which the first control signal is output to the first control line. In the imaging device according to any one of claims 1 to 6,
The first holding unit has a capacitive element that holds the first pixel signal ,
The second holding unit is an imaging device having a capacitive element that holds the second pixel signal . In the imaging device according to claim 7,
A capacitive element included in the second holding section has a capacity different from that of the capacitive element included in the first holding section. In the imaging device according to any one of claims 1 to 8,
An imaging device comprising a first amplification section used to amplify the first output signal. In the imaging device according to claim 9,
A said 1st comparator is an image pick-up element used in order to convert the said 1st output signal amplified using a said 1st amplifier into a digital signal. In the imaging device according to any one of claims 1 to 10,
The image pickup device, wherein the first output signal is generated using the first pixel signal held in the first holding section and the second pixel signal held in the second holding section. In the imaging device according to claim 1,
a third holding unit holding a third pixel signal from a third pixel among the plurality of pixels; and a fourth pixel arranged at a position on the column direction side from the third pixel among the plurality of pixels; a second holding circuit having a fourth holding unit that holds the fourth pixel signal of
a second comparator used to convert the second output signal output from the second holding circuit into a digital signal;
a second connection portion electrically connecting the second holding circuit and the second comparator;
An image sensor. In the imaging device according to claim 12,
The first holding circuit includes a first switch that electrically connects the first pixel and the first holding section, and a second switch that electrically connects the second pixel and the second holding section. has
The second holding circuit includes a third switch that electrically connects the third pixel and the third holding section, and a fourth switch that electrically connects the fourth pixel and the fourth holding section. An image sensor having In the imaging device according to claim 12 or 13,
the second holding unit holds the second pixel signal when the first pixel signal is held in the first holding unit;
The fourth holding unit is an imaging device that holds the fourth pixel signal when the third holding unit holds the third pixel signal. In the imaging device according to any one of claims 12 to 14,
a first control line outputting a first control signal for controlling the first pixel;
a second control line outputting a second control signal for controlling the second pixel;
a third control line outputting a third control signal for controlling the third pixel;
a fourth control line outputting a fourth control signal for controlling the fourth pixel;
An image sensor. In the imaging device according to claim 15,
The first pixel includes a first photoelectric conversion unit that converts light into electric charge, and a first transfer unit that is connected to the first control line and transfers the electric charge of the first photoelectric conversion unit,
the second pixel includes a second photoelectric conversion unit that converts light into an electric charge, and a second transfer unit that is connected to the second control line and transfers the electric charge of the second photoelectric conversion unit;
the third pixel includes a third photoelectric conversion unit that converts light into an electric charge, and a third transfer unit that is connected to the third control line and transfers the electric charge of the third photoelectric conversion unit;
The fourth pixel is an imaging device having a fourth photoelectric conversion section that converts light into electric charge, and a fourth transfer section that is connected to the fourth control line and transfers the electric charge of the fourth photoelectric conversion section. In the imaging device according to claim 15 or claim 16,
the second control signal is output to the second control line at a timing different from the timing at which the first control signal is output to the first control line;
The fourth control signal is output to the fourth control line at a timing different from the timing at which the third control signal is output to the third control line. In the imaging device according to any one of claims 12 to 14,
a first control line outputting a first control signal for controlling the first pixel and the third pixel;
a second control line outputting a second control signal for controlling the second pixel and the fourth pixel;
An image sensor. In the imaging device according to claim 18,
The first pixel includes a first photoelectric conversion unit that converts light into electric charge, and a first transfer unit that is connected to the first control line and transfers the electric charge of the first photoelectric conversion unit,
the second pixel includes a second photoelectric conversion unit that converts light into an electric charge, and a second transfer unit that is connected to the second control line and transfers the electric charge of the second photoelectric conversion unit;
the third pixel includes a third photoelectric conversion unit that converts light into an electric charge, and a third transfer unit that is connected to the first control line and transfers the electric charge of the third photoelectric conversion unit;
The fourth pixel is an imaging device having a fourth photoelectric conversion section that converts light into electric charge, and a fourth transfer section that is connected to the second control line and transfers the electric charge of the fourth photoelectric conversion section. In the imaging device according to claim 18 or 19,
The imaging device in which the second control signal is output to the second control line at a timing different from the timing at which the first control signal is output to the first control line. In the imaging device according to any one of claims 12 to 20,
The first holding unit has a capacitive element that holds the first pixel signal,
The second holding unit has a capacitive element that holds the second pixel signal,
The third holding unit has a capacitive element that holds the third pixel signal,
The fourth holding unit is an imaging device having a capacitive element that holds the fourth pixel signal. 22. The imaging device according to claim 21,
the capacitive element of the second holding unit has a capacitance different from that of the capacitive element of the first holding unit;
A capacitive element included in the fourth holding section has a capacity different from that of the capacitive element included in the third holding section. In the imaging device according to any one of claims 12 to 22,
the first output signal is generated using the first pixel signal held in the first holding unit and the second pixel signal held in the second holding unit;
The image pickup device, wherein the second output signal is generated using the third pixel signal held in the third holding section and the fourth pixel signal held in the fourth holding section. a plurality of pixels;
a first holding unit that holds a first pixel signal from a first pixel among the plurality of pixels; a first holding circuit having a second holding unit that holds a second pixel signal;
a first amplifier used to amplify the first output signal output from the first holding circuit ;
a first connecting portion electrically connecting the first holding circuit and the first amplifying portion;
An image sensor. 25. The imaging device according to claim 24 ,
The first holding circuit includes a first switch that electrically connects the first pixel and the first holding section, and a second switch that electrically connects the second pixel and the second holding section. An image sensor having In the imaging device according to claim 24 or 25 ,
The second holding unit is an imaging device that holds the second pixel signal when the first pixel signal is held in the first holding unit. In the imaging device according to any one of claims 24 to 26 ,
a first control line outputting a first control signal for controlling the first pixel;
a second control line outputting a second control signal for controlling the second pixel;
An image sensor. 28. The imaging device according to claim 27 ,
The first pixel includes a first photoelectric conversion unit that converts light into electric charge, and a first transfer unit that is connected to the first control line and transfers the electric charge of the first photoelectric conversion unit,
The second pixel is an imaging device having a second photoelectric conversion section that converts light into electric charge, and a second transfer section that is connected to the second control line and transfers the electric charge of the second photoelectric conversion section. In the imaging device according to claim 27 or claim 28 ,
The imaging device in which the second control signal is output to the second control line at a timing different from the timing at which the first control signal is output to the first control line. In the imaging device according to any one of claims 24 to 29 ,
The first holding unit has a capacitive element that holds the first pixel signal ,
The second holding unit is an imaging device having a capacitive element that holds the second pixel signal . In the imaging device according to claim 30 ,
A capacitive element included in the second holding section has a capacity different from that of the capacitive element included in the first holding section. In the imaging device according to any one of claims 24 to 31,
The image pickup device, wherein the first output signal is generated using the first pixel signal held in the first holding section and the second pixel signal held in the second holding section. 25. The imaging device according to claim 24,
a third holding unit holding a third pixel signal from a third pixel among the plurality of pixels; and a fourth pixel arranged at a position on the column direction side from the third pixel among the plurality of pixels; a second holding circuit having a fourth holding unit that holds the fourth pixel signal of
a second amplifier used to amplify the second output signal output from the second holding circuit;
a second connecting portion electrically connecting the second holding circuit and the second amplifying portion;
An image sensor. 34. The imaging device according to claim 33,
The first holding circuit includes a first switch that electrically connects the first pixel and the first holding section, and a second switch that electrically connects the second pixel and the second holding section. has
The second holding circuit includes a third switch that electrically connects the third pixel and the third holding section, and a fourth switch that electrically connects the fourth pixel and the fourth holding section. An image sensor having In the imaging device according to claim 33 or claim 34,
the second holding unit holds the second pixel signal when the first pixel signal is held in the first holding unit;
The fourth holding unit is an imaging device that holds the fourth pixel signal when the third holding unit holds the third pixel signal. In the imaging device according to any one of claims 33 to 35,
a first control line outputting a first control signal for controlling the first pixel;
a second control line outputting a second control signal for controlling the second pixel;
a third control line outputting a third control signal for controlling the third pixel;
a fourth control line outputting a fourth control signal for controlling the fourth pixel;
An image sensor. 37. The imaging device according to claim 36,
The first pixel includes a first photoelectric conversion unit that converts light into electric charge, and a first transfer unit that is connected to the first control line and transfers the electric charge of the first photoelectric conversion unit,
the second pixel includes a second photoelectric conversion unit that converts light into an electric charge, and a second transfer unit that is connected to the second control line and transfers the electric charge of the second photoelectric conversion unit;
the third pixel includes a third photoelectric conversion unit that converts light into an electric charge, and a third transfer unit that is connected to the third control line and transfers the electric charge of the third photoelectric conversion unit;
The fourth pixel is an imaging device having a fourth photoelectric conversion section that converts light into electric charge, and a fourth transfer section that is connected to the fourth control line and transfers the electric charge of the fourth photoelectric conversion section. In the imaging device according to claim 36 or claim 37,
the second control signal is output to the second control line at a timing different from the timing at which the first control signal is output to the first control line;
The fourth control signal is output to the fourth control line at a timing different from the timing at which the third control signal is output to the third control line. In the imaging device according to any one of claims 33 to 35,
a first control line outputting a first control signal for controlling the first pixel and the third pixel;
a second control line outputting a second control signal for controlling the second pixel and the fourth pixel;
An image sensor. 40. The imaging device according to claim 39,
the first pixel includes a first photoelectric conversion unit that converts light into electric charge, and a first transfer unit that is connected to the first control line and transfers the electric charge of the first photoelectric conversion unit;
the second pixel includes a second photoelectric conversion unit that converts light into an electric charge, and a second transfer unit that is connected to the second control line and transfers the electric charge of the second photoelectric conversion unit;
the third pixel includes a third photoelectric conversion unit that converts light into an electric charge, and a third transfer unit that is connected to the first control line and transfers the electric charge of the third photoelectric conversion unit;
The fourth pixel is an imaging device having a fourth photoelectric conversion section that converts light into electric charge, and a fourth transfer section that is connected to the second control line and transfers the electric charge of the fourth photoelectric conversion section. In the imaging device according to claim 39 or claim 40,
The imaging device in which the second control signal is output to the second control line at a timing different from the timing at which the first control signal is output to the first control line. In the imaging device according to any one of claims 33 to 41,
The first holding unit has a capacitive element that holds the first pixel signal,
The second holding unit has a capacitive element that holds the second pixel signal,
The third holding unit has a capacitive element that holds the third pixel signal,
The fourth holding unit is an imaging device having a capacitive element that holds the fourth pixel signal. 43. The imaging device according to claim 42,
the capacitive element of the second holding unit has a capacitance different from that of the capacitive element of the first holding unit;
A capacitive element included in the fourth holding section has a capacity different from that of the capacitive element included in the third holding section. In the imaging device according to any one of claims 33 to 43,
the first output signal is generated using the first pixel signal held in the first holding unit and the second pixel signal held in the second holding unit;
The image pickup device, wherein the second output signal is generated using the third pixel signal held in the third holding section and the fourth pixel signal held in the fourth holding section. An imaging device comprising the imaging element according to any one of claims 1 to 44 .

Images