JP7294226B2 - electronic controller - Google Patents

Description

The present invention relates to electronic control units.

As a technique for improving the processing performance of a microcomputer due to the complication of automobile control, there is a parallel arithmetic processor disclosed in Patent Document 1, for example.

A parallel arithmetic processor is composed of an arithmetic control section and a parallel arithmetic section. The operation control unit has a function of causing the parallel operation unit to process, for example, an operation instruction group, which is a set of operation instructions requested by the core, in order of priority. Hereinafter, the operation instruction group will be referred to as a graph. The parallel computing section is composed of a plurality of computing units. In addition, the parallel operation unit cannot execute a plurality of graph processes at the same time, and cannot terminate the current graph process and start another graph process in the middle of the process.

Therefore, the calculation control unit sends the graph with the highest priority to the parallel calculation unit, and the parallel calculation unit sends the processing result to the calculation control unit when the processing is completed. When the graph processing by the parallel operation unit is completed and the parallel operation unit becomes empty, the operation control unit sends the graph with the next highest priority to the parallel operation unit.

JP 2012-141852 A

The technique of Patent Literature 1 has a configuration in which graph processing with a high priority is immediately added as soon as the parallel processing unit becomes empty. In addition, since the above technology cannot execute the next graph processing until the graph processing in progress is completed, even if the core determines that it is unnecessary in another processing, cannot end with As a result, there arises a problem that useless processing time increases and execution of processing that should be executed is delayed.
Moreover, when a priority process that must be executed immediately is requested from the core, there is also a problem that the process cannot be executed preferentially immediately if other processes are being executed.

The present invention has been made in view of the above circumstances, and its object is to terminate the processing of a group of arithmetic instructions being processed by a parallel arithmetic processor in response to a request from a control unit, for example, a core, and perform an arithmetic operation with a high priority. An object of the present invention is to provide an electronic control device capable of processing an instruction group.

According to the first aspect of the invention, the control section (12a-12d) of the microcomputer (11) requests processing of a group of operational instructions, which is a collection of operational instructions. The arithmetic control unit (18) stocks the arithmetic instruction group requested by the control unit in descending order of priority, extracts arithmetic instructions from the arithmetic instruction group with the highest priority, and allocates them to the parallel arithmetic unit (19).
In response to a request from the control unit, the parallel processing unit terminates processing of the processing instruction group being parallel-processed by the parallel processing unit, and processes the stocked high-priority processing instruction group. The parallel arithmetic processor adds an end judgment instruction to the arithmetic instruction group requested by the control unit and sets an end judgment flag (20). In the parallel arithmetic processor, if the end judgment flag is set when the end judgment instruction is processed, the parallel arithmetic processor ends the processing of the arithmetic instruction group being parallel-processed. This enables the parallel processor to process a group of high-priority arithmetic instructions.

1 is a functional block diagram showing the configuration of a microcomputer according to a first embodiment; FIG. Block diagram showing connections between the engine ECU and each ECU Block diagram schematically showing the configuration of a parallel processor Diagram showing graph structure Schematic diagram showing the configuration of a parallel processor Flowchart showing the operation of the arithmetic control unit (Part 1) Flowchart showing the operation of the arithmetic control unit (part 2) Flowchart showing the operation of the parallel operation part FIG. 11 is a functional block diagram showing the configuration of a parallel computing unit according to the second embodiment; FIG. Flowchart showing the operation of the arithmetic control unit Flowchart showing the operation of the arithmetic control unit according to the third embodiment Flowchart showing the operation of the core Flowchart showing the operation of the arithmetic control unit according to the fourth embodiment Flowchart showing the operation of the arithmetic control unit according to the fifth embodiment Flowchart showing the operation of the arithmetic control unit according to the sixth embodiment Flowchart showing the operation of the arithmetic control unit according to the seventh embodiment

A plurality of embodiments will be described below with reference to the drawings. In several embodiments, functionally or structurally corresponding parts are given the same reference numerals.

(First embodiment)
A first embodiment will be described with reference to FIGS. 1 to 8. FIG.
As shown in FIG. 1, the microcomputer 11 comprises a core group 12 consisting of a plurality of cores 12a to 12d and a parallel processor 13. As shown in FIG. These cores 12a to 12d and the parallel processor 13 perform a plurality of arithmetic processes in parallel to achieve high-speed processing.

The cores 12a to 12d and the parallel processor 13 are connected to each other via an internal bus 14, and are also connected to a memory 15 such as ROM and RAM, and peripheral circuits 16 such as an AD converter and CAN interface.

The cores 12a to 12d receive digital values obtained by digitally converting detection signals from various sensors for detecting the operation of actuators for controlling the engine and the operating state of the engine by an AD converter, and process the digital values. Then, when it becomes necessary to perform arithmetic processing to obtain a predetermined physical value, a processing request is made to the parallel arithmetic processor 13 .

As shown in FIG. 2, the vehicle is equipped with an engine ECU (Electronic Control Unit) 1 . The engine ECU 1 is mainly composed of the microcomputer 11 described above. The engine ECU 1 corresponds to an electronic control unit. The engine ECU 1 is communicably connected to other ECUs such as an automatic transmission ECU 3, a meter ECU 4 and an air conditioning ECU 5 via an in-vehicle LAN 2. A protocol of the in-vehicle LAN 2 is CAN (Controller Area Network), for example. CAN is a registered trademark.

As shown in FIG. 3, the parallel arithmetic processor 13 comprises a memory 17, an arithmetic control section 18, and a parallel arithmetic section 19. As shown in FIG. The memory 17 sequentially stores a group of operation instructions requested by the cores 12a to 12d.

The arithmetic control unit 18 cooperates with the parallel arithmetic unit 19 to arithmetically process the arithmetic instruction group stored in the memory 17 . That is, the arithmetic control unit 18 has a scheduler function, and automatically allocates arithmetic instructions stored in the memory 17 to the parallel arithmetic unit 19 .

The parallel operation unit 19 is of a FIFO (First-In First-Out) type, and sequentially performs operation processing on operation instructions assigned to the parallel operation unit 19 by the operation control unit 18 . The parallel operation unit 19 is a set of arithmetic units of the same type or different types, and is capable of parallel processing of arithmetic instructions of the same type or different types. The parallel computation unit 19 stores the computation result in the memory 17 .

The plurality of cores 12a to 12d shown in FIG. 1 acquires the computation result via the memory 17 when requesting the parallel computation processor 13 to process the computation instruction group, and performs subsequent processing based on the computation result. to run.

The processing order of the operation instructions for the group of operation instructions requested by the cores 12a to 12d is defined. For example, in the group of arithmetic instructions shown in FIG. It defines that the operation instruction E of is to be operated.

As shown in FIG. 5, the memory 17 is provided with an end determination flag 20 . The end determination flag 20 is set by the arithmetic control unit 18 in response to requests from the cores 12a to 12d, as will be described later.

The arithmetic control unit 18 stacks the graphs requested for processing from the cores 12a to 12d according to their priorities. That is, the graph with the highest priority is stacked as the graph to be processed next, and the graph with the next highest priority is stacked as the graph to be processed next. Each time graph processing is requested from the cores 12a to 12d, the stacking order is changed according to the priority of the requested graph. In the case of the same priority, the graph stacked earlier is stacked as the higher priority graph.

When the graph processing currently being executed by the parallel operation unit 19 is completed, the operation control unit 18 sends the stack with the highest priority among the stacked graphs to the parallel operation unit 19 . That is, when the parallel computation unit 19 executes graph processing, the computation control unit 18 extracts computation instructions that form the graph and allocates them to the parallel computation unit 19 . The parallel operation unit 19 executes the operation of the operation instruction, and returns the processing result to the operation control unit 18 upon completion. Such operations are performed for all operation instructions to be executed in one graph, and when all processing is completed, the next graph processing is executed.

By the way, the cores 12a to 12d that have requested the graph processing may determine that the graph processing is no longer necessary, for example, in another process. However, the parallel computing unit 19 cannot process a plurality of graphs at the same time, and cannot terminate the graph processing in progress and start another graph processing in the middle of the processing. Therefore, the next graph processing cannot be executed until the graph processing being processed by the parallel computing unit 19 is completed.
For this reason, in this embodiment, the parallel processors are provided with a function of terminating graph processing in progress in response to requests from the cores 12a to 12d.

Specifically, as shown in FIG. 6, when the arithmetic control unit 18 of the parallel arithmetic processor 13 receives a request for graph processing from the cores 12a to 12d of the microcomputer (S101: YES), processing ends with the requested graph. A judgment command is given (S102). This termination determination instruction is an instruction for making the parallel operation unit 19 confirm whether to terminate the graph being processed, and is given as an instruction constituting the graph. In other words, the graphs stacked in the parallel processor 13 are composed of computation instructions and termination determination instructions.

As shown in FIG. 5, the cores 12a to 12d request the parallel processor 13 to terminate the graphs requested to the parallel processor 13 if they determine that the graph is unnecessary due to, for example, other processing. do.

As shown in FIG. 7, when there is a termination request from the cores 12a to 12d (S201: YES), the arithmetic control unit 18 of the parallel arithmetic processor 13 is executing the graph processing to be terminated or waits. It is determined whether it is in the middle (S202). When waiting (S202: NO), the graph to be terminated is cleared (S204). If the processing is in progress (S202: YES), the end determination flag 20 is set (S203).

As shown in FIG. 8, when the parallel operation unit 19 executes the termination determination instruction attached to the graph (S301: YES), it refers to the termination determination flag 20 (S302), and the termination determination flag 20 is set. It is determined whether there is (S303). If the end determination flag 20 is set (S303: YES), the graph processing currently being executed is immediately ended (S304).

In this case, the calculation control unit 18 still has the remaining calculation instructions of the completed graph as uncompleted instructions. Therefore, when the processing result of the end determination instruction is returned from the parallel operation unit as "end", all the unfinished instructions are cleared. As a result, the graph with the highest priority is sent to the parallel arithmetic unit 19 by the arithmetic control unit 18, and the processing is executed.
On the other hand, if the end determination flag 20 is not set (S303: NO), the parallel operation unit 19 continues the graph processing because the graph being processed needs processing.

If the end determination instruction attached to the graph has already been executed at the timing when the end determination flag 20 is set, the parallel processor 13 continues the graph processing as it is, and when the graph processing ends, The calculation results are sent to the cores 12a-12d. In this case, the cores 12a to 12d ignore the calculation results received from the parallel processor 13 because the calculation results are unnecessary.

According to such an embodiment, the following effects can be obtained.
When an end request is received from the cores 12a to 12d, the parallel processor 13 terminates the graph processing and executes the graph processing with the highest priority, so the graph processing with the highest priority can be executed immediately.

(Second embodiment)
A second embodiment will be described with reference to FIGS. 9 and 10. FIG. The second embodiment is characterized in that the parallel processor 13 terminates graph processing in response to priority processing requests from the cores 12a to 12d.

As in the first embodiment, the parallel processor 13 gives an end determination command to the graph when the cores 12a to 12d request graph processing.
As shown in FIG. 9, when the cores 12a to 12d want to preferentially process graphs, they request graph processing and preferential processing at the same time. As shown in FIG. 10, when there is a priority processing request (S401: YES), the arithmetic control unit 18 of the parallel arithmetic processor 13 raises the priority of the requested graph and stocks it (S402). ), and it is determined whether there is a graph currently being processed (S403). If there is a graph currently being processed (S403: YES), the end determination flag 20 is set (S404). On the other hand, if there is no graph currently being processed (S403: NO), the graph processing with the higher priority is executed as it is.

As in the first embodiment, the parallel operation unit 19 refers to the end determination flag 20 when executing the end determination instruction attached to the graph being processed, and when the end determination flag 20 is set, terminates the graph processing in progress. The arithmetic control unit receives the processing result of the end determination instruction from the parallel arithmetic unit and clears the incomplete processing.

According to such an embodiment, the parallel processor 13 stocks the graph with the highest priority in response to priority processing requests from the cores 12a to 12d and ends the processing. , the graph processing requested by the cores 12a to 12d can be preferentially executed.

(Third Embodiment)
3rd Embodiment is described with reference to FIG.11 and FIG.12. This third embodiment is characterized by cores 12a-12d reclaiming graph processing.
As shown in FIG. 11, when the parallel processor 9 has finished processing (S501: YES), the arithmetic controller 18 of the parallel arithmetic processor 13 notifies the cores 12a to 12d of the completion (S502).

As shown in FIG. 12, when the cores 12a to 12d receive the end notification (S601: YES), the cores 12a to 12d determine whether to re-execute the ended graph processing (S602). In other words, although the requested graph processing is no longer necessary, it is determined whether it has become necessary due to other processing, for example. If it is determined to re-execute the graph (S602: YES), the parallel processor 13 is re-requested for the graph processing (S603). Graphs requested for processing are stacked in the arithmetic control unit 18 in accordance with their priorities. On the other hand, if it is determined not to re-request the graph processing (S602: NO), no action is taken for the terminated graph processing.

According to such an embodiment, the cores 12a to 12d re-request the graph processing as necessary when the end notification is received from the parallel processor 13. Therefore, even when the graph processing ends, The graph processing can be re-executed.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. This fourth embodiment is characterized in that the parallel arithmetic processor 13 determines whether to give an end determination instruction according to the scale of graph processing.

As shown in FIG. 13, when there is a request for graph processing (S701: YES), the arithmetic control unit 18 of the parallel arithmetic processor 13 determines whether the scale of the graph processing is equal to or greater than a predetermined value (S702). . The predetermined value is set depending on whether the termination determination command given to the graph functions effectively. If it is equal to or greater than the predetermined value (S702: YES), an end determination command is given to the graph (S703). On the other hand, if it is less than the predetermined value (S702: NO), no end determination command is given to the graph (S704).

That is, when the scale of the graph processing is small, graph processing is performed rather than waiting until completion of an end determination instruction, processing performed to end the graph, rewriting of the end determination flag 20, transmission to the cores 12a to 12d, and the like. Since it is faster to wait for the completion of , the end judgment instruction is not given.

According to such an embodiment, when the scale of graph processing is small, the parallel processing unit 13 does not add an end determination command to the graph, so it is possible to suppress the operation of adding meaningless end determination commands to the graph. can be done.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. The fifth embodiment is characterized in that the parallel processor 13 determines the number of end determination instructions to be given.

As shown in FIG. 14, when there is a request for graph processing (S701: YES), the arithmetic control unit 18 of the parallel arithmetic processor 13, when the scale of graph processing is equal to or greater than a predetermined value (S702: YES) , one or a plurality of end determination instructions are added to the graph (S705). On the other hand, if the scale of graph processing is less than the predetermined value (S702: NO), no end determination command is given.

According to this embodiment, when the scale of graph processing is equal to or greater than a predetermined value, the parallel processor 13 gives one or a plurality of end determination instructions to the graph. It is possible to increase the possibility of executing the termination determination instruction even if

(Sixth embodiment)
A sixth embodiment will be described with reference to FIG. The sixth embodiment is characterized in that the parallel arithmetic processor 13 gives the end determination instruction to the graph for each fixed number of instructions.

As shown in FIG. 15, when there is a request for graph processing (S701: YES), the arithmetic control unit 18 gives one or more end determination instructions (S705). An end determination command is given so that the position interval is a constant number of commands (S706).

Specifically, each time the number of operation instructions forming the graph reaches a certain number, the assignment position of the end determination instruction is determined. As a result, it is only necessary to add end determination instructions to the graph at intervals of a constant number of commands, so end determination instructions can be quickly added to the graph.

According to this embodiment, when the scale of graph processing is equal to or greater than a predetermined value, the parallel processor 13 assigns end determination commands based on a certain number of commands. can be suppressed.

(Seventh embodiment)
A seventh embodiment will be described with reference to FIG. The seventh embodiment is characterized in that the parallel arithmetic processor 13 gives the end determination instruction to the graph at regular processing time intervals.

As shown in FIG. 16, when there is a request for graph processing (S701: YES), the arithmetic control unit 18 of the parallel arithmetic processor 13 gives one or a plurality of end determination instructions (S705). , is added to the graph so that the time interval for executing the end determination instruction is a constant processing time (S707).

Specifically, the assignment position of the end determination instruction is determined according to the type, number, and processing time of each operation instruction forming the graph. As a result, the processing interval between the end determination commands becomes constant, so the end determination commands can be executed periodically.

According to this embodiment, when the scale of graph processing is equal to or greater than a predetermined value, the parallel processor 13 gives an end determination instruction based on a certain processing time. end determination can be stably performed.

(Other embodiments)
The electronic control device is not limited to the engine ECU.
The processing requested by the core to the parallel processor is not limited to a termination request or priority processing request.
The number of cores mounted on the microcomputer is not limited to a plurality, and may be one.

Although the present disclosure has been described with reference to embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 is an engine ECU (electronic control unit), 11 is a microcomputer, 12a to 12d are cores (controllers), 13 is a parallel processor, 18 is an arithmetic controller, 19 is a parallel processor, and 20 is the end. It is a judgment flag.

Claims (8)

A control unit (12a to 12d) requesting processing of a group of operational instructions, which is a set of operational instructions, and a processing control unit (18) giving high priority to the group of operational instructions requested by the control unit. A parallel arithmetic processor (13) capable of parallel processing a plurality of said arithmetic instructions by stocking them in order and extracting said arithmetic instructions from said arithmetic instruction group with high priority and allocating them to corresponding parallel arithmetic units (19); a microcomputer (11) having
The parallel arithmetic processor terminates processing of the arithmetic instruction group being parallel-processed by the parallel arithmetic unit in response to a request from the control unit, and processes the stock arithmetic instruction group with high priority. ,
The parallel arithmetic processor adds an end determination instruction to the operation instruction group requested by the control unit and sets an end determination flag (20),
The parallel arithmetic processor is an electronic control device for terminating processing of the arithmetic instruction group being parallel-processed by the parallel arithmetic unit when the end determination flag is set when the end determination instruction is processed. The control unit issues a termination request to the parallel arithmetic processor when processing of the arithmetic instruction group requested to be processed becomes unnecessary,
2. The electronic control device according to claim 1, wherein said parallel arithmetic processor terminates processing of said arithmetic instruction group being parallel-processed by said parallel arithmetic unit when said termination request is received. the control unit, when preferentially processing the operation instruction group, raises the priority of the operation instruction group and requests the priority processing;
2. The electronic control device according to claim 1, wherein said parallel arithmetic processor terminates processing of said arithmetic instruction group being parallel-processed by said parallel arithmetic unit when said priority processing request is made. The parallel arithmetic processor notifies the control unit of completion when processing of the arithmetic instruction group being parallel-processed by the parallel arithmetic unit is completed;
4. The method according to any one of claims 1 to 3 , wherein said control unit determines whether or not to re-execute said group of operation instructions that have been terminated when said end notification is received, and re-requests processing of said group of operation instructions if it determines to re-execute said group of operation instructions. The electronic control device according to any one of claims 1 to 3. 2. The electronic control device according to claim 1 , wherein said parallel arithmetic processor gives said end determination instruction according to the scale of said arithmetic instruction group. 2. The electronic control device according to claim 1 , wherein said parallel arithmetic processor gives one or a plurality of said end determination instructions when the scale of said arithmetic instruction group is equal to or greater than a predetermined value. 2. The electronic control device according to claim 1 , wherein said parallel arithmetic processor determines a position to give said end determination instruction based on the number of instructions constituting said arithmetic instruction group. 2. The electronic control device according to claim 1 , wherein the parallel arithmetic processor determines the position where the end determination instruction is given based on the processing time of the arithmetic instructions forming the arithmetic instruction group.

Images