JP7298752B2 - Semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device.

Conventionally, alignment (position) for patterning a circuit pattern corresponding to the surface element structure of the front surface (first main surface) of a semiconductor substrate (second main surface) of a semiconductor substrate (semiconductor wafer) on the back surface (second main surface) or a material film on the back surface. Alignment) is known to use an alignment mark (hereinafter referred to as a back surface alignment mark) formed on the front surface of the semiconductor substrate together with the surface element structure.

As an alignment method using infrared light, an alignment mark for the back surface of a SON (Silicon-On-Nothing) structure is formed inside an invalid area such as a dicing line of a silicon wafer, and this alignment mark for the back surface is irradiated with a red laser (transmission laser). A method of recognizing a change in reflected light of a type laser) has been proposed (see, for example, Patent Document 1 below (paragraphs [0041] to [0047], FIGS. 5 and 7).). In Japanese Patent Laid-Open No. 2002-200002, a back alignment mark of an SON structure is formed by connecting a plurality of hole trenches arranged in a region where a back alignment mark is to be formed to form one cavity by heat treatment.

JP 2012-089540 A

The present invention is a semiconductor device in which patterning is performed using alignment marks on a second main surface different from the first main surface on which alignment marks are formed in a semiconductor substrate having a first main surface and a second main surface which are substantially parallel to each other. It is an object of the present invention to provide a manufacturing method of a semiconductor device capable of improving alignment accuracy.

In order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention provides a first region in which an insulated gate bipolar transistor is arranged and a second region in which a diode is arranged. , are adjacent in a direction parallel to a first main surface of a semiconductor substrate, the method for manufacturing the semiconductor device having the following features. First, on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type, the base region of the insulated gate bipolar transistor and the diode are formed over the entire first region and the second region as a surface element structure. A first step is performed to form a first semiconductor region of a second conductivity type, which will be the anode region of the second conductive type, and to form a predetermined mark apart from the surface element structure. Next, a second step of forming a resist film on the second main surface of the semiconductor substrate is performed. Next, the semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is detected by a detector arranged at a position facing the second main surface of the semiconductor substrate. A third step of detecting the reflected light of the above to specify the position of the predetermined mark is performed. Next, a fourth step is performed in which alignment is performed using the position of the predetermined mark identified in the third step as a reference, and a predetermined pattern corresponding to the surface element structure is transferred onto the resist film and exposed. Next, by using the resist film as a mask, first conductivity type impurity ions are implanted into the surface layer of the second main surface of the semiconductor substrate over the entire second region to form the cathode region of the diode. A fifth step of forming a second semiconductor region of the first conductivity type having an impurity concentration higher than that of the semiconductor substrate is performed. In the first step, a detection waveform in a first direction parallel to the first main surface of the semiconductor substrate, of reflected light of the light in the predetermined wavelength range detected by the detector; A layout in which two or more peaks are detected in a second direction parallel to the surface and perpendicular to the first direction, and a plurality of peaks reaching a predetermined depth from the first main surface of the semiconductor substrate. Form a trench. As the trenches, four straight planar first trenches arranged in a point-symmetric cross-shaped layout with one end positioned at the center with a predetermined location as the center are formed. A step formed on the first main surface of the semiconductor substrate by the plurality of trenches is used as the predetermined mark. Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the inside of the trench is filled with a polysilicon film. Further, in the method of manufacturing a semiconductor device according to the present invention, in the invention described above, in the first step, the trench is formed at the same time as the gate trench of the insulated gate bipolar transistor, and the gate electrode of the insulated gate bipolar transistor is formed. and forming the polysilicon film at the same time. Moreover, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the first trenches are arranged apart from each other in the first step. Moreover, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the first trench is covered with a metal film containing aluminum.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention provides a first region in which an insulated gate bipolar transistor is arranged and a second region in which a diode is arranged. A method of manufacturing a semiconductor device in which a region and a region are adjacent in a direction parallel to a first main surface of a semiconductor substrate, the method having the following features. First, on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type, the base region of the insulated gate bipolar transistor and the diode are formed over the entire first region and the second region as a surface element structure. A first step is performed to form a first semiconductor region of a second conductivity type, which will be the anode region of the second conductive type, and to form a predetermined mark apart from the surface element structure. Next, a second step of forming a resist film on the second main surface of the semiconductor substrate is performed. Next, the semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is detected by a detector arranged at a position facing the second main surface of the semiconductor substrate. A third step of detecting the reflected light of the above to specify the position of the predetermined mark is performed. Next, a fourth step is performed in which alignment is performed using the position of the predetermined mark identified in the third step as a reference, and a predetermined pattern corresponding to the surface element structure is transferred onto the resist film and exposed. Next, by using the resist film as a mask, first conductivity type impurity ions are implanted into the surface layer of the second main surface of the semiconductor substrate over the entire second region to form the cathode region of the diode. A fifth step of forming a second semiconductor region of the first conductivity type having an impurity concentration higher than that of the semiconductor substrate is performed. In the first step, a laminated film is formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate. A cross-shaped planar groove is formed that penetrates the laminated film in the depth direction and has four linear portions arranged in a point-symmetrical cross-shaped layout with one end positioned at the center with a predetermined location as the center. . A step formed in the laminated film by the groove is used as the predetermined mark.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention provides a first region in which an insulated gate bipolar transistor is arranged and a second region in which a diode is arranged. A method of manufacturing a semiconductor device in which a region and a region are adjacent in a direction parallel to a first main surface of a semiconductor substrate, the method having the following features. First, on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type, the base region of the insulated gate bipolar transistor and the diode are formed over the entire first region and the second region as a surface element structure. A first step is performed to form a first semiconductor region of a second conductivity type, which will be the anode region of the second conductive type, and to form a predetermined mark apart from the surface element structure. Next, a second step of forming a resist film on the second main surface of the semiconductor substrate is performed. Next, the semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is detected by a detector arranged at a position facing the second main surface of the semiconductor substrate. A third step of detecting the reflected light of the above to specify the position of the predetermined mark is performed. Next, a fourth step is performed in which alignment is performed using the position of the predetermined mark identified in the third step as a reference, and a predetermined pattern corresponding to the surface element structure is transferred onto the resist film and exposed. Next, by using the resist film as a mask, first conductivity type impurity ions are implanted into the surface layer of the second main surface of the semiconductor substrate over the entire second region to form the cathode region of the diode. A fifth step of forming a second semiconductor region of the first conductivity type having an impurity concentration higher than that of the semiconductor substrate is performed. In the first step, a laminated film is formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate. The laminated film is formed so that a part of the laminated film remains in four straight lines in a point-symmetrical cross-shaped layout that penetrates the laminated film in the depth direction and has one end positioned at the center with a predetermined location as the center. Form a groove around the circumference of the part. A step formed in the laminated film by the groove is used as the predetermined mark.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the trench is filled with a metal film containing aluminum. Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the trench is formed to penetrate the laminated film in the depth direction and terminate at the first main surface of the semiconductor substrate. characterized by Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the fifth step, the surface layer of the second main surface of the semiconductor substrate is coated with the second semiconductor region over the entire first region. and a third semiconductor region of the second conductivity type, which will be the collector region of the insulated gate bipolar transistor.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the fifth step, ion implantation of a second conductivity type impurity is performed to form the semiconductor device on the surface layer of the second main surface of the semiconductor substrate. The third semiconductor region is formed over the entire second main surface of the substrate, ion implantation of the impurity of the first conductivity type is performed using the resist film as a mask, and the second region portion of the third semiconductor region is the second region. The second semiconductor region is formed by changing to one conductivity type.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, a sixth step of forming a first electrode electrically connected to the first semiconductor region on the first main surface of the semiconductor substrate; and a seventh step of forming a second electrode in contact with the second semiconductor region and the third semiconductor region on the second main surface of the semiconductor substrate.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a floating second conductivity type region, which has the following features. have First, a first step of forming the surface element structure on the first main surface of the semiconductor substrate of the first conductivity type and forming a predetermined mark apart from the surface element structure is performed. Next, a second step of forming a resist film on the second main surface of the semiconductor substrate is performed. Next, the semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is detected by a detector arranged at a position facing the second main surface of the semiconductor substrate. A third step of detecting the reflected light of the above to specify the position of the predetermined mark is performed. Next, a fourth step is performed in which alignment is performed using the position of the predetermined mark identified in the third step as a reference, and a predetermined pattern corresponding to the surface element structure is transferred onto the resist film and exposed. Next, a fifth step is performed in which second conductivity type impurity ions are implanted using the resist film as a mask to form the second conductivity type region at a depth position away from the second main surface of the semiconductor substrate. In the first step, a detection waveform in a first direction parallel to the first main surface of the semiconductor substrate, of reflected light of the light in the predetermined wavelength range detected by the detector; A layout in which two or more peaks are detected in a second direction parallel to the surface and perpendicular to the first direction, and a plurality of peaks reaching a predetermined depth from the first main surface of the semiconductor substrate. Form a trench. As the trenches, four straight planar first trenches arranged in a point-symmetric cross-shaped layout with one end positioned at the center with a predetermined location as the center are formed. A step formed on the first main surface of the semiconductor substrate by the plurality of trenches is used as the predetermined mark. Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the inside of the trench is filled with a polysilicon film. Moreover, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the first trenches are arranged apart from each other in the first step. Moreover, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the first trench is covered with a metal film containing aluminum.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a floating second conductivity type region, which has the following features. have First, a first step of forming the surface element structure on the first main surface of the semiconductor substrate of the first conductivity type and forming a predetermined mark apart from the surface element structure is performed. Next, a second step of forming a resist film on the second main surface of the semiconductor substrate is performed. Next, the semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is detected by a detector arranged at a position facing the second main surface of the semiconductor substrate. A third step of detecting the reflected light of the above to specify the position of the predetermined mark is performed. Next, a fourth step is performed in which alignment is performed using the position of the predetermined mark identified in the third step as a reference, and a predetermined pattern corresponding to the surface element structure is transferred onto the resist film and exposed. Next, a fifth step is performed in which second conductivity type impurity ions are implanted using the resist film as a mask to form the second conductivity type region at a depth position away from the second main surface of the semiconductor substrate. In the first step, a laminated film is formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate. A cross-shaped planar groove is formed that penetrates the laminated film in the depth direction and has four linear portions arranged in a point-symmetrical cross-shaped layout with one end positioned at the center with a predetermined location as the center. . A step formed in the laminated film by the groove is used as the predetermined mark.

Further, in order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a floating second conductivity type region, which has the following features. have First, a first step of forming the surface element structure on the first main surface of the semiconductor substrate of the first conductivity type and forming a predetermined mark apart from the surface element structure is performed. Next, a second step of forming a resist film on the second main surface of the semiconductor substrate is performed. Next, the semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is detected by a detector arranged at a position facing the second main surface of the semiconductor substrate. A third step of detecting the reflected light of the above to specify the position of the predetermined mark is performed. Next, a fourth step is performed in which alignment is performed using the position of the predetermined mark identified in the third step as a reference, and a predetermined pattern corresponding to the surface element structure is transferred onto the resist film and exposed. Next, a fifth step is performed in which second conductivity type impurity ions are implanted using the resist film as a mask to form the second conductivity type region at a depth position away from the second main surface of the semiconductor substrate. In the first step, a laminated film is formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate. The laminated film is formed so that a part of the laminated film remains in four straight lines in a point-symmetrical cross-shaped layout that penetrates the laminated film in the depth direction and has one end positioned at the center with a predetermined location as the center. Form a groove around the circumference of the part. A step formed in the laminated film by the groove is used as the predetermined mark.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the trench is filled with a metal film containing aluminum. In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, the laminated film is penetrated in the depth direction and terminated at the first main surface of the semiconductor substrate. Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the first step, a first semiconductor of a second conductivity type as the surface element structure is formed on a surface layer of the first main surface of the semiconductor substrate. form a region. In the fifth step, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate is formed in a surface layer of the second main surface of the semiconductor substrate. The second conductivity type region is formed at a position deeper than the second semiconductor region. a sixth step of forming a first electrode in contact with the first semiconductor region on the first main surface of the semiconductor substrate; and a seventh step of forming a second electrode in contact with the two semiconductor regions.

According to the method for manufacturing a semiconductor device according to the present invention, in a semiconductor substrate having a first principal surface and a second principal surface which are substantially parallel to each other, the alignment mark is formed on the second principal surface different from the first principal surface. In the method of manufacturing a semiconductor device in which patterning is performed using marks, it is possible to improve the detection accuracy of the alignment marks, so that it is possible to improve the alignment accuracy.

3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. FIG. 2 is a plan view showing an example of the layout of back surface alignment marks used in the method of manufacturing the semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 6 is a cross-sectional view showing the cross-sectional structure taken along the line A-A' of FIG. 5; FIG. 2 is a plan view showing an example of the layout of back surface alignment marks used in the method of manufacturing the semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 2 is a plan view showing an example of the layout of back surface alignment marks used in the method of manufacturing the semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 9 is a cross-sectional view showing a cross-sectional structure taken along line B-B' in FIG. 8; FIG. 2 is a plan view showing an example of the layout of back surface alignment marks used in the method of manufacturing the semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 2 is a plan view showing an example of the layout of back surface alignment marks used in the method of manufacturing the semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along line C-C' of FIG. 11; FIG. 10 is a plan view showing an example of the layout of back surface alignment marks used in the method of manufacturing a semiconductor device according to the second embodiment, viewed from the front surface side of the semiconductor substrate; FIG. 13 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the second embodiment; 5 is an enlarged cross-sectional view showing the vicinity of the alignment mark for the back surface of FIG. 4; FIG. FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment; 11 is a flow chart showing an overview of a method for manufacturing a semiconductor device according to a third embodiment; FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment; 10 is a flow chart showing an outline of a method for manufacturing a semiconductor device according to a fourth embodiment; FIG. 11 is an explanatory diagram showing a detected waveform of reflected infrared light that is irradiated onto a semiconductor substrate from the back surface thereof in the method of manufacturing a semiconductor device according to the fifth embodiment; FIG. 21 is a plan view showing an example of a layout viewed from the front surface side of the semiconductor substrate, which is a modification of the back surface alignment mark shown in FIG. 20 ; 4A and 4B are diagrams showing detection results of back surface alignment marks in Example 1. FIG. FIG. 10 is a diagram showing detection results of the alignment marks for the back surface of Example 2; FIG. 11 is a diagram showing a preferable range of thickness of a semiconductor substrate of Example 3; FIG. 4 is a cross-sectional view showing a state in the middle of manufacturing a semiconductor device of a comparative example; FIG. 4 is a cross-sectional view showing a state in the middle of manufacturing a semiconductor device of a comparative example; FIG. 4 is a cross-sectional view showing a state in the middle of manufacturing a semiconductor device of a comparative example; It is a sectional view showing an example of an alignment method of a comparative example. It is a sectional view showing an example of an alignment method of a comparative example. FIG. 5 is a plan view showing an example of a layout of a back surface alignment mark of a comparative example viewed from the front surface side of a semiconductor substrate; FIG. 11 is a plan view showing a layout of the periphery of a back surface alignment mark of a comparative example as seen from the front surface side of a semiconductor substrate; FIG. 11 is a plan view showing a layout of the periphery of a back surface alignment mark of a comparative example as seen from the front surface side of a semiconductor substrate;

Preferred embodiments of the method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. In the following description of the embodiments and accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.

(Comparative example)
25 to 27 are cross-sectional views showing states in the middle of manufacturing the semiconductor device of the comparative example. 28 and 29 are cross-sectional views showing an example of the alignment method of the comparative example. FIG. 30 is a plan view showing an example of the layout of the rear surface (second main surface) alignment mark of the comparative example viewed from the front surface (first main surface) side of the semiconductor substrate.

An alignment method of a comparative example will be described. First, a predetermined surface element structure 202 is formed on the surface 201a side of the semiconductor substrate 201'. At this time, along with the surface element structure 202, alignment used in normal patterning (patterning in which the main surface of the semiconductor substrate 201 on which the alignment marks are formed and the main surface on which patterning is performed using the alignment marks are the same main surface) A back surface alignment mark 203 having a step formed by a trench 204 is formed at an arbitrary location on the front surface 201a of the semiconductor substrate 201' by the same method as the mark formation method (FIG. 25). FIG. 25 shows a simplified one-layer surface element structure 202 (also shown in FIGS. 26-29).

Next, the semiconductor substrate 201' is ground from the back surface 201b' side to fabricate the semiconductor substrate 201 having a product thickness to be used as a semiconductor device (FIG. 26). Next, a resist film 205 is formed on the back surface 201b of the semiconductor substrate 201 after grinding. Next, using an exposure apparatus 210 capable of alignment of the front surface and the back surface of the semiconductor substrate 201, the back surface alignment mark 203 on the front surface 201a of the semiconductor substrate 201 is detected, and alignment is performed using the rear surface alignment mark 203 as a reference. , a predetermined mask pattern is exposed (transferred) to the resist film 205 and developed. Thereby, the resist film 205 is patterned into a predetermined circuit pattern corresponding to the surface device structure 202 (FIG. 27). Then, etching, ion implantation, or the like is performed using the resist film 205 as a mask to form a back surface element structure (not shown) on the ground back surface 201b of the semiconductor substrate 201 . After that, the semiconductor substrate 201 is cut along the dicing lines 207 to separate into individual chips, thereby completing the semiconductor device.

As a method of detecting the back alignment mark 203 (not shown in FIG. 28) formed on the front surface 201a of the semiconductor substrate 201, the front surface 201a of the semiconductor substrate 201 is detected through an opening window 211a passing through the chuck stage 211 of the exposure apparatus 210. A method of detecting the back alignment mark 203 using a camera (hereinafter referred to as a back camera) 212 arranged at a position opposite to is known (FIG. 28). In FIG. 28 , the upward arrow indicates a state in which the back surface alignment mark 203 formed at a position 203 a facing the back surface camera 212 on the front surface 201 a of the semiconductor substrate 201 is photographed by the back surface camera 212 .

As another method of detecting the back alignment mark 203 (not shown in FIG. 29) formed on the front surface 201a of the semiconductor substrate 201, infrared (IR: Infrared) light irradiated to the semiconductor substrate 201 from the back surface 201b is reflected. A method of measuring the reflection intensity of the light 222 using a detector 223 arranged at a position facing the back surface 201 b of the semiconductor substrate 201 and detecting the back surface alignment mark 203 based on the reflection intensity of the reflected light 222 . known (Fig. 29). In FIG. 29 , the back alignment mark 203 is simplified and shown by a rectangular frame surrounding the formation location of the back alignment mark 203 . Reference numeral 221 is incident light of infrared light.

In this way, using the back camera 212 or the reflected infrared light 222, for example, the dicing line 207 or the like between the effective areas (areas to be semiconductor chips) 206 of the semiconductor substrate 201, the back surface formed by the steps of the trenches 204. Detect the alignment mark 203 (FIG. 30). In FIG. 30, trenches 204 having a cross-shaped planar shape in part of the semiconductor substrate 201 are shown by straight lines. The back surface alignment mark 203 is formed by a step between the bottom surface of the trench 204 and the surface (surface 201 a ) of the cross-shaped planar portion of the semiconductor substrate 201 surrounded by the trench 204 . A reference numeral 208 denotes a field oxide film formed along the outer periphery of the effective region 206 .

However, in the above-described alignment using the back camera 212 (see FIG. 28), the formation position of the back alignment mark 203 on the semiconductor substrate 201 is limited to the position 203a of the back camera 212 of the exposure device 210. The problem is that the degree of freedom is low. Further, the rear camera 212 is fixed to the exposure device 210, and the distance d201 to the semiconductor substrate 201' cannot be changed. Therefore, the position and shape of the back alignment mark 203 are measured by the back camera 212 at a low magnification, which poses a problem of low alignment accuracy.

In the detection of the back alignment mark 203 using the reflected infrared light 222 (see FIG. 29), when the pattern around the back alignment mark 203 is dense (not shown) or when the back alignment mark 203 is When another pattern 231 having a planar shape similar to the back alignment mark 203 exists in the periphery (FIG. 32), there is a problem that the detection accuracy of the back alignment mark 203 is lowered. This problem can be solved by increasing the size of the back alignment mark 203 or widening the pattern prohibition zone (portion surrounded by a rectangular frame of broken lines) 230 around the back alignment mark 203 .

The pattern prohibition zone 230 is an area in which other patterns 231 (patterns other than the back alignment marks 203) are not arranged. 31 and 32 are plan views showing the layout of the periphery of the back surface alignment mark of the comparative example viewed from the front surface side of the semiconductor substrate. FIG. 31 shows a state in which the pattern prohibition zone 230 around the back alignment mark 203 is widened. FIG. 32 shows a state in which another pattern 231 similar in planar shape to the back alignment mark 203 and likely to be erroneously detected as the back alignment mark 203 by the detector 223 exists within the pattern prohibition band 230 .

However, in either case of increasing the size of the back alignment mark 203 or widening the pattern prohibition zone 230 around the back alignment mark 203 , the back alignment mark 203 is not formed on the front surface 201 a of the semiconductor substrate 201 . The surface area (occupied area) of the region occupied by is increased. Since the area occupied by the back alignment mark 203 is an invalid area of the semiconductor substrate 201 where no element structure is formed, this leads to a problem that the number of chips that can be cut from the semiconductor substrate 201 (the number of semiconductor chips obtained) decreases.

(Embodiment 1)
A method for manufacturing the semiconductor device according to the first embodiment will be described. 1 to 4 are cross-sectional views showing states in the process of manufacturing the semiconductor device according to the first embodiment. 5, 7, 8, 10, and 11 show alignment marks for the back surface (second main surface) used in the manufacturing method of the semiconductor device according to the first embodiment, viewed from the front surface (first main surface) side of the semiconductor substrate. It is a top view which shows an example of a layout. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line AA' of FIG. FIG. 9 is a cross-sectional view showing a cross-sectional structure taken along line BB' of FIG. FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along line CC' of FIG.

In the method for manufacturing a semiconductor device according to the first embodiment, a semiconductor substrate (semiconductor wafer) 1 having a front surface (first main surface) 1a and a back surface (second main surface) 1b which are substantially parallel to each other, is provided with a semiconductor substrate 1 patterning (hereinafter referred to as back surface patterning) on the back surface 1b of the semiconductor substrate 1 using alignment marks (alignment marks for the back surface: not shown in FIG. 4) 3 formed on the front surface 1a of the semiconductor substrate 1 are included. Using a detector 23 arranged at a position facing the back surface 1b of the semiconductor substrate 1, detecting the reflection intensity of the reflected light 22 of the light in a predetermined wavelength range irradiated to the semiconductor substrate 1 from the back surface 1b of the semiconductor substrate 1. , the position of the back alignment mark 3 is specified. The light in the predetermined wavelength range with which the semiconductor substrate 1 is irradiated is, for example, infrared (IR) light. A case of specifying the positions of the back surface alignment marks 3 using infrared light from an infrared microscope of a general exposure apparatus 10 will be described below as an example.

Specifically, first, as shown in FIG. 1, a predetermined surface element structure 2 is formed on the surface 1a side of a semiconductor substrate 1'. At this time, the alignment mark 3 for the back surface is formed at an arbitrary location on the front surface 1a of the semiconductor substrate 1' by a method similar to the method of forming an alignment mark used in normal patterning. Alignment marks (not shown) formed by normal patterning are used for alignment for forming the surface element structure 2 . Normal patterning means that the main surface of the semiconductor substrate 1 on which the alignment marks are formed and the main surface on which patterning is performed using the alignment marks are the same main surface, and the main surface of the semiconductor substrate 1 on which the alignment marks are formed. This patterning is performed by visually recognizing the alignment mark from the side using a CCD (Charge Coupled Device) camera or the like.

The back surface alignment mark 3 is composed of a step formed on the front surface 1a of the semiconductor substrate 1'. Specifically, the back-surface alignment mark 3 is composed of, for example, a step due to a trench formed on the surface 1a of the semiconductor substrate 1' (recess: height difference between the surface 1a of the semiconductor substrate 1' and the bottom surface of the trench). may The back alignment mark 3 is formed by a groove formed in a laminated film (for example, a laminated film in which a field oxide film, a polysilicon film, an interlayer insulating film, etc. are laminated in order) laminated on the front surface 1a of the semiconductor substrate 1'. Surroundings of steps (concave portions: height difference between the surface of the laminated film and the surface of the semiconductor substrate 1′) and part of the laminated film (convex portions: height difference between the surface of the laminated film and the surface of the semiconductor substrate 1′) a step due to a groove surrounding the . The back alignment mark 3 is formed, for example, simultaneously with each portion of the front element structure 2 . A detailed description of the back alignment mark 3 will be given later.

Next, as shown in FIG. 2, the semiconductor substrate 1' is ground from the back surface 1b' side to obtain a semiconductor substrate 1 having a thickness t1 for use as a semiconductor device. Next, as shown in FIG. 3, a resist is applied to the back surface 1b of the semiconductor substrate 1 after grinding to form a resist film 4. Next, as shown in FIG. Next, using a general exposure device (not shown), a predetermined mask pattern is exposed (transferred) to the resist film 4 and developed, thereby forming a predetermined circuit pattern corresponding to the surface element structure 2 on the resist film 4 . is patterned (back surface patterning). Alignment for transferring a predetermined mask pattern to resist film 4 on back surface 1b of semiconductor substrate 1 will be described with reference to FIG. In FIG. 4 , the back alignment mark 3 is simplified and shown by a rectangular frame surrounding the formation location of the back alignment mark 3 .

For alignment (alignment) between the semiconductor substrate 1 and a mask pattern for transferring a predetermined mask pattern to the resist film 4 on the back surface 1 b of the semiconductor substrate 1 , the back alignment marks 3 on the front surface 1 a of the semiconductor substrate 1 are used. is used. For this reason, first, the infrared microscope of the general exposure apparatus 10 is used to detect the back surface alignment mark 3 on the front surface 1 a of the semiconductor substrate 1 . Specifically, as shown in FIG. 4, the semiconductor substrate 1 is placed on the chuck stage 11 of a general exposure apparatus 10 capable of aligning the front and back surfaces of the semiconductor substrate 1 with the front surface 1a facing the chuck stage 11 side. to be placed.

Next, the detector 23 measures the reflection intensity of the reflected infrared light 22 that irradiates the semiconductor substrate 1 from the back surface 1 b , and the back alignment mark 3 is detected based on the reflection intensity of the reflected light 22 . Infrared light is laser light in the infrared wavelength range. The infrared light is applied at a power density (W (watt)/cm ² ) that does not heat the semiconductor substrate 1 . A method for detecting the back alignment mark 3 will be described later. The detector 23 is arranged above the chuck stage 11 with the semiconductor substrate 1 interposed therebetween so as to face the back surface 1 b of the semiconductor substrate 1 . In FIG. 4, the semiconductor substrate 1 is shown separated from the chuck stage 11 in order to clarify the paths of the incident light 21 and the reflected light 22 of infrared light. It is placed in contact with the stage 11 .

Incident infrared light 21 travels inside the semiconductor substrate 1 from the back surface 1b of the semiconductor substrate 1 toward the front surface 1a. The reflected infrared light 22 travels inside the semiconductor substrate 1 from the front surface 1a side of the semiconductor substrate 1 toward the back surface 1b side. The detector 23 is arranged at a position facing the back alignment mark 3 on the front surface 1 a of the semiconductor substrate 1 with the semiconductor substrate 1 interposed therebetween. The detector 23 is movable in a direction parallel to the back surface 1 b of the semiconductor substrate 1 . Therefore, there is a high degree of freedom in the layout of the locations where the back alignment marks 3 are formed on the front surface 1 a of the semiconductor substrate 1 . The locations where the back alignment marks 3 are formed are, for example, invalid areas (areas not used as semiconductor chips) such as dicing lines.

Alignment (positioning) is performed using the back surface alignment mark 3 as a reference, and the resist film 4 is exposed to a predetermined mask pattern and developed. As a result, the resist film 4 can be patterned into a predetermined circuit pattern corresponding to the surface element structure 2. Next, as shown in FIG. Next, etching, ion implantation, and the like are performed using the resist film 4 as a mask to form a back element structure (not shown) on the ground back surface 1 b of the semiconductor substrate 1 . After that, the semiconductor substrate 1 is diced (cut) along the dicing lines to separate into individual chips, thereby completing a semiconductor device having a predetermined element structure.

As shown in FIGS. 5 and 6, the back alignment mark 3 is configured using a step (recess) formed by the surface 1a of the semiconductor substrate 1 and the bottom surface of a trench formed on the surface 1a of the semiconductor substrate 1. be done. The back surface alignment mark 3 has a planar shape with a layout in which three or more trenches are arranged in a direction parallel to the front surface 1 a of the semiconductor substrate 1 . Specifically, for example, the back surface alignment mark 3 has a planar shape with a layout in which three trenches 31 a to 31 c are arranged in a direction parallel to the front surface 1 a of the semiconductor substrate 1 .

In this case, the back surface alignment mark 3 is composed of, for example, trenches (hereinafter referred to as first trenches) 33 arranged in a cross-shaped layout when viewed from the front surface 1a side of the semiconductor substrate 1, and separated from the first trenches 33. and one trench (hereinafter referred to as a second trench) 34 arranged along the first trench 33 in a layout surrounding the periphery of the first trench 33 in a cross shape. . A polysilicon (poly-Si) film 35 is buried inside the first and second trenches 33 and 34 .

For example, when the surface element structure 2 is a trench gate structure, the first and second trenches 33 and 34 are formed at the same time as the gate trench (the trench in which the gate electrode is buried), and the polysilicon film 35 is formed at the same time as the gate electrode. . For example, the first trench 33 may be composed of four linear planar trench portions having a predetermined location as the center 32 and having one end located at the center 32 and being spaced apart from each other in a cross-shaped layout. preferable. That is, it is preferable that the four linear planar trench portions that constitute the first trench 33 do not contact at the center 32 of the cross-shaped layout. The reason is as follows.

When the four linear planar trench portions forming the first trench 33 intersect at the center 32 of the cross-shaped layout, the width of the trench is wider at the center 32 than at other locations. For this reason, the first trench 33 cannot be completely filled with the polysilicon film 35 at the center 32 of the cross-shaped layout. This is because there is a possibility that the detection accuracy of the back surface alignment mark 3 may be lowered. When forming the back surface alignment mark 3 with the first and second trenches 33 and 34 in this way, among the three trenches 31a to 31c arranged in the direction parallel to the front surface 1a of the semiconductor substrate 1, the middle trench 31b is the first trench. The trench 33 is formed, and the trenches 31 a and 31 c on both sides are formed by the second trenches 34 .

For example, when the back alignment mark 3 is formed on a dicing line having a width about the blade width of a dicing saw (for example, about 100 μm), the maximum widths w11 and w12 ( 5) is preferably, for example, about 30 μm or more and 80 μm or less. The first and second directions X and Y are directions parallel to the surface 1a of the semiconductor substrate 1 and perpendicular to each other. In other words, it is preferable that the back surface alignment mark 3 has a size that can be accommodated in a region having a surface area of about 80 μm square. The minimum widths w1 and w2 (see FIG. 6) of the first and second trenches 33 and 34 are approximately equal to or greater than the minimum processing limit of etching (0.3 μm, for example), preferably 0.8 μm or greater, for example. The width (mesa width) w3 between the first and second trenches 33 and 34 (mesa region) is preferably six times or more the minimum widths w1 and w2 of the first and second trenches 33 and 34, for example about 16 μm or less. may be

As shown in FIG. 7, the back surface alignment mark 3 ′ may have a configuration in which five trenches are arranged in a direction parallel to the surface of the semiconductor substrate 1 . In this case, the back alignment mark 3' in FIG. 7 is located between the adjacent first and second trenches 33 and 34 of the back alignment mark 3 in FIGS. Furthermore, a trench (hereinafter referred to as a third trench) 36 may be arranged apart from the first and second trenches 33 and 34 . The third trenches 36 are arranged in, for example, an L-shaped layout along the two first trenches 33 arranged in a substantially right-angled layout when viewed from the front surface 1a side of the semiconductor substrate 1 . The second trenches 34 are arranged, for example, in a layout that surrounds the third trenches 36 along the third trenches 36 so as to form a cross shape when viewed from the front surface 1a side of the semiconductor substrate 1 .

Further, as shown in FIGS. 8 and 9, the back alignment mark 40a includes the surface of the laminated film 45 on the surface 1a of the semiconductor substrate 1 and the bottom surface of the groove 44 penetrating the laminated film 45 in the depth direction Z ( The surface 1a) of the semiconductor substrate 1 may be configured using a step (recess) formed by the surface 1a). The laminated film 45 is formed by laminating, for example, a field oxide film 41, a polysilicon film 42 and an interlayer insulating film 43 in this order. The field oxide film 41 is, for example, an initial oxide film. The interlayer insulating film 43 is, for example, a BPSG (Boro Phospho Silicate Glass) film. The depth direction Z is the direction from the front surface 1a of the semiconductor substrate 1 to the back surface 1b. The planar shape of the groove 44 may be, for example, a cross shape obtained by intersecting two linear portions parallel to the first and second directions X and Y, respectively.

As the number of laminated films 45 in which the grooves 44 are formed (penetrated) increases, the step due to the grooves 44 increases. Infrared light 22 reflected by the upper step), infrared light 22 reflected by the surface of the interlayer insulating film 43 (lower step when viewed from the back surface 1b side of the semiconductor substrate 1), contrast (difference in light and shade) is increased, and the detection accuracy of the back alignment mark 40a is improved. The back surface alignment mark 40a has a cross-sectional shape that is recessed from the surface of the interlayer insulating film 43 toward the semiconductor substrate 1 side.

The back alignment mark 40a' in FIG. 10 differs from the back alignment mark 40a in FIGS. The point is that the laminated film 45' is selectively left inside the penetrating groove 44'. The groove 44' surrounds the laminated film 45'. Laminated membrane 45' is a portion of laminated membrane 45 separated by groove 44'. That is, the back surface alignment mark 40a' in FIG. 10 is configured using a step formed by the surfaces of the laminated films 45 and 45' and the bottom surface of the groove 44' (the surface 1a of the semiconductor substrate 1). . The planar shape of the groove 44' may be, for example, a cross shape formed by intersecting two linear portions parallel to the first and second directions X and Y, respectively. The planar shape of the laminated film 45 ′ may be, for example, a cross shape formed by intersecting two linear portions parallel to the first and second directions X and Y, respectively.

As the number of laminated films 45 in which the groove 44 ′ is formed (through) and the number of laminated films 45 ′ remaining inside the groove 44 ′ are increased, the step due to the groove 44 ′ increases. 8 and 9, the contrast due to the reflected infrared light 22 is increased, and the detection accuracy of the back alignment mark 40a' can be improved. The planar shape of the laminated film 45' may be, for example, a cross shape. The back alignment mark 40a' protrudes away from the front surface 1a of the semiconductor substrate 1 at the central portion and has a cross-sectional shape recessed from the surface of the interlayer insulating film 43 toward the semiconductor substrate 1 at the outer peripheral portion (not shown).

As shown in FIGS. 11 and 12, the back surface alignment mark 40b is formed by the bottom surface of the groove 46 (the surface 1a of the semiconductor substrate 1) and the surface of the laminated film 47 surrounded by the groove 46. You may be comprised using a level|step difference. The trench 46 penetrates the interlayer insulating film 43, the polysilicon film 42 and the field oxide film 41 in the depth direction Z. As shown in FIG. Laminated film 47 is part of field oxide film 41 , polysilicon film 42 and interlayer insulating film 43 separated by trench 46 .

That is, the back-surface alignment mark 40b has a cross-sectional shape that protrudes away from the front surface 1a of the semiconductor substrate 1 . The planar shape of the laminated film 47 may be, for example, a cross shape obtained by intersecting two linear portions parallel to the first and second directions X and Y, respectively. As with the back alignment mark 40a in FIGS. 8 and 9, as the number of layers of the laminated film 47 increases, the difference in level due to the groove 46 increases. 40b can be improved in detection accuracy.

The alignment marks 3, 3', 40a, 40a', and 40b for the back surface are formed with such a configuration. As a result, the alignment marks 3, 3', 40a, 40a', 40b for the back surface formed on the front surface 1a of the semiconductor substrate 1 based on the reflection intensity of the reflected infrared light 22 irradiated from the back surface 1b of the semiconductor substrate 1 are aligned. can be improved in detection accuracy of the back alignment marks 3, 3', 40a, 40a', and 40b.

As described above, according to the first embodiment, steps of a plurality of trenches arranged in a layout of three or more each in the first direction and the second direction on the surface of the semiconductor substrate, or steps of the semiconductor substrate. The alignment mark for the back surface is formed by the step due to the groove penetrating the laminated film laminated on the front surface in the depth direction. As a result, using an infrared microscope of a general exposure apparatus, it is possible to improve the detection accuracy of the back surface alignment mark on the front surface of the semiconductor substrate by reflected light of the infrared light irradiated from the back surface of the semiconductor substrate. . Therefore, alignment accuracy can be improved.

Further, according to the first embodiment, since the detection accuracy of the back alignment mark is improved, the size of the back alignment mark and the area (pattern forbidden zone) in which patterns other than the back alignment mark are not arranged are increased. The alignment marks for the back surface can be detected without the Therefore, the number of chips (the number of semiconductor chips obtained) that can be cut from the semiconductor substrate (semiconductor wafer) can be maintained. Further, according to the first embodiment, since the back alignment mark is detected by infrared light, the position where the back alignment mark is formed is not limited. Therefore, the degree of freedom in layout design is high.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be explained. FIG. 13 is a plan view showing an example of the layout of the back surface alignment marks used in the semiconductor device manufacturing method according to the second embodiment, viewed from the front surface side of the semiconductor substrate. In FIG. 13, reference numeral 5 denotes an effective area (area to be a semiconductor chip) of the semiconductor substrate 1 surrounded by the field oxide film 41 on the outer periphery. The semiconductor device manufacturing method according to the second embodiment differs from the semiconductor device manufacturing method according to the first embodiment in that a metal film 52 is formed on the front surface 1a of the semiconductor substrate 1 so as to cover the rear surface alignment marks 51. This is the point.

The back alignment marks 51 are the back alignment marks 3, 3', 40a, 40a', 40b (FIGS. 5 to 12) of the first embodiment. The maximum widths w11 and w12 of the back alignment mark 51 in the first and second directions X and Y are preferably about 70 μm or less, for example. The metal film 52 has, for example, a rectangular planar shape. The minimum values of the lengths of the two sides sharing one vertex of the metal film 52 are the maximum widths w11 and w12 of the back alignment mark 51 in the first and second directions X and Y, respectively. Widths w21 and w22 of the metal film 52 in the first and second directions X and Y are equal to or greater than the maximum widths w11 and w12 of the back alignment mark 51 in the first and second directions X and Y, respectively, and are equal to or larger than the width w31 of the dicing line 6. narrower than

The metal material of the metal film 52 can be changed variously. Specifically, the metal film 52 is a part of a metal film deposited (formed) on the surface 1a of the semiconductor substrate 1 for forming a surface electrode (for example, an emitter electrode 68 described later: see FIG. 16). , may be formed by leaving them on the surface of the back surface alignment mark 51 . That is, the metal material of the metal film 52 is the same metal material as the surface electrode, specifically, for example, aluminum (Al) or an aluminum alloy containing aluminum, such as aluminum-silicon (Al--Si). good too.

The method of manufacturing the semiconductor device according to the second embodiment is the same as the method of manufacturing the semiconductor device according to the first embodiment, after forming the alignment marks 51 for the back surface and before patterning the back surface, the surface of the alignment marks 51 for the back surface is coated with a metal. It may be covered with a film 52 . FIG. 14 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the second embodiment. FIG. 14 shows an example in which the back alignment mark 51 is the back alignment mark 3 of FIGS. FIG. 15 is an enlarged cross-sectional view showing the vicinity of the back surface alignment mark in FIG.

As shown in FIGS. 14 and 15, during alignment for patterning the back surface, the semiconductor substrate 1 is irradiated with infrared light substantially perpendicularly from the back surface 1b of the semiconductor substrate 1 to the back surface 1b of the semiconductor substrate 1, as described above. . Since the incident infrared light 21 does not pass through the polysilicon film 35 inside the trenches 31a to 31c, it is reflected at the bottoms of the trenches 31a to 31c. Reflected light 22a of the infrared light reflected at the bottoms of the trenches 31a to 31c travels from the back surface 1b of the semiconductor substrate 1 to the outside of the semiconductor substrate 1 substantially perpendicularly to the back surface 1b of the semiconductor substrate 1, and reaches the back surface 1b of the semiconductor substrate 1. is detected by the detector 23 facing the .

When the back surface alignment mark 3 is not covered with the metal film 52 as shown in FIG. At locations other than the arrangement locations, the semiconductor substrate 1 is penetrated and progresses outward from the surface 1a of the semiconductor substrate 1 substantially perpendicular to the surface 1a of the semiconductor substrate 1 . For this reason, the reflection intensity of the reflected light 22b of the infrared light irradiated to the locations other than the locations where the trenches 31a to 31c are arranged decreases as the thickness t1 of the semiconductor substrate 1 increases, and the reflection intensity of the reflected light 22b decreases as the thickness t1 of the semiconductor substrate 1 increases. It is difficult to be detected by the detector 23 that does.

On the other hand, when the back surface alignment mark 51 is covered with the metal film 52 as shown in FIG. Since the incident light 21 does not pass through the metal film 52, it is reflected by the metal film 52 (the interface between the metal film 52 and the semiconductor substrate 1). Therefore, the reflected light 22c of the infrared light reflected by the metal film 52 has little decrease in reflection intensity, and travels from the back surface 1b of the semiconductor substrate 1 to the outside of the semiconductor substrate 1 substantially perpendicularly to the back surface 1b of the semiconductor substrate 1. Therefore, it is easily detected by the detector 23 facing the back surface 1 b of the semiconductor substrate 1 .

Therefore, by covering the back alignment mark 51 with the metal film 52, the detection accuracy of the back alignment mark 51 by the reflected infrared light 22 can be improved as compared with the case where the metal film 52 is not provided. . In addition, since the incident infrared light 21 that travels through the semiconductor substrate 1 from the back surface 1 b of the semiconductor substrate 1 and reaches the front surface 1 a of the semiconductor substrate 1 can be reliably reflected by the metal film 52 , the metal film 52 The thickness t1 of the semiconductor substrate 1 can be increased as compared with the case where the is not provided. Specifically, when the semiconductor substrate 1 is a silicon substrate, the upper limit of the thickness t1 of the semiconductor substrate 1 is, for example, about 400 μm.

Further, by improving the detection accuracy of the back alignment mark 51, the surface area of the pattern prohibition zone 50 (the portion surrounded by the rectangular frame of the dashed line in FIG. 13) can be made smaller than the configuration of the comparative example (FIGS. 31 and 32). can be done. Specifically, the surface area of the pattern forbidden zone 50 can be reduced to approximately the same surface area as the metal film 52 (=width w21×width w22), for example. Therefore, other patterns (for example, patterns similar in planar shape to the back alignment mark 51) 53 that are likely to be erroneously detected as the back alignment mark 51 by the detector 23 are not arranged in the pattern prohibition zone 50. FIG.

Further, the back alignment mark 51 may have the same configuration as the back alignment mark 203 (see FIG. 31) of the comparative example. Even if the back alignment mark 51 has the same configuration as the back alignment mark 203 of the comparative example, the detection accuracy of the back alignment mark 51 can be improved by covering the back alignment mark 51 with the metal film 52 . .

As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained. Further, according to the second embodiment, a metal film is provided on the front surface of the semiconductor substrate so as to cover the back surface alignment mark. As a result, the incident light of the infrared light, which is irradiated to the semiconductor substrate from the back surface of the semiconductor substrate, travels through the semiconductor substrate and reaches the front surface of the semiconductor substrate, is transferred to the metal film covering the alignment marks for the back surface on the front surface of the semiconductor substrate. can be reflected by Therefore, compared with the case where the back alignment mark is not covered with a metal film, the reflection intensity of the reflected infrared light is less reduced, and the detection accuracy of the back alignment mark can be improved.

Further, according to the second embodiment, the size of the back surface alignment mark and the area (pattern forbidden zone) in which patterns other than the alignment mark for the back surface are not increased are not increased. Only alignment marks can be detected.

(Embodiment 3)
Next, as the semiconductor device according to the third embodiment, an example of the structure of the semiconductor device manufactured by the method for manufacturing the semiconductor device according to the first and second embodiments will be described. FIG. 16 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

The semiconductor device according to the third embodiment shown in FIG. 16 includes an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure and an FWD (Free Wheeling Diode) connected in anti-parallel to the IGBT. are integrated on the same semiconductor substrate (semiconductor chip) 1 (RC-IGBT: Reverse Conducting IGBT).

On the same n ⁻ -type semiconductor substrate 1 , an IGBT region 81 and an FWD region 82 are provided in parallel in the active region in a direction parallel to the surface 1 a of the semiconductor substrate 1 . The IGBT region 81 is a region in which the IGBT is arranged and which becomes an operating region of the IGBT. The FWD area 82 is an area in which the FWD is arranged and becomes an operating area of the FWD. The active region is the region through which the main current flows when in the ON state.

Only the active region is shown in FIG. 16 and the edge termination region surrounding the active region is omitted. The edge termination region is a region between the active region and the side surface of the semiconductor substrate 1, and is a region for alleviating the electric field on the chip surface side of the n ⁻ -type drift region 61 and maintaining the breakdown voltage (breakdown voltage). . The withstand voltage is the limit voltage at which the element does not malfunction or break down. A breakdown voltage structure such as a guard ring or field plate may be provided in the edge termination region.

A surface layer of the surface 1a of the semiconductor substrate 1 is provided with a p-type base region 62 of the IGBT. The p-type base region 62 is provided over the entire active region from the IGBT region 81 to the FWD region 82 . The p-type base region 62 also serves as the p-type anode region in the FWD region 82 . Inside the p-type base region 62 , an n ⁺ -type emitter region 63 and a p ⁺ -type contact region 64 are selectively provided only in the IGBT region 81 .

The n ⁺ -type emitter region 63 only needs to be arranged in at least one mesa region between adjacent gate trenches 65 (mesa regions), which will ^be described later. good. Portions of the semiconductor substrate 1 other than the p-type base region 62, an n-type field stop (FS: Field Stop) region 69, a p ⁺ -type collector region 70, and an n ⁺ -type cathode region 71, which will be described later, are the n ⁻ -type drift regions 61. be.

A gate trench 65 is provided in the depth direction Z from the surface 1 a of the semiconductor substrate 1 to reach the n ⁻ type drift region 61 through the n ⁺ type emitter region 63 and the p type base region 62 . The gate trenches 65 are arranged, for example, in a striped layout extending in a direction (depth direction in the figure) perpendicular to the direction in which the IGBT regions 81 and the FWD regions 82 are arranged when viewed from the front surface 1a side of the semiconductor substrate 1. .

A plurality of gate trenches 65 are arranged with the same layout from the IGBT region 81 to the FWD region 82 . That is, the gate trench 65 of the FWD region 82 is arranged parallel to the gate trench 65 of the IGBT region 81 when viewed from the surface 1a side of the semiconductor substrate 1 . In the FWD region 82 , the gate trench 65 reaches the n ⁻ -type drift region 61 through the p-type base region 62 (p-type anode region).

A gate electrode 67 is provided inside the gate trench 65 with a gate insulating film 66 interposed therebetween. A field oxide film 41 (see FIGS. 6, 9 and 11) covers the surface 1a of the semiconductor substrate 1 in the edge termination region. Interlayer insulating film 43 is provided on field oxide film 41 and surface 1 a of semiconductor substrate 1 in the active region to cover gate electrode 67 . An emitter electrode 68 is provided on the interlayer insulating film 43 .

Emitter electrode 68 is in contact with n ⁺ -type emitter region 63 and p ⁺ -type contact region 64 in IGBT region 81 through a contact hole, which is an opening in interlayer insulating film 43 . Further, the emitter electrode 68 is in contact with the p-type base region 62 through the contact hole of the interlayer insulating film 43 in the FWD region 82 and functions as an anode electrode. A surface passivation film (not shown) covers the surface 1a of the semiconductor substrate 1 in the edge termination region.

An n-type FS region 69 is provided from the IGBT region 81 to the FWD region 82 in the surface layer of the back surface 1 b of the semiconductor substrate 1 . A plurality of n-type FS regions 69 may be arranged at different depths from the back surface 1 b of the semiconductor substrate 1 . In the surface layer of the back surface 1b of the semiconductor substrate 1, a p ⁺ -type collector region 70 is provided in the IGBT region 81 at a position shallower than the n-type FS region 69, and an n ⁺ -type cathode region 71 is provided in the FWD region 82. is provided.

The p ⁺ -type collector region 70 contacts the n ⁺ -type cathode region 71 in the direction in which the IGBT region 81 and the FWD region 82 are aligned. The p ⁺ -type collector region 70 and the n ⁺ -type cathode region 71 may be in contact with the n-type FS region 69 in the depth direction Z. A collector electrode 72 is provided on the back surface 1 b of the semiconductor substrate 1 . The collector electrode 72 is in contact with the p ⁺ -type collector region 70 and the n ⁺ -type cathode region 71 to serve also as a cathode electrode.

Next, a method for manufacturing the semiconductor device according to the third embodiment (that is, a specific example of the method for manufacturing the semiconductor device according to the first embodiment) will be described. FIG. 17 is a flowchart outlining the method for manufacturing a semiconductor device according to the third embodiment. First, an n ^- -type semiconductor substrate (semiconductor wafer) 1' that will be the n ^- -type drift region 61 is prepared. Next, on the front surface 1a side of the semiconductor substrate 1', each part of the front element structure 2 and the back alignment mark 3 are formed by normal patterning (step S1: see FIGS. 1, 5 and 6).

In step S1, a surface device structure 2 is formed in the active area. A breakdown voltage structure may be formed in the edge termination region along with the surface device structure 2 . The active area and the edge termination area are effective areas (areas that will become semiconductor chips) of the semiconductor substrate 1'. The back surface alignment marks 3 are formed, for example, on dicing lines that are invalid regions of the semiconductor substrate 1'. Instead of the back alignment marks 3 shown in FIGS. 5 and 6, back alignment marks 3' shown in FIG. 7 may be formed.

In the RC-IGBT shown in FIG. 16, the parts of the surface element structure 2 are the p-type base region 62, the n ⁺ -type emitter region 63, the p ⁺ -type contact region 64, the gate trench 65, the gate insulating film 66, and the gate electrode. 67, an interlayer insulating film 43, an emitter electrode 68, a field oxide film (not shown), a surface protective film (not shown), and the like. Specifically, for example, the surface element structure 2 is formed as follows.

First, a p-type base region 62 is formed in the surface layer of the surface 1a of the semiconductor substrate 1'. Next, the surface 1a of the semiconductor substrate 1' is thermally oxidized to form a field oxide film covering the surface 1a of the semiconductor substrate 1' in the edge termination region. Next, by photolithography and etching, a gate trench 65 that penetrates the p-type base region 62 in the depth direction Z and reaches the n ⁻ -type drift region 61 is formed.

At this time, along with the gate trench 65, the first and second trenches 33 and 34 (trenches 31a to 31c: see FIG. 6) are formed as the alignment marks 3 for the rear surface. Instead of the back alignment marks 3 shown in FIGS. 5 and 6, back alignment marks 3' shown in FIG. 7 may be formed. In this case, the first to third trenches 33, 34, 36 may be formed together with the gate trench 65. FIG.

Next, the inner wall of the gate trench 65 is thermally oxidized to form a gate insulating film 66 along the inner wall of the gate trench 65 . Next, a polysilicon film is formed on the surface 1a of the semiconductor substrate 1' so as to fill the inside of the gate trench 65 and the insides of the first and second trenches 33 and 34 (or the first to third trenches 33, 34 and 36). Deposit (form). Next, this polysilicon film is etched back to leave the polysilicon film that will become the gate electrode 67 inside the gate trench 65 with the gate insulating film 66 interposed therebetween. In addition, the polysilicon film 35 is left inside the first and second trenches 33 and 34 (or the first to third trenches 33, 34 and 36).

Next, an n ⁺ -type emitter region 63 and a p ⁺ -type contact region 64 are selectively formed inside the p-type base region 62 in the IGBT region 81 . Next, an interlayer insulating film 43 is formed to cover the gate electrode 67 on the surface 1a of the semiconductor substrate 1'. Next, the interlayer insulating film 43 is patterned to form a plurality of contact holes penetrating the interlayer insulating film 43 in the depth direction Z. As shown in FIG.

Instead of the alignment marks 3, 3' for the rear surface, a step formed by trenches 44, 44' passing through the interlayer insulating film 43, the polysilicon film 42 and the field oxide film 41 (laminated film 45) in the depth direction Z is used. Rear alignment marks 40a and 40a' (see FIGS. 8 to 10) may be formed.

Alternatively, instead of the alignment marks 3, 3' for the back surface, a step formed by a groove 46 surrounding the interlayer insulating film 43, the polysilicon film 42 and a portion of the field oxide film 41 (laminated film 47) is used for the back surface. Alignment marks 40b (see FIGS. 11 and 12) may be formed.

Next, a metal film made of, for example, aluminum-silicon (Al—Si) containing aluminum (Al) is formed on the interlayer insulating film 43 so as to fill the contact hole. Next, the metal film is patterned to leave a portion that will become the emitter electrode 68 in a predetermined region (for example, only the active region). Next, a surface protection film is formed on the surface 1a of the semiconductor substrate 1 to cover the edge termination region. Through the steps up to this point, the surface element structure 2 is completed.

Next, the semiconductor substrate 1' is ground from the back surface 1b' side (back surface grinding) to obtain a semiconductor substrate 1 having a thickness t1 for use as a semiconductor device (step S2: see FIG. 2).

Next, by ion implantation of n-type impurities, an n-type FS region 69 is formed in the surface layer of the back surface 1b of the semiconductor substrate 1 over the entire back surface 1b of the semiconductor substrate 1 (step S3). Next, p + -type collector region 70 is formed over the entire back surface 1b of semiconductor substrate 1 at a position shallower than n-type FS region 69 in the surface layer of back surface 1b of semiconductor substrate 1 by ion implantation of p ^- type impurities. form (step S4).

Next, a resist is applied on the back surface 1b of the semiconductor substrate 1 to form a resist film 4 (see FIG. 3). Next, using a general exposure device (not shown), a predetermined mask pattern is exposed (transferred) to the resist film 4 and developed, thereby forming a predetermined circuit pattern corresponding to the surface element structure 2 on the resist film 4 . patterning (rear surface patterning) to form a resist mask with an opening corresponding to the formation region of the n ⁺ -type cathode region 71 (step S5). The process of step S5 corresponds to back surface patterning (see FIG. 4) in the method of manufacturing the semiconductor device according to the first embodiment.

Next, using this resist mask as an ion implantation mask, an n-type impurity is ion-implanted to change part of the p ⁺ -type collector region 70 to n ⁺ -type, thereby forming an n ⁺ -type cathode region 71 (step S6). . If p-type impurity ions are implanted only in the formation region of the p ⁺ -type collector region 70 in the process of step S4, then in the process of step S6, the opening of the resist mask on the rear surface 1b of the semiconductor substrate 1 is filled with ions. An n ⁺ -type cathode region 71 is formed in the exposed n ^- -type portion.

Also, the formation order of the p ⁺ -type collector region 70 and the n ⁺ -type cathode region 71 may be changed. In this case, the n ⁺ -type cathode region 71 is formed over the entire back surface 1b of the semiconductor substrate 1 in the process of step S4, and the resist mask is opened in the portion corresponding to the forming region of the p ⁺ -type collector region 70 in the process of step S5. to form Then, in the process of step S6, the p ⁺ -type collector region 70 may be formed using the resist mask as an ion implantation mask. The n-type FS region 69 in step S3 may be formed after the p ⁺ -type collector region 70 and the n ⁺ -type cathode region 71 are formed.

Next, the resist mask is removed by ashing. Next, annealing (heat treatment) is performed for activating the impurity ion-implanted into the semiconductor substrate 1 (step S7). Next, a collector electrode 72 is formed on the entire back surface 1b of the semiconductor substrate 1 (step S8). Thereafter, the semiconductor substrate 1 is cut (diced) into individual chips to complete the RC-IGBT chips (semiconductor chips) shown in FIG.

The semiconductor device according to the third embodiment may be formed by the manufacturing method of the semiconductor device according to the second embodiment. In this case, in step S1, the surfaces of the back surface alignment marks 3, 3′, 40a, 40a′, and 40b of the metal film deposited (formed) on the surface 1a of the semiconductor substrate 1 for forming the emitter electrode 68 are aligned. The covering portion may be left as the metal film 52 (see FIGS. 13 and 14).

As described above, the semiconductor device according to the third embodiment can be manufactured using the method for manufacturing the semiconductor device according to the first and second embodiments.

(Embodiment 4)
Next, another example of the structure of the semiconductor device manufactured by the method of manufacturing the semiconductor device according to the first and second embodiments will be described as the semiconductor device according to the fourth embodiment. FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. In the semiconductor device according to the fourth embodiment shown in FIG. 18, a floating (electrically floating) p-electrode is provided at a position deeper than the n ⁺ -type cathode region 93 from the back surface 1b of the n ⁻ -type semiconductor substrate (semiconductor chip) 1 . The FWD has a type region (hereinafter referred to as a p-type floating region) 94 .

Only the active region is shown in FIG. 18 and the edge termination region surrounding the active region is omitted. Also, although one unit cell of the FWD is shown in FIG. 18, a plurality of adjacent unit cells may be arranged in the active region. The edge termination region is a region between the active region and the side surface of the semiconductor substrate 1, and is a region for alleviating the electric field on the chip surface side of the n ⁻ -type drift region 91 and maintaining the breakdown voltage. A breakdown voltage structure such as a guard ring or field plate may be provided in the edge termination region.

A p ⁺ -type anode region 92 is selectively provided in the surface layer of the surface 1 a of the semiconductor substrate 1 . The p ⁺ -type anode region 92 may be provided over the entire surface of the semiconductor substrate 1 in the active region. An n ⁺ -type cathode region 93 is provided in the surface layer of the back surface 1b of the semiconductor substrate 1 from the active region to the edge termination region. A p-type floating region 94 is selectively provided in the surface layer of the back surface of the semiconductor substrate 1 at a position deeper than the n ⁺ -type cathode region 93 from the back surface 1 b of the semiconductor substrate 1 .

A plurality of p-type floating regions 94 are arranged at predetermined intervals in a direction parallel to back surface 1b of semiconductor substrate 1 . The p-type floating region 94 is arranged apart from a cathode electrode 97, which will be described later, and is floating (electrically floating). The p-type floating region 94 may be in contact with the n ⁺ -type cathode region 93 . A portion of semiconductor substrate 1 other than p ⁺ -type anode region 92 , n ⁺ -type cathode region 93 and p-type floating region 94 is n ⁻ -type drift region 91 .

An n ^- type FS region 95 is provided inside the n − -type drift region 91 from the active region to the edge termination region. The n-type FS region 95 is arranged inside the n ⁻ -type drift region 91 and closer to the n ⁺ -type cathode region 93 . The n-type FS region 95 is arranged at a position deeper than the p-type floating region 94 from the back surface 1 b of the semiconductor substrate 1 . The n-type FS region 95 may be in contact with the n ⁺ -type cathode region 93 and the p-type floating region 94 . A plurality of n-type FS regions 95 may be arranged at different depths from back surface 1 b of semiconductor substrate 1 .

In the edge termination region, the surface 1a of the semiconductor substrate 1 is covered with a field oxide film 41 (see FIGS. 6, 9 and 11). A polysilicon film 42 and an interlayer insulating film 43 are laminated in this order on the field oxide film 41 . A contact hole, which is an opening of the interlayer insulating film 43 , exposes the p ⁺ -type anode region 92 .

Anode electrode 96 is in contact with p ⁺ -type anode region 92 through a contact hole in interlayer insulating film 43 . A surface passivation film (not shown) covers the surface 1a of the semiconductor substrate 1 in the edge termination region. Interlayer insulating film 43, field oxide film 41 and surface protective film surround the active region. Cathode electrode 97 is provided on the entire back surface 1 b of semiconductor substrate 1 and is in contact with n ⁺ -type cathode region 93 .

Next, a method for manufacturing the semiconductor device according to the fourth embodiment (that is, a specific example of the method for manufacturing the semiconductor device according to the first embodiment) will be described. FIG. 19 is a flowchart outlining the method for manufacturing a semiconductor device according to the fourth embodiment. First, an n ^- -type semiconductor substrate (semiconductor wafer) 1' to be the n ^- -type drift region 91 is prepared.

Next, on the front surface 1a side of the semiconductor substrate 1', each part of the front surface element structure 2 and the rear surface alignment mark 40a are formed by normal patterning (step S11: see FIGS. 1, 8 and 9). In step S11, the conditions other than the structure of each part of the front surface element structure 2 and the structure of the back surface alignment mark 40a are the same as those of the third embodiment.

Instead of the back alignment mark 40a, a back alignment mark 40a' in FIG. 10 or a back alignment mark 40b in FIGS. 11 and 12 may be formed. In the FWD shown in FIG. 18, the parts of the surface element structure 2 are the p ⁺ -type anode region 92, the interlayer insulating film 43, the anode electrode 96, the field oxide film 41 (see FIGS. 8 and 9), and the surface protective film. (not shown), etc.

Specifically, for example, the surface element structure 2 is formed as follows. First, the surface 1a of the semiconductor substrate 1' is thermally oxidized to form a field oxide film 41 covering the surface 1a of the semiconductor substrate 1' in the edge termination region. Next, a p ⁺ -type anode region 92 is formed in the surface layer of the surface 1a of the semiconductor substrate 1' in the active region. Next, an interlayer insulating film 43 is formed on the surface 1a of the semiconductor substrate 1'.

Next, the interlayer insulating film 43 is patterned to form a plurality of contact holes penetrating the interlayer insulating film 43 in the depth direction Z. As shown in FIG. At this time, a contact hole was formed in the interlayer insulating film 43, and a step formed by a groove 44 penetrating the interlayer insulating film 43, the polysilicon film 42 and the field oxide film 41 (laminated film 45) in the depth direction Z was used. A rear alignment mark 40a (see FIGS. 8 and 9) is formed.

Instead of the back alignment mark 40a, a groove 44' is formed so that the laminated film 45' (part of the laminated film 45) remains inside, and the back alignment mark 40a' using the step formed by the groove 44' is formed. (see FIG. 10) may be formed.

Further, instead of the back alignment mark 40a, a back alignment mark 40b using a step made up of a groove 46 surrounding an interlayer insulating film 43, a polysilicon film 42 and a portion of the field oxide film 41 (laminated film 47). (See FIGS. 11 and 12).

Next, a metal film made of an aluminum alloy such as aluminum-silicon is formed on the interlayer insulating film 43 so as to fill the contact holes. Next, the metal film is patterned to leave a portion that will become the anode electrode 96 in a predetermined region (for example, only the active region). Next, a surface protection film is formed on the surface 1a of the semiconductor substrate 1 to cover the edge termination region. Through the steps up to this point, the surface element structure 2 is completed.

Next, as in step S2 of the third embodiment, the semiconductor substrate 1' is ground from the back surface 1b' side (back surface grinding) to obtain a semiconductor substrate 1 having a thickness t1 of a product used as a semiconductor device (step S12: See FIG. 2). As in step S3 of the third embodiment, the n-type FS region 95 is formed in the surface layer of the back surface 1b of the semiconductor substrate 1 (step S13).

Next, a resist is applied on the back surface 1b of the semiconductor substrate 1 to form a resist film 4 (see FIG. 3). Next, using a general exposure device (not shown), a predetermined mask pattern is exposed (transferred) to the resist film 4 and developed, thereby forming a predetermined circuit pattern corresponding to the surface element structure 2 on the resist film 4 . patterning (rear surface patterning) to form a resist mask with an opening corresponding to the formation region of the p-type floating region 94 (step S14). The process of step S14 corresponds to back surface patterning (see FIG. 4) of the method for manufacturing the semiconductor device according to the first embodiment.

Next, using this resist mask as an ion implantation mask, p-type impurity ions are implanted to form a p-type floating region 94 (step S15). Next, the resist mask is removed. Next, an n-type impurity is ion-implanted into the surface layer of the back surface 1b of the semiconductor substrate 1 at a position shallower than the p-type floating region 94 from the back surface 1b of the semiconductor substrate 1 over the entire surface of the back surface 1b of the semiconductor substrate 1. ^{A +} type cathode region 93 is formed (step S16).

Note that the p-type floating region 94 in step S15 may be formed after the formation of the n ⁺ -type cathode region 93 in step S16. The n-type FS region 95 in step S13 may be formed after the p-type floating region 94 and the n ⁺ -type cathode region 93 are formed.

Next, annealing (heat treatment) is performed for activating the impurity ion-implanted into the semiconductor substrate 1 (step S17). Next, a cathode electrode 97 is formed on the entire back surface 1b of the semiconductor substrate 1 (step S18). After that, by cutting (dicing) the semiconductor substrate 1 into individual chips, the FWD chips (semiconductor chips) shown in FIG. 18 are completed.

When the semiconductor device according to the fourth embodiment is formed by the manufacturing method of the semiconductor device according to the second embodiment, in step S1, when patterning the metal film that will be the anode electrode 96, the back alignment marks 40a and 40a' are formed. , 40b.

As described above, the semiconductor device according to the fourth embodiment can be manufactured using the method for manufacturing the semiconductor device according to the first and second embodiments.

(Embodiment 5)
Next, as a method of manufacturing the semiconductor device according to the fifth embodiment, a method of detecting the back surface alignment marks 3, 3′, 40a, 40a′, and 40b (FIGS. 5 to 12) during back surface patterning (see FIG. 4). , the rear surface alignment mark 100 in which the layout viewed from the front surface 1a side of the semiconductor substrate 1 is simplified. FIG. 20 is an explanatory diagram showing a detected waveform of reflected light of infrared light that irradiates the semiconductor substrate from the back surface thereof in the manufacturing method of the semiconductor device according to the fifth embodiment.

FIG. 20 shows detection waveforms (hereinafter referred to as first detection waveforms) of a pair of mark portions (hereinafter referred to as first mark portions) 101 and 102 of the back alignment mark 100 in a direction parallel to the first direction X. ) 111 and a detected waveform (hereinafter referred to as a second detected waveform) 112 in a direction parallel to the second direction Y of another set of two or more mark portions (hereinafter referred to as second mark portions) 103 and 104 . and indicate.

As shown in FIG. 20, the back surface alignment mark 100 is the first and second directions parallel to the first and second directions X and Y of the reflected light 22 of the infrared light irradiated from the back surface 1 b of the semiconductor substrate 1 to the semiconductor substrate 1 . The 1st and 2nd detection waveforms 111 and 112 are arranged in such a layout that two or more peaks can be detected. Specifically, the back surface alignment mark 100 includes a set of two or more first mark portions (here, two first mark portions indicated by ), and a pair of second mark portions (here, two second mark portions indicated by reference numerals 103 and 104 are described as an example) that are spaced apart in the second direction Y and face each other. .

The pair of first mark portions 101 and 102 are both linear portions arranged in a linear layout parallel to the second direction Y, for example, when viewed from the front surface 1a side of the semiconductor substrate 1 . The other set of second mark portions 103 and 104 are both linear portions arranged in a linear layout parallel to the first direction X, for example, when viewed from the front surface 1a side of the semiconductor substrate 1 . When viewed from the front surface 1a side of the semiconductor substrate 1, the back alignment mark 100 is a rectangle having the pair of first mark portions 101 and 102 as opposite sides and the other pair of second mark portions 103 and 104 as opposite sides. Arranged in a shape layout.

The first mark portions 101 and 102 and the second mark portions 103 and 104 arranged in such a layout constitute the alignment mark 100 for back surface. As a result, peaks 111a and 111b are detected at the positions where the first mark portions 101 and 102 are arranged in the first detection waveform 111 parallel to the first direction X of the reflected light 22 of infrared light, respectively. In addition, peaks 112a and 112b are detected at the positions where the second mark portions 103 and 104 are arranged in the second detection waveform 112 parallel to the second direction Y of the reflected light 22 of the infrared light.

Then, the center line Y1′ parallel to the second direction Y passing through the center between the peaks 111a and 111b of the pair of first mark portions 101 and 102 of the first detected waveform 111, and the second detected waveform 112, The center 110 of the back surface alignment mark 100 is defined as the point of intersection with a center line X1' parallel to the first direction X and passing through the center between the peaks 112a and 112b of the other pair of second mark portions 103 and 104. FIG. Using the position of the center 110 of the back surface alignment mark 100 as a reference, alignment can be performed during back surface patterning.

Thus, the back alignment mark 100 has a set of first mark portions having two or more straight portions parallel to the second direction Y and two or more straight portions parallel to the first direction X. and another set of second mark portions. By measuring the position of the center 110 of the back surface alignment mark 100 based on two or more peaks respectively detected from the first and second detection waveforms 111 and 112 of the reflected light 22 of the infrared light, The position of the alignment mark 100 can be identified.

As the number of peaks detected in the first and second detection waveforms 111 and 112 of the reflected infrared light 22 increases, erroneous measurement of the position of the center 110 of the back surface alignment mark 100 is reduced. The size of the alignment mark 100 is increased. Therefore, the back alignment mark 100 should be arranged in a layout (see FIGS. 5 and 6, for example) in which three peaks are detected in the first and second detection waveforms 111 and 112 of the reflected infrared light 22, respectively. is preferred.

For example, one first mark portion 101 of the pair of first mark portions 101 and 102 consists of trenches arranged in a stripe-like layout extending in the second direction Y and a poly (poly) layer embedded in the trench. and a silicon film. Due to the height difference between the depth from the back surface 1b of the semiconductor substrate 1 to the bottom surface of the trench and the depth from the back surface 1b of the semiconductor substrate 1 to the front surface 1a of the semiconductor substrate 1, reflected light 22 of infrared light is reflected at the location of the trench. , one peak 111a of the first detected waveform 111 is formed.

For example, of the pair of first mark portions 101 and 102, the other first mark portion 102 consists of trenches arranged in a layout extending in the second direction Y in a stripe shape and poly (poly) buried inside the trenches. and a silicon film. Due to the height difference between the depth from the back surface 1b of the semiconductor substrate 1 to the bottom surface of the trench and the depth from the back surface 1b of the semiconductor substrate 1 to the front surface 1a of the semiconductor substrate 1, reflected light 22 of infrared light is reflected at the location of the trench. One peak 111b of the first detected waveform 111 of is formed.

For example, one of the second mark portions 103 and 104 of the other set of second mark portions 103 and 104 includes trenches arranged in a stripe-like layout extending in the first direction X and and a polysilicon film. Due to the height difference between the depth from the back surface 1b of the semiconductor substrate 1 to the bottom surface of the trench and the depth from the back surface 1b of the semiconductor substrate 1 to the front surface 1a of the semiconductor substrate 1, reflected light 22 of infrared light is reflected at the location of the trench. A single peak 112a of the second detected waveform 112 of is formed.

For example, of the other set of second mark portions 103 and 104, the other second mark portion 104 is composed of trenches arranged in a layout extending in the first direction X in a stripe shape and and a polysilicon film. Due to the height difference between the depth from the back surface 1b of the semiconductor substrate 1 to the bottom surface of the trench and the depth from the back surface 1b of the semiconductor substrate 1 to the front surface 1a of the semiconductor substrate 1, reflected light 22 of infrared light is reflected at the location of the trench. A single peak 112b of the second detected waveform 112 of is formed.

FIG. 21 is a modification of the back surface alignment mark 100 of FIG. 20, and is a plan view showing an example of the layout viewed from the front surface side of the semiconductor substrate. 21(a) to 21(d) respectively show back alignment marks 100a, 100a', 100b, and 100b' as modifications of the back alignment mark 100 of FIG.

As shown in FIG. 21A, the back surface alignment mark 100a has trenches 121a and 122a arranged in a layout extending in a stripe shape in the second direction Y in orthogonal coordinates XY centered at a predetermined position. The trenches 121b and 122b, which are arranged on the positive side in the X direction and arranged in a layout extending in the second direction Y in a stripe shape, may be arranged on the negative side in the first direction X. In addition, the back surface alignment mark 100a has trenches 121c and 122c arranged in a layout extending in a stripe shape in the first direction X on the negative side of the second direction Y in orthogonal coordinates XY centered at a predetermined position. , the trenches 121d and 122d arranged in a layout extending in the first direction X in stripes may be arranged on the positive side in the second direction Y. As shown in FIG.

By arranging the trenches 121a to 121d and 122a to 122d in this manner, the back surface alignment mark 100a has a rectangular planar inner peripheral side trench made up of the trenches 121a to 121d and a rectangular shape made up of the trenches 122a to 122d. , and are arranged doubly so as to surround the center of the orthogonal coordinates XY. Therefore, in the back surface alignment mark 100a, four peaks are detected in each of the first and second detection waveforms of the reflected light 22 of the infrared light. Therefore, a center line Y1′ parallel to the second direction Y passing through the centers of four peaks of the first detected waveform and a center line parallel to the first direction X passing through the centers of four peaks of the second detected waveform X1' and the intersection (that is, the center of the orthogonal coordinates XY) may be set as the center 120a of the back surface alignment mark 100a. The position of the center 120a of the back alignment mark 100a in FIG. 21A is measured at the same position as the center 110 of the back alignment mark 100 in FIG.

The ends of the trenches 121a to 121d forming the rectangular planar shape of the outer trench may be in contact with each other (FIG. 21(a)) or may be separated from each other. The ends of the trenches 122a to 122d forming the rectangular planar shape of the inner trench may be in contact with each other (FIG. 21(a)) or may be separated from each other. In the back surface alignment mark 100a' shown in FIG. 21(b), the ends of the trenches 121a' to 121d' forming the outer trench are separated from each other at the same vertex, and the trenches forming the inner trench are separated from each other. In this example, the ends of 122a' to 122d' located at the same vertex are separated from each other. That is, the back surface alignment marks 100 may be arranged in a closed rectangular layout when viewed from the front surface 1a side of the semiconductor substrate 1 (back surface alignment marks 100a shown in FIG. 21A). may be arranged in an open layout at the vertex of (back surface alignment mark 100a' shown in FIG. 21(b)). The position of the center 120a' of the back alignment mark 100a' in FIG. 21(b) is measured at the same position as the center 120a of the back alignment mark 100a in FIG. 21(a).

As shown in FIG. 21(c), the back surface alignment mark 100b includes trenches 123a and 124a arranged linearly and in parallel extending in the second direction Y when viewed from the front surface 1a side of the semiconductor substrate 1; The trenches 123b and 124b arranged linearly and in parallel extending in one direction X may be arranged in an L-shaped layout. In the back alignment mark 100b of FIG. 21(c), the trenches 123a and 124a cause two peaks in the first detection waveform of the line Xa in the direction parallel to the first direction X at the center 120b of the back alignment mark 100b. , and the trenches 123b and 124b cause two peaks in the second detection waveform of the line Ya in the direction parallel to the second direction Y. As shown in FIG.

The ends located at the L-shaped corners of the trenches 123a and 123b arranged in the L-shaped layout may be in contact with each other (FIG. 21(c)) or may be separated from each other. Trenches 124a and 124b are arranged in an L-shaped layout so as to be adjacent to the trenches 123a and 123b arranged in an L-shaped layout and overlap with these trenches 123a and 123b. The ends located at the L-shaped corners of these trenches 124a and 124b may be in contact with each other (FIG. 21(c)) or may be separated from each other. The back surface alignment mark 100b shown in FIG. 21C is an example in which the ends of the trenches 123a and 123b are in contact with each other and the ends of the trenches 124a and 124b are in contact with each other. The back surface alignment mark 100b' shown in FIG. 21D is an example in which the ends of the trenches 123a' and 123b' are separated from each other and the ends of the trenches 124a' and 124b' are separated from each other. The position of the center 120b' of the back alignment mark 100b' in FIG. 21(d) may be the same as the center 120b of the back alignment mark 100b in FIG. 21(c).

In FIG. 21, each trench is illustrated by a straight line, but of course, a polysilicon film (not shown) is embedded inside each trench in the modification shown in FIG. As a result, due to the height difference between the depth from the back surface 1b of the semiconductor substrate 1 to the bottom surface of the trench and the depth from the back surface 1b of the semiconductor substrate 1 to the front surface 1a of the semiconductor substrate 1, infrared light is emitted at the location where the trench is arranged. A peak of the reflected light 22 is detected.

21(a) and 21(b) and back alignment marks 100b and 100b' in FIGS. Instead of the film, the groove 44 (see FIGS. 8 and 9) or the laminated film 47 (see FIGS. 11 and 12) remaining between the trenches 46 may be used.

(Example 1)
Next, the detection accuracy of the back alignment marks 3, 3' was verified. 22A and 22B are diagrams showing detection results of the alignment marks for the back surface of Example 1. FIG. FIG. 22 shows the result of measuring four back surface alignment marks (hereinafter referred to as marks 1 to 4) each having a level difference due to trenches formed in a semiconductor substrate, using an IR microscope of an exposure apparatus. Marks 2 to 4 are alignment marks for the rear surface of Embodiment 1 (hereinafter referred to as Example 1). All of the marks 2 to 4 have the thickness (silicon thickness) t1 of the semiconductor substrate 1 set to 140 μm, and the maximum widths w11 and w12 in the first and second directions X and Y to facilitate comparison of visibility and recognition rate. 80 μm.

Specifically, the mark 2 is the alignment mark 3 for back surface shown in FIGS. That is, the mark 2 is formed by arranging the first trenches 33 arranged in a cross-shaped layout and the second trenches 34 surrounding the first trenches 33 so as to form a cross-shaped layout. It has a configuration in which 31a to 31c are arranged. A polysilicon film 35 is buried inside the first and second trenches 33 and 34 . The mark 2 has the minimum widths w1 and w2 of the first and second trenches 33 and 34 both set to 0.8 μm, and the width (mesa width) w3 between the first and second trenches 33 and 34 set to 5.2 μm.

The mark 3 is the rear alignment mark 3' of FIG. That is, the mark 3 has first and second trenches 33 and 34 similar to those of the mark 2 and a third trench 36 separated from the first and second trenches 33 and 34 so as to form the surface 1a of the semiconductor substrate 1. It has a configuration in which five trenches are arranged in a direction parallel to the . A polysilicon film 35 is buried inside the first to third trenches 33 , 34 , 36 . Moreover, the mark 3 is such that the widths of the first to third trenches 33, 34, 36 are all set to 0.8 μm, and the width (mesa width) between the first and third trenches 33, 36 and the width between the second and third trenches 34, 36 are 0.8 μm. (mesa width) was set to 2.2 μm.

The mark 4 is obtained by applying the second embodiment to the back alignment mark 3' of FIG. That is, in the mark 4, the first to third trenches 33, 34, 36 are arranged similarly to the mark 3, the interiors of the first to third trenches 33, 34, 36 are filled with the polysilicon film 35, and the third trenches 33, 34, 36 are filled. 1 to 3 trenches 33 , 34 , 36 are covered with a metal film 52 . The metal film 52 is an aluminum-silicon film. The width of the first to third trenches 33, 34, 36 of the mark 4 is 0.8 .mu.m, and the width (mesa width) between the first and third trenches 33, 36 and the width between the second and third trenches 34, 36 are 0.8 .mu.m. (mesa width) was set to 2.8 μm.

A mark 1 is a rear alignment mark 203 (see FIGS. 25 and 30) of a comparative example. The mark 1 is formed of a stepped portion of a semiconductor substrate 201 formed by a trench 204 having a cross-shaped planar shape. That is, the mark 1 has a structure in which two trenches are arranged in a direction parallel to the surface 201a of the semiconductor substrate 201. As shown in FIG. A polysilicon film is buried inside the trench 204 . The mark 1 has a minimum width w201 of the trench 204 of 0.8 μm, a width (mesa width) w202 between the trenches 204 of 11.2 μm, and widths w211 and w212 in the first and second directions X and Y of the mark 2 4 to 80 μm, and the thickness t201 of the semiconductor substrate 201 is 140 μm.

FIG. 22 shows an IR image obtained by irradiating infrared light from the back surface of the semiconductor substrate (see FIG. 29) and measuring the marks 1 on the front surface of the semiconductor substrate from the back surface of the semiconductor substrate with the detector 223. indicates In addition, an image (hereinafter referred to as IR image). The higher the density of the trenches inside the trenches 204 and 34 (mark 1: none, mark 2: first trench 33, mark 3: first and third trenches 33 and 36) inside the trenches 204 and 34 imitating a cross-shaped planar shape, the IR image becomes , and it was confirmed that the mark 3 was difficult to visually recognize. In the mark 4 having the structure in which the mark 3 is covered with the metal film 52, the IR image has a higher contrast than the marks 1 to 3, and all the first to third trenches 33, 34, 36 are black and clearly visible. It was confirmed that

In addition, the IR image in FIG. 22 includes a detected waveform 241 of the reflected infrared light 222 corresponding to the IR image of the comparative example (mark 1), and infrared rays corresponding to the IR images of the marks 2 to 4. Detected waveforms 132, 133, and 134 of reflected light 22 of light are illustrated. Detected waveforms 241, 132, 133 and 134 correspond to the first and second detected waveforms 111 and 112 in FIG. The mark 1 is confirmed by the detection waveform 241 of the reflected infrared light 222 . The marks 2 and 3 are confirmed by detection waveforms 132 and 133 of the reflected infrared light 22, respectively. In the mark 3 having a narrow mesa width between trenches, the peaks due to the first to third trenches 33, 34, and 36 cannot be separated from the detection waveform 133, so that the reflection intensity of the reflected infrared light 22 is reduced as a whole. It is presumed that the contrast between the surface 1a of the semiconductor substrate 1 and the bottom surface of the trench decreased due to the decrease in the surface area.

It has been confirmed that the mark 2 can separate the peaks due to the first and second trenches 33 and 34 from the detected waveform 132 . It was also confirmed that the peak due to the trench 204 could be separated from the detected waveform 241 for the mark 1 as well. It was also confirmed that the recognition rate (detection rate) of mark 1 was 80%, while the recognition rate of mark 2 was as high as 90%. The reason for this is presumed to be due to the following two reasons. The first reason is that the peaks due to the first and second trenches 33 and 34 could be separated from the detected waveform 132 of mark 2 as described above. The second reason is that in the mark 2, compared with the mark 1, the density of the first trenches 33 inside the second trenches 34 is increased, which contributes to the improvement of the contrast of the IR image. . The mark 4 covered with the metal film 52 has a higher recognition rate than the mark 2 . In order to carry out stable alignment, the recognition rate of the alignment marks for the back surface needs to be 65% or more.

(Example 2)
Next, the detection accuracy of the back alignment marks 40a and 40b was verified. 23A and 23B are diagrams showing the detection results of the alignment marks for the back surface of Example 2. FIG. 4 shows the result of measuring four back surface alignment marks (hereinafter referred to as marks 5 to 8), which are formed of steps due to grooves formed in a laminated film on the surface of a semiconductor substrate 1, using an IR microscope of an exposure apparatus. 23. Marks 5 to 8 are the alignment marks for the rear surface of the first embodiment (hereinafter referred to as the second embodiment). For the marks 5 to 8, the thickness t1 of the semiconductor substrate 1 was set to 400 μm, and the maximum widths w11 and w12 in the first and second directions X and Y were set to 80 μm to facilitate comparison of visibility and recognition rate.

Specifically, the mark 5 is the rear alignment mark 40a shown in FIGS. That is, the mark 5 has a configuration in which a groove 44 that penetrates the laminated film 45 in the depth direction Z and has a cross-shaped planar shape is arranged. The film type for forming the mark 5 (hereinafter referred to as mark forming film type), that is, the film type of the laminated film 45 is the field oxide film 41 (initial oxide film), the polysilicon film from the surface 1a side of the semiconductor substrate 1. 42 (Poly-Si film) and an interlayer insulating film 43 (BPSG film) were laminated in this order. The mark 5 has both maximum widths w14 and w15 in the first and second directions X and Y (maximum width of the groove 44) of 4.2 μm, and minimum widths in the first and second directions X and Y (maximum width of the groove 44). (small width) w4 and w5 are both set to 1.6 μm.

The mark 6 is the rear alignment mark 40b shown in FIGS. That is, the mark 6 has a configuration in which a groove 46 surrounding the laminated film 47 is arranged. Similar to the mark 5, the film type of the layered film 47 for forming the mark 6 is the field oxide film 41 (initial oxide film), the polysilicon film 42 ( Poly-Si film) and an interlayer insulating film 43 (BPSG film) were laminated in this order. The mark 6 has a maximum width (maximum remaining width of the laminated film 47) w14' and w15' in the first and second directions X and Y of 4.2 μm, and a minimum width in the first and second directions X and Y ( The minimum remaining widths w4′ and w5′ of the laminated film 47 were both set to 1.6 μm.

The mark 7 is obtained by applying the second embodiment to the back alignment mark 40a shown in FIGS. That is, similarly to the mark 5, the mark 7 has a structure in which a groove 44 penetrating the laminated film 45 in the depth direction Z is arranged, and the metal film 52 is embedded in the groove 44 to cover it. As a mark forming film type for forming the mark 7, the laminated film 45 (the field oxide film 41 (initial oxide film), the polysilicon film 42 (Poly-Si film) and the interlayer insulating film 43 (BPSG film) similar to the mark 5 are used. )), an aluminum-silicon film was laminated as the metal film 52 thereon. The maximum widths w14 and w15 in the first and second directions X and Y of the mark 7 and the minimum widths w4 and w5 in the first and second directions X and Y of the mark 7 are the same as those of the mark 5 .

The mark 8 is obtained by applying the second embodiment to the back alignment mark 40b of FIGS. That is, the mark 8 has a groove 46 surrounding the laminated film 47 in the same manner as the mark 6 , and the laminated film 47 is covered with the metal film 52 . As a mark forming film type for forming the mark 8, the laminated film 47 (the field oxide film 41 (initial oxide film), the polysilicon film 42 (Poly-Si film) and the interlayer insulating film 43 (BPSG film) similar to the mark 6 are used. )), an aluminum-silicon film was laminated as the metal film 52 thereon. The maximum widths w14' and w15' in the first and second directions X and Y of the mark 8 and the minimum widths w4' and w5' in the first and second directions X and Y of the mark 8 are the same as those of the mark 6.

From the results shown in FIG. 23, according to the manufacturing method of the semiconductor device according to the first embodiment, infrared light is irradiated from the back surface of the semiconductor substrate (see FIG. 4), and the detector 23 In the image (IR image) obtained by measuring the marks 5 to 8 on the surface 1a of the semiconductor substrate 1, it was confirmed that the recognition rate of the marks 7 and 8 was higher than that of the marks 5 and 6. FIG. Even when confirmed by the peak intensities of the detected waveforms 135 to 138 shown together with the IR images of the marks 5 to 8 in the bottom row of FIG. It was confirmed that the intensity was greater than the peak intensity of the detected waveforms 135, 136 of the marks 5,6. That is, even in the back alignment marks 40a and 40b using the stepped portions formed by the laminated films 45 and 47 and the grooves 44 and 46, the detection accuracy can be improved by covering the back alignment marks 40a and 40b with the metal film 52. was confirmed.

(Example 3)
Next, a suitable range of the thickness t1 of the semiconductor substrate 1 (thickness of a product used as a semiconductor device) was verified. FIG. 24 is a diagram showing a preferable range of thickness of the semiconductor substrate of Example 3. FIG. FIG. 24 shows the results of fabricating RC-IGBTs (see FIG. 16) by variously changing the thickness (Si thickness) t1 of the semiconductor substrate 1 according to the semiconductor device manufacturing method according to the third embodiment (metal film Without cover: RC-IGBT). FIG. 24 shows the result of fabricating FWD (see FIG. 18) by variously changing the thickness t1 of the semiconductor substrate 1 according to the manufacturing method of the semiconductor device according to the fourth embodiment (no metal film cover: FWD).

Further, the second embodiment (that is, covering the back surface alignment mark 3 with the metal film 52) is applied to the method of manufacturing the semiconductor device according to the third embodiment, and the thickness t1 of the semiconductor substrate 1 is variously changed to obtain the RC. -IGBT (see FIG. 16) is shown in FIG. 24 (with metal film cover: RC-IGBT). The second embodiment (that is, covering the back surface alignment mark 40a with the metal film 52) is applied to the method of manufacturing the semiconductor device according to the fourth embodiment, and the thickness t1 of the semiconductor substrate 1 is variously changed to produce an FWD (FIG. 18) is shown in FIG. 24 (with metal film cover: FWD).

From the result of "no metal film cover: RC-IGBT" in FIG. 24, when forming the back alignment marks 3, 3' using the steps of the trenches, the upper limit of the thickness t1 of the semiconductor substrate 1 is 150 μm. was confirmed. Also, from the result of "with metal film cover" in FIG. 3' and the rear surface alignment marks 40a, 40a', and 40b using a step formed by grooves penetrating the laminated film have high detection accuracy, and it has been confirmed that the thickness t1 of the semiconductor substrate 1 can be increased. In the case of "with a metal film cover", the upper limit of the thickness t1 of the semiconductor substrate 1 is 400 μm.

As described above, the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the scope of the present invention. For example, in the above-described third and fourth embodiments, the case of manufacturing RC-IGBT and FWD is described as an example, but the present invention is applied to a second main surface different from the first main surface on which alignment marks are formed. It can be applied to a semiconductor device manufactured by patterning using the alignment mark. In the third and fourth embodiments, the same holds true even if the conductivity type (n-type, p-type) is reversed.

As described above, in the method for manufacturing a semiconductor device according to the present invention, a semiconductor device is manufactured (manufactured) by patterning the second principal surface, which is different from the first principal surface on which the alignment marks are formed, using the alignment marks. It is particularly useful for RC-IGBTs and FWDs having a p-type floating region at a position deeper than the n ⁺ -type cathode region from the back surface of the semiconductor substrate.

1 semiconductor substrate (after backside grinding)
1' semiconductor substrate (before back surface grinding)
1a front surface of semiconductor substrate 1b rear surface of semiconductor substrate (after rear surface grinding)
1b' Backside of semiconductor substrate (before backside grinding)
2 front element structure 3, 3', 40a, 40a', 40b, 51, 100, 100' rear alignment mark 4 resist film 5 effective area of semiconductor substrate 6 dicing line 10 exposure device 11 chuck stage 21 incidence of infrared light Light 22, 22a-22c Infrared reflected light 23 Detector 31a-31c, 33, 34, 36, 121a-121d, 121a'-121d', 122a-122d, 122a'-122d', 123a, 123b, 123a ', 123b', 124a, 124b, 124a', 124b' trench used for back alignment mark 32 center of cross-shaped layout formed by four trenches used for back alignment mark 35 polysilicon film 41 field oxide film 42 Polysilicon film 43 Interlayer insulating film 44, 44', 46 Groove used for alignment mark for back surface 45, 45', 47 Laminated film used for alignment mark for back surface 50 Pattern forbidden band 52 Metal film 61 n ^- type drift region 62 p type Base region 63 n ⁺ type emitter region 64 p ⁺ type contact region 65 gate trench 66 gate insulating film 67 gate electrode 68 emitter electrode 69 n type FS region 70 p ⁺ type collector region 71, 93 n ⁺ type cathode region 72 collector electrode 81 IGBT region 82 FWD region 91 n ^- type drift region 92 p ⁺ type anode region 94 p type floating region 95 n type FS region 96 anode electrode 97 cathode electrode 101, 101', 102, 102', 103, 103', 104 back surface Mark portions 110, 120a, 120a', 120b, 120b' constituting alignment marks for back surface 111, 112, 132 to 138 Detection waveforms of reflected light of infrared light 111a, 111b, 112a, 112b Infrared Peak of detected waveform of reflected light X Direction parallel to the surface of the semiconductor substrate (first direction)
X1′, X2′, Y1′, Y2′ Center line between peaks of detection waveform of reflected light of infrared light Y Direction parallel to the surface of the semiconductor substrate and perpendicular to the first direction (second direction)
Z Depth direction w1, w2 Minimum width of alignment mark for back surface using trench (minimum width of trench)
w3 Width between trenches (mesa width) used for back alignment marks
w4, w5 Minimum width of alignment mark for back surface using groove (minimum width of groove)
w4', w5' minimum width of alignment mark for back surface using grooves (minimum remaining width of laminated film)
w11, w12, w14, w14', w15, w15' Maximum width of alignment mark for back surface w21, w22 Width of metal film w31 Width of dicing line

Claims (21)

A method for manufacturing a semiconductor device in which a first region in which an insulated gate bipolar transistor is arranged and a second region in which a diode is arranged are adjacent to each other in a direction parallel to a first main surface of a semiconductor substrate,
A base region of the insulated gate bipolar transistor and an anode of the diode are formed on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type over the entirety of the first region and the second region as a surface element structure. a first step of forming a first semiconductor region of a second conductivity type as a region and forming a predetermined mark apart from the surface element structure;
a second step of forming a resist film on the second main surface of the semiconductor substrate;
The semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is reflected by a detector arranged at a position facing the second main surface of the semiconductor substrate. a third step of identifying the position of the predetermined mark by detecting the
a fourth step of performing alignment using the position of the predetermined mark specified in the third step as a reference, transferring a predetermined pattern corresponding to the surface element structure to the resist film, and exposing the resist film;
Using the resist film as a mask, impurity ions of the first conductivity type are implanted into the surface layer of the second main surface of the semiconductor substrate over the entire second region from the semiconductor substrate to become the cathode region of the diode. a fifth step of forming a second semiconductor region of the first conductivity type with a higher impurity concentration;
including
In the first step,
a detection waveform in a first direction parallel to the first main surface of the semiconductor substrate, of the reflected light of the light in the predetermined wavelength range detected by the detector; forming a plurality of trenches reaching a predetermined depth from the first main surface of the semiconductor substrate in a layout in which two or more peaks are detected in each of the detection waveform in a second direction orthogonal to the first direction;
forming, as the trenches, four linear planar first trenches arranged in a point-symmetric cross-shaped layout centered on a predetermined location and having one end positioned at the center;
A method of manufacturing a semiconductor device, wherein steps formed by the plurality of trenches on the first main surface of the semiconductor substrate are used as the predetermined marks. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in said first step, a polysilicon film is buried inside said trench. In the first step,
forming the trench at the same time as the gate trench of the insulated gate bipolar transistor;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the polysilicon film is formed at the same time as the gate electrode of the insulated gate bipolar transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in said first step, said first trenches are arranged apart from each other. 5. The method of manufacturing a semiconductor device according to claim 1, wherein in said first step, said first trench is covered with a metal film containing aluminum. A method for manufacturing a semiconductor device in which a first region in which an insulated gate bipolar transistor is arranged and a second region in which a diode is arranged are adjacent to each other in a direction parallel to a first main surface of a semiconductor substrate,
A base region of the insulated gate bipolar transistor and an anode of the diode are formed on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type over the entirety of the first region and the second region as a surface element structure. a first step of forming a first semiconductor region of a second conductivity type as a region and forming a predetermined mark apart from the surface element structure;
a second step of forming a resist film on the second main surface of the semiconductor substrate;
The semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is reflected by a detector arranged at a position facing the second main surface of the semiconductor substrate. a third step of identifying the position of the predetermined mark by detecting the
a fourth step of performing alignment using the position of the predetermined mark specified in the third step as a reference, transferring a predetermined pattern corresponding to the surface element structure to the resist film, and exposing the resist film;
Using the resist film as a mask, impurity ions of the first conductivity type are implanted into the surface layer of the second main surface of the semiconductor substrate over the entire second region from the semiconductor substrate to become the cathode region of the diode. a fifth step of forming a second semiconductor region of the first conductivity type with a higher impurity concentration;
including
In the first step,
An oxide film, a polysilicon film and an interlayer insulating film are sequentially stacked on the first main surface of the semiconductor substrate.
forming a layered film,
A cross-shaped planar groove is formed that penetrates the laminated film in the depth direction and has four linear portions arranged in a point-symmetrical cross-shaped layout with one end positioned at the center with a predetermined location as the center. ,
A method of manufacturing a semiconductor device, wherein a step formed in the laminated film by the groove is used as the predetermined mark. A method for manufacturing a semiconductor device in which a first region in which an insulated gate bipolar transistor is arranged and a second region in which a diode is arranged are adjacent to each other in a direction parallel to a first main surface of a semiconductor substrate,
A base region of the insulated gate bipolar transistor and an anode of the diode are formed on the surface layer of the first main surface of the semiconductor substrate of the first conductivity type over the entirety of the first region and the second region as a surface element structure. a first step of forming a first semiconductor region of a second conductivity type as a region and forming a predetermined mark apart from the surface element structure;
a second step of forming a resist film on the second main surface of the semiconductor substrate;
The semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is reflected by a detector arranged at a position facing the second main surface of the semiconductor substrate. a third step of identifying the position of the predetermined mark by detecting the
a fourth step of performing alignment using the position of the predetermined mark specified in the third step as a reference, transferring a predetermined pattern corresponding to the surface element structure to the resist film, and exposing the resist film;
Using the resist film as a mask, impurity ions of the first conductivity type are implanted into the surface layer of the second main surface of the semiconductor substrate over the entire second region from the semiconductor substrate to become the cathode region of the diode. a fifth step of forming a second semiconductor region of the first conductivity type with a higher impurity concentration;
including
In the first step,
forming a laminated film formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate;
The laminated film is formed so that a part of the laminated film remains in four straight lines in a point-symmetrical cross-shaped layout that penetrates the laminated film in the depth direction and has one end positioned at the center with a predetermined location as the center. forming a groove surrounding a portion,
A method of manufacturing a semiconductor device, wherein a step formed in the laminated film by the groove is used as the predetermined mark. 7. The method of manufacturing a semiconductor device according to claim 5, wherein in said first step, a metal film containing aluminum is embedded in said trench. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in said first step, said trench is formed to penetrate said laminated film in a depth direction and terminate at said first main surface of said semiconductor substrate. In the fifth step, a second semiconductor region is formed on the surface layer of the second main surface of the semiconductor substrate over the entire first region and adjacent to the second semiconductor region to serve as a collector region of the insulated gate bipolar transistor. 8. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a conductive type third semiconductor region. In the fifth step,
implanting ions of a second conductivity type impurity to form the third semiconductor region in a surface layer of the second main surface of the semiconductor substrate over the entire second main surface of the semiconductor substrate;
The second semiconductor region is formed by performing ion implantation of the impurity of the first conductivity type using the resist film as a mask to change the portion of the second region of the third semiconductor region to the first conductivity type. 11. The method of manufacturing a semiconductor device according to claim 10. a sixth step of forming a first electrode electrically connected to the first semiconductor region on the first main surface of the semiconductor substrate;
and a seventh step of forming a second electrode in contact with the second semiconductor region and the third semiconductor region on the second main surface of the semiconductor substrate. Production method. A method of manufacturing a semiconductor device having a floating second conductivity type region, comprising:
a first step of forming a surface element structure on a first main surface of a semiconductor substrate of a first conductivity type and forming a predetermined mark apart from the surface element structure;
a second step of forming a resist film on the second main surface of the semiconductor substrate;
The semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is reflected by a detector arranged at a position facing the second main surface of the semiconductor substrate. a third step of identifying the position of the predetermined mark by detecting the
a fourth step of performing alignment using the position of the predetermined mark specified in the third step as a reference, transferring a predetermined pattern corresponding to the surface element structure to the resist film, and exposing the resist film;
a fifth step of implanting ions of a second conductivity type impurity using the resist film as a mask to form the second conductivity type region at a depth position away from the second main surface of the semiconductor substrate;
including
In the first step,
a detection waveform in a first direction parallel to the first main surface of the semiconductor substrate, of the reflected light of the light in the predetermined wavelength range detected by the detector; forming a plurality of trenches reaching a predetermined depth from the first main surface of the semiconductor substrate in a layout in which two or more peaks are detected in each of the detection waveform in a second direction orthogonal to the first direction;
forming, as the trenches, four linear planar first trenches arranged in a point-symmetric cross-shaped layout centered on a predetermined location and having one end positioned at the center;
A method of manufacturing a semiconductor device, wherein steps formed by the plurality of trenches on the first main surface of the semiconductor substrate are used as the predetermined marks. 14. The method of manufacturing a semiconductor device according to claim 13, wherein in said first step, a polysilicon film is buried inside said trench. 14. The method of manufacturing a semiconductor device according to claim 13, wherein in said first step, said first trenches are arranged apart from each other. 16. The method of manufacturing a semiconductor device according to claim 13, wherein in said first step, said first trench is covered with a metal film containing aluminum. A method of manufacturing a semiconductor device having a floating second conductivity type region, comprising:
a first step of forming a surface element structure on a first main surface of a semiconductor substrate of a first conductivity type and forming a predetermined mark apart from the surface element structure;
a second step of forming a resist film on the second main surface of the semiconductor substrate;
The semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is reflected by a detector arranged at a position facing the second main surface of the semiconductor substrate. a third step of identifying the position of the predetermined mark by detecting the
a fourth step of performing alignment using the position of the predetermined mark specified in the third step as a reference, transferring a predetermined pattern corresponding to the surface element structure to the resist film, and exposing the resist film;
a fifth step of implanting ions of a second conductivity type impurity using the resist film as a mask to form the second conductivity type region at a depth position away from the second main surface of the semiconductor substrate;
including
In the first step,
forming a laminated film formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate;
A cross-shaped planar groove is formed that penetrates the laminated film in the depth direction and has four linear portions arranged in a point-symmetrical cross-shaped layout with one end positioned at the center with a predetermined location as the center. ,
A method of manufacturing a semiconductor device, wherein a step formed in the laminated film by the groove is used as the predetermined mark. A method of manufacturing a semiconductor device having a floating second conductivity type region, comprising:
a first step of forming a surface element structure on a first main surface of a semiconductor substrate of a first conductivity type and forming a predetermined mark apart from the surface element structure;
a second step of forming a resist film on the second main surface of the semiconductor substrate;
The semiconductor substrate is irradiated with light in a predetermined wavelength range from the second main surface of the semiconductor substrate, and the light in the predetermined wavelength range is reflected by a detector arranged at a position facing the second main surface of the semiconductor substrate. a third step of identifying the position of the predetermined mark by detecting the
a fourth step of performing alignment using the position of the predetermined mark specified in the third step as a reference, transferring a predetermined pattern corresponding to the surface element structure to the resist film, and exposing the resist film;
a fifth step of implanting ions of a second conductivity type impurity using the resist film as a mask to form the second conductivity type region at a depth position away from the second main surface of the semiconductor substrate;
including
In the first step,
forming a laminated film formed by sequentially laminating an oxide film, a polysilicon film and an interlayer insulating film on the first main surface of the semiconductor substrate;
The laminated film is formed so that a part of the laminated film remains in four straight lines in a point-symmetrical cross-shaped layout that penetrates the laminated film in the depth direction and has one end positioned at the center with a predetermined location as the center. forming a groove surrounding a portion,
A method of manufacturing a semiconductor device, wherein a step formed in the laminated film by the groove is used as the predetermined mark. 19. The method of manufacturing a semiconductor device according to claim 17, wherein in said first step, a metal film containing aluminum is embedded in said trench. 20. The method of manufacturing a semiconductor device according to claim 19, wherein in said first step, said trench is formed to penetrate said laminated film in a depth direction and terminate at said first main surface of said semiconductor substrate. In the first step, a first semiconductor region of a second conductivity type is formed as the surface element structure in a surface layer of the first main surface of the semiconductor substrate,
In the fifth step,
forming a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate in a surface layer of the second main surface of the semiconductor substrate;
forming the second conductivity type region at a position deeper than the second semiconductor region from the second main surface of the semiconductor substrate;
a sixth step of forming a first electrode in contact with the first semiconductor region on the first main surface of the semiconductor substrate;
and a seventh step of forming, on the second main surface of the semiconductor substrate, a second electrode separated from the second conductivity type region and in contact with the second semiconductor region. 19. The method for manufacturing a semiconductor device according to any one of 18.

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