JP7313414B2 - Treatment to improve material structure - Google Patents

Description

[0001] Embodiments described herein relate generally to the manufacture of semiconductor devices, and more particularly to systems and methods for forming high quality, high-k dielectric material layers in semiconductor structures.

[0002] As the size of metal oxide semiconductor field effect transistors (MOSFETs) has shrunk to achieve high device performance and low power consumption, the thickness of conventional silicon dioxide ( _SiO2 ) gate dielectrics has decreased to physical limits. As a result, replacement of silicon dioxide gate dielectrics with high-k dielectric materials has been imperative to achieve further scaling. Among various high-k dielectric materials, hafnium oxide (HfO ₂ ) has been applied since the 45 nm MOSFET technology node due to its high dielectric constant and excellent thermal stability on silicon substrates. However, further scaling of equivalent oxide thickness (EOT) beyond the 32 nm MOSFET technology node is problematic because simply reducing the thickness of the high-k dielectric material layer increases leakage current through the high-k dielectric material layer.

[0003] Accordingly, there is a need for systems and methods that can be used to form thin (e.g., less than 1 nm EOT) high-k dielectric material layers with chemical structures that can be controlled to ensure desired structural and electrical properties.

[0004] Embodiments of the present disclosure provide methods of forming semiconductor structures. The method includes precleaning a surface of a substrate, forming an interfacial layer on the precleaned surface of the substrate, depositing a high-k dielectric layer on the interfacial layer, performing a plasma nitridation process to intercalate nitrogen atoms into the deposited high-k dielectric layer, and performing a post-nitridation annealing process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer.

[0005] Embodiments of the present disclosure also provide a method of forming a semiconductor structure. The method includes precleaning the surface of the substrate, depositing a high-k dielectric layer on the substrate, and performing a plasma nitridation process to intercalate nitrogen atoms into the deposited high-k dielectric layer.

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, and a system controller. The system controller is configured to preclean the surface of the substrate in a first processing chamber, form an interfacial layer on the precleaned surface of the substrate in a second processing chamber, deposit a high-k dielectric layer on the interfacial layer in a third processing chamber, expose the deposited high-k dielectric layer to a nitrogen plasma in a fourth processing chamber, and anneal the plasma-nitrided high-k dielectric layer in a fifth processing chamber. Substrates are transferred between the first, second, third, fourth and fifth processing chambers without breaking the vacuum environment within the processing system.

[0007] So that the above features of the disclosure may be understood in detail, a more particular description of the disclosure, briefly summarized above, is provided by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, as the disclosure may concede other equally effective embodiments.

1 is a schematic top view of an exemplary multi-chamber processing system according to one embodiment; FIG. FIG. 3 is a process flow diagram of a method of forming a semiconductor structure according to one embodiment; 3A and 3B are schematic diagrams of a semiconductor structure according to one embodiment.

[0011] For ease of understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration.

[0012] As gate structures scale to smaller dimensions, new material structures are sought to provide improvements. The use of a high-k dielectric material results in a gate structure with a higher dielectric constant than conventional gate structures using materials such as silicon oxide. However, as with silicon oxide, leakage current increases as the thickness of the gate structure decreases. For example, gate leakage increases as the equivalent oxide thickness decreases. Therefore, the inverse relationship between gate leakage and equivalent oxide thickness can create limitations in the performance of transistors and fabricated devices.

[0013] High-k dielectric materials can provide greater channel mobility than silicon oxide at similar thicknesses. Efforts to maximize the dielectric constant (also called the "K value") of known high-k materials are being limited by morphological properties as the industry continues to push for lower equivalent oxide thicknesses without increasing gate leakage. Prior art has struggled to overcome the natural properties of high-k materials that can set an upper limit on the κ value, and has since modified devices in an attempt to incorporate new films.

[0014] Embodiments described herein provide systems and methods for improving the properties of high-k dielectric materials. By producing high-k dielectric materials that exhibit specific morphologies or grain structures, higher dielectric constants and subsequent improved device performance may be possible. To control grain formation in exemplary devices, treatments are performed to provide an activated substrate surface that can induce specific grain growth, as well as to stabilize the film after formation, which can lead to a higher dielectric constant.

[0015] FIG. 1 is a schematic top view of an example multi-chamber processing system 100 according to some examples of this disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in processing system 100 may be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside of processing system 100 (e.g., atmospheric environments such as may exist in a fab). For example, wafers may be processed in various chambers and transferred between various chambers at low pressure (e.g., about 300 Torr or less) or vacuum environments without breaking the low pressure or vacuum environment between various processes performed on the wafers in processing system 100. Accordingly, processing system 100 can provide an integrated solution for several processes of wafers.

[0016] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer® or Centura® integrated processing systems available from Applied Materials, Inc. of Santa Clara, California, or other suitable processing systems. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from the aspects described herein.

[0017] In the illustrated example of FIG. 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate wafer transfer. Docking station 140 is configured to receive one or more front-opening monolithic pods (FOUPs) 144 . In some examples, each factory interface robot 142 generally comprises a blade 148 located at one end of the respective factory interface robot 142 configured to transfer wafers from the factory interface 102 to the loadlock chambers 104, 106.

[0018] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber . Transfer chamber 108 further has ports 158, 160 coupled to holding chambers 116, 118, respectively, and ports 162, 164, coupled to processing chambers 120, 122, respectively. Similarly, transfer chamber 110 has respective ports 166, 168 coupled to holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to processing chambers 124, 126, 128, 130. FIG. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be, for example, slit valve openings with slit valves for passing wafers by transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open for wafers to pass through. Otherwise the port is closed.

[0019] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). A gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to various chambers. In operation, factory interface robot 142 transfers wafers from FOUP 144 through port 150 or 152 to loadlock chamber 104 or 106 . The gas and pressure control system then pumps down the loadlock chamber 104 or 106 . Additionally, the gas and pressure control system maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low pressure or vacuum environment (which may include inert gases). Thus, pumping down the loadlock chambers 104 or 106 facilitates passing wafers between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0020] Wafers in the pumped-down loadlock chambers 104 or 106 are transferred from the loadlock chambers 104 or 106 to the transfer chamber 108 via ports 154 or 156 by the transfer robot 112 . The transfer robot 112 can then transfer the wafers to and/or between any of the processing chambers 120, 122 via respective ports 162, 164 for processing, and via respective ports 158, 160 to and/or between any of the holding chambers 116, 118 for holding awaiting further transfer. Similarly, transfer robot 114 can access wafers in holding chambers 116 or 118 via ports 166 or 168, to any of processing chambers 124, 126, 128, 130 via respective ports 170, 172, 174, 176 for processing, to any of holding chambers 116, 118 via respective ports 166, 168 to hold awaiting further transfer, and/or between them. , the wafer can be transferred. Wafer transfer and holding within and between the various chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.

[0021] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing wafers. In some examples, processing chamber 122 may perform a cleaning process, processing chamber 120 may perform an etching process, and processing chambers 124, 126, 128, 130 may perform respective epitaxial growth processes. Processing chamber 122 can be a SiCoNi™ preclean chamber available from Applied Materials of Santa Clara, California. Processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials of Santa Clara, California.

[0022] A system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, system controller 190 may use direct control of chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of processing system 100, or may be associated with chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. The operation of the processing system 100 can be controlled by controlling the controller. In operation, system controller 190 allows data collection and feedback from each chamber to adjust the performance of processing system 100 .

[0023] The system controller 190 generally includes a central processing unit (CPU) 192, memory 194, and support circuits 196. CPU 192 may be one of any form of general purpose processor that can be used in an industrial environment. Memory 194, a non-transitory computer-readable medium, is accessible by CPU 192 and may be one or more of memory such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or other forms of digital storage, local or remote. Support circuits 196 are coupled to CPU 192 and may include cache, clock circuits, input/output subsystems, power supplies, and the like. The various methods disclosed herein may generally be performed by, for example, as software routines, executing computer instruction code stored in memory 194 (or the memory of a particular processing chamber) under the control of CPU 192. When the computer instruction code is executed by CPU 192, CPU 192 controls the chambers to perform processes according to various methods.

[0024] Other processing systems may have other configurations. For example, more or fewer processing chambers may be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108,110 and holding chambers 116,118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and/or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices in the processing system.

[0025] Figure 2 is a process flow diagram of a method 200 of forming a semiconductor structure 300 according to one or more embodiments of the present disclosure. 3A and 3B are cross-sectional views of a portion of semiconductor structure 300 corresponding to various states of method 200. FIG. 3A and 3B show only a partial schematic view of semiconductor structure 300, and it should be understood that semiconductor structure 300 may include any number of transistor sections and additional materials having aspects as shown. It should also be noted that although the method steps shown in FIG. 2 are described sequentially, other process sequences that include one or more method steps omitted and/or added and/or rearranged in another desired order are within the scope of the embodiments of the disclosure provided herein.

[0026] Method 200 begins with a pre-cleaning process at block 210 for pre-cleaning the surface of substrate 302 . The precleaning process may etch the surface of the substrate ₃₀₂ by a wet etching process using an etching solution such as a Standard Clean 1 (SC1) etching solution containing _NH4OH (ammonium hydroxide), _H2O2 (hydrogen peroxide), and _H2O (water), or by a dry etching process, such as the SiConi™ remote plasma assisted dry etching process, in which the surface of the substrate 302 is exposed to _N2 , _NF3 , and _NH3 plasma byproducts. can include The preclean process can be performed in a preclean chamber, such as processing chamber 122 or 120 shown in FIG.

[0027] At block 220, an interface formation process is performed to form an interface layer 304 on the pre-cleaned surface of the substrate 302, as shown in Figure 3A. The interfacial formation process may include a suitable thermal oxidation process such as an enhanced in-situ steam generation (eISSG) process utilizing nitrous oxide ( _N2O ) gas. The interfacial layer 304 formed at block 220 is a thin amorphous silicon oxide ( _SiO2 ) layer having a thickness of between about 3 Å and about 10 Å, such as about 5 Å, corresponding to one or more monolayers of silicon oxide. In some embodiments, the interfacial layer 304 may be formed by an in-situ steam generation (ISSG) process utilizing _H2 and _O2 gases or a rapid thermal oxidation (RTO) process utilizing _NH3 and _O2 gases. The interfacial layer 304 may serve as a nucleation layer for the high-k dielectric material layer deposited thereon and improve the quality of the interface between the substrate 302 and the high-k dielectric material layer (e.g., interface state density, storage capacitance, frequency dispersion, leakage current, etc.). The interface formation process can be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

[0028] In some embodiments, the interface formation process of block 220 is omitted and the interface layer 304 is not formed prior to depositing the high-k dielectric material layer on the substrate 302 . In that case, interfacial layer 304 is formed by the thermal oxidation process of block 250 or block 290 described below that thermally oxidizes substrate 302 through a layer of high-k dielectric material deposited on substrate 302 . The interfacial layer 304 formed by the thermal oxidation process of block 250 or block 290 may be thick enough to ensure reliable device properties (e.g., interface state density, storage capacitance, frequency dispersion, leakage current, etc.) and to reduce atomic diffusion from the high-k dielectric material layer to the substrate 302, and have a thickness between about 0.3 nm and about 1 nm, for example, about 0.5 nm.

[0029] At block 230, a deposition process is performed to deposit a high-k dielectric layer 306 on the exposed surface of the semiconductor structure 300 (i.e., the interfacial layer 304 as shown in FIG. 3B if the interfacial layer 304 is formed at block 220, and the substrate 302 if the interfacial layer 304 is not formed at block 220). High- _k dielectric layer 306 may be formed of a high-k dielectric material such as hafnium dioxide ( _HfO2 ), zirconium dioxide _{( ZrO2} ), ytterbium oxide ( _Y2O3 ), or aluminum oxide ( _Al2O3 ). The deposition process may include an atomic layer deposition (ALD) process in which metal-containing precursors and oxygen-containing precursors are alternately delivered to exposed surfaces of semiconductor structure 300 . In some embodiments, the metal-containing precursor is purged prior to delivering the oxygen-containing precursor. The metals can be transition metals such as hafnium (Hf), zirconium (Zr), titanium (Ti), rare earth metals such as lanthanum (La), ytterbium (Yb), yttrium (Y), alkaline earth metals such as strontium (Sr), or other metals such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with metals can be used. For example, the oxygen-containing precursor can be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen and oxygen-containing precursors, plasma-enhanced oxygen, including locally or remotely enhanced oxygen, or any other material containing oxygen that can be incorporated into the metal to produce a metal oxide layer on the substrate 302. In one example, the metal-containing precursor is hafnium tetrachloride ( _HfCl4 ) and the oxidant is water ( _H2O ) to form a hafnium dioxide ( _HfO2 ) layer. The ALD process can be performed at a temperature between about 200°C and about 400°C, such as about 270°C. High-k dielectric layer 306 deposited by an ALD process may be amorphous and have a thickness between about 10 Å and about 30 Å. The deposition process can be performed in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG.

[0030] At block 240, an optional post-deposition annealing process is performed to harden and densify the as-deposited high-k dielectric layer 306. FIG. Crystallization of the amorphous high-k dielectric layer 306 as deposited may occur. Post-deposition annealing processes can include thermal annealing processes in inert atmospheres, such as nitrogen ( _N2 ) and argon (Ar) atmospheres, performed in rapid thermal processing (RTP) chambers, such as RADOX™ chambers available from Applied Materials, Inc., Santa Clara, California. The RTP chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. A post-deposition annealing process can thermally harden and densify the interfacial layer 304 and the high-k dielectric layer 306 .

[0031] The post-deposition annealing process can be performed for about 1 second to about 60 seconds, at a temperature between about 500°C and about 800°C, and at a pressure between about 0.01 Torr and 10 Torr.

[0032] At block 250, instead of the post-deposition annealing process of block 240, an optional re-oxidation process is performed to thermally oxidize the substrate 302. FIG. The reoxidation process can include a thermal annealing process in oxygen ( _O2 ), nitrous oxide ( _N2O ), and _H2 atmospheres performed in a rapid thermal processing (RTP) chamber, such as the RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. The re-oxidation process of block 250 can thermally oxidize the underlying layers through the high-k dielectric layer 306, thus thickening the interfacial layer 304 to a thickness between about 3 Å and about 10 Å if the interfacial layer 304 is formed at block 220, and can form the interfacial layer 304 in the substrate 302 near the interface with the high-k dielectric layer 306 if the interfacial layer 304 is not formed at block 220.

[0033] The reoxidation process can be carried out for about 1 second to about 30 seconds, at a temperature between about 400°C and about 900°C, and at a pressure between about 0.01 Torr and 100 Torr.

[0034] At block 260 , a plasma nitridation process is performed to insert nitrogen atoms into the vacancies and defects of the high-k dielectric layer 306 . The plasma nitridation process can be a decoupled plasma nitridation (DPN) process performed in a DPN chamber, such as the CENTURA® DPN chamber available from Applied Materials, Inc., Santa Clara, California. The DPN chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. The plasma nitridation process exposes the high-k dielectric layer 306 to a nitrogen plasma, which allows nitrogen radicals or nitrogen atoms to be incorporated into the high-k dielectric layer 306 throughout the thickness of the high-k dielectric layer 306. During the plasma nitridation process, nitrogen atoms can form metastable bonds with oxygen (O). Gases that can be used in plasma processes include nitrogen-containing gases such as nitrogen ( _N2 ), ammonia ( _NH3 ), or mixtures thereof. In one example, the nitrogen gas is ammonia ( _NH3 ) mixed with about 3% to about 8% nitrogen ( _N2 ). The plasma nitridation process does not change the thickness of the high-k dielectric layer 306 as a result of incorporation of nitrogen into vacancies and defects in the as-deposited high-k dielectric layer 306 .

[0035] The nitridation process can be performed at a temperature between about 0°C and about 500°C for about 10 seconds to about 300 seconds.

[0036] At block 270, an optional thermal nitridation process is performed to further insert nitrogen atoms into the vacancies and defects of the plasma-nitrided high-k dielectric layer 306. FIG. A thermal nitridation process can include a thermal annealing process in an ammonia (NH ₃ ) atmosphere performed in a rapid thermal processing (RTP) chamber, such as the RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG.

[0037] The thermal nitridation process can be performed for about 10 seconds to about 300 seconds, at a temperature between about 700°C and about 900°C, and at a pressure between about 10 Torr and 740 Torr.

[0038] At block 280, a post-nitridation annealing process is performed to passivate any remaining chemical bonds in the plasma-nitrided high-k dielectric layer 306. FIG. The post-nitridation anneal process can include a spike thermal anneal process in a nitrogen ( _N2 ) and argon (Ar) atmosphere performed in a rapid thermal processing (RTP) chamber, such as the RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California. The RTP chamber can be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. A post-nitridation annealing process can passivate the metastable nitrogen bonds formed in the plasma nitridation process of block 240, and crystallization of the amorphous high-k dielectric layer 306 can occur.

[0039] The spike thermal anneal process can be performed for about 1 second to about 30 seconds, at a temperature between about 700°C and about 850°C, and at a pressure between about 10 Torr and 740 Torr.

[0040] In block 290, instead of the post-nitridation anneal process of block 280, a post-nitridation anneal and re-oxidation process is performed to passivate the remaining chemical bonds in the high-k dielectric layer 306, as in block 280, while thermally oxidizing the substrate 302, as in block 250. The post-nitridation anneal and re-oxidation process at block 290 is the same as the re-oxidation process at block 250 . Therefore, details of the post-nitridation anneal and re-oxidation processes at block 290 are omitted here.

[0041] Embodiments described herein provide systems and methods for forming high quality thin high-k dielectric material layers. The properties of such high-k dielectric material layers can be well controlled. For example, the nitridation process in blocks 260 and 270 may be controlled to provide between about 3 atomic % and about 20 atomic % nitrogen incorporation into the high-k dielectric layer 306 to achieve higher κ values than more nitrogen incorporation and better structural stabilization than less nitrogen incorporation. The annealing process of blocks 240, 270, 280, and 290 may also be controlled to provide high-k dielectric layer 306 with particles having a size greater than about 20 Å to reduce leakage current through high-k dielectric layer 306.

[0042] While the above is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure are conceived without departing from its basic scope, which scope is determined by the following claims.

100 Processing System 102 Factory Interface 104 Loadlock Chamber 106 Loadlock Chamber 108 Transfer Chamber 110 Transfer Chamber 112 Transfer Robot 114 Transfer Robot 116 Chamber 118 Chamber 120 Processing Chamber 122 Processing Chamber 124 Processing Chamber 126 Processing Chamber 128 Processing Chamber 130 Processing Chamber 140 Station 142 Factory Interface Robot 144 Front Opening Integrated Pod ( FOUPs)
148 Blades 150 Ports 152 Ports 154 Ports 156 Ports 158 Ports 160 Ports 162 Ports 164 Ports 166 Ports 168 Ports 170 Ports 172 Ports 174 Ports 176 Ports 190 System Controller 192 Central Processing Unit (CPU)
194 memory 196 support circuit 200 method 210 block 220 block 230 block 240 block 250 block 260 block 270 block 280 block 290 block 300 semiconductor structure 302 substrate 304 interface layer 306 gate dielectric layer 400 method 410 block 420 block 430 block 440 block 450 block 460 block 480 block 500 metal gate structure 502 dielectric body cap layer 504 sacrificial silicon cap layer 506 metal layer

Claims (18)

A method of forming a semiconductor structure, comprising:
pre-cleaning the surface of the substrate;
forming an interfacial layer on the pre-cleaned surface of the substrate;
depositing a high-k dielectric layer on the interfacial layer;
annealing the substrate in an atmosphere of oxygen ( _O2 ), nitrous oxide (N2O ₎ , and H2 _after depositing the high-k dielectric layer to thermally oxidize the substrate;
performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer;
performing a post-nitridation annealing process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer;
forming a semiconductor structure comprising
forming the semiconductor structure is performed in a processing system without breaking vacuum;
Method. wherein the interfacial layer comprises silicon oxide (SiO ₂ );
2. The method of claim 1, wherein forming the interfacial layer comprises thermally oxidizing the substrate utilizing nitrous oxide ( _N2O ) gas. 2. The method of claim 1, wherein the high-k dielectric layer comprises hafnium oxide ( _HfO2 ). 2. The method of claim 1, wherein the plasma nitridation process comprises exposing the deposited high-k dielectric layer to a nitrogen plasma using a mixture of nitrogen ( _N2 ) and ammonia ( _NH3 ) gases. The method of claim 1, wherein the post-nitridation annealing process comprises spike annealing the deposited high-k dielectric layer at a temperature between 700°C and 850°C in a nitrogen ( _N2 ) and argon (Ar) atmosphere. 2. The method of claim 1, further comprising performing a post-deposition annealing process prior to said plasma nitridation process to harden and densify said deposited high-k dielectric layer. 7. The method of claim 6 , wherein the post-deposition annealing process comprises annealing the deposited high-k dielectric layer at a temperature between 500[deg.]C and 800[deg.]C in a nitrogen ( _N2 ) and argon (Ar) atmosphere. 2. The method of claim 1, further comprising performing a thermal nitridation process prior to the post-nitridation annealing process to further intercalate nitrogen atoms into the plasma-nitrided high-k dielectric layer. 9. The method of claim 8 , wherein the thermal nitridation process comprises annealing the plasma-nitrided high-k dielectric layer at a temperature between 700[deg.]C and 900[deg.]C in an ammonia ( _NH3 ) ambient. A method of forming a semiconductor structure, comprising:
pre-cleaning the surface of the substrate;
depositing a high-k dielectric layer on the substrate;
annealing the substrate in an atmosphere of oxygen ( _O2 ), nitrous oxide (N2O ₎ , and H2 _after depositing the high-k dielectric layer to thermally oxidize the substrate;
performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer;
forming a semiconductor structure comprising
forming the semiconductor structure is performed in a processing system without breaking vacuum;
Method. 11. The method of claim 10 , further comprising forming an interfacial layer on the pre-cleaned surface of the substrate comprising thermally oxidizing the substrate using nitrous oxide ( _N2O ) gas, wherein the interfacial layer comprises silicon oxide ( _SiO2 ). 11. The method of claim 10 , wherein the high-k dielectric layer comprises hafnium oxide ( _HfO2 ). 11. The method of claim 10 , wherein the plasma nitridation process comprises exposing the deposited high-k dielectric layer to a nitrogen plasma using a mixture of nitrogen ( _N2 ) and ammonia ( _NH3 ) gases. performing a post-nitridation annealing process following the plasma nitridation process to passivate chemical bonds in the plasma-nitrided high-k dielectric layer ;
11. The method of claim 10 , further comprising: said annealing of said substrate is performed at a temperature between 400° C. and 900° C.;
15. The method of claim 14, wherein the post-nitridation annealing process comprises spike annealing the plasma-nitrided high-k dielectric layer at a temperature between 700<0>C and 850<0>C in a nitrogen ( _N2 ) and argon (Ar) atmosphere. 11. The method of claim 10 , further comprising performing a re-oxidation process following the plasma nitridation process to passivate remaining chemical bonds in the plasma-nitrided high-k dielectric layer and thermally oxidize the substrate. 17. The method of claim 16 , wherein the re-oxidation process comprises annealing the high-k dielectric layer at a temperature between 400<0>C and 900<0>C in an atmosphere of oxygen ( _O2 ), nitrous oxide ( _N2O ) and _H2 . a first processing chamber;
a second processing chamber;
a third processing chamber;
a fourth processing chamber;
a fifth processing chamber;
a sixth processing chamber;
and system controller,
wherein the system controller comprises:
precleaning a surface of a substrate in the first processing chamber;
forming an interfacial layer on the pre-cleaned surface of the substrate in the second processing chamber;
depositing a high-k dielectric layer on the interfacial layer in the third processing chamber;
annealing the substrate in an atmosphere of oxygen (O2), nitrous oxide (N2O), and H2 in the _fourth processing _chamber after _depositing the high-k dielectric layer;
exposing the deposited high-k dielectric layer to a nitrogen plasma in the fifth processing chamber;
annealing the plasma-nitrided high-k dielectric layer in the sixth processing chamber;
is configured to do
The processing system wherein the substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber , the fifth processing chamber, and the sixth processing chamber without breaking the vacuum environment within the processing system.

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