JP7316083B2 - Information processing equipment - Google Patents

Description

The present invention relates to information processing devices, and more particularly to clock supply in integrated circuits.

In general, data is transferred in synchronization with a clock within a circuit. When designing such a circuit, the timing is designed in consideration of clock and data delay times so that timing converges in all synchronous paths. For example, when transferring data between flip-flops (FFs), it is necessary to satisfy the setup/hold time of the FFs in order to pass the data normally.

A clock supplied to the circuit is generated by a clock generator. In a typical configuration, the clock generator is placed at the chip top level. The clock generator may change the clock frequency and turn the clock on or off for each functional block that supplies the clock, as required. A clock generated by the clock generator is supplied to each functional block through wiring on the chip top hierarchy, and further distributed to each FF within the functional block. CTS (Clock Tree Synthesis) is a technique for physically wiring clocks so that the delay times for clocks to reach each functional block or each FF from a clock source are equal. Timing design can be facilitated by reducing the clock delay time difference (clock skew).

In recent years, in order to reduce the power consumption of information equipment such as digital cameras and smartphones, there has been a demand for controlling the frequency and on/off of clocks used in circuits (for example, integrated circuits such as LSIs) in information processing devices. ing. For example, software or the like can use a clock setting register that stores a setting value to control clock generation by the clock generator. Such registers are often implemented as a functional block and located downstream of the CTS to reduce clock skew between other functional blocks. On the other hand, the clock generator, which is the source of the clock, is driven by the CTS upstream clock. Therefore, the clock delay between the clock generator and the register becomes very large, and it is impossible to design the timing so that data can be passed between the register (and its FFs) and the clock generator (and its FFs). It's not easy. In particular, in recent years, circuits have become larger in scale and higher in frequency, making timing design more difficult.

US Pat. No. 6,200,000 proposes avoiding timing problems by stopping the clock or lowering the frequency of the clock during transitions of long-delayed signals such as reset signals.

JP 2010-277608 A

However, the method of Patent Literature 1 has a problem that the operating speed is lowered because the clock frequency is lowered or the clock is stopped every time the clock generation is controlled.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a new control technique for facilitating timing design in a configuration for controlling clocks supplied to functional blocks.

In order to achieve the object of the present invention, for example, an information processing apparatus of the present invention has the following configuration. i.e.
a plurality of generation means for generating clocks to be supplied to corresponding functional blocks among the plurality of functional blocks;
A first control for controlling clock generation by a first group of generation means composed of one or more generation means among the plurality of generation means, and operating using a clock common to the first group. means and
a second control means, which is one of the plurality of functional blocks and asynchronously transfers control information for clock generation by the generation means of the first group to the first control means;
Prepare.

Timing design can be facilitated in a configuration that controls clocks supplied to functional blocks.

1 is a system configuration diagram of an information processing apparatus according to an embodiment; FIG. 1 is a system configuration diagram of an information processing apparatus according to an embodiment; FIG. 4 is a timing chart of clock frequency switching in one embodiment. 4 is a timing chart of on/off operation of a clock in one embodiment; 1 is a diagram showing a configuration for asynchronous transfer of an information processing device according to an embodiment; FIG. FIG. 4 is a diagram illustrating an example of register fields according to one embodiment; 4 is a timing chart of setting value transfer in one embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In addition, the following embodiments do not limit the invention according to the scope of claims. Although multiple features are described in the embodiments, not all of these multiple features are essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant description is omitted.

First, with reference to FIG. 1, a configuration example of an information processing apparatus 100 according to one embodiment is shown. In this specification, embodiments of the present invention will be described with reference to an information processing apparatus 100 shown in FIG. However, it should be noted that not all configurations of the information processing apparatus 100 are essential in the present invention.

The information processing device 100 shown in FIG. 1 is a semiconductor device called a system-on-chip, and can be called a semiconductor integrated circuit. Each block inside the information processing apparatus 100 shown in FIG. 1 may be, for example, a circuit that exhibits each function. The use of the information processing apparatus 100 is not particularly limited, and the information processing apparatus 100 has functional blocks that perform processing for realizing functions suitable for use, as will be described later. The information processing device 100 may be, for example, an information processing device for a digital camera system.

Each block inside the information processing apparatus 100 is interconnected via a bus system. Such a bus system may be a system called interconnect, fabric, on-chip network, or network-on-chip. A plurality of functional blocks are connected to the bus system, each of which performs a specific process. The information processing apparatus 100 according to one embodiment has a function of receiving video data from an external sensor (not shown), a function of transferring the video data to a DRAM (not shown) via a bus system, and a function of processing the video data. It has a function of processing and storing in the DRAM. The functional blocks 7a-7f shown in FIG. 1 each carry out processing to implement at least some of these and other functions. Also connected to the bus system is a CPU 8 which is one of a plurality of functional blocks and controls the processing performed by the information processing apparatus 100 as a whole.

A configuration for supplying clocks used for operating the functional blocks to the functional blocks in the information processing apparatus 100 will be described below. The information processing apparatus 100 has a mechanism for oscillating clocks, and this mechanism may be capable of supplying a low-speed clock and a high-speed clock as shown in FIG.

In FIG. 1, an oscillator 1 oscillates a low-speed clock. The PLL2 and PLL3 each use the low-speed clock generated by the oscillator 1 and, for example, multiply the low-speed clock to output a high-speed clock faster than the low-speed clock. The clock MUX 4 selects the low-speed clock generated by the oscillator 1 or the high-speed clock generated by the PLL 2, and supplies it to the generators 6a to 6e and the controllers 31 and 32 located in the subsequent stage. Also, the clock MUX 5 selects the low-speed clock generated by the oscillator 1 or the high-speed clock generated by the PLL 3, and supplies it to the generator 6f and the controller 33 located in the subsequent stage. In this specification, the clock selected by clock MUX4 is referred to as reference clock 1, and the clock selected by clock MUX5 is referred to as reference clock 2. FIG.

The generators 6a to 6f supply clocks to corresponding functional blocks among the plurality of functional blocks. In the example of FIG. 1, generators 6a, 6b, 6e, and 6f supply clocks to functional blocks 7a, 7b, 7e, and 7f, respectively. In addition, the generation unit 6c and the generation unit 6d supply clocks to the control unit 9 and the CPU 8, which are one of the functional blocks, respectively. For this purpose, the generators 6a to 6f generate clocks to be supplied to the functional blocks. The clocks generated by the generators 6a to 6f and supplied to the functional blocks are called clocks a to f, respectively.

The generators 6a to 6f use a reference clock (for example, reference clock 1 or reference clock 2) to generate clocks to be supplied to the functional blocks. For example, generators 6a and 6b, which are the plurality of generators, supply clocks generated using the common reference clock 1 to corresponding functional blocks 7a and 7b. The generators 6a to 6f divide the frequency of the reference clock to reduce the frequency of the reference clock, and then supply the clock to the functional blocks. In addition, the generators 6a to 6f can turn on or off clocks to be supplied to the functional blocks.

The control units 31 to 33 control clock generation by the generation units 6a to 6f. In the example of FIG. 1 , the control unit 31 controls clocks supplied by the generation units 6 a and 6 b, which are groups corresponding to the control unit 31 . Similarly, the control unit 32 controls the clock supplied by the generation units 6c to 6e that are the group corresponding to the control unit 32, and the control unit 33 is supplied by the generation unit 6f that is the group corresponding to the control unit 33. Control the clock.

In this embodiment, the control units 31 to 33 control the frequencies of the clocks supplied from the generating units 6a to 6f to the functional blocks, and control to turn on or off the clock supply from the generating units 6a to 6f to the functional blocks. can be performed, but the content of control is not limited to this. In this specification, the control units 31 to 33 may be called a first control unit.

The control unit 9 transfers control information for clock generation by the generation units 6a-6f to the control units 31-33. That is, the control unit 9 transfers to the control unit 31 control information for clock generation by the generation units 6a and 6b, which are a group corresponding to the control unit 31. FIG. Similarly, the control unit 9 transmits control information for clock generation by the generation units 6c to 6e, which are the group corresponding to the control unit 32, to the control unit 31, and controls clock generation by the generation unit 6f, which is the group corresponding to the control unit 33. Control information is transferred to the control unit 33, respectively. Thus, the controller 9 controls clocks supplied to the functional blocks via the controllers 31-33.

The control unit 9 can have, for example, a register that stores a set value of the clock frequency generated by each of the generation units 6a to 6f and a set value indicating whether the clock is turned on or off. The control unit 9 can supply the setting values stored in these registers to the control units 31-33. Note that the CPU 8 may read and write the setting values stored in the register by the control section 9 via the register bus. Thus, the CPU 8 can control the clock supplied to the functional blocks. In this specification, the controller 9 may be called a second controller.

The reset unit 20 generates a reset signal inside the information processing device 100 . The reset section 20 can operate using the low-speed clock oscillated by the oscillator 1. In this case, the reset signal output by the reset section 20 is synchronized with the low-speed clock. According to this reset signal, counters and FFs (described later) of the generators 6a to 6f are initialized. In accordance with this reset signal, the functional blocks 7a-7f, CPU 8, controller 9, and controllers 31-33 may be initialized at the same time (not shown).

The low-speed clock oscillated by the oscillator 1 can be selected for the clock MUXs 4 and 5 when resetting is executed. At this time, all units of the information processing apparatus 100 operate in synchronization with the low-speed clock. After the reset is released, when the information processing apparatus 100 starts normal processing, the clocks MUX4 and 5 can select the high-speed clocks generated by the PLL2 and PLL3. Thus, the information processing apparatus 100 can perform high-speed processing.

Next, detailed configuration examples of the generators 6a to 6f will be described. Although the generating unit 6a will be described below, the generating units 6b to 6f can also have the same configuration. In FIG. 1, the generator 6a generates a clock with a reduced frequency by reducing the number of pulses of the reference clock 1. FIG. For example, the generation unit 6a can halve the frequency by thinning the pulse of the reference clock 1 once every two times, and can halve the frequency by thinning it three times every four times. The pulse width of the clock generated by such a method (also called toothless method) is the same as the pulse width of the reference clock.

The generation unit 6a has a counter 61a and a frequency dividing circuit, and operates using the reference clock 1. FIG. In the example of FIG. 1, the frequency dividing circuit has a decoder 62a, a flip-flop (FF) 63a, and a gated clock buffer (GCB) 64a.

The counter 61a performs a counting operation and holds a count value. The count value is initialized to 0 at reset. The counter 61a starts counting up after the reset is released, and then continues counting up without stopping. When the count value reaches a predetermined expire value, the next count value becomes 0 and counting up is started again. Thus, in one embodiment, the reset unit 20 can simultaneously initialize the counter values of the counters (counters 61a, 61b, etc.) included in each of the plurality of generation units (generation units 6a, 6b, etc.). In addition, the reset unit 20 can simultaneously start the operation of initialized counters (counters 61a, 61b, etc.) included in each of the plurality of generation units (generation units 6a, 6b, etc.).

The frequency dividing circuit divides the frequency of the reference clock 1 based on the value of the counter 61a. Then, the frequency dividing circuit supplies the clock a generated by frequency division to the corresponding functional block 7a. Here, the frequency dividing circuit can generate the clock a under the control of the control section 31 .

In the example of FIG. 1, the decoder 62a generates a timing signal indicating the timing of thinning out the pulses of the reference clock 1 according to the count value of the counter 61a. Here, the decoder 62 a can generate this signal further according to the set value 51 a of the clock frequency input from the control section 31 .

The FF 63a latches the timing signal generated by the decoder 62a and inputs it to the GCB 64a.

The GCB 64a thins out the pulses of the reference clock 1 according to the input timing signal, thereby generating a clock a having a frequency lower than that of the reference clock 1. FIG. For example, the GCB 64a can halve the frequency by thinning the pulse of the reference clock 1 once every two times, and can halve the frequency by thinning the pulse three times every four times. can. The GCB 64a can also output a clock a having the same frequency as the reference clock 1 without thinning the reference clock 1 pulses. Furthermore, the GCB 64a can also turn on or off the clock a according to the set value 50a input from the control unit 31 and indicating whether the clock is on or off.

Synchronization groups in the information processing apparatus 100 will be described below. In the example of FIG. 1, since data is transferred (not shown) between the functional blocks 7a and 7b, clocks are supplied to the functional blocks 7a and 7b so that the phases of the clocks are aligned. . In this way, the functional blocks 7a and 7b supplied with phase-aligned clocks are grouped as a synchronization group 11 in this specification. Similarly, the CPU 8, the control unit 9, and the functional block 7e are grouped as a synchronous group 12, and the functional block 7f is grouped as a synchronous group 13 by itself. That is, the control units 31-33 control the clocks belonging to the corresponding synchronization groups 11-13. Functional blocks grouped into the same synchronous group in this way are referred to as synchronously related functional blocks in this specification. In one embodiment, functional blocks in a synchronous relationship are configured such that synchronous data transfers occur between the functional blocks. It should be noted that there is no need to match the phases of the supplied clocks between different synchronous groups, since data synchronized with the clock is not transferred.

In addition, as shown in FIG. 1, even if there is a clock delay due to the length of the wiring from the generator that generates the clock to the functional block, the clock phase is aligned between the generator and the functional block. Clock trees 40a-40f may be formed between. For example, the clock trees 40a and 40b are formed on wiring carrying the clocks a and b between the generators 6a and 6b and the functional blocks 7a and 7b. Specifically, wiring is performed so that the clock delay times of the clock tree 40a of clock a and the clock tree 40b of clock b, which belong to the same synchronization group 11, are equal. A CTS buffer is inserted. The same is true for the clock trees 40c-40e for the clocks c-e belonging to the synchronization group 12. FIG.

By the way, the control unit 9 is located downstream of the clock tree 40c of the clock c. On the other hand, the control units 31 and 32 are positioned upstream of the clock tree 40c and operate using the reference clock 1 . Therefore, a large clock skew exists between the control unit 9 and the control units 31 and 32, and it is not guaranteed that the phases of the clock c and the reference clock 1 are aligned. Also, the control unit 33 operates using the reference clock 2 whose clock system is different from that of the clock c. Therefore, it is not guaranteed that the phases of the clock c and the reference clock 2 are aligned.

[Embodiment 1]
An information processing apparatus according to Embodiment 1 of the present invention includes a plurality of functional blocks in a synchronous relationship and a plurality of generation units. Each of the plurality of generating units has a counter and a frequency dividing circuit that divides the frequency of the reference clock based on the value of the counter, and supplies the clock to the corresponding functional block among the plurality of functional blocks. . According to such a configuration, it becomes easy to suppress variations in clock delay of clocks supplied to a plurality of functional units. Such a configuration will be described below.

The configuration according to the first embodiment can be realized using the information processing apparatus 100 shown in FIG. 1, for example, using a plurality of functional blocks 7a and 7b and a plurality of generating units 6a and 6b. That is, the plurality of generators 6a and 6b belong to the same synchronous group 11 and are in a synchronous relationship. Further, each of the plurality of generating units 6a and 6b includes counters 61a and 61b, and frequency dividing circuits (decoders 62a and 62b, FFs 63a and 63b, and GCBs 64a and 64b) that divide the frequency of the reference clock based on the values of the counters. ,have. Each of the plurality of generators 6a and 6b supplies clocks to the corresponding functional blocks 7a and 7b among the plurality of functional blocks. On the other hand, it is not essential to use all the configurations shown in FIG.

In the present embodiment, although the functional blocks 7a and 7b are in a synchronous relationship, clocks generated by different generators 6a and 6b are supplied to the functional blocks 7a and 7b, respectively. By adopting such a configuration, it becomes possible to arrange the generators 6a and 6b in the vicinity of the corresponding functional blocks 7a and 7b. For example, one of the plurality of generators 6a and 6b can be arranged closer to the corresponding functional block than the other functional blocks. A clock line for supplying a clock from one of the plurality of generators 6a and 6b to the corresponding functional blocks 7a and 7b is a clock line for supplying the reference clock 1 from the clock MUX 4 to the generators 6a and 6b. can be shorter. Therefore, the clock wiring from the generators 6a and 6b to the functional blocks 7a and 7b can be shortened. Furthermore, a common clock line extending to the vicinity of the functional blocks 7a, 7b can be used to supply the reference clock 1. FIG. With such a configuration, it is possible to reduce the influence of variations in clock delay. By adopting the configuration of this embodiment and shortening the clock wiring, timing convergence between the functional blocks 7a and 7b becomes easier.

FIG. 2 shows an example of a physical layout of an LSI that implements the information processing apparatus according to this embodiment in such a configuration. As shown in FIG. 2, each processing unit belonging to the synchronization group 11 can be arranged so as to be physically grouped together. That is, in FIG. 2, the functional blocks 7a and 7b belonging to the synchronous group 11 are arranged adjacently within the area of the synchronous group 11. As shown in FIG. Further, the generator 6a for supplying the clock to the functional block 7a is arranged near the functional block 7a, and similarly the generator 6b is arranged near the functional block 7b.

In one embodiment, the clock line that supplies the reference clock 1 from the clock MUX 4 to each of the generators 6a and 6b branches off near the generators 6a and 6b. For example, in FIG. 2, the reference clock 1 is distributed to each of the generators 6a and 6b through branched wiring at a branch point 81 near the generators 6a and 6b. As a specific example, the clock lines from the branch point 81 to the generation unit 6a and from the branch point 81 to the generation unit 6b are the clock lines from the processing unit (for example, the clock MUX 4) that supplies the reference clock 1 to the branch point 81. can be shorter. Also, as shown in FIG. 2, a clock line supplying the reference clock 1 to a further functional block 7e different from the functional blocks 7a and 7b is connected at a branch point 84 to the plurality of generators 6a and 6b. may be branched from the clock line that supplies the The clock lines that supply the reference clock 1 from the clock MUX 4 to each of the plurality of generators 6a and 6b may branch off from each other at a branch point 81 downstream of the branch point 84 . With such a configuration, since the clock wiring after branching for the clocks supplied to the functional blocks 7a and 7b is shortened, timing convergence between the functional blocks 7a and 7b is facilitated.

In one embodiment, the control unit 31 may control clocks supplied to the functional blocks 7 a and 7 b belonging to the synchronization group 11 . Specifically, the control unit 31 can control clock generation by the plurality of generation units 6a and 6b. Here, one controller 31 may control the plurality of generators 6a and 6b. Such a configuration facilitates synchronizing the control of the clocks a and b supplied to the functional blocks 7a and 7b. In this case, the control unit 31 can be arranged within the area of the synchronization group 11, that is, in the vicinity of the functional blocks 7a and 7b. The control unit 31 may operate using the reference clock 1 common to the plurality of generation units 6a and 6b. For example, the reference clock 1 may be distributed to the control unit 31 through a branched wire in the vicinity of the control unit 31, for example, a branched wire at the branch point 81 described above. Such a configuration improves timing convergence between the control unit 31 and the generation units 6a and 6b.

Similarly, the CPU 8, the control unit 9, the functional block 7e belonging to the synchronization group 12, the generation units 6c to 6e that supply clocks to them, and the control unit 32 that controls the generation units 6c to 6e are physically grouped together. can be arranged as follows. The synchronization group 13 is also the same.

Operations of the generators 6a and 6b when the information processing apparatus 100 shown in FIG. 1 is used in the first embodiment will be described below with reference to FIGS. FIG. 3 is a timing chart showing clock frequency switching operations performed by the generators 6a and 6b.

In the following example, the counters 61a and 61b of the plurality of generators 6a and 6b are configured to operate synchronously. For example, the counter values of the counters 61a and 61b can be incremented at the same timing. In the example of FIG. 1, the bit widths of the counters 61a and 61b of the plurality of generators 6a and 6b are the same. Here, the bit width of the counter indicates the number of bits of the counter value, and may correspond to the maximum value of the count value. Also, the counters 61a and 61b of the plurality of generators 6a and 6b may wrap around at the same time (that is, the count values may return to 0 at the same time). Furthermore, the counters 61a and 61b of the plurality of generators 6a and 6b may be configured to indicate the same counter value. Such a configuration facilitates synchronizing the clocks a and b supplied to the functional blocks 7a and 7b. Here, the counters 61a and 61b of the generators 6a and 6b are both 4-bit counters, and can count up to 15.

In the following example, due to the circuit characteristics of the functional blocks 7a and 7b, the following frequency relationship must always be maintained between the clock a frequency and the clock b frequency. Suppose there is
Frequency of clock a > Frequency of clock b

At time T0, the information processing apparatus 100 is in a reset state, the counters 61a and 61b are stopped, and the counter values are both zero. The setting values 50a and 50b, which indicate whether the clock is on or off, are set on the clock output side. Also, the initial values of the FFs 63a and 63b are Low, and the output clock is stopped.

Furthermore, the initial values of the internal set values (hereinafter simply referred to as internal set values) are both 2'b00. Here, the internal setting values are values obtained by latching the clock frequency setting values 51a and 51b output from the control section 31 by the decoders 62a and 62b. The decoders 62a and 62b latch the set values 51a and 51b at the timing when the count values of the counters 61a and 61b wrap around from 15 to 0. 2'b00 indicates division by 1, 2'b01 indicates division by 2, 2'b10 indicates division by 4, and 2'b11 indicates division by 8, respectively. . On the other hand, the internal setting values of the generation unit 6b are such that 2'b00 indicates division by 2, 2'b01 indicates division by 4, 2'b10 indicates division by 8, and 2'b11 indicates division by 16. and Therefore, in the initial state, the clock a is set to the reference clock 1 divided by 1, and the clock b is set to the reference clock 1 divided by 2, respectively. Note that the clock frequency setting value is not limited to a 2-bit signal. Also, the relationship between the internal set value and the frequency division ratio is not limited to the above example, and can be arbitrarily defined.

The reset is released at time T1. At time T2, the counters 61a and 61b simultaneously start counting up. Also, the FFs 63a and 63b latch the output values of the decoders 62a and 62b, respectively, and become High.

At time T3, the outputs of the FFs 63a and 63b are High, so the GCBs 64a and 64b start outputting clocks. Further, the decoder 62a always outputs High in accordance with the internal set value indicating division by one. On the other hand, the decoder 62b outputs a signal that repeats High and Low so as to form one cycle High period in two cycles according to an internal setting value indicating division by two. As a result, one cycle pulse is thinned out every two cycles, and the frequency division by two is realized. Similar operations are performed at times T4 to T8.

On the other hand, at time T7, the set values 51a and 51b input to the control unit 31 are both switched from 2'b00 to 2'b01. This switching may be performed, for example, by the CPU 8 rewriting the register of the control unit 9 and the control unit 9 transferring the setting value in the register to the control unit 31 . However, the method of switching the setting values in the first embodiment is not particularly limited.

The count values of the counters 61a and 61b both count up to the maximum count value of 15 at time T8, and both wrap around to 0 at time T9. The internal set value switches from 2'b00 to 2'b01 at the same time that the counters 61a and 61b wrap around. Therefore, the clock frequency output from the generating unit 6a is changed from dividing by 1 to dividing by 2, and the clock frequency output from the generating unit 6b is changed from dividing by 2 to dividing by 4. That is, from time T9, the decoder 62a outputs a signal that repeats High and Low with a period of one cycle every two cycles. Start output. Further, from time T9, the decoder 62b outputs a signal that becomes High only in one cycle out of four cycles, and from time T11, the generator 6b starts outputting a four-frequency-divided clock.

According to such a configuration, the counters 61a and 61b of the generating section 6a and the generating section 6b operate in the same manner in synchronization, so that the switching timings of the clock frequencies can be made at the same time. Therefore, clock control can be performed while observing the frequency-related restrictions of the clock frequency as described above. However, when supplying clocks to a plurality of functional blocks in a synchronous relationship, it is not essential to change the clock frequency at the same timing.

FIG. 4 is a timing chart showing the ON/OFF operation of the clock frequency performed by the generator 6a. Note that the generation unit 6b and the other generation units 6c to 6f can also operate in the same manner as the generation unit 6a.

At time T0, the information processing apparatus 100 is in a reset state. Here, the internal setting value of the generator 6a indicates 2'b00, that is, the generator 6a is set to output a clock obtained by dividing the frequency of the reference clock 1 by one. However, since the set value 50a representing whether the clock is on or off, which is output by the control unit 31, is Low, the clock a, which is the output clock from the generation unit 6a, is stopped. Here, the set value 50a is a High active signal, that is, High indicates clock on and Low indicates clock off.

At time T3, the control unit 31 changes the set value 50a to High. At time T4, the set value 50a is High, so the GCB 64a starts outputting the clock a. At time T10, the control unit 31 changes the set value 50a to Low. Therefore, clock a stops at time T11. Note that the setting value 50a can be switched in the same manner as the setting value 51a. Note that the counter 61a can continue counting even while the clock a is stopped.

As in the above example, the maximum frequency division ratio of the clock generated by the generator 6a and the maximum frequency division ratio of the clock generated by the generator 6b may be different. On the other hand, the maximum frequency division ratio of the generator 6a is 8 frequency division, and it is sufficient to use a 3-bit width counter (maximum count value 7) to output an 8 frequency division clock. The maximum frequency division ratio of the generator 6b is 16 divisions, and a 4-bit width counter (maximum count value 15) is used to output a 16 division clock. In the above example, the counter width of the counter 61a of the generation unit 6a is 4 bits, which is larger than the required 3 bits, so that the counter width is the same as that of the counter 61b of the generation unit 6b. In this manner, the behavior of the counters 61a and 61b can always be made the same by a simple configuration in which the counter widths of the counters 61a and 61b are aligned and the wraparound is performed at the same time. Therefore, according to the above example, it is possible to easily switch the clock frequencies at the same time. However, in another example, the control of the generator 6a and the control of the generator 6b may be performed independently.

In the above example, a toothless method of thinning out pulses is used as the frequency division method for dividing the clock, but the frequency division method that can be used is not limited to a specific method. For example, as the frequency division method, a method (also called a frequency division method) using the Q output of each bit of the down counter included in the generator as a frequency-divided clock may be adopted. In this case, for example, the Q output of the first digit bit of the counter has a frequency of 1/2, and the Q output of the second digit bit has a frequency of 1/4. In this case, a MUX that selects one of the frequency-divided clocks for each bit of the down counter can be used instead of the decoder of the generator. When the frequency division method is used, the pulse width of the clock generated by the generator increases in proportion to the division ratio. For example, dividing by two makes the pulse width twice that of the reference clock, and dividing by four makes the pulse width four times that of the reference clock. According to the configuration of the first embodiment, various frequency division methods can be applied.

In the above example, the reference clock has the same constant frequency during reset and after reset release. On the other hand, in one embodiment, while the clock MUX 4 supplies the low-speed clock as the reference clock 1, the reset unit 20 resets the initialized counters 61a and 61b of the plurality of generators 6a and 6b, respectively. action can be initiated. The reset unit 20 can supply the high-speed clock as the reference clock 1 after the counters 61a and 61b start operating. Thus, after the reset is released, the clock MUX4 may be used to switch the reference clock 1 from the low-speed clock to the high-speed clock. Such a configuration facilitates timing design for synchronizing the operations of the counters 61a and 61b. When the reference clock is switched to the high-speed clock, the period of one cycle becomes shorter than that of the low-speed clock, but the behavior of each signal does not change.

In the above example, it is assumed that the counter continues to count up after the reset is released, and the count values of the counters 61a and 61b continue to be synchronized. However, due to external factors such as cosmic rays, the synchronization of the counter values may be lost. In order to contrast with such an event, the information processing apparatus according to one embodiment further includes a configuration for detecting out-of-synchronization between the counters (61a, 61b) provided in each of the plurality of generation units 6a, 6b. may have. In this case, the reset unit 20 can initialize the counter values of the counters 61a and 61b included in the plurality of generation units 6a and 6b in response to detection of the synchronization deviation.

As an example of such a configuration, the counters 61a and 61b may have check circuits for checking whether the counter values are incremented by one. When the check circuit detects an abnormality, that is, the counter value is not incremented by one, the reset unit 20 can be notified of the abnormality of the counter value. In this case, the reset unit 20 switches the supplied reference clock to the low-speed clock oscillated by the oscillator 1 and resets all generation units that generate clocks for the same synchronization group as the counter that issued the notification. can be done. According to such a configuration, the counters of all generating units that generate clocks for the same synchronization group can be initialized and counted up from 0 at the same time, that is, the counter values can be synchronized.

[Embodiment 2]
An information processing apparatus according to Embodiment 2 of the present invention includes a plurality of generation units, a first control unit, and a second control unit. Each of the plurality of generators generates clocks to be supplied to corresponding functional blocks among the plurality of functional blocks. A first control unit controls clock generation by a first group of the plurality of generation units, and operates using a clock common to the first group. The second control unit is one of the plurality of functional blocks, and asynchronously transfers control information for clock generation by the first group to the first control unit. Such a configuration facilitates timing design for the second controller to control the generator. Such a configuration will be described below.

The configuration according to the second embodiment can be realized by using the information processing apparatus 100 shown in FIG. That is, the plurality of generators 6a and 6b respectively generate clocks to be supplied to the corresponding functional blocks 7a and 7b among the plurality of functional blocks. The control unit 31 controls the clock generation by the generating units 6a and 6b forming the first group among the plurality of generating units, and uses the clock common to the generating units 6a and 6b forming the first generating unit. works. The generators 6a and 6b forming the first group may supply the generated clocks to a plurality of functional blocks 7a and 7b that are in a synchronous relationship with each other. The control unit 9 is one of a plurality of functional blocks, and asynchronously transfers to the control unit 31 control information for clock generation by the generation units 6a and 6b forming the first group. In the example of FIG. 1, the second group of generation units (generation units 6 c to 6 e ) whose clock generation is controlled by the control unit 32 supplies the generated clocks to the control unit 9 . Here, the second group operates using the reference clock 1 common to the first group. On the other hand, it is not essential to use all the configurations shown in FIG. Further, the information processing apparatus according to the second embodiment may have the configuration of the information processing apparatus according to the first embodiment, but may be an information processing apparatus different from the first embodiment.

In this embodiment, the controller 9 is connected to the controller 31 via an I/F 34 that is an interface for asynchronous data transfer. The control unit 9 can asynchronously transfer control information for clock generation to the control unit 31 via the I/F 34 . This control information may include at least one of clock frequency information generated by the generator and information for controlling on/off of the clock generated by the generator. For example, the control unit 9 sets clock frequency setting values 51a and 51b for the generating units 6a and 6b and setting values 50a and 50b indicating whether the clocks are turned on or off as control information for clock generation by the generating units 6a and 6b. can be transferred.

Similarly, the information processing apparatus according to one embodiment controls clock generation by a second group (generation units 6c to 6e) composed of one or more generation units among a plurality of generation units, It may have a control unit 32 that operates using a clock common to the group. The control unit 9 can asynchronously transfer control information for clock generation by the second group to the control unit 32 . In the example of FIG. 1, the controller 9 is connected to controllers 32 and 33 via I/Fs 35 and 36, which are interfaces for asynchronous data transfer. In this case, the control unit 9 can asynchronously transfer the setting values for the generating units 6c to 6e to the control unit 32 and the setting value for the generating unit 6f to the control unit 33, respectively.

An example of the configuration of the control unit 9 and the control unit 31 for performing asynchronous transfer will be described with reference to FIG. FIG. 5 is a block diagram showing an example of the configuration of the control section 9 and the control section 31. As shown in FIG. The controller 9 has a transfer controller 91 and a register 92 . The register 92 stores clock generation control information for the synchronization group 11 . The control unit 9 may similarly have registers 93 and 94 for storing clock generation control information for the synchronization groups 12 and 13 . Registers 92-94 have different address spaces for register access and are exclusively readable and writable. The control information in these registers 92-94 can be rewritten by one of a plurality of functional blocks. For example, CPU 8 may read from and write to registers 92-94 via a register bus.

In the following, a case where writing to the register 92 is performed will be described, but similar operations can be performed when writing is performed to the registers 93 and 94 as well. Also, in the following example, a case where the control unit 9 and the control unit 31 are connected by a bus and the control unit 9 transfers control information to the control unit 31 via the bus will be described.

Register access between the control unit 9 and the control unit 31 in the example shown in FIG. 5 is performed using a bus protocol using address signals and data signals. In FIG. 5, the controller 9 and the controller 31 are further connected by signal lines (req, ack) for controlling transfer of control information.

When a write to a register occurs, the transfer control unit 91 determines for which synchronous group the write has occurred to the register based on the register access address, and starts asynchronous data transfer to the corresponding control unit. First, the control unit 9 sends a signal requesting acquisition of control information to the control unit 31 . In the example of FIG. 5, the transfer control unit 91 asserts a request signal (req) to the I/F 34 with the control unit 31 when determining that writing has occurred in the register 92 for the synchronization group 11, for example. On the other hand, the transfer control unit 91 outputs the register value of the register 92 as a data signal (data) to the I/F 34 .

The control unit 31 synchronizes the input req using a two-stage FF synchronizer 312 including FFs 313 and 314 for metastability countermeasures. The control unit 31 also generates a pulse that is a logical product 317 of the Q output of FF 314 indicating the synchronized req and the inverse of the Q output of FF 315 . Then, the register 311 latches the data of the I/F 34 according to the generated pulse. After that, the control unit 31 sends a signal notifying that the control information has been acquired to the control unit 9 . In the example of FIG. 5, the control unit 31 loops back the Q output of FF314 via FF315 and FF316 as a response signal (ack) to I/F34.

The control unit 9 uses a two-stage FF synchronizer 95 to synchronize ack input from the I/F 34 . The ack after synchronization is input to the transfer control unit 91 . The transfer control unit 91 deasserts req in accordance with the assertion of ack after synchronization. Eventually ack is also deasserted, thus completing the asynchronous data transfer. A detailed operation example of the asynchronous data transfer will be described later with reference to the timing chart of FIG.

The control unit 31 generates the data signal latched by the register 311 as setting values for the generating units 6a and 6b (for example, clock frequency setting values 50a and 50b and clock ON/OFF setting values 51a and 51b). Output to the units 6a and 6b. In the example described here, the control unit 31 synchronizes control information (for example, the above set values 50a, 50b, 51a, 51b) with each of the one or more generation units 6a, 6b included in the first group. Forward. Also, the control unit 31 can output the control information to each of the one or more generation units 6a and 7b included in the first group at the same timing.

The control units 32 and 33 can also have the same configuration for asynchronous data transfer as the control unit 31, and can latch the register values of the registers 93 and 94. FIG. In this way, the transfer control unit 91 may centrally control all the I/Fs 34-36.

The delivery of the set value of the frequency of the clock a will be described with reference to the timing chart of FIG. Note that the set value of the frequency of clock b can also be transferred in the same manner. In the following description, the control unit 9 operates in synchronization with the clock c, which is the reference clock 1 divided by two. The clock c is located downstream of the CTS with respect to the reference clock 1, and the pulse generated according to the reference clock 1 at the time T0 is delayed until the time T2' when it reaches the control unit 9 due to the clock delay of the CTS. there is Because of this clock delay difference, it is not easy to guarantee phase synchronization between clock c and reference clock 1 .

At time T0, the set value of the frequency of clock a is 2'b00 (divided by 1). This setting value is input to the control unit 31 as data via the I/F 34 . At time T'4, the setting value of the frequency of clock a held by the register 92 is changed from 2'b00 to 2'b01 (divided by 2) by writing to the register 92 of the control unit 9. FIG. At the same time, the transfer control unit 91 asserts req of the I/F 34 . Here, req and ack are High active signals, and assert means High.

The req asserted at time T4' is latched by the FF 313 of the control unit 31 at time T5. However, the phases of clock c, which is the transmission clock, and reference clock 1, which is the reception clock, may not be synchronized. Therefore, metastability may occur at time T5. However, since the two-stage FF synchronizer 312 is used in this example, the metastability generated at time T5 converges at time T6, and the Q output of FF 313 becomes High. At time T7, this High propagates from FF313 to FF314. Then, the logical AND 317 of the inverted Q output of FF 315 and the Q output of FF 314 becomes High. Since the AND 317 is High at time T8, the MUX 318 selects the data assigned to No. 1, so the data is latched into the register 311. FIG.

The set value 51a of the clock frequency according to the data latched in the register 311 at time T8 reaches the generator 6a at time T8' due to the data delay. This set value 51a can be latched by the decoder 62a at time T9 when the reference clock 1 rises at the earliest. Timing can be designed assuming that this timing path is a path that transfers data in one cycle of the reference clock 1 .

At time T9, the controller 31 asserts ack of the I/F 34 . Upon receiving the assertion of ack, the transfer control unit 91 deasserts req at time T12'. At time T13, metastability may occur as at time T5, but metastability converges at time T14 and the Q output of FF 313 becomes Low. Thereafter, ack is propagated to Low until time T17, and the asynchronous data transfer is completed.

Thus, in the above example, control information for clock generation (for example, clock frequency setting value and clock ON/OFF) is transmitted from the control unit 9 downstream of the CTS to the control unit 31 operating with the reference clock 1 upstream of the CTS. setting value) can be transferred asynchronously. Therefore, the timing path from the control unit 9 downstream of the CTS to the control unit 31 upstream of the CTS can be cut off. In one embodiment, the one or more generation units 6a and 6b and the control unit 31 included in the first group use clocks upstream in the clock tree from the control unit 9 (including clocks not covered by the clock tree). works. As described above, even if the operation clock of the control unit 9 and the operation clocks of the generation units 6a and 6b are not synchronized, in the present embodiment, the control unit 9 controls clock generation to the generation units 6a and 6b. Easier to transfer information. That is, in the present embodiment, it is only necessary to synchronously transfer the set values between the control unit 31 and the generation units 6a and 6b that operate using a common clock, which facilitates timing design.

In particular, as described in the first embodiment, data delay from the control unit 31 to the generation units 6a and 6b is reduced by placing the control unit 31 near the first group (generation units 6a and 6b). be able to. For example, the controller 31 can be arranged closer to the generators 6a and 6b than any of the other generators 6c to 6f. According to such a configuration, timing design can be easily performed so that the control information for clock generation is transferred from the control section 31 to the generation sections 6a and 6b in one cycle of the reference clock 1. FIG.

Note that the control unit 9 may be included in any synchronization group. For example, the controller 9 may be one of the functional blocks included in the synchronization group 11 . In this case, the first group of generation units (generation units 6 a and 6 b ) can supply the generated clock to the control unit 9 . Also, the control unit 9 may be one of the functional blocks included in the synchronization group 13 . In this case, the third group of generators (generators 6f) whose clock generation is controlled by the controller 33 can supply the generated clocks to the controller 9, where the third group is It operates using a reference clock 2 different from that of the first group. Even when the control unit 31 and the control unit 9 operate using different reference clocks in this manner, the timing design for transferring control information is facilitated by dividing the timing path.

Further, as described in the first embodiment, when the clock frequencies generated by the generators 6a and 6b are subject to frequency-related restrictions, the generators 6a and 6b generate It may be necessary to change the clock frequency to be used at the same time. Thus, the configuration of this embodiment is also effective for simultaneously changing the clock frequencies. For example, in one embodiment, a single register write changes the frequency settings for both clock a and clock b. An example of register fields that can implement such a configuration will be described with reference to FIG.

FIG. 6 represents register 92 . It is assumed that reading and writing of the register 92 are executed in units of 4 bytes. That is, in FIG. 6, reading and writing of the 0th bit to the 31st bit are possible at the same time. sel a is a set value of the frequency of clock a assigned to the 0th bit to the 1st bit. sel b is a set value of the frequency of clock b assigned to the 2nd to 3rd bits. Reserved from the 4th bit to the 31st bit is an unused area.

In such an embodiment, when changing the frequency of clock a and clock b, sel a and sel b are rewritten at the same time. In this case, the set values of the frequencies of the clocks a and b indicated by the data output by the register 92 via the I/F 34 change at the same time. Therefore, the data signal stored in the register 311 also reflects the change in the set values of the frequencies of the clocks a and b at the same time. Therefore, the set values 51a and 51b of the clock frequencies output by the register 311 are also changed at the same time. Thus, the frequencies of clock a and clock b can be changed simultaneously. The configuration for changing the clock frequency according to the set value is not particularly limited, but for example, by adopting the same configuration as in the first embodiment, by simultaneously changing the set values 51a and 51b, clock a and clock The frequency of b can be changed at the same time.

In the second embodiment, mainly the case of changing the set value of the clock frequency has been described, but similarly, the set value of turning on or off the clock can also be changed.

In this embodiment, the CPU 8 rewrites the register of the control unit 9 via the register bus, and asynchronously transfers control information for clock generation from the control unit 9 to the control unit 31 . On the other hand, the CPU 8 may asynchronously transfer the clock generation control information directly to the control section 31 . As described above, the controller 31 can be provided for each synchronization group. For example, the CPU 8 can asynchronously transfer clock generation control information to the control unit 31 by rewriting a register provided in the control unit 31 via a register bus capable of asynchronous bus transfer.
[Other embodiments]

In FIG. 1, the generators 6a to 6f are provided so as to have a one-to-one relationship with the functional blocks, but the present invention is not limited to such a configuration. That is, one generator may supply clocks to two or more functional blocks. In this case, considering the layout of the functional blocks, the clocks to be supplied to the multiple functional blocks are generated so that the timing design is not affected by the delay variation of the clock wiring on the chip top layer between the generator and the functional blocks. A generator may be provided.

The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the claims are appended to make public the scope of the invention.

6a, 6b: generator, 7a, 7b: functional block, 8: CPU, 9: controller, 31: controller, 61a, 61b: counter

Claims (17)

a plurality of generating means each generating a clock to be supplied to a corresponding functional block among the plurality of functional blocks;
A first control for controlling clock generation by a first group of generation means composed of one or more generation means among the plurality of generation means, and operating using a clock common to the first group. means and
a second control means, which is one of the plurality of functional blocks and asynchronously transfers control information for clock generation by the generation means of the first group to the first control means;
An information processing device comprising: 2. The information processing according to claim 1, wherein said first control means outputs said control information to each of said one or more generating means included in said first group at the same timing. Device. 3. The information processing apparatus according to claim 2, wherein said first control means synchronously transfers said control information to each of said one or more generating means included in said first group. The first control means and the second control means are connected by a bus, and the second control means transfers the control information to the first control means via the bus. 4. The information processing apparatus according to any one of claims 1 to 3. 5. The information processing apparatus according to claim 4, wherein said second control means transfers said control information to said first control means using a bus protocol using address signals and data signals. . 6. The information processing apparatus according to claim 4, wherein said first control means and said second control means are further connected by a signal line for controlling transfer of said control information. . 7. The information processing apparatus according to claim 4, wherein said second control means further sends a signal requesting acquisition of said control information to said first control means. . 7. The information processing apparatus according to claim 4, wherein said first control means sends a signal notifying that said control information has been acquired to said second control means. . The second control means has a register for storing the control information, and the control information in the register can be rewritten by one of the plurality of functional blocks. 9. The information processing device according to any one of 1 to 8. 10. The information processing apparatus according to any one of claims 1 to 9, wherein said first group generating means supplies the generated clock to a plurality of functional blocks that are in a synchronous relationship with each other. 11. The information processing apparatus according to claim 1, wherein said first group generation means supplies the generated clock to said second control means. The second control means is clocked by a second group of generating means comprising one or more generating means of the plurality of generating means, the second group being the first group. 11. The information processing apparatus according to any one of claims 1 to 10, wherein each operates using a common clock. The second control means is clocked by a third group of generating means comprising one or more generating means of the plurality of generating means, the third group being the first group. 11. The information processing apparatus according to any one of claims 1 to 10, wherein said clocks are different from each other. The one or more generation means and the first control means included in the first group operate using a clock upstream in a clock tree from the second control means. 14. The information processing device according to any one of 1 to 13. a third control for controlling clock generation by a second group of generation means composed of one or more generation means among the plurality of generation means, and operating using a common clock with the second group; further equipped with means,
15. The apparatus according to any one of claims 1 to 14, wherein said second control means asynchronously transfers control information for clock generation by said second group of generation means to said third control means. The information processing device described. The control information includes frequency information of the clock generated by the generating means included in the first group and information for controlling on/off of the clock generated by the generating means included in the first group. 16. The information processing apparatus according to any one of claims 1 to 15, wherein the information processing apparatus is at least one of: 17. The information processing apparatus according to any one of claims 1 to 16, wherein said first control means is arranged in the vicinity of said first group generating means.

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