JP7324699B2 - Clock generation circuit and power supply IC - Google Patents

Description

The present invention relates to clock generation circuits.

Electronic devices are required to have EMC (Electro-Magnetic Compatibility). . The former is rated as Electro Magnetic Interference (EMI) and the latter as Electro Magnetic Susceptibility (EMS).

Power supply ICs such as PMICs (power management ICs) with multiple DC/DC converters are known to be noise sources. Therefore, the power supply IC needs to take measures against EMI.

As one of EMI countermeasures, a spread spectrum function is known (for example, Patent Document 1). The spread spectrum function disperses the frequency of the spectrum and suppresses the power peak of the spectrum by temporally changing the frequency of the generated clock.

JP 2019-110733 A

Here, it is desirable that the number of terminals of the power supply IC be as small as possible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock generation circuit capable of reducing the number of terminals associated with the spread spectrum function.

To achieve the above object, one aspect of the present invention is a clock generation circuit included in an IC having a terminal to which an external capacitor can be externally connected,
a first constant current circuit and a second constant current circuit arranged between a power supply voltage and ground and connected at a connection node;
a first input terminal connected to the connection node to which the terminal is connected; a second input terminal to which a first reference voltage and a second reference voltage lower than the first reference voltage are switchably applied; a first comparator for controlling on/off of the first constant current circuit and the second constant current circuit by an output;
a first input to which the terminal is connected; and a second input to which the first reference voltage and a third reference voltage lower than the first reference voltage are switchably applied; a second comparator that outputs a signal;
a first switch that selects either a fourth reference voltage or a terminal voltage generated at the terminal according to the enable signal;
a selection unit that selects the lower one of the voltage selected by the first switch and a fifth reference voltage that is higher than the first reference voltage and lower than the fourth reference voltage;
a VCO (Voltage-controlled oscillator) that generates a clock signal having a frequency corresponding to the voltage selected by the selection unit;
(first configuration).

Further, in the above first configuration, the selection unit may
a first PNP transistor having a base to which a voltage selected by the switch is applied and a collector connected to ground;
a second PNP transistor having a base to which the fifth reference voltage is applied and a collector connected to ground;
a third constant current circuit arranged between a supply voltage application terminal and emitters of the first PNP transistor and the second PNP transistor;
(second configuration).

Further, in the above second configuration, the VCO is
an NPN transistor having a base connected to each emitter of the first PNP transistor and the second PNP transistor;
a resistor connected between the emitter of the NPN transistor and ground;
a current mirror connected to the collector of the NPN transistor;
a capacitor that can be charged by the output current from the current mirror;
a second switch for discharging the capacitor;
a third comparator having a first input terminal to which the voltage of the capacitor is input and a second input terminal to which a sixth reference voltage is applied, the output of which controls the second switch;
(third configuration).

Another embodiment of the present invention is a power supply IC including the clock generation circuit having any of the structures described above and the terminal (fourth structure).

Further, the fourth configuration is a power supply IC having a rectangular shape in a plan view,
including a DC/DC converter;
having a first side, a second side facing the first side, a third side, and a fourth side facing the third side;
A power supply terminal to which a power supply voltage is input, a ground terminal, a switching terminal connected to a node where an upper transistor and a lower transistor included in the DC/DC converter are connected, a feedback voltage terminal to which a feedback voltage is input, an internal A VREG terminal to which a voltage is output and a BOOT terminal to which a boot capacitor for bootstrap can be connected are arranged on at least one of the first side, the second side and the third side,
Only other terminals may be arranged on the fourth side.

According to the clock generation circuit of the present invention, the number of terminals related to the spread spectrum function can be reduced.

3 is a diagram showing an external terminal configuration of PMIC; FIG. 2 is a block diagram showing the internal configuration of PMIC; FIG. Fig. 2 shows a CMOS sensor powered by a PMIC; FIG. 2 is a diagram mainly showing a configuration example of an oscillator in a PMIC; 4 is a timing chart showing the start-up operation of the oscillator when a capacitor is externally connected to the SSCG terminal; FIG. 2 is a diagram mainly showing the configuration of a first DC/DC converter in PMIC; FIG. 2 is a diagram mainly showing a configuration of a second DC/DC converter or a third DC/DC converter in PMIC; FIG. 3 is a diagram mainly showing a configuration in a PMIC related to an LDO outside the IC; 4 is a timing chart showing an example of a start-up sequence; FIG. 10 is a timing chart showing a fall sequence corresponding to the rise sequence shown in FIG. 9; FIG. FIG. 9 is a diagram showing a case where an external LDO is temporarily not used in the configuration of the PMIC of FIG. 8; FIG. 9 is a diagram showing a modified example of the configuration of the PMIC shown in FIG. 8; 4 is a table showing mask determination of overvoltage/undervoltage detection signals; FIG. 13 is a timing chart showing a start-up sequence in the configuration of FIG. 12; FIG. It is a figure which shows an example of the usage pattern of LDO. FIG. 10 is a diagram illustrating another example of how LDOs are used; 4 is a table showing an example of setting contents according to mode setting by MODE0 to MODE2 terminals; It is the top view which looked at PMIC from upper direction. FIG. 4 is a plan view schematically showing a layout example on a substrate;

Exemplary embodiments of the invention are described below with reference to the drawings. Here, a PMIC (power management IC) will be described as an example of a power supply device.

<1. Overall configuration of PMIC>
FIG. 1 is a diagram showing an external terminal configuration of PMIC 1 according to an exemplary embodiment of the present invention. FIG. 2 is a block diagram showing the internal configuration of PMIC1. The PMIC 1 is an IC that supplies power to an in-vehicle CMOS sensor (CMOS camera).

The PMIC 1 has a VCC terminal, an EN terminal, an SSCG terminal, an RT terminal, a MODE0 terminal, a MODE1 terminal, a MODE2 terminal, an FB_LDO terminal, a VO1 terminal, a VO2 terminal, and a VO3 terminal as external terminals for establishing electrical connection with the outside. , VS2 terminal, VS3 terminal, SW1 terminal, SW2 terminal, SW3 terminal, PGND23 terminal, GND terminal, PGND1 terminal, BOOT terminal, PVCC terminal, PGOOD terminal, EN_LDO terminal, and VREG terminal.

The internal configuration of the PMIC 1 includes a UVLO section 2, an internal voltage generation section 3, a reference voltage generation section 4, a reference voltage generation section 5, a TSD section 6, a UVLO section 7, a UVLO section 8, and an oscillator ( a clock generation circuit) 9, a control logic unit 10, a first DC/DC converter 11, a second DC/DC converter 12, a third DC/DC converter 13, an overvoltage/lowvoltage detection unit 14, a driver 15, and an NMOS transistor 16 are integrated into one chip.

A power supply voltage Vcc is applied to the VCC terminal from the outside, and a capacitor C1, which is a bypass capacitor, is externally connected between the VCC terminal and the ground.

A UVLO (Under Voltage Lock Out) section 2 is a circuit for detecting that the power supply voltage Vcc has become equal to or lower than a predetermined detection voltage. The UVLO unit 2 puts the detection signal UVLO_VCC into a UVLO detection state when the power supply voltage Vcc is lower than or equal to the detection voltage, and puts the detection signal UVLO_VCC into a UVLO cancellation state when the power supply voltage Vcc is higher than or equal to a predetermined recovery voltage. . The control logic unit 10 performs control according to the detection signal UVLO_VCC.

VREG3 generates an internal voltage Vreg based on power supply voltage Vcc. The internal voltage Vreg is used as a power supply voltage inside the IC and is output from the VREG terminal. A bypass capacitor C2 is connected between the VREG terminal and the ground.

An enable signal En is input from the outside to the EN terminal. The enable signal En is input to the internal voltage generating section 3 and the control logic section 10 via the EN terminal.

Reference voltage generators 4 and 5 generate reference voltages Vref1 and Vreg2 based on the internal voltage Vreg, respectively.

When the TSD (thermal shutdown) section 6 detects that the junction temperature of the IC has reached or exceeded a predetermined temperature, it outputs an overheat detection signal Tsd indicating that fact to the control logic section 10 . As a result, the control logic unit 10 shuts down the IC.

The UVLO unit 7 is a circuit that performs UVLO detection on the internal voltage Vreg, and outputs a detection signal UVLO_VREG to the control logic unit 10 . The UVLO unit 8 is a circuit that performs UVLO detection for the output voltage Vo1 applied to the VS2 terminal, and outputs a detection signal UVLO_VS to the control logic unit 10 . The output voltage Vo1 is the voltage output by the first DC/DC converter 11 .

The oscillator 9 is a circuit that generates a clock signal, and outputs the generated clock signal to the control logic unit 10, the first DC/DC converter 11, the second DC/DC converter 12, and the third DC/CD converter 13 (clock signal CLKi (i=1 to 3)). The oscillator 9 has a spectrum spread function that temporally changes the frequency of the clock signal. A spread spectrum modulation frequency is set by a capacitor C3 externally connected to the SSCG terminal. As will be described later, in the present embodiment, one terminal of the SSCG terminals is capable of performing control for switching between valid/invalid of the spread spectrum function. A detailed configuration of the oscillator 9 will be described later. Also, the oscillation frequency of the clock signal generated by the oscillator 9 can be set by the resistor R1 externally connected to the RT terminal.

The control logic unit 10 outputs a UVLO detection signal UVLO_VCC, a UVLO detection signal UVLO_VREG, a UVLO detection signal UVLO_VS, an overvoltage detection signal VSOVP, a low voltage detection signal LVDi (i=1 to 4), and an overvoltage detection signal OVDi (i=1 to 4). , an overcurrent detection signal OCP, and an overheat detection signal Tsd are input, and protection control is performed based on the protection signals. In addition, the control logic unit 10 can also control the startup/shutdown sequence of the power supply circuit as will be described later.

High or Low level is set to the MODE0 to MODE2 terminals (FIG. 1 is an example in which Low level (ground) is set to all the terminals). The control logic unit 10 performs mode switching control according to the level setting of the MODE0 to MODE3 terminals.

The first DC/DC converter 11 is a power supply circuit that DC/DC-converts a power supply voltage Vcc applied to a PVCC terminal to an output voltage Vo1 and outputs the output voltage Vo1. The first DC/DC converter 11 receives the control signal CTL1 from the control logic unit 10 and the clock signal CLK1 from the oscillator 9 .

The second DC/DC converter 12 is a power supply circuit for DC/DC converting the output voltage Vo1 applied to the VS2 terminal to an output voltage Vo2 as an input voltage and outputting the output voltage Vo2. The second DC/DC converter 12 receives the control signal CTL2 from the control logic unit 10 and the clock signal CLK2 from the oscillator 9 .

The third DC/DC converter 13 is a power supply circuit for DC/DC converting the output voltage Vo1 applied to the VS3 terminal to an output voltage Vo3 as an input voltage and outputting the output voltage Vo3. A control signal CTL3 is input from the control logic unit 10 and a clock signal CLK3 is input from the oscillator 9 to the third DC/DC converter 13 .

Detailed configurations of the first DC/DC converter 11, the second DC/DC converter 12, and the third DC/DC converter 13 will be described later.

An LDO (Low Dropout) 20 shown in FIG. 1 is a linear regulator (power supply circuit) that is arranged outside the PMIC 1 and converts the output voltage Vo1 to the output voltage Vo4. The output voltage Vo4 is fed back to the FB_LDO terminal. The overvoltage/lowvoltage detection unit 14 monitors the output voltage Vo4 input from the FB_LDO terminal and outputs an overvoltage detection signal OVD4 and a low voltage detection signal LVD4 to the control logic unit 10 . A detailed configuration of the overvoltage/lowvoltage detection unit 14 will be described later.

Also, the LDO 20 is controlled to start/stop based on the enable signal En_LDO output from the EN_LDO terminal by the control logic unit 10 .

Driver 15 and NMOS transistor 16 are configured for the power good function. The power good function is a function of outputting a flag when the output of the power supply circuit reaches a set voltage value. A flag signal PG is output from the PGOOD terminal to the outside. The details of the configuration regarding the power good function will be described later.

FIG. 3 shows a CMOS sensor 30 powered by PMIC1. The CMOS sensor 30 has a Digital terminal, an I/O terminal, an LVDS terminal, an Analog terminal, and a Reset terminal. The output voltage Vo2 is applied to the Digital terminal, the output voltage Vo3 is applied to the I/O terminal and the LVDS terminal, and the output voltage Vo4 is applied to the Analog terminal. A flag signal PG is input to the Reset terminal.

<2. Configuration of Oscillator>
Next, the details of the configuration of the oscillator 9 will be described. FIG. 4 is a diagram mainly showing a configuration example of the oscillator 9 in the PMIC 1. As shown in FIG. As shown in FIG. 4, the oscillator 9 includes a constant current circuit 91, a constant current circuit 92, a comparator 93, a comparator 94, a switch 95, a constant current circuit 96, a PNP transistor 97, and a PNP transistor 98. , VCO99.

A constant current circuit 91 and a constant current circuit 92 are arranged between the terminal to which the power supply voltage (internal voltage) Vreg is applied and the ground. A non-inverting input terminal (+) of the comparator 93 is connected to a connection node N91 between the constant current circuits 91 and 92 . The inverting input terminal (-) of the comparator 93 is switchably connected to the application terminals of the reference voltages V2 and V3. On/off of the constant current circuits 91 and 92 is controlled according to the output of the comparator 93 .

The connection node N91 and the non-inverting input terminal (+) of the comparator 94 are connected to the SSCG terminal. The inverting input terminal (-) of the comparator 94 is switchably connected to the application terminals of the reference voltages V2 and V4.

The switch 95 selects the terminal voltage Vsscg generated at the SSCG terminal or the power supply voltage Vreg according to the enable signal En9 output from the comparator 94, and outputs it as the voltage V91.

A voltage V 91 output from the switch 95 is applied to the base of the PNP transistor 97 . The collector of PNP transistor 97 is connected to ground. A reference voltage V1 is applied to the base of the PNP transistor 98, and the ground is connected to the collector. A constant current circuit 96 is arranged between the application terminal of the power supply voltage Vreg and the emitters of the PNP transistors 97 and 98 .

A VCO (Voltage-controlled oscillator) 99 is a circuit that outputs a clock signal CLK having an oscillation frequency corresponding to a voltage V92 generated at a connection node N92 where the emitters of PNP transistors 97 and 98 and constant current circuit 96 are connected. VCO 99 has NPN transistor 99B, current mirror 99C, capacitor 99D, comparator 99E, and switch 99F.

A voltage V92 is applied to the base of the NPN transistor 99B. A first end of the resistor R1 is connected to the emitter of the NPN transistor 99B via the RT terminal. A second end of the resistor R1 is connected to ground. The current mirror 99C is composed of a PMOS transistor, and passes a current having the same current value as the current flowing through the resistor R1 to the capacitor 99D. A first terminal of a capacitor 99D is connected to the non-inverting input terminal (+) of the comparator 99E. A reference voltage Ref9 is applied to the inverting input terminal (-) of the comparator 99E. A switch 99F is a switch for discharging the capacitor 99D.

The lower of voltage V91 and reference voltage V1 is selected and the base-emitter voltage of PNP transistors 97 and 98 is added to the selected voltage to produce voltage V92. A constant current I99 is generated by a voltage obtained by subtracting the base-emitter voltage of NPN transistor 99B from voltage V92 and resistor R1. Assuming that the voltage selected from the voltage V91 and the reference voltage V1 is Vs, the current value of the constant current I99 is Vs/R1 (R1: resistance value of resistor R1). Such constant current I99 is mirrored to capacitor 99D by current mirror 99C.

When the switch 99F is off and the capacitor 99D is charged with a constant current, the voltage V93 generated in the capacitor 99D rises from 0V and exceeds the reference voltage Ref9, the clock signal CLK output from the comparator 99E becomes High. becomes. Then, the switch 99F is turned on, the capacitor 99D is discharged, the voltage V93 is lowered to 0V, and the clock signal CLK is made Low. Then, the switch 99F is turned off again, and charging of the capacitor 99D is started. Thus, the clock signal CLK that repeats High and Low is generated.

The frequency f of clock signal CLK is expressed as follows.
f=1/t
However, t=(C×Ref9)/(Vs/R1) C: Capacitance of capacitor 99D

That is, the clock signal CLK having a frequency corresponding to the voltage Vs selected from the voltage V91 and the reference voltage V1 is generated. Also, the frequency f of the clock signal CLK can be set by the resistance value of the resistor R1.

The operation of the oscillator 9 having such a configuration will be described. FIG. 5 is a timing chart showing the startup operation of the oscillator 9 when the capacitor C3 (FIG. 4) is externally connected to the SSCG terminal. As shown in FIG. 5, the magnitude relationship of each voltage is Vreg>V1>V2>V3>V4.

First, at timing t0, the terminal voltage Vsscg is 0 V, the output of the comparator 93 is Low compared to the reference voltage V2, the constant current circuit 91 is turned on, and the constant current circuit 92 is turned off. As a result, the capacitor C3 starts to be charged by the constant current circuit 91, and the terminal voltage Vsscg starts to rise. At this time, the comparator 94 compares the enable signal En9 with the reference voltage V2 and sets the enable signal En9 to Low, and the switch 95 selects the power supply voltage Vreg. As a result, the voltage V91 becomes Vreg, and the lower one of Vreg and V1, V1, is selected. Therefore, a clock signal CLK having a constant frequency corresponding to the reference voltage V1 is generated.

After that, when the terminal voltage Vsscg exceeds the reference voltage V2 at timing t1, the enable signal En9 becomes High, and the switch 95 selects the terminal voltage Vsscg. As a result, the voltage V91 becomes the terminal voltage Vsscg (=V2), and the lower one of Vsscg and V1, VVsscg, is selected. Therefore, a clock signal CLK having a frequency corresponding to Vsscg is generated.

At this time, the output of the comparator 93 becomes High, the constant current circuit 91 is turned off, the constant current circuit 92 is turned on, the capacitor C3 starts to discharge, and the terminal voltage Vsscg starts to drop. When the terminal voltage Vsscg becomes lower than the reference voltage V3, the output of the comparator 93 becomes Low, the constant current circuit 91 is turned on, the constant current circuit 92 is turned off, and charging of the capacitor C3 is started. As a result, the terminal voltage Vsscg becomes a triangular wave that rises and falls between the reference voltages V2 and V3. Therefore, of the terminal voltages Vsscg and V1, the terminal voltage Vsscg is always selected to be lower, and the clock signal CLK having a frequency corresponding to the terminal voltage Vsscg as a triangular wave is generated.

Although the comparator 94 switches the reference voltage to V4 at timing t1, the terminal voltage Vsscg becomes a triangular wave between V2 and V3, so it does not fall below V4 and the enable signal En9 is maintained at High.

As a result, the frequency of the clock signal CLK changes with time, so that the spread spectrum function of dispersing the frequency of the spectrum and suppressing the peak of the power of the spectrum becomes effective. Since the frequency of the triangular terminal voltage Vsscg is determined according to the capacitance of the capacitor C3 externally connected to the SSCG terminal, the spread spectrum modulation frequency is also determined. Specifically, the larger the capacitance of the capacitor C3, the lower the spread spectrum modulation frequency.

The lower the spread spectrum modulation frequency, the lower the power peak. However, in this embodiment, the SSCG terminal is provided and the capacitor C3 is arranged externally. is easy.

When disabling the spread spectrum function, the ground may be externally connected to the SSCG terminal. In this case, the enable signal En9, which is the output of the comparator 94, is maintained at Low, and the switch 95 maintains the selection of Vreg. As a result, a clock signal CLK having a constant frequency corresponding to V1, which is the lower one of Vreg and V1, is generated, disabling the spread spectrum function.

As described above, in the present embodiment, it is possible to set the modulation frequency of the spread spectrum and enable/disable the spread spectrum function with one terminal of the SSCG terminals, so that the number of terminals can be reduced. can.

<3. Configuration of DC/DC converter>
Next, the structure of the DC/DC converter incorporated in PMIC1 is described.

FIG. 6 is a diagram mainly showing the configuration of the first DC/DC converter 11 in the PMIC 1. As shown in FIG. The first DC/DC converter 11 is a step-down DC/DC converter that steps down the power supply voltage Vcc and converts it into an output voltage Vo1.

The first DC/DC converter 11 includes an error amplifier 11A, a soft start section 11B, a PWM comparator 11C, a slope generation section 11D, a current detection section 11E, a drive logic section 11F, a comparator 11G, and an upper driver 11H. , a lower driver 11I and a driver 11J. Further, the first DC/DC converter 11 has resistors R11 to R20, comparators CP11 to CP13, a detection resistor Rs11, an upper MOS transistor M11, a lower MOS transistor M12, and a PMOS transistor M14. .

Also, inductor L1, boot capacitor Cb, input capacitor Cin1, and output capacitor Co1 are arranged outside PMIC1.

The output voltage Vo1 is applied as a feedback voltage to the VO1 terminal and divided by resistors R11 and R12. The voltage after voltage division is input to the inverting input terminal (-) of the error amplifier 11A. A soft start voltage ss1 generated by the soft start section 11B is applied to the first non-inverting input terminal (+) of the error amplifier 11A. A voltage obtained by dividing the reference voltage Vref1 by resistors R13 and R14 is applied to the second non-inverting input terminal (+) of the error amplifier 11A.

The error amplifier 11A is a transconductance amplifier that outputs a current corresponding to the error between the voltage applied to the first and second non-inverting input terminals, whichever is lower, and the voltage applied to the inverting input terminal. . The inverting input terminal (-) of the PWM comparator 11C and the first terminal of the resistor R15 are connected to the output terminal of the error amplifier 11A. A second end of resistor R15 is connected to a first end of capacitor C11. A second end of capacitor C11 is connected to ground.

A signal based on the slope voltage generated by the slope generator 11D is input to the non-inverting input terminal (+) of the PWM comparator 11C. The PWM comparator 11C outputs a PWM signal as a comparison result to the driving logic section 11F. The drive logic unit 11F outputs the upper control signal HSC1 and the lower control signal LSC1 based on the PWM signal.

The drain of the upper MOS transistor M11, which is an NMOS transistor, is connected to the PVCC terminal. A power supply voltage Vcc is applied to the PVCC terminal. The source of the upper MOS transistor M11 is connected to the drain of the lower MOS transistor M12, which is an NMOS transistor, at a connection node Nsw1. The source of the lower MOS transistor M12 is connected to the PGND1 terminal. The PGND1 terminal is connected to the ground. An input capacitor Cin1 is connected between the power supply voltage Vcc and the ground.

The connection node Nsw1 is connected to the SW1 terminal. The SW1 terminal is externally connected to the first end of inductor L1. An output capacitor Co1 is connected between the second end of the inductor L1 and ground.

The upper driver 11H drives the gate of the upper MOS transistor M11 based on the upper control signal HSC1 output from the driving logic section 11F. The upper driver 11H applies the boot voltage Vboot generated at the BOOT terminal or the switching voltage Vsw1 at the SW1 terminal to the gate of the upper MOS transistor M11.

The lower driver 11I drives the gate of the lower MOS transistor M12 based on the lower control signal LSC1 output from the driving logic section 11F. The lower driver 11I applies the internal voltage Vreg or the ground potential of the PGND1 terminal to the gate of the lower MOS transistor M12.

As a result, PWM control is performed so that the voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12 matches the reference voltage based on the reference voltage Vref1. The side MOS transistor M12 is switched complementarily. As a result, the output voltage Vo1 is controlled to a voltage corresponding to the voltage division ratio of the reference voltage and the resistors R11 and R12.

A bootstrap is formed to drive upper MOS transistor M11. A boot capacitor Cb is connected between the BOOT terminal and the SW1 terminal. When turning off the upper MOS transistor M11, the drive logic unit 11F causes the driver 11J to output the switching voltage Vsw1 to the PMOS transistor M14 by the boot control signal BOOT_C. As a result, the PMOS M14 is turned on, the VREG terminal and the BOOT terminal are electrically connected, and the boot capacitor Cb is charged by the internal voltage Vreg.

As a result, when the upper MOS transistor M11 is turned on next time, the boot voltage Vboot higher than the switching voltage Vsw1 can be applied to the gate of the upper MOS transistor M11 by the upper driver 11H. At this time, the PMOS transistor 14 is turned off by the boot control signal BOOT_C, and the boot capacitor Cb is discharged.

Also, the first end of the detection resistor Rs11 is connected to the PVCC terminal. A second end of the detection resistor Rs11 is connected to the drain of the NMOS transistor 13 . The source of the NMOS transistor 13 is connected to the connection node Nsw1.

The node where the detection resistor Rs11 and the NMOS transistor 13 are connected is connected to the inverting input terminal (-) of the comparator 11G. A voltage lower than the PVCC terminal voltage by a reference voltage REF11 is applied to the non-inverting input terminal (+) of the comparator 11G.

The gate of NMOS transistor 13 is driven by upper driver 11H. That is, the NMOS transistor 13 is turned on and off in synchronization with the upper MOS transistor M11. When the upper MOS transistor M11 is on, that is, when the NMOS transistor 13 is on, a voltage generated by the current flowing through the upper MOS transistor M11 and the on-resistance of the upper MOS transistor M11 is applied across the detection resistor Rs11. When the voltage obtained by lowering the PVCC terminal voltage by the voltage across the detection resistor Rs11 becomes lower than the voltage obtained by lowering the PVCC terminal voltage by the reference voltage REF11, the comparator 11G determines that an overcurrent has been detected and outputs a High overcurrent detection signal OCP1. Output to the drive logic section 11F. Thereby, the drive logic unit 11F can perform overcurrent protection.

The current detector 11E outputs a current detection signal based on the voltage across the detection resistor Rs11. The current detection signal is added to the slope voltage and input to the PWM comparator 11C.

A voltage obtained by dividing the output voltage Vo1 applied to the VS2 terminal by resistors R19 and R20 is applied to the non-inverting input terminal (+) of the comparator CP11, and the reference voltage Vref2 is applied to the inverting input terminal (-) of the comparator CP11. applied. Comparator CP11 is a hysteresis comparator and outputs overvoltage detection signal VSOVP.

A voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12 is applied to the non-inverting input terminal (+) of the comparator CP12, and a voltage obtained by dividing the reference voltage Vref2 by the combined resistance of the resistor R16 and the resistors R17 and R18. is applied to the inverting input (-) of the comparator CP12. Comparator CP12 is a hysteresis comparator and outputs overvoltage detection signal OVD1.

A voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12 is applied to the inverting input terminal (-) of the comparator CP13, and a voltage obtained by dividing the reference voltage Vref2 by the combined resistance of the resistors R16 and R17 and the resistor R18 is obtained. It is applied to the non-inverting input terminal (+) of the comparator CP13. Comparator CP13 is a hysteresis comparator and outputs low voltage detection signal LVD1.

Next, configurations of the second DC/DC converter 12 and the third DC/DC converter 13 will be described. FIG. 7 is a diagram mainly showing the configuration of the second DC/DC converter 12 or the third DC/DC converter 13 in the PMIC 1. As shown in FIG. As for the suffix i in the figure, i=2 indicates the second DC/DC converter 12, and i=3 indicates the third converter DC/DC 13. FIG. The subscripts are used in the following description.

The second DC/DC converter 12 and the third DC/DC converter are step-down DC/DC converters that step down the output voltage Vo1 and convert it to the output voltage Voi.

The second DC/DC converter 12 and the third DC/DC converter 13 include an error amplifier 21A, a soft start section 21B, a PWM comparator 21C, a slope generation section 21D, a current detection section 21E, a drive logic section 21F, It has a comparator 21G, an upper driver 21H, a lower driver 21I, and a comparator 21J. Furthermore, the second DC/DC converter 12 and the third DC/DC converter 13 include resistors R21 to R28, comparators CP21 and CP22, detection resistors Rs21 and Rs22, an upper MOS transistor M21, a lower MOS transistor M22, It has a PMOS transistor M23, an NMOS transistor M24, and an NMOS transistor M25.

Also, the inductor Li and the output capacitor Coi are arranged outside the PMIC1.

Since the configurations of the second DC/DC converter 12 and the third DC/DC converter 13 are similar to the configuration of the first DC/DC converter 11 described above, the description thereof will be omitted as appropriate. The output voltage Voi applied to the Voi terminal as a feedback voltage is divided by resistors R21 and R22 and applied to the inverting input terminal (-) of the error amplifier 21A. The error amplifier 21A outputs a current corresponding to the error between the lower of the voltage obtained by dividing the reference voltage Vref1 by the resistors R23 and R24 and the soft start voltage ssi by the soft start section 21B and the divided voltage of the output voltage Voi. do.

The source of the upper MOS transistor M21, which is a PMOS transistor, is connected to the VSi terminal to which the output voltage Vo1 is applied. The drain of the upper MOS transistor M21 is connected to the drain of the lower MOS transistor M22, which is an NMOS transistor, at a connection node Nswi. The source of the lower MOS transistor M22 is connected to the PGND23 terminal. The PGND terminal 23 is connected to the ground.

The connection node Nswi is connected to the SWi terminal. The SWi terminal is connected to the first end of the inductor Li. A second end of the inductor Li is connected to a first end of the output capacitor Coi.

The VSi terminal voltage and the SWi terminal voltage are switched by the upper driver 21H and applied to the gate of the upper MOS transistor M21 to drive the upper MOS transistor M21. The VSi terminal voltage and the SWi terminal voltage are switched by the lower driver 21I and applied to the gate of the lower MOS transistor M22 to drive the lower MOS transistor M22. The upper MOS transistor M21 and the lower MOS transistor M22 are complementarily switched.

The PMOS transistor M23, the detection resistor Rs21, and the comparator 21G are configured to detect overcurrent flowing through the upper MOS transistor M21 when the upper MOS transistor M21 is on. output.

The NMOS transistor M24, the detection resistor Rs22, and the comparator 21J are configured to detect overcurrent flowing through the lower MOS transistor M22 when the lower MOS transistor M22 is on. A signal OCPLi is output.

The NMOS transistor M25 is turned on when the control signal CTLi is Low (invalid), and discharges the output capacitor Coi.

Further, the comparator CP21 compares the voltage obtained by dividing the output voltage Voi by the resistors R21 and R22 with the voltage obtained by dividing the reference voltage Vref2 by the resistor R26 and the combined resistance of the resistors R27 and R28, and outputs the overvoltage detection signal OVDi. to output

Further, the comparator CP22 compares the voltage obtained by dividing the output voltage Voi by the resistors R21 and R22 with the voltage obtained by dividing the reference voltage Vref2 by the combined resistance of the resistors R26 and R27 and the resistor R28, and outputs the low voltage detection signal LVDi. to output

The resistance voltage division ratio by the resistors R11 and R12 in the first DC/DC converter 11 and the resistance voltage division ratio by the resistors R21 and R22 in the second DC/DC converter 12 can be switched according to the mode set by the MODE0 to MODE2 terminals. , which will be discussed later.

<4. Configuration Regarding External LDO>
Here, as described above with reference to FIG. 1, the LDO 20 is arranged outside the PMIC 1 in this embodiment. A configuration of the PMIC 1 in which the LDO 20 is arranged outside the IC in this way will be described.

FIG. 8 is a diagram mainly showing the configuration of the PMIC 1 related to the LDO 20 outside the IC. The LDO 20 is a linear regulator that steps down the output voltage Vo1 generated by the first DC/DC converter 11 to the output voltage Vo4. By arranging the LDO 20 externally to the PMIC 1, it becomes possible to arrange the LDO 20 close to the CMOS sensor 30 shown in FIG. can be reduced, making it easier to take measures against external noise. Also, by arranging the LDO outside the IC, it is possible to disperse the heat source.

In this embodiment, as shown in FIG. 8, the EN_LDO terminal provided in the PMIC1 is connected to the enable terminal 20A of the LDO20. This makes it possible to perform start/stop control (on/off control) of the LDO 20 by the enable signal En_LDO output from the EN_LDO terminal.

As shown in FIG. 8, when using the LDO 20, the output voltage Vo1 is applied to the input terminal 20B of the LDO 20, and the output terminal 20C outputting the output voltage Vo4 of the LDO 20 is short-circuited with the FB_LDO terminal by wiring outside the IC. Let As a result, the output voltage Vo4 is fed back to the FB_LDO terminal.

Here, as shown in FIG. 8, the overvoltage/undervoltage detector 14 has resistors 14A to 14C, a switch 14D, resistors 14E to 14G, and comparators 14H and 14I. Resistors 14A, 14B, and 14C are connected in series between the FB_LDO terminal and the ground.

The switch 14D selects either the node N141 to which the resistors 14 and 14B are connected or the node N142 to which the resistors 14B and 14C are connected according to the mode set by the MODE0 to MODE2 terminals. The potential of the selected node is applied to the non-inverting input terminal (+) of comparator 14H and the inverting input terminal (-) of comparator 14I. That is, the voltage division ratio for dividing the FB_LDO terminal voltage by resistance is switched according to the mode. Mode setting will be described later.

A voltage obtained by dividing the power supply voltage Vreg by the resistor 14E and the combined resistance of the resistors 14F and 14G is applied to the inverting input terminal (-) of the comparator 14H. A voltage obtained by dividing the power supply voltage Vreg by the combined resistance of the resistors 14E and 14F and the resistor 14G is applied to the non-inverting input terminal (+) of the comparator 14I. Comparators 14H and 14I are hysteresis comparators.

As a result, the comparator 14H outputs an overvoltage detection signal OVD4 for detecting an overvoltage of the output voltage Vo4, and the comparator 14I outputs a low voltage detection signal LVD4 for detecting a low voltage of the output voltage Vo4. The overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are input to the control logic section 10. FIG. The control logic unit 10 can perform protection control using the overvoltage detection signal OVD4 and the low voltage detection signal LVD4.

FIG. 8 also shows a configuration related to the power good function. The PMIC 1 has an OR circuit 10A, a counter 10B, a driver 15 (FIG. 2), and an NMOS transistor 16 (FIG. 2) as components related to the power good function. Note that the OR circuit 10A and the counter 10B are included in the control logic section 10. FIG.

In addition to OVD4 and LVD4, other overvoltage detection signals OVD1 to OVD3 and low voltage detection signals LVD1 to LVD3 are also input to the OR circuit 10A. The driver 15 drives the NMOS transistor 16 on and off. The source of NMOS transistor 16 is connected to ground. The drain of NMOS transistor 16 is connected to the PGOOD terminal. A first end of the resistor R2 is externally connected to the PGOOD terminal. The output voltage Vo3 is applied to the second end of the resistor R2. The operation of the configuration related to such a power good function will be described later.

<5. Rising/falling sequence>
Next, start-up sequence control by the PMIC 1 having the configuration shown in FIG. 8 will be described. FIG. 9 is a timing chart showing an example of a start-up sequence.

First, the power supply voltage Vcc starts rising, and then the enable signal En starts rising. When the enable signal En reaches the threshold voltage Vth_EN, the internal voltage generator 3 starts raising the internal voltage Vreg. When the UVLO 7 detects that the internal voltage Vreg has reached the return voltage (release voltage) Vth_UVLOVREG_OFF, it outputs a detection signal UVLO_VREG indicating UVLO release to the control logic unit 10 .

Then, the control logic unit 10 instructs the first DC/DC converter 11 to start the soft start signal ss1 after a predetermined period T1 (for example, 200 μs) has elapsed. Specifically, the soft start section 11B (FIG. 6) in the first DC/DC converter 11 includes a DAC (DA converter), and a soft start signal which is an analog output according to the digital command from the control logic section 10. Output ss1. The soft start section 21B (FIG. 7) similarly includes a DAC.

Until the soft start signal ss1 rises and reaches the reference voltage obtained by dividing the reference voltage Vref1 by the resistors R23 and R24, the soft start signal ss1 is selected as the reference voltage by the error amplifier 21A, and the soft start signal ss1 remains at the reference voltage Vref1. After exceeding the reference voltage based on, the reference voltage is selected by the error amplifier 21A. As a result, as shown in FIG. 9, the output voltage Vo1 rises at the same time as the soft start signal ss1 rises, and becomes a constant voltage in the middle of the rise of the soft start signal ss1.

When the soft start signal ss1 rises and reaches the final voltage ss1_finish, the control logic unit 10 commands the second DC/DC converter 12 to start the soft start signal ss2. The output voltage Vo2 rises at the same time as the soft start signal ss2 rises, and becomes a constant voltage in the middle of the rise of the soft start signal ss2.

When the soft start signal ss2 rises and reaches the final voltage ss2_finish, the control logic unit 10 commands the third DC/DC converter 13 to start the soft start signal ss3. The output voltage Vo3 rises at the same time as the soft start signal ss3 rises, and becomes a constant voltage in the middle of the rise of the soft start signal ss3.

Here, as shown in FIG. 8, the control logic section 10 has a NOR circuit 10C, an AND circuit 10D, and an AND circuit 10E as a configuration related to the start-up sequence. Overvoltage detection signals LVD1 to LVD3 are input to the NOR circuit 10C. The AND circuit 10D includes a soft-start detection signal SS1H indicating whether the soft-start signal ss1 has reached the final voltage ss1_finish, a soft-start detection signal SS2H indicating whether the soft-start signal ss2 has reached the final voltage ss2_finish, and a soft-start detection signal SS2H. A soft start detection signal SS3H indicating whether the signal ss3 has reached the final voltage ss3_finish is input. The output of the NOR circuit 10C and the output of the AND circuit 10D are input to the AND circuit 10E. The AND circuit 10E outputs the enable signal En_LDO to the LDO 20 via the EN_LDO terminal. The output voltage Vo1 is applied to the AND circuit 10E through the VS2 terminal as a power supply voltage.

Returning to FIG. 9, at the timing when the soft start signal ss3 rises and reaches the final voltage ss3_finish, the output voltages Vo1 to Vo3 exceed the low voltage threshold voltages Vth_LVD12 to Vth_LVD32 by the hysteresis comparator, respectively, and the low voltage detection signals LVD1 to Since all of LVD3 are Low and all of the soft start detection signals SSH1 to SSH3 are High, the enable signal En_LDO switches from Low to High.

As a result, the LDO 20 is activated and the output voltage Vo4 starts to rise. Then, when the output voltage Vo4 exceeds the low voltage threshold voltage Vth_LVD42 by the hysteresis comparator, the low voltage detection signal LVD4 becomes Low. At this time, the overvoltage detection signals OVD1 to OVD4 are all Low, and the low voltage detection signals LVD1 to LVD4 are all Low, so the output of the OR circuit 10A switches from High to Low. Then, the counter 10B starts counting, and after a predetermined period T2 (for example, 10 ms) has passed, the driver 15 switches the NMOS transistor 16 from on to off under the control of the counter 10B. As a result, the flag signal PG generated at the PGOOD terminal switches from Low to High.

Thus, in the present embodiment, the first DC/DC converter 11, the second DC/DC converter 12, the third DC/DC converter 13, and the LDO 20 are started in this order by the start-up sequence, and then the flag signal PG by the power good function can be activated.

Next, the falling sequence corresponding to the rising sequence shown in FIG. 9 will be described using the timing chart of FIG.

In FIG. 10, when the enable signal En falls and reaches the threshold voltage Vth_EN, the control logic unit 10 switches the enable signal En_LDO from High to Low and switches the flag signal PG from High to Low. As a result, the LDO 20 is controlled to stop, and the output voltage Vo4 falls.

When the output voltage Vo4 falls and reaches the low voltage threshold voltage Vth_LVD41 by the hysteresis comparator, the low voltage detection signal LVD4 becomes High. Then, the control logic unit 10 commands the third DC/DC converter 13 to fall the soft start signal ss3 and the output voltage Vo3.

When the output voltage Vo3 falls and reaches the low voltage threshold voltage Vth_LVD31 by the hysteresis comparator, the low voltage detection signal LVD3 becomes High. Then, the control logic unit 10 commands the second DC/DC converter 12 to fall the soft start signal ss2 and the output voltage Vo2.

When the output voltage Vo2 falls and reaches the low voltage threshold voltage Vth_LVD21 by the hysteresis comparator, the low voltage detection signal LVD2 becomes High. Then, the control logic unit 10 commands the first DC/DC converter 11 to drop the soft start signal ss1 and the output voltage Vo1, and commands the internal voltage generation unit 3 to drop the internal voltage Vreg.

In this manner, the power supply circuit can be stopped in the order opposite to the start-up sequence shown in FIG.

<6. LDO overvoltage/undervoltage detection mask function>
FIG. 11 shows a case where the external LDO 20 is temporarily not used in the configuration of the PMIC 1 shown in FIG. In this case, as shown in FIG. 11, the FB_LDO terminal is open. Then, the signal input to the inverting input terminal (-) of the comparator 14I becomes Low (ground potential). As a result, the low voltage detection signal LVD4 is kept High. Therefore, the low voltage protection works, the flag signal PG output from the PGOOD terminal does not become High, and the next sequence does not proceed.

Therefore, the PMIC 1 of this embodiment may adopt the configuration shown in FIG. In the configuration shown in FIG. 12, a mask section 10F is added to the control logic section 10. FIG. The mask unit 10F has a function of masking the overvoltage detection signal OVD4 and the low voltage detection signal LVD4.

More specifically, as shown in the table of FIG. 13, the mask unit 10F controls the overvoltage detection signal OVD4 and the low voltage detection signal based on the combination of the levels of the overvoltage detection signal OVD4 before and after the enable signal En_LDO rises. It is determined whether to mask the signal LVD4 or to perform normal processing without masking.

Further, as shown in FIG. 12, when the external LDO 20 is not used, the EN_LDO terminal and the FB_LDO terminal are short-circuited by wiring outside the IC. Also, the output voltage Vo1 is applied to the VS2 terminal.

The start-up sequence in such a configuration of FIG. 12 will be described with reference to the timing chart of FIG. The timing chart of FIG. 14 is the same as that of FIG. 9 described above until the rise of the enable signal En_LDO. However, in FIG. 14, the level (High) after the rise of the enable signal En_LDO becomes the level of the output voltage Vo1 due to the output voltage Vo1 supplied to the AND circuit 10E via the VS2 terminal.

At the same time when the enable signal En_LDO rises, the FB_LDO terminal voltage also rises to the level of the output voltage Vo1 by short-circuiting the EN_LDO terminal and the FB_LDO terminal. As a result, the FB_LDO terminal voltage exceeds the overvoltage threshold voltage Vth_OVD42 by the hysteresis comparator, so the overvoltage detection signal OVD4 switches from Low to High.

Then, in the mask unit 10F, the overvoltage detection signal OVD4 is Low before the enable signal En_LDO rises, and the overvoltage detection signal OVD4 is High after the enable signal En_LDO rises. Thereafter, the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are masked. The masked overvoltage detection signal OVD4 and low voltage detection signal LVD4 are set to Low.

As a result, as shown in FIG. 14, the masked overvoltage detection signal OVD4 (broken line) is set to Low, and at that timing the output of the OR circuit 10A is switched to Low. After T2 has elapsed, the NMOS transistor 16 is turned off, and the flag signal PG rises to High. Thus, with the configuration of FIG. 12, the flag signal PG of the power-good function can be raised to High (active state) even when the LDO 20 is not used.

When using the LDO 20, the LDO 20 is connected in the configuration of the PMIC 1 in FIG. 12 in the same manner as in FIG. That is, the EN_LDO terminal is connected to the enable terminal 20A of the LDO 20, and the output terminal 20C outputting the output voltage Vo4 is applied to the FB_LDO terminal. As a result, in the rising sequence, the level of the overvoltage detection signal OVD4 becomes Low both before and after the rise of the enable signal En_LDO. The low voltage detection signal LVD4 is not masked. Therefore, when the low voltage detection signal LVD4 switches to Low due to the rise of the output voltage Vo4, the flag signal PG rises to High. Also, the protection function by the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 is enabled.

As another form using the LDO 20, the configuration shown in FIG. 15 may be used. That is, the EN_LDO terminal is connected to the enable terminal 20A of the LDO 20 and short-circuited with the FB_LDO terminal. As a result, in the start-up sequence, when the enable signal En_LDO rises, the FB_LDO terminal voltage also rises to the level of the output voltage Vo1, and the overvoltage detection signal OVD4 rises from Low to High. Become. That is, this is an embodiment in which the LDO 20 is used but the overvoltage/undervoltage protection function of the output voltage Vo4 is unnecessary.

Moreover, FIG. 16 shows still another form in the case of using the LDO 20. FIG. In the configuration shown in FIG. 16, the EN_LDO terminal is open, the enable terminal 20A of the LDO 20 is connected to the application terminal of the output voltage Vo1, and the FB_LDO terminal is connected to the output terminal 20C from which the output voltage Vo4 is output. As a result, in the startup sequence, the output voltage Vo1 rises, the LDO 20 is activated, and the output voltage Vo4 rises. Also, since the level of the overvoltage detection signal OVD4 is Low both before and after the rise of the enable signal En_LDO, the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are not masked as shown in FIG. Therefore, the overvoltage/undervoltage protection function of the output voltage Vo4 becomes effective.

<7. Mode switching control>
Mode switching using the MODE0 terminal, the MODE1 terminal, and the MODE2 terminal (FIGS. 1 and 2) will now be described with reference to the table in FIG. FIG. 17 shows setting contents corresponding to mode setting by the MODE0 to MODE2 terminals.

As shown in FIG. 17, eight modes from A mode to H mode can be set according to the combination of signal levels (High or Low) set to the MODE0 to MODE2 terminals. Note that FIG. 1 shows an example in which all of the MODE0 to MODE2 terminals are Low and the A mode is set. As shown in FIG. 17, mode setting is performed according to the type (A to F) of the CMOS sensor 30 (FIG. 3) to be used.

As shown in FIG. 17, the output voltage Vo4 of the LDO 20 differs depending on the type of CMOS sensor 30 used. Here, the dropout voltage, which is the minimum potential difference between the input and output at which stable operation is possible, is specified for the LDO, and the input voltage of the LDO is set to a voltage higher than the output voltage by a voltage equal to or higher than the dropout voltage. is desirable. In FIG. 17, the output voltage Vo1 of the first DC/DC converter 11 is set to a voltage higher by 0.6 V as an example of the predetermined voltage than the output voltage Vo4 which differs depending on the mode setting. This is because the output voltage Vo1 becomes the input voltage of the LDO 20 .

Here, in the configuration of the first DC/DC converter 11 described above (FIG. 6), the resistance voltage division ratio for dividing the output voltage Vo1 fed back into the VO1 terminal by the resistances R11 and R12 can be changed according to the mode setting. be. A change in the resistance voltage division ratio is based on a command from the control logic unit 10 . It should be noted that the resistance voltage division ratio can be changed by a configuration similar to the switching configuration using the switch 14D as shown in FIG. 8, for example. Such a configuration that changes the resistance voltage division ratio in the first DC/DC converter 11 enables switching of the output voltage Vo1 according to the mode setting. As shown in FIG. 6, since a configuration for changing the resistance voltage division ratio is provided inside the IC, it is possible to reduce the number of parts outside the IC and to improve reliability by manufacturing inside the IC. can be done.

Further, as shown in FIG. 17, the output voltage Vo2 of the second DC/DC converter 12 can be switched by mode setting according to the type of the CMOS sensor 30. FIG. In the example shown in FIG. 17, the output voltage Vo2 is set to 1.2V in the A to D modes, and the output voltage Vo2 is set to 1.1V in the E and F modes.

Such switching of the output voltage Vo2 is achieved by mode setting of the resistor voltage division ratio for dividing the output voltage Vo2 fed back to the VO2 terminal by the resistors R21 and R22 in the configuration of the second DC/DC converter 12 shown in FIG. It is realized by a modified configuration.

In the example of FIG. 17, the output voltage Vo3 of the third DC/DC converter 13 is set to the same voltage (eg, 1.8 V) regardless of the mode setting according to the CMOS sensor 30 used. In this case, the third DC/DC converter 13 does not need a configuration for changing the resistance voltage division ratio. However, in the third DC/DC converter 13 (FIG. 7), the output voltage Vo3 may be variable.

Also, as shown in FIG. 17, the order of the output voltages Vo2, Vo3, and Vo4 in the rise sequence and the order of the output voltages Vo2, Vo3, and Vo4 in the fall sequence can be set according to the mode setting according to the CMOS sensor 30 to be used. The fall order is variable. In FIG. 17, as an example, in A, C to F modes, it is set to rise in the order of Vo2→Vo3→Vo4 and to fall in the order of Vo4→Vo3→Vo2, and in B mode, Vo4→Vo3→ It is set to rise in order of Vo2 and fall in order of Vo2→Vo3→Vo4. As a result, an appropriate rise sequence and fall sequence can be set according to the type of CMOS sensor 30 used.

The timing chart of FIG. 9 described above shows the rise in order of Vo2→Vo3→Vo4, and the timing chart of FIG. 10 described above shows the fall in order of Vo4→Vo3→Vo2. The order in the rise/fall sequence is controlled by control logic portion 10 .

Further, as shown in FIG. 17, the protection operation (Protect) of the PMIC 1 is variably set by mode setting according to the CMOS sensor 30 to be used. The protection operation can be switched between self-restart and timer off latch.

In self-recovery, when an abnormality detection state such as overvoltage detection (OVD), low voltage detection (LVD), and overcurrent detection (OCP) is maintained for a predetermined period (for example, 10 ms), the control logic unit 10 performs the first DC/ DC converter 11, second DC/DC converter 12, third DC/DC converter 13, and LDO 20 are all stopped. Then, after a predetermined period of time (for example, 10 ms) has elapsed, the control logic unit 10 activates all of the first DC/DC converter 11, the second DC/DC converter 12, the third DC/DC converter 13, and the LDO 20. If the abnormal state continues, stop and start will be repeated.

On the other hand, in the timer latch, when an abnormality detection state such as overvoltage detection (OVD), low voltage detection (LVD), and overcurrent detection (OCP) is maintained for a predetermined period (for example, 10 ms), the control logic unit 10 outputs the first DC /DC converter 11, second DC/DC converter 12, third DC/DC converter 13, and LDO 20 are all stopped. This stopped state is maintained until reset by the enable signal EN or UVLO.

In the example shown in FIG. 17, self-recovery is set in A to E modes, and timer latch is set in F mode.

<8. Arrangement of External Terminals of IC>
Next, the features of the external terminal arrangement (pin arrangement) of the PMIC 1 will be described. FIG. 18 is a plan view of the PMIC 1 (package product) viewed from above. In addition to the PMIC1, FIG. 18 also shows the peripheral elements of the PMIC1 and the LDO 20. As shown in FIG.

As shown in FIG. 18, 24 external terminals are arranged on the rear side of the PMIC 1 (the back side of the paper surface) (numbers are pin numbers). The PMIC 1 has a rectangular shape when viewed from above, and has a first side S1, a second side S2, a third side S3, and a fourth side S4. The first side S1 and the second side S2 face each other, and the third side S3 and the fourth side S4 face each other.

Along the first side S1, the SW3 terminal, the VS3 terminal, the PGND23 terminal, the VS2 terminal, the SW2 terminal, and the VO2 terminal are arranged in this order from the third side S3 side. Along the second side S2, a PVCC terminal, a VCC terminal, an EN terminal, a GND terminal, a VREG terminal, and a MODE0 terminal are arranged in order from the side of the third side S3. Along the third side S3, the VO3 terminal, the FB_LDO terminal, the VO1 terminal, the BOOT terminal, the SW1 terminal, and the PGND1 terminal are arranged in this order from the first side S1 side. Along the fourth side S4, an EN_LDO terminal, a PGOOD terminal, an SSCG terminal, an RT terminal, a MODE2 terminal, and a MODE1 terminal are arranged in this order from the first side S1 side.

The EN_LDO terminal is arranged at the end of the fourth side S4 on the first side S1 side, and the PVCC terminal and the VCC terminal are arranged at the end of the second side S2 on the third side S3 side. As a result, the EN_LDO terminal, which has a low withstand voltage, can be arranged at a position away from the PVCC terminal and the VCC terminal to which the power supply voltage Vcc is applied.

The EN_LDO terminal is arranged on the fourth side S4, and the FB_LDO terminal is arranged on the third side S3 opposite to the fourth side S4. As a result, when the external LDO 20 is used for the PMIC 1 having the configuration shown in FIG. It is possible to avoid erroneous mask processing.

Also, the MODE0 terminal, the MODE1 terminal, and the MODE2 terminal are arranged adjacent to each other. In FIG. 18, the MODE0 terminal, the MODE1 terminal, and the MODE2 terminal are adjacent across different sides (the second side S2 and the fourth side S4), but they may be adjacent on the same side (for example, the fourth side S4). .

Further, as shown in FIG. 18, power supply terminals (VS2 terminal, VS3 terminal, PVCC terminal, VCC terminal), ground terminals (PGND23 terminal, PGND1 terminal, GND terminal), switching terminals (SW1 terminal, SW2 terminal, SW3 terminal) , feedback voltage terminals (VO1 terminal, VO2 terminal, VO3 terminal), VREG terminal, and BOOT terminal (first terminal group) are arranged on at least one of the first side S1 to the third side S3. (Second terminal group) is arranged on the fourth side S4.

As shown in FIG. 18, the wiring (thick line in FIG. 18) electrically connected to the first terminal group outside the IC needs to have low impedance. Therefore, each element (input capacitor, output capacitor, inductor, bypass capacitor, boot capacitor) connected to the wiring must be arranged near the PMIC 1 in the region surrounding the first side S1 to the third side S3 from the outside. be.

Here, FIG. 19 is a plan view schematically showing a layout example on the substrate 40. FIG. As shown in FIG. 19, input capacitors Cin1 to Cin3, output capacitors Co1 to Co3, inductors L1 to L3, bypass capacitors C1 and C2, and boot capacitor Cb are arranged in a region surrounding first side S1 to third side S3 from the outside. , PMIC1.

However, since the second terminal group is arranged on the fourth side S4 and there is little need to reduce the impedance of wiring electrically connected to the second terminal group outside the IC, elements connected to the wiring (LDO 20, resistor R2, capacitor C3, and resistor R1) need not be arranged in the IC vicinity region R on the fourth side S4 side, as shown in FIG. This eliminates the dead space due to the arrangement of the elements.

<9. Others>
Although various embodiments of the present invention have been described above, the embodiments can be further modified in various ways within the spirit and scope of the present invention.

INDUSTRIAL APPLICABILITY The present invention can be used, for example, in a vehicle power supply IC.

1 PMICs
2 UVLO section 3 internal voltage generation section 4, 5 reference voltage generation section 6 TSD section 7 UVLO section 8 UVLO section 9 oscillator 10 control logic section 11 first DC/DC converter 12 second DC/DC converter 13 third DC/DC converter 14 overvoltage /Low Voltage Detector 15 Driver 16 NMOS Transistor 20 LDO
30 CMOS sensor 40 substrate

Claims (5)

A clock generation circuit included in an IC having a terminal to which an external capacitor can be externally connected,
a first constant current circuit and a second constant current circuit arranged between a power supply voltage and ground and connected at a connection node;
a first input terminal connected to the connection node to which the terminal is connected; a second input terminal to which a first reference voltage and a second reference voltage lower than the first reference voltage are switchably applied; a first comparator for controlling on/off of the first constant current circuit and the second constant current circuit by an output;
a first input to which the terminal is connected; and a second input to which the first reference voltage and a third reference voltage lower than the first reference voltage are switchably applied; a second comparator that outputs a signal;
a first switch that selects either a fourth reference voltage or a terminal voltage generated at the terminal according to the enable signal;
a selection unit that selects the lower one of the voltage selected by the first switch and a fifth reference voltage that is higher than the first reference voltage and lower than the fourth reference voltage;
a VCO (Voltage-controlled oscillator) that generates a clock signal having a frequency corresponding to the voltage selected by the selection unit;
a clock generation circuit. The selection unit
a first PNP transistor having a base to which a voltage selected by the switch is applied and a collector connected to ground;
a second PNP transistor having a base to which the fifth reference voltage is applied and a collector connected to ground;
a third constant current circuit arranged between a supply voltage application terminal and emitters of the first PNP transistor and the second PNP transistor;
2. The clock generation circuit of claim 1, comprising: The VCO is
an NPN transistor having a base connected to each emitter of the first PNP transistor and the second PNP transistor;
a resistor connected between the emitter of the NPN transistor and ground;
a current mirror connected to the collector of the NPN transistor;
a capacitor that can be charged by the output current from the current mirror;
a second switch for discharging the capacitor;
a third comparator having a first input terminal to which the voltage of the capacitor is input and a second input terminal to which a sixth reference voltage is applied, the output of which controls the second switch;
3. The clock generation circuit of claim 2, comprising: a clock generation circuit according to any one of claims 1 to 3;
A power supply IC, comprising: the terminal; A power supply IC having a rectangular shape in a plan view,
including a DC/DC converter;
having a first side, a second side facing the first side, a third side, and a fourth side facing the third side;
A power supply terminal to which a power supply voltage is input, a ground terminal, a switching terminal connected to a node where an upper transistor and a lower transistor included in the DC/DC converter are connected, a feedback voltage terminal to which a feedback voltage is input, an internal A VREG terminal to which a voltage is output and a BOOT terminal to which a boot capacitor for bootstrap can be connected are arranged on at least one of the first side, the second side and the third side,
5. The power supply IC according to claim 4, wherein only terminals other than the terminals are arranged on said fourth side.

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