JP7400518B2 - Manufacturing method of semiconductor device - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

Patent Document 1 discloses a method for manufacturing a semiconductor device. In this manufacturing method, impurities are injected from the upper surface of a semiconductor wafer into a dicing region that is cut by dicing. As a result, a damaged layer (that is, a region having lower hardness than other semiconductor regions) exposed on the upper surface of the semiconductor wafer is formed inside the semiconductor wafer in the dicing region. Thereafter, the semiconductor wafer is divided into a plurality of semiconductor devices by dicing the semiconductor wafer from the upper surface side along the dicing area. In this manufacturing method, dicing is performed along the damaged layer exposed on the upper surface of the semiconductor wafer, so that the dicing blade easily penetrates into the semiconductor wafer, making it possible to suppress the occurrence of chipping.

JP2019-33141A

Although the manufacturing method of Patent Document 1 has the effect of suppressing chipping on the upper surface of the semiconductor wafer, it does not take into account chipping that may occur on the lower surface of the semiconductor wafer. In the manufacturing method of Patent Document 1, in the process of dicing the semiconductor wafer, a large stress is applied to the semiconductor wafer immediately before the semiconductor wafer is cut, and chipping may occur on the lower surface of the semiconductor wafer. This specification provides a technique for suppressing chipping from occurring near the bottom surface of a semiconductor wafer.

A method for manufacturing a semiconductor device disclosed in this specification includes a step of forming a metal layer that covers the lower surface of a semiconductor wafer containing silicon, and irradiating the surface of the metal layer with light so that the semiconductor wafer and the metal The method includes a step of forming a silicide layer at an interface between layers, and a step of dicing the semiconductor wafer from above. In the step of forming the silicide layer, the light is irradiated on the lower surface of the semiconductor wafer so that the temperature inside the dicing region cut by the dicing is higher than the temperature outside the dicing region.

In the manufacturing process of a semiconductor device, a silicide layer is sometimes formed at the interface between the semiconductor wafer and the metal layer in order to reduce the contact resistance between the semiconductor wafer and the metal layer. The silicide layer is formed, for example, by irradiating a metal layer formed on the surface of a semiconductor wafer with light and performing heat treatment. In the above manufacturing method, in the step of forming the silicide layer, light is irradiated onto the lower surface of the semiconductor wafer so that the temperature inside the dicing region is higher than the temperature outside the dicing region. That is, in the dicing region, the temperature near the bottom surface of the semiconductor wafer becomes high, and distortion occurs inside the semiconductor wafer near the bottom surface. Thereafter, the semiconductor wafer is diced from above. In this way, in this manufacturing method, distortion is formed on the lower surface of the semiconductor wafer within the dicing area, so when dicing is performed from the upper surface of the semiconductor wafer, stress is less likely to be applied to the vicinity of the lower surface of the semiconductor wafer, which prevents chipping. is unlikely to occur.

FIG. 3 is a plan view of the semiconductor wafer 12 from the top surface 12a. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 1. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 1. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 1. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 1. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 1. FIG. 7 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 1, viewed from a direction perpendicular to FIG. 6. FIG. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 2. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 2. FIG. 3 is a cross-sectional view of the semiconductor wafer 12 in the manufacturing process of Example 2.

(Example 1)
The manufacturing method of Example 1 will be described with reference to the drawings. In addition, below, only the process which is the characteristic of Example 1 is demonstrated. Therefore, the actual manufacturing method may include one or more steps not included in the following description, as necessary. The same applies to Example 2, which will be described later.

First, a semiconductor wafer 12 shown in FIG. 1 is prepared. The semiconductor wafer 12 is made of SiC (silicon carbide). However, the semiconductor wafer 12 may be made of other semiconductor materials containing silicon. A plurality of semiconductor elements 10 are integrally formed on the semiconductor wafer 12. Each semiconductor element 10 is a power semiconductor element such as a MOSFET or IGBT. Each semiconductor element 10 is regularly arranged vertically and horizontally on a semiconductor wafer 12. A broken line 16 shown in FIG. 1 indicates an area to be diced later (hereinafter referred to as dicing area 16).

Next, as shown in FIG. 2, a metal layer 20 is formed to cover the lower surface 12b of the semiconductor wafer 12. The metal layer 20 is made of, for example, Ni (nickel), Ti (titanium), Mo (molybdenum), or the like.

Next, as shown in FIG. 3, the semiconductor wafer 12 is irradiated with light from the lower surface 12b side to form a silicide layer 22. In this embodiment, the silicide layer 22 is formed by laser annealing. That is, the surface of the metal layer 20 formed on the lower surface 12b of the semiconductor wafer 12 is irradiated with a laser. This causes the metal layer 20 and the semiconductor wafer 12 to react at the interface between the metal layer 20 and the semiconductor wafer 12 . Then, a silicidation reaction progresses at the interface. The entire metal layer 20 is silicided to form a silicide layer 22. Further, this step is performed on the lower surface 12b of the semiconductor wafer 12 so that the temperature inside the dicing region 16 is higher than the temperature outside the dicing region 16. For example, the irradiation energy of the laser that irradiates the surface of the metal layer 20 within the dicing region 16 is set higher than the irradiation energy of the laser that irradiates the surface of the metal layer 20 outside the dicing region 16. For example, the number of times the laser beam is irradiated on the surface of the metal layer 20 within the dicing area 16 (that is, the number of times the laser spot passes) is set to be greater than the number of times that the laser beam is irradiated on the surface of the metal layer 20 outside the dicing area 16. do. The arrow 100 in FIG. 3 indicates the amount of energy of the irradiated light. That is, in this step, the energy applied to the surface of the metal layer 20 within the dicing region 16 is made higher than the energy applied to the surface of the metal layer 20 outside the dicing region 16. In this way, the temperature of the lower surface 12b of the semiconductor wafer 12 in the dicing region 16 is locally raised to a high temperature, and the strained layer facing the lower surface 12b of the semiconductor wafer 12 is formed in the vicinity of the lower surface 12b of the semiconductor wafer 12 in the dicing region 16. Form 24. The strained layer 24 has lower strength than other semiconductor regions. Note that the strained layer 24 may be formed near the lower surface 12b of the semiconductor wafer 12 over the entire area within the dicing region 16, or the strained layer 24 may be formed near the lower surface 12b of the semiconductor wafer 12 in a part of the dicing region 16. You can. Further, the thickness of the strained layer 24 can be adjusted as appropriate by adjusting the laser irradiation energy and the thickness of the metal layer 20.

Next, as shown in FIG. 4, an electrode layer 26 in which Ti, Ni, and Au (gold) are stacked is formed on the surface of the silicide layer 22. The silicide layer 22 and the electrode layer 26 constitute a lower surface electrode 28.

Next, as shown in FIG. 5, the semiconductor wafer 12 is diced from the upper surface 12a side of the semiconductor wafer 12 along the dicing region 16 using the dicing blade 30. In the dicing region 16, a strained layer 24 is formed near the lower surface 12b of the semiconductor wafer 12. Therefore, in this step, when the semiconductor wafer 12 is diced along the dicing region 16, the strained layer 24 is cut off on the lower surface 12b side of the semiconductor wafer 12. Through the above steps, the semiconductor wafer 12 is divided into a plurality of semiconductor devices 2, as shown in FIG.

As shown in FIG. 7, when cutting the semiconductor wafer 12, the thickness of the semiconductor wafer 12 becomes thinner at a portion A near the dicing blade 30. In general, chipping and cracking are likely to occur in the thin portion A due to vibration and shaking. However, in the manufacturing method of this embodiment, the strained layer 24 is formed near the lower surface 12b of the semiconductor wafer 12 before dicing the semiconductor wafer 12. This strained layer 24 has lower strength than other semiconductor regions. Therefore, the dicing blade 30 easily enters the strained layer 24, and it is difficult to apply stress to the portion A near the dicing blade 30. Therefore, chipping and cracking are less likely to occur in the portion A on the lower surface 12b side of the semiconductor wafer 12. That is, according to this manufacturing method, it is possible to suppress chipping and cracking from occurring near the lower surface 12b of the semiconductor wafer 12. Therefore, this manufacturing method can ensure high reliability. Note that since the strained layer 24 is formed within the dicing region 16, it is removed by dicing. Therefore, the strained layer 24 does not remain in the semiconductor device 2 that has been diced into pieces.

(Example 2)
Next, the manufacturing method of Example 2 will be explained. In the manufacturing method of Example 2, after the step shown in FIG. 2 of Example 1, the steps shown in FIG. 8 and subsequent steps are performed.

As shown in FIG. 8, the surface of the metal layer 20 within the dicing area 16 is cut. As a result, grooves 32 are formed on the surface of the metal layer 20. That is, in this step, by forming the grooves 32, the thickness of the metal layer 20 within the dicing area 16 is made thinner than the thickness of the metal layer 20 outside the dicing area 16.

Next, as shown in FIG. 9, light is irradiated from the lower surface 12b side of the semiconductor wafer 12 to form a silicide layer 22. In this example, unlike Example 1, the silicide layer 22 is formed by lamp annealing. That is, as shown by arrow 102, substantially the entire surface of the metal layer 20 formed on the lower surface 12b of the semiconductor wafer 12 is irradiated with light having uniform energy at once. As a result, the entire metal layer 20 is silicided to form a silicide layer 22. In this embodiment, as described above, since the groove 32 is formed in the metal layer 20 within the dicing area 16, the thickness of the metal layer 20 within the dicing area 16 is equal to the thickness of the metal layer 20 outside the dicing area 16. thinner than Therefore, the effective energy applied to the lower surface 12b of the semiconductor wafer 12 within the dicing region 16 is higher than that outside the dicing region 16. Therefore, on the lower surface 12b of the semiconductor wafer 12, the temperature inside the dicing region 16 becomes higher than the temperature outside the dicing region 16. As a result, in the dicing region 16, a strained layer 24 facing the lower surface 12b of the semiconductor wafer 12 is formed in the vicinity of the lower surface 12b of the semiconductor wafer 12, as in the first embodiment. The thickness of the strained layer 24 can be adjusted as appropriate by adjusting the energy of the lamp and the depth of the grooves 32.

Thereafter, as shown in FIG. 10, the same electrode layer 26 as in Example 1 is laminated to form a lower surface electrode 28. In this embodiment, since the groove 32 is formed in the metal layer 20 in the dicing region 16, a depression 34 is formed in the surface of the electrode layer 26 in the dicing region 16. Next, as in Example 1, the semiconductor wafer 12 is diced from the upper surface 12a side of the semiconductor wafer 12 along the dicing region 16 using a dicing blade. Through the above steps, the semiconductor wafer 12 is divided into a plurality of semiconductor devices.

In Example 2, as in Example 1, the strained layer 24 is formed near the lower surface 12b of the semiconductor wafer 12. Therefore, similarly to the first embodiment, stress is hardly applied to the vicinity of the lower surface 12b of the semiconductor wafer 12. Therefore, occurrence of chipping or cracking near the lower surface 12b of the semiconductor wafer 12 can be suppressed. Furthermore, since the strained layer 24, the groove 32, and the depression 34 are formed within the dicing region 16, they are removed by dicing. Therefore, the strained layer 24, the groove 32, and the depression 34 do not remain in the semiconductor device 2 that has been diced.

Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims as filed. Furthermore, the techniques illustrated in this specification or the drawings simultaneously achieve multiple objectives, and achieving one of the objectives has technical utility in itself.

2: Semiconductor device 10: Semiconductor element 12: Semiconductor wafer 12a: Upper surface 12b: Lower surface 16: Dicing region 20: Metal layer 22: Silicide layer 24: Strained layer 26: Electrode layer 28: Lower surface electrode 30: Dicing blade 32: Groove

Claims (1)

A method for manufacturing a semiconductor device, the method comprising:
forming a metal layer covering the bottom surface of the semiconductor wafer containing silicon;
forming a silicide layer at the interface between the semiconductor wafer and the metal layer by irradiating the surface of the metal layer with light;
dicing the semiconductor wafer from above;
Equipped with
In the step of forming the silicide layer, on the lower surface of the semiconductor wafer, the temperature inside the dicing region and the dicing region cut by the dicing is higher than the temperature outside the dicing region. By irradiating the light outside the area , the silicide layer is formed inside the dicing area and outside the dicing area, and the silicide layer outside the dicing area is formed in a range facing the lower surface of the semiconductor wafer inside the dicing area. forming a strained layer with lower strength than the semiconductor region ,
Production method.

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