JP7415801B2 - multilayer ceramic capacitor - Google Patents

Description

The present invention relates to a multilayer ceramic capacitor.

Conventionally, a multilayer ceramic capacitor is known that has a multilayer body including a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and an external electrode including a base electrode layer. Such laminated ceramic capacitors are subjected to thermal stress during mounting, etc., and there is a risk that cracks may occur in the laminated body. Patent Document 1 discloses a multilayer ceramic capacitor in which a base electrode layer is formed so that the ridgeline portion of the multilayer body is exposed in order to alleviate thermal stress.

Japanese Patent Application Publication No. 2008-300769

However, in the case of the configuration of Patent Document 1, moisture from the outside may infiltrate from the exposed portion of the laminate near the ridgeline, causing insulation deterioration of the laminate. For example, during plating, there is a risk that moisture such as a plating solution may infiltrate through minute gaps existing between the laminate and the base electrode layer, causing insulation deterioration of the laminate.

An object of the present invention is to provide a multilayer ceramic capacitor that can reduce thermal stress, suppress the occurrence of cracks in the laminate, and suppress insulation deterioration of the laminate due to moisture infiltration from the outside. be.

A multilayer ceramic capacitor according to the present invention includes a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and has a first side surface and a second side surface facing the stacking direction, and a second side surface orthogonal to the stacking direction. a laminate including a third side surface and a fourth side surface facing each other in the width direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the lamination direction and the width direction; A multilayer ceramic capacitor has a first external electrode disposed on one end surface side, and a second external electrode disposed on the second end surface side, wherein the plurality of internal electrode layers It has a plurality of first internal electrode layers drawn out to the first end surface and a plurality of second internal electrode layers drawn out to the second end surface, and the first external electrode is formed on a first base layer. The second external electrode has an electrode layer and a first plating layer disposed on the first base electrode layer, and the second external electrode has a second base electrode layer and a first plating layer disposed on the first base electrode layer. a second plating layer disposed on the first end surface, a first internal electrode layer located closest to the first side surface among the plurality of first internal electrode layers on the first end surface; A region sandwiched between the first internal electrode layer located closest to the second side surface among the first internal electrode layers is defined as a first region, and the plurality of second a second internal electrode layer located closest to the first side surface among the internal electrode layers; and a second internal electrode layer located closest to the second side surface among the plurality of second internal electrode layers; When the sandwiched region is a second region, a first glass layer is disposed on the first end surface so as to surround at least the first region, and a first glass layer is arranged on the second end surface so as to surround at least the first region. A second glass layer is disposed so as to surround the region No. 2, and the first base electrode layer is arranged to surround the first internal electrode layer and the first glass layer exposed on the first end surface. The first end-side base electrode layer covering at least a portion of the side surface and the first end-side base electrode layer are separated by a first dividing region, and at least one side surface of the four side surfaces is separated by a first dividing region. a first side-side base electrode layer that covers a part of the first end face, and the second base electrode layer includes a second internal electrode layer exposed on the second end face. and a second end-side base electrode layer that covers at least a portion of the second glass layer and the second end-side base electrode layer are separated by a second dividing region, and the four side faces a second side-side base electrode layer covering a portion of at least one side surface on the second end surface side.

According to the present invention, it is possible to provide a multilayer ceramic capacitor that can reduce thermal stress, suppress the occurrence of cracks in the multilayer structure, and suppress insulation deterioration of the multilayer structure due to intrusion of moisture from the outside. can.

FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to a first embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II. 3 is a sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2. FIG. 3 is a sectional view taken along the line IV-IV of the multilayer ceramic capacitor shown in FIG. 2. FIG. FIG. 3 is a hypothetical view of the multilayer ceramic capacitor shown in FIG. 2 taken along the line VA-VA in a case where external electrodes are excluded from the multilayer ceramic capacitor. FIG. 3 is a hypothetical view taken along the line VB-VB of the multilayer ceramic capacitor shown in FIG. 2 when external electrodes are excluded from the multilayer ceramic capacitor. FIG. 7 is an external perspective view of a multilayer ceramic capacitor according to a second embodiment. 7 is a sectional view taken along line VII-VII of the multilayer ceramic capacitor shown in FIG. 6. FIG. 8 is a sectional view taken along line VIII-VIII of the multilayer ceramic capacitor shown in FIG. 7. FIG. 8 is a hypothetical view taken along the line IXA-IXA of the multilayer ceramic capacitor shown in FIG. 7 when external electrodes are excluded from the multilayer ceramic capacitor. FIG. 8 is a hypothetical view taken along the line IXB-IXB of the multilayer ceramic capacitor shown in FIG. 7 when external electrodes are excluded from the multilayer ceramic capacitor. FIG. FIG. 7 is a sectional view of a multilayer ceramic capacitor according to a third embodiment, and corresponds to FIG. 7 of the second embodiment. 11 is a sectional view taken along the line XI-XI of the multilayer ceramic capacitor shown in FIG. 10. FIG. 11 is a sectional view taken along line XII-XII of the multilayer ceramic capacitor shown in FIG. 10. FIG. FIG. 7 is an external perspective view showing a multilayer ceramic capacitor according to a third embodiment before forming a first plating layer and a second plating layer. FIG. 7 is an external perspective view showing a modification of the multilayer ceramic capacitor of the third embodiment before forming a first plating layer and a second plating layer. FIG. 2 is a diagram showing a multilayer ceramic capacitor with a double-layer structure. FIG. 3 is a diagram showing a multilayer ceramic capacitor with a triple structure. FIG. 3 is a diagram showing a multilayer ceramic capacitor with a quadruple structure.

<First embodiment>
Hereinafter, a multilayer ceramic capacitor 1 according to a first embodiment of the present invention will be described. FIG. 1 is an external perspective view of a multilayer ceramic capacitor 1 according to this embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 1 taken along line II-II. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 2 taken along line III-III. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 2 taken along the line IV-IV.

Multilayer ceramic capacitor 1 includes a multilayer body 10 and an external electrode 40.

An XYZ orthogonal coordinate system is shown in FIGS. 1 to 4. The length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

As shown in FIGS. 1 to 4, the laminate 10 has a first side surface TS1 and a second side surface TS2 facing the stacking direction T, and a third side surface WS1 facing the width direction W perpendicular to the stacking direction T. and a fourth side surface WS2, and a first end surface LS1 and a second end surface LS2 facing in the length direction L perpendicular to the stacking direction T and the width direction W.

As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. Note that the dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. It is preferable that the corner portions and ridgeline portions E1, E2, and E3 of the laminate 10 are rounded. The corner portion is a portion where three sides of the laminate intersect, and the ridgeline portions E2, E2, and E3 are portions where two sides of the laminate intersect. Incidentally, unevenness may be formed on a part or all of the surface constituting the laminate 10.

As shown in FIGS. 2 and 3, the laminate 10 includes an inner layer 11, a first side outer layer 12 and a second side outer layer that are arranged to sandwich the inner layer 11 in the stacking direction T. 13.

The inner layer section 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. In the stacking direction T, the inner layer portion 11 includes an internal electrode layer 30 located closest to the first side surface TS1 to an internal electrode layer 30 located closest to the second side surface TS2. In the inner layer portion 11, a plurality of internal electrode layers 30 are arranged facing each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates capacitance and essentially functions as a capacitor.

The plurality of dielectric layers 20 are made of dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ or CaZrO ₃ . Further, the dielectric material may be one in which subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added to these main components.

The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of dielectric layers 20 to be laminated is preferably 15 or more and 700 or less. Note that the number of dielectric layers 20 is the total number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first side outer layer portion 12 and the second side outer layer portion 13.

The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are buried so as to be arranged alternately in the stacking direction T of the stacked body 10.

The first internal electrode layer 31 includes a first opposing portion 31A that faces the second internal electrode layer 32, and a first drawn-out portion 31B that is drawn out from the first opposing portion 31A to the first end surface LS1. have. The first drawer portion 31B is exposed at the first end surface LS1. As shown in FIGS. 2 and 4, in this embodiment, the first drawer portion 31B slightly protrudes from the first end surface LS1.

The second internal electrode layer 32 includes a second opposing portion 32A that faces the first internal electrode layer 31, and a second drawn-out portion 32B that is drawn out from the second opposing portion 32A to the second end surface LS2. have. The second drawer portion 32B is exposed at the second end surface LS2. As shown in FIG. 2, in this embodiment, the second drawer portion 32B slightly protrudes from the second end surface LS2.

In this embodiment, a capacitance is formed by the first opposing portion 31A and the second opposing portion 32A facing each other with the dielectric layer 20 in between, and the characteristics of a capacitor are exhibited.

The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the rectangular corner portions may be rounded, or the rectangular corner portions may be formed obliquely. The shapes of the first drawer part 31B and the second drawer part 32B are not particularly limited, but are preferably rectangular. However, the rectangular corner portions may be rounded, or the rectangular corner portions may be formed obliquely.

The dimension in the width direction W of the first facing portion 31A and the dimension in the width direction W of the first drawer portion 31B may be formed to be the same dimension, or one of the dimensions may be formed smaller. . The dimension in the width direction W of the second facing portion 32A and the dimension in the width direction W of the second drawer portion 32B may be the same, or one of the dimensions may be formed narrower. .

The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. be done. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag--Pd alloy.

The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of first internal electrode layers 31 and second internal electrode layers 32 is preferably 15 or more and 200 or less.

The first side surface side outer layer portion 12 is located on the first side surface TS1 side of the stacked body 10. The first side surface side outer layer portion 12 is an aggregate of a plurality of dielectric layers 20 located between the first side surface TS1 and the internal electrode layer 30 closest to the first side surface TS1. The dielectric layer 20 used in the first side outer layer section 12 may be the same as the dielectric layer 20 used in the inner layer section 11.

The second side surface side outer layer portion 13 is located on the second side surface TS2 side of the stacked body 10. The second side surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second side surface TS2 and the internal electrode layer 30 closest to the second side surface TS2. The dielectric layer 20 used in the second side outer layer section 13 may be the same as the dielectric layer 20 used in the inner layer section 11.

Note that the laminate 10 has a counter electrode section 11E. The opposing electrode portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The counter electrode section 11E is configured as a part of the inner layer section 11. FIG. 4 shows the range in the width direction W and length direction L of the counter electrode portion 11E. Note that the counter electrode portion 11E is also referred to as a capacitor effective portion.

Note that the laminate 10 has a third side surface side outer layer portion WG1 and a fourth side surface side outer layer portion WG2. The third side surface side outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the third side surface WS1. The fourth side surface side outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the fourth side surface WS2. 3 and 4 show the range in the width direction W of the third side-side outer layer portion WG1 and the fourth side-side outer layer portion WG2. Note that the third side surface side outer layer portion WG1 and the fourth side surface side outer layer portion WG2 are also referred to as a W gap or a side gap.

Note that the laminate 10 has an end surface side outer layer portion LG. The end surface side outer layer portion LG has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. 2 and 4 show the range in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. Note that the end surface side outer layer portion LG is also referred to as an L gap or an end gap.

The external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side.

The first external electrode 40A is connected to the first internal electrode layer 31 and arranged on the first end surface LS1. Further, the first external electrode 40A is connected to the first side of at least one of the four side surfaces, that is, the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2. It is also arranged at a portion on the end face LS1 side. In this embodiment, the first external electrode 40A is arranged on all four side surfaces: the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2.

The second external electrode 40B is connected to the second internal electrode layer 32 and arranged on the second end surface LS2. Further, the second external electrode 40B is connected to the second side of at least one of the four side surfaces, that is, the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2. It is also arranged at a portion on the end face LS2 side. In this embodiment, the second external electrode 40B is arranged on all four side surfaces: the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2.

As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other with the dielectric layer 20 in between. This creates a capacitance. Therefore, capacitor characteristics are developed between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

The first external electrode 40A includes a first base electrode layer 50A and a first plating layer 70A disposed on the first base electrode layer 50A.

The second external electrode 40B includes a second base electrode layer 50B and a second plating layer 70B disposed on the second base electrode layer 50B.

Note that the basic configuration of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. Further, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the WT cross section at the center of the multilayer ceramic capacitor 1 in the length direction L. Therefore, if it is not necessary to specifically explain the first external electrode 40A and the second external electrode 40B, they may be collectively referred to as the external electrode 40.

The first base electrode layer 50A is a first side base electrode layer that is separated from a first end face base electrode layer 51A and a first end face base electrode layer 51A by a first dividing region 90A. 52A. The first end surface side base electrode layer 51A is connected to the first internal electrode layer 31 and arranged on the first end surface LS1. The first end surface side base electrode layer 51A covers all of the first internal electrode layer 31 exposed on the first end surface LS1. The first divided region 90A is provided along the four ridgeline portions E1 located between the first end surface LS1 and each side surface. In this embodiment, the four ridgeline portions E1 of the laminate 10 located in the first divided region 90A are exposed on the outer surface. The first side surface side base electrode layer 52A is formed on at least one of the four side surfaces, that is, the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2. It covers a part of the end face LS1 side of 1. In the present embodiment, the first side surface side base electrode layer 52A is arranged on all four side surfaces: the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2. and is arranged so as to cover four ridgeline portions E3 located between adjacent side surfaces.

The second base electrode layer 50B is a second side base electrode layer that is separated from the second end face base electrode layer 51B and the second end face base electrode layer 51B by a second dividing region 90B. 52B. The second end surface side base electrode layer 51B is connected to the second internal electrode layer 32 and arranged on the second end surface LS2. The second end surface side base electrode layer 51B covers all of the second internal electrode layer 32 exposed on the second end surface LS2. The second divided region 90B is provided along the four ridgeline portions E2 located between the second end surface LS2 and each side surface. In this embodiment, the four ridgeline portions E2 of the laminate 10 located in the second divided region 90B are exposed on the outer surface. The second side surface side base electrode layer 52B is formed on at least one of the four side surfaces, that is, the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2. It covers a part of the end face LS2 side of 2. In the present embodiment, the second side surface base electrode layer 52B is arranged on all four side surfaces: the first side surface TS1, the second side surface TS2, the third side surface WS1, and the fourth side surface WS2. and is arranged so as to cover four ridgeline portions E3 located between adjacent side surfaces.

It is preferable that the first divided region 90A and the second divided region 90B have a predetermined size or more. For example, the length of the first divided region 90A and the second divided region 90B on the first side surface TS1 side in the LT cross-sectional view shown in FIG. 2 is the thickness of the first side surface side outer layer portion 12 in the stacking direction T. It is preferable that it is 0.001 times or more. Further, the length of the first divided region 90A and the second divided region 90B on the second side surface TS2 side in the LT cross-sectional view is the thickness of the second side surface side outer layer portion 13 of the laminate 10 in the lamination direction T. It is preferable that it is 0.001 times or more. Further, the length of the first divided region 90A and the second divided region 90B on the third side surface WS1 side in the LW cross-sectional view shown in FIG. 4 is the thickness of the third side surface side outer layer portion WG1 in the width direction W. It is preferable that it is 0.001 times or more. In addition, the length of the first divided region 90A and the second divided region 90B on the fourth side surface WS2 side in the LW cross-sectional view is 0 of the thickness in the width direction W of the fourth side surface side outer layer portion WG2 of the laminate 10. It is preferable that it is .001 times or more. Thereby, generation of cracks in the laminate 10 can be effectively suppressed.

Note that the lengths of the first divided region 90A and the second divided region 90B are measured by the following method. First, the multilayer ceramic capacitor 1 is polished in the width direction W so that the LT cross section at the center position in the width direction W of the multilayer ceramic capacitor 1 is exposed. Alternatively, the multilayer ceramic capacitor 1 is polished in the stacking direction T so that the LW cross section at the center position in the stacking direction T of the multilayer ceramic capacitor 1 is exposed. Thereafter, cross-sectional observation is performed using a scanning electron microscope (SEM), and the lengths of the first divided region 90A and the second divided region 90B are measured. For example, the length of the first divided region 90A on the first side surface TS1 side in the LT cross-sectional view shown in FIG. 2 is the length indicated by the broken line indicated by the reference numeral 90A in FIG. The distance along the outer surface of the laminate 10 from the point where the first end surface side base electrode layer 51A is interrupted at to the point where the first side surface side base electrode layer 52A is interrupted at the first side surface TS1. It is. The lengths of the first divided region 90A and the second divided region 90B at other positions are also measured by the same method.

The first base electrode layer 50A and the second base electrode layer 50B are baked layers in this embodiment. The baking layer contains a glass component and metal. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The metal of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, and the like. The baked layer is obtained by applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be obtained by simultaneously firing a multilayer chip having an internal electrode layer and a dielectric layer and a conductive paste applied to the multilayer chip, or by baking a multilayer chip having an internal electrode layer and a dielectric layer to create a multilayer product. After obtaining the laminate, a conductive paste may be applied to the laminate and baked. Note that when the multilayer chip having the internal electrode layer 30 and the dielectric layer 20 and the conductive paste applied to the multilayer chip are simultaneously fired, the baked layer may contain a dielectric material added instead of a glass component. It is preferable to form by baking. The baking layer may have multiple layers.

The thickness in the length direction L of the first end surface side base electrode layer 51A located on the first end surface LS1 is, for example, The thickness is preferably about 3 μm or more and 160 μm or less.

The thickness in the length direction L of the second end surface side base electrode layer 51B located on the second end surface LS2 is, for example, The thickness is preferably about 3 μm or more and 160 μm or less.

When the first side surface base electrode layer 52A is also provided on a part of the first side surface TS1 and/or a part of the second side surface TS2, the first side surface base electrode layer provided on this part The thickness of the electrode layer 52A in the stacking direction T is preferably, for example, approximately 3 μm or more and 40 μm or less at the central portion in the length direction L and width direction W of the first side surface base electrode layer 52A provided in this portion. .

When the first side surface side base electrode layer 52A is also provided on a part of the third side surface WS1 and/or a part of the fourth side surface WS2, the first side surface side base electrode layer provided on this part The thickness of the electrode layer 52A in the width direction W is preferably, for example, about 3 μm or more and 40 μm or less in the center portion of the first side-side base electrode layer 52A provided in this portion in the length direction L and the stacking direction T. .

When the second side surface base electrode layer 52B is also provided on a part of the first side surface TS1 and/or a part of the second side surface TS2, the second side surface side base electrode layer provided on this part The thickness of the electrode layer 52B in the stacking direction T is preferably, for example, about 3 μm or more and 40 μm or less at the central portion in the length direction L and width direction W of the second side-side base electrode layer 52B provided in this portion. .

When the second side surface base electrode layer 52B is also provided on a part of the third side surface WS1 and/or a part of the fourth side surface WS2, the second side surface side base electrode layer provided on this part The thickness of the electrode layer 52B in the width direction W is preferably, for example, about 3 μm or more and 40 μm or less at the center of the second side-side base electrode layer 52B provided in this portion in the length direction L and the stacking direction T. .

Note that the base electrode layer 50 is not limited to a baked layer, and may be a thin film layer. The thin film layer is formed by a thin film forming method such as a sputtering method or a vapor deposition method, and is a layer having a thickness of 1 μm or less on which metal particles are deposited.

The first plating layer 70A is arranged to cover the first base electrode layer 50A. More specifically, the first plating layer 70A includes a first end surface side plating layer 71A and a first side surface side plating layer 72A. The first end surface side plating layer 71A is arranged to cover the first end surface side base electrode layer 51A. The first side plating layer 72A is arranged to cover the first side surface base electrode layer 52A. In this embodiment, plating is not provided on the four ridgeline portions E1 of the stacked body 10 located in the first divided region 90A. Therefore, the four ridgeline portions E1 of the laminate 10 are exposed on the outer surface. Note that there is no location where the first plating layer 70A and the internal electrode layer 30 are in direct contact.

The second plating layer 70B is arranged to cover the second base electrode layer 50B. More specifically, the second plating layer 70B includes a second end surface side plating layer 71B and a second side surface side plating layer 72B. The second end surface side plating layer 71B is arranged to cover the second end surface side base electrode layer 51B. The second side plating layer 72B is arranged to cover the second side surface base electrode layer 52B. In this embodiment, no plating is provided on the four ridgeline portions E2 of the laminate 10 located in the second divided region 90B. Therefore, the four ridgeline portions E2 of the laminate 10 are exposed on the outer surface. Note that there is no location where the second plating layer 70B and the internal electrode layer 30 are in direct contact.

The first plating layer 70A and the second plating layer 70B may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, and the like. The first plating layer 70A and the second plating layer 70B may each be formed of multiple layers.

The first plating layer 70A and the second plating layer 70B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In that case, the Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves solder wettability when mounting the multilayer ceramic capacitor 1. This facilitates mounting of the multilayer ceramic capacitor 1. When each of the first plating layer 70A and the second plating layer 70B has a two-layer structure of a Ni plating layer and a Sn plating layer, the thickness of each of the Ni plating layer and the Sn plating layer is 1 μm or more and 15 μm or less. It is preferable.

Note that the first external electrode 40A and the second external electrode 40B of this embodiment may have a conductive resin layer containing, for example, conductive particles and a thermosetting resin. Such a conductive resin layer is disposed between the first base electrode layer 50A and the first plating layer 70A in the first external electrode 40A, and is disposed between the second base electrode layer 50A and the first plating layer 70A in the second external electrode 40B. It is preferable to arrange it between the electrode layer 50B and the second plating layer 70B. A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to physical impact or shock due to thermal cycles, the conductive resin layer functions as a buffer layer, suppressing the occurrence of cracks in the multilayer ceramic capacitor 1. .

Next, the first glass layer 80A and the second glass layer 80B will be explained. The multilayer ceramic capacitor 1 of this embodiment has a first base electrode layer 50A and a second base electrode layer 50B by arranging the first glass layer 80A and the second glass layer 80B at predetermined positions. This prevents moisture from plating solution or the like from penetrating into the internal electrode layer 30 through the minute gap existing between the stacked body 10 and the internal electrode layer 30 .

FIG. 5A is a virtual view taken along the line VA-VA of the multilayer ceramic capacitor 1 shown in FIG. 2 when the external electrode 40 is excluded from the multilayer ceramic capacitor 1. In this embodiment, as the plurality of first internal electrode layers 31, first internal electrode layers 311, 312, 313, 314, and 315 are arranged in order from the first side surface TS1 side. The ends of the plurality of first internal electrode layers 31 are arranged so as to be exposed to the first end surface LS1 of the stacked body 10. Here, as shown in FIG. 5A, among the plurality of first internal electrode layers 31 on the first end surface LS1, the first internal electrode layer 311 located closest to the first side surface TS1 and the plurality of first internal electrode layers 311 located closest to the first side surface TS1, The region sandwiched between the first internal electrode layer 315 and the first internal electrode layer 315 located closest to the second side surface TS2 among the first internal electrode layers 31 is referred to as a first region LS1E. As shown in FIG. 5A, the dimension in the width direction W of the first region LS1E is the same as the dimension in the width direction W of the counter electrode portion 11E. The dimension of the first region LS1E in the stacking direction T is smaller than the dimension of the counter electrode section 11E in the stacking direction T, that is, the dimension of the inner layer section 11 in the stacking direction T, as shown by 11F in FIG. 5A. The first region LS1E has a rectangular shape.

FIG. 5B is a virtual view along the line VB-VB of the multilayer ceramic capacitor 1 shown in FIG. 2 when the external electrode 40 is excluded from the multilayer ceramic capacitor 1. In this embodiment, as the plurality of second internal electrode layers 32, second internal electrode layers 321, 322, 323, 324, and 325 are arranged in order from the second side surface TS2 side. The ends of the plurality of second internal electrode layers 32 are arranged so as to be exposed to the second end surface LS2 of the stacked body 10. Here, as shown in FIG. 5B, the second internal electrode layer 321 located closest to the first side surface TS1 among the plurality of second internal electrode layers 32 on the second end surface LS2, and the second internal electrode layer 321 located closest to the first side surface TS1, Of the two internal electrode layers 32, a region sandwiched between the second internal electrode layer 325 and the second internal electrode layer 325 located closest to the second side surface TS2 is referred to as a second region LS2E. As shown in FIG. 5B, the dimension in the width direction W of the second region LS2E is the same as the dimension in the width direction W of the counter electrode portion 11E. The dimension in the stacking direction T of the second region LS2E is smaller than the dimension in the stacking direction T of the counter electrode part 11E, that is, the dimension in the stacking direction T of the inner layer part 11, as shown by 11G in FIG. 5B. The second region LS2E has a rectangular shape.

As shown in FIG. 5A, the first glass layer 80A is arranged on the first end surface LS1 so as to surround the first region LS1E. In this embodiment, the first glass layer 80A has a frame shape surrounding the first region LS1E. The thickness of the first glass layer 80A located on the first end surface LS1 in the length direction L is preferably 0.1 μm or more. For example, the thickness of the inner peripheral side portion of the first glass layer 80A is 0.1 μm or more and 1 μm or less. For example, it is preferable that the thickness of the inner circumferential portion of the frame-shaped first glass layer 80A is 0.1 μm or more. As shown in FIGS. 2 and 4, the amount of protrusion of the first internal electrode layer 31 protruding from the first end surface LS1 is approximately equal to the thickness of the inner circumferential portion of the first glass layer 80A. You can. In this embodiment, the first end surface side base electrode layer 51A covers all of the first internal electrode layer 31 and all of the first glass layer 80A exposed on the first end surface LS1.

As shown in FIG. 5B, the second glass layer 80B is arranged to surround the second region LS2E on the second end surface LS2. In this embodiment, the second glass layer 80B has a frame shape surrounding the second region LS2E. The thickness of the second glass layer 80B located on the second end surface LS2 in the length direction L is preferably 0.1 μm or more. For example, the thickness of the inner circumferential portion of the second glass layer 80B is 0.1 μm or more and 1 μm or less. For example, it is preferable that the thickness of the inner peripheral side portion of the frame-shaped second glass layer 80B is 0.1 μm or more. As shown in FIG. 2, the amount of protrusion of the second internal electrode layer 32 protruding from the second end surface LS2 may be approximately the same as the thickness of the inner circumferential portion of the second glass layer 80B. . In this embodiment, the second end surface side base electrode layer 51B covers all of the second internal electrode layer 32 and all of the second glass layer 80B exposed on the second end surface LS2. In this embodiment, the shape of the second glass layer 80B is approximately the same as the shape of the first glass layer 80A, but is shifted by one pitch of the stacking pitch of the internal electrode layer 30 in the stacking direction T. It is placed in the same position.

The dielectric layer 20 of the laminate 10 and the glass component have high adhesion. Therefore, gaps are less likely to form at the interface between the dielectric layer 20 and the glass component than at the interface between the dielectric layer 20 and the metal component. Therefore, the first glass layer 80A is arranged to surround at least the first region LS1E, and the second glass layer 80B is arranged to surround at least the second region LS2E. This prevents moisture such as a plating solution from penetrating into the internal electrode layer 30 through minute gaps existing between the first base electrode layer 50A and the second base electrode layer 50B and the laminate 10. I can do it. Furthermore, as in the present embodiment, by setting the thickness of the first glass layer 80A and the second glass layer 80B to 0.1 μm or more, insulation deterioration of the laminate 10 due to intrusion of moisture from the outside is suppressed. It is possible to enhance the effect of

Note that the thicknesses of the first glass layer 80A and the second glass layer 80B are measured by the following method. First, the multilayer ceramic capacitor 1 is polished in the width direction W so that the LT cross section at the center position in the width direction W of the multilayer ceramic capacitor 1 is exposed. Thereafter, cross-sectional observation is performed using a scanning electron microscope (SEM), and the thicknesses of the first glass layer 80A and the second glass layer 80B are measured. The thickness of the first glass layer 80A is the distance in the length direction L from the first end surface LS1 of the laminate 10 to the interface between the first glass layer 80A and the first end surface side base electrode layer 51A. . In the cross section, the longest distance is defined as the thickness of the first glass layer 80A. The thickness of the second glass layer 80B is the distance in the length direction L from the second end surface LS2 of the laminate 10 to the interface between the second glass layer 80B and the second end surface base electrode layer 51B. . In the cross section, the longest distance is defined as the thickness of the second glass layer 80B.

The first glass layer 80A and the second glass layer 80B preferably contain silicon oxide as a main component. The method of forming the first glass layer 80A and the second glass layer 80B is not particularly limited. For example, the first glass layer 80A and the second glass layer 80B may be formed by applying or dipping a glass coating solution and then applying heat treatment. Alternatively, the first glass layer 80A and the second glass layer 80B may be formed by a sputtering method.

Note that, when the dimension in the length direction L of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrode 40 is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. Moreover, when the dimension of the multilayer ceramic capacitor 1 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. Further, the dimension of the multilayer ceramic capacitor 1 in the width direction W is defined as the W dimension. The W dimension is preferably 0.1 mm or more and 10 mm or less.

Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be explained.

A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and internal electrodes contains a binder and a solvent. The binder and solvent may be known ones.

A conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing. As a result, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

By laminating a predetermined number of dielectric sheets on which the internal electrode layer pattern is not printed, a portion that will become the first side surface side outer layer portion 12 on the first side surface TS1 side is formed. A dielectric sheet with a pattern of the first internal electrode layer 31 printed thereon and a dielectric sheet with a pattern of the second internal electrode layer 32 printed thereon are sequentially laminated to form the inner layer section 11. parts are formed. A predetermined number of dielectric sheets on which the internal electrode layer pattern is not printed are laminated on the portion that will become the inner layer portion 11, thereby forming the second side surface side outer layer portion 13 on the second side surface TS2 side. parts are formed. In this way, a laminated sheet is produced.

A laminated block is produced by pressing the laminated sheet in the lamination direction T by means such as a hydrostatic press.

A laminated chip is cut out by cutting the laminated block to a predetermined size. At this time, the corners and ridges of the laminated chip may be rounded by barrel polishing or the like.

The stacked body 10 is produced by firing the stacked chips. The firing temperature is preferably 900° C. or higher and 1400° C. or lower, although it depends on the materials of the dielectric layer 20 stacked chip and the internal electrode layer 30.

Note that in this embodiment, the first extended portion 31B of the first internal electrode layer 31 protrudes from the first end surface LS1. Further, the second drawn-out portion 32B of the second internal electrode layer 32 protrudes from the second end surface LS2. This protrusion may be formed by selectively etching the first end surface LS1 and the second end surface LS2 of the stacked chip or the stacked body 10. Alternatively, a metal that will be deposited on the internal electrode layer 30 during the baking process may be added to the conductive paste that will become the first base electrode layer 50A and the second base electrode layer 50B, which will be described later. In this case, when baking the conductive paste, the volume of the internal electrode layer 30 increases, and a protruding portion of the internal electrode layer 30 is formed.

A first glass layer 80A and a second glass layer 80B are formed in the laminate 10. In this embodiment, the first glass layer 80A and the second glass layer 80B are formed by applying a glass coating solution and then applying heat treatment. As the glass coating solution, a glass coating solution containing perhydropolysilazane as a main component may be used. It is preferable to perform a masking process in advance on portions where the first glass layer 80A and the second glass layer 80B are not provided. Thereby, a glass layer can be formed at a desired position. Note that the first glass layer 80A and the second glass layer 80B may be formed thicker and then adjusted to a desired thickness by polishing or the like. Thereby, the amount of protrusion of the first internal electrode layer 31 protruding from the first end surface LS1 may be made substantially equal to the thickness of the first glass layer 80A. Further, the amount of protrusion of the second internal electrode layer 32 protruding from the second end surface LS2 may be approximately the same as the thickness of the second glass layer 80B.

A conductive paste that becomes the first base electrode layer 50A and the second base electrode layer 50B is applied to the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by, for example, dipping. The conductive paste is applied to cover the first end surface LS1 of the laminate 10 and to cover the portions of the four side surfaces TS1, TS2, WS1, and WS2 on the first end surface LS1 side. Further, the conductive paste is applied so as to cover the second end surface LS2 of the laminate 10 and to cover the portions of the four side surfaces TS1, TS2, WS1, and WS2 on the second end surface LS2 side.

At this time, a masking process may be performed on the first divided region 90A and the second divided region 90B so that the conductive paste is not applied to the four ridgeline portions E1 and the four ridgeline portions E2. Alternatively, the conductive paste is also applied to the four ridgeline parts E1 and the four ridgeline parts E2, and after the conductive paste is dried, it is applied to the four ridgeline parts E1 and the four ridgeline parts E2 by barrel polishing. The conductive paste may be removed. Thereby, the four ridgeline parts E1 and the four ridgeline parts E2 of the laminate 10 are exposed, and the first divided region 90A and the second divided region 90B are formed. The sizes of the first divided region 90A and the second divided region 90B can be adjusted by adjusting barrel polishing conditions such as the size of masking or the processing time of barrel polishing treatment. Note that when barrel polishing is performed, the four ridgeline portions E1 and the four ridgeline portions E2 of the laminate 10 can be rounded at the same time as the conductive paste is removed. Further, by this barrel polishing process, the corners of the laminate 10 can also be exposed and rounded.

Thereafter, a baking process is performed to form a first base electrode layer 50A and a second base electrode layer 50B. The temperature of the baking treatment at this time is preferably 700°C or more and 900°C or less.

After that, a first plating layer 70A is formed on the surface of the first base electrode layer 50A. Further, a second plating layer 70B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. The Ni plating layer and the Sn plating layer are sequentially formed by, for example, a barrel plating method.

In this embodiment, the conditions of the plating process are adjusted so that plating is formed only on the surfaces of the first base electrode layer 50A and the second base electrode layer 50B. That is, the plating process is performed so that no plating is formed on the four ridgeline portions E1 of the laminate 10 located in the first division region 90A and the four ridgeline portions E2 of the laminate 10 located in the second division region 90B. Adjust the conditions.

Note that the presence of the first glass layer 80A described above prevents the plating solution from penetrating into the first region LS1E from the exposed portion of the laminate near the ridgeline E1 of the laminate 10 during this plating process. can be suppressed. Further, the presence of the second glass layer 80B described above makes it possible to suppress the plating solution from penetrating into the second region LS2E from the exposed portion of the laminate near the ridgeline E2 of the laminate 10. . Therefore, insulation deterioration of the laminate due to penetration of the plating solution can be suppressed.

The multilayer ceramic capacitor 1 is manufactured by the above manufacturing method.

As described above, the method for manufacturing the multilayer ceramic capacitor 1 of the present embodiment includes forming the first glass layer 80A so as to surround at least the first region LS1E of the multilayer body 10, and A glass layer forming step of forming a second glass layer 80B to surround the second region LS2E, and a first end-side base electrode layer 51A and a first side-side base electrode layer 52A as base electrode layers. , a base electrode layer forming step of forming a second end surface side base electrode layer 51B and a second side surface side base electrode layer 52B, and a plating layer forming step of forming a plating layer on the surface of the base electrode layer. I'm here.

According to the multilayer ceramic capacitor 1 of this embodiment, the following effects are achieved.

(1) The multilayer ceramic capacitor 1 according to the present embodiment includes a plurality of stacked dielectric layers 20 and a plurality of stacked internal electrode layers 30, and includes a first side surface TS1 and a first side surface TS1 facing the stacking direction T. 2, a third side surface WS1 and a fourth side surface WS2 facing in the width direction W perpendicular to the lamination direction T, and a first side face TS2 facing in the length direction L perpendicular to the lamination direction T and width direction W. A laminate 10 including an end surface LS1 and a second end surface LS2, a first external electrode 40A disposed on the first end surface LS1 side, and a second external electrode disposed on the second end surface LS2 side. A multilayer ceramic capacitor 1 having an electrode 40B, in which the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 drawn out to a first end surface LS1, and a plurality of first internal electrode layers 31 drawn out to a second end surface LS2. The first external electrode 40A has a first base electrode layer 50A and a first plating layer 70A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 70B disposed on the second base electrode layer 50B, and the second external electrode 40B has a second base electrode layer 50B and a second plating layer 70B disposed on the second base electrode layer 50B. The first internal electrode layer 311 is located closest to the first side surface TS1 among the plurality of first internal electrode layers 31, and the first internal electrode layer 311 is located closest to the second side surface TS2 among the plurality of first internal electrode layers 31. A region sandwiched between the first internal electrode layer 315 and the first internal electrode layer 315 is referred to as a first region LS1E, and a second region located closest to the first side surface TS1 among the plurality of second internal electrode layers 32 on the second end surface LS2 is defined as a first region LS1E. When the region sandwiched between the internal electrode layer 321 and the second internal electrode layer 325 located closest to the second side surface TS2 among the plurality of second internal electrode layers 32 is defined as the second region LS2E, A first glass layer 80A is disposed on the end surface LS1 of the first glass layer so as to surround at least the first region LS1E, and a first glass layer 80A is disposed on the second end surface LS2 so as to surround at least the second region LS2E. The second base electrode layer 50A covers at least a portion of the first internal electrode layer 31 and the first glass layer 80A exposed to the first end surface LS1. The end surface side base electrode layer 51A and the first end surface side base electrode layer 51A are arranged separated by the first dividing region 90A, and at least one side surface of the four side surfaces TS1, TS2, WS1, and WS2 is arranged. The second base electrode layer 50B has a first side-side base electrode layer 52A that covers a part of the first end face LS1 side of the second internal electrode exposed on the second end face LS2. A second end-side base electrode layer 51B that covers at least a portion of the layer 32 and the second glass layer 80B and a second end-side base electrode layer 51B are separated by a second dividing region 90B, It has a second side surface side base electrode layer 52B that covers a part of the second end surface LS2 side of at least one side surface of the four side surfaces TS1, TS2, WS1, and WS2. This makes it possible to alleviate thermal stress and suppress the occurrence of cracks in the laminate 10, while also suppressing insulation deterioration of the laminate 10 due to intrusion of moisture from the outside.

It should be noted that the first base electrode layer 50A is arranged such that the first end surface side base electrode layer 51A and the first end surface side base electrode layer 51A are separated by the first dividing region 90A, and are divided into four a first side surface side base electrode layer 52A that covers a part of the first end surface LS1 side of at least one side surface of the side surfaces TS1, TS2, WS1, and WS2; The above-mentioned second end surface side base electrode layer 51B and second end surface side base electrode layer 51B are arranged separated by the second dividing region 90B, and are arranged so as to be separated by the second dividing region 90B, and the second end surface side base electrode layer 51B is separated by the second dividing region 90B. It has a second side surface side base electrode layer 52B that covers a part of at least one side surface on the second end surface LS2 side. This improves the board mountability of the multilayer ceramic capacitor 1 compared to the case where only the first end-side base electrode layer 51A and the second end-side base electrode layer 51B are present. Furthermore, if the base electrode layer is provided on all four side surfaces TS1, TS2, WS1, and WS2 as in the present embodiment, the board mountability is further improved. In addition, the process of dipping the conductive paste that becomes the base electrode layer, etc. becomes easier.

Note that in this embodiment, the first glass layer 80A is arranged only around the first region LS1E. Further, the second glass layer 80B is arranged only around the second region LS2E. Thereby, the range and amount to which the raw materials for the first glass layer 80A and the second glass layer 80B are deposited can be minimized.

Note that it is preferable that the first extended portion 31B of the first internal electrode layer 31 protrudes from the first end surface LS1; It does not need to protrude from the end surface LS1. Further, it is preferable that the second extended portion 32B of the second internal electrode layer 32 protrudes from the second end surface LS2; It does not need to protrude from the end surface LS2.

<Second embodiment>
A multilayer ceramic capacitor 1 according to a second embodiment of the present invention will be described below. In the following description, the same components as in the first embodiment are given the same reference numerals, and detailed description will be omitted. FIG. 6 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. FIG. 7 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 6 taken along line VII-VII. FIG. 8 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 7 taken along the line VIII-VIII.

The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the region where the first plating layer 70A and the second plating layer 70B are provided. Furthermore, the multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the region where the first glass layer 80A and the second glass layer 80B are provided.

In the first embodiment, the first plating layer 70A was not provided on the four ridgeline portions E1 of the stacked body 10 located in the first divided region 90A. Moreover, the second plating layer 70B was not provided on the four ridgeline portions E2 of the stacked body 10 located in the second divided region 90B. In this embodiment, as shown in FIGS. 6 to 8, the first plating layer 70A includes the first divided layer 51A, the first end surface side base electrode layer 51A, and the first side surface side base electrode layer 52A. It is arranged so as to cover the region 90A. Further, the second plating layer 70B is arranged to cover the second divided region 90B in addition to the second end surface side base electrode layer 51B and the second side surface side base electrode layer 52B.

More specifically, the first plating layer 70A includes a first connection plating layer 73A in addition to the first end surface plating layer 71A and the first side surface plating layer 72A. The first connection plating layer 73A is provided so as to cover the four ridgeline portions E1 of the laminate 10 located in the first divided region 90A. The first connection plating layer 73A connects the first end surface side plating layer 71A and the first side surface side plating layer 72A.

The second plating layer 70B includes a second connection plating layer 73B in addition to the second end surface side plating layer 71B and the second side surface side plating layer 72B. The second connection plating layer 73B is provided so as to cover the four ridgeline portions E2 of the laminate 10 located in the second divided region 90B. The second plating layer 70B connects the second end surface side plating layer 71B and the second side surface side plating layer 72B.

Next, the first glass layer 80A and the second glass layer 80B of this embodiment will be explained.

9A is a hypothetical view taken along the line IXA-IXA of the multilayer ceramic capacitor 1 shown in FIG. 7 when the external electrode 40 is excluded from the multilayer ceramic capacitor 1. FIG.

FIG. 9B is a hypothetical view along the line IXB-IXB of the multilayer ceramic capacitor 1 shown in FIG. 7 when the external electrode 40 is excluded from the multilayer ceramic capacitor 1.

In this embodiment, the first glass layer 80A is arranged not only around the first region LS1E but also on the dielectric layer 20 in the first region LS1E, as shown in FIGS. 7 and 9A. has been done. Also in this embodiment, the first extended portion 31B of the first internal electrode layer 31 protrudes from the first end surface LS1. Therefore, the first internal electrode layer 31 penetrates the first glass layer 80A and is joined to the first base electrode layer 50A. Here, also in this embodiment, the thickness of the first glass layer 80A located at the first end surface LS1 in the length direction L is preferably 0.1 μm or more. As shown in FIGS. 7 and 8, the amount of protrusion of the first internal electrode layer 31 protruding from the first end surface LS1 may be approximately the same as the thickness of the first glass layer 80A.

In this embodiment, the second glass layer 80B is provided on the dielectric layer 20 in the second region LS2E in addition to the periphery of the second region LS2E, as shown in FIGS. 7, 8, and 9B. It is also located in The second extended portion 32B of the second internal electrode layer 32 protrudes from the second end surface LS2. Therefore, the second internal electrode layer 32 penetrates the second glass layer 80B and is joined to the second base electrode layer 50B. Here, also in this embodiment, the thickness of the second glass layer 80B located at the second end surface LS2 in the length direction L is preferably 0.1 μm or more. As shown in FIG. 7, the amount of protrusion of the second internal electrode layer 32 protruding from the second end surface LS2 may be approximately the same as the thickness of the inner circumferential portion of the second glass layer 80B. .

The multilayer ceramic capacitor 1 of this embodiment can be manufactured by a method similar to the manufacturing method of the first embodiment. However, in this embodiment, the conditions of the plating process are adjusted so that plating is also formed on the first divided region 90A and the second divided region 90B. In the first divided region 90A and the second divided region 90B, the dielectric layer 20 of the laminate 10 is exposed, but since this exposed region is not large, it is necessary to adjust the conditions of the plating process. Accordingly, plating can also be formed on the first divided region 90A and the second divided region 90B.

The first glass layer 80A and the second glass layer 80B may be formed by applying or dipping a glass coating solution and then applying heat treatment, as in the first embodiment. Alternatively, the first glass layer 80A and the second glass layer 80B may be formed by a sputtering method. Alternatively, the first glass layer 80A and the second glass layer 80B may be formed from a glass component contained in the conductive paste that becomes the first base electrode layer 50A and the second base electrode layer 50B. A solution containing lithium may be added to the conductive paste to facilitate softening of the glass component. During the baking process of the first base electrode layer 50A and the second base electrode layer 50B, the glass component softens and flows to the surface side of the laminate 10, and the first end surface LS1 and the second end surface of the laminate 10 are heated. A first glass layer 80A and a second glass layer 80B are formed in LS2.

Note that the amount of glass contained in the first base electrode layer 50A and the second base electrode layer 50B after the baking process is preferably 18% or less.

The amount of glass contained in the first base electrode layer 50A and the second base electrode layer 50B is measured by the following method. First, the multilayer ceramic capacitor 1 is polished in the width direction W so that the LT cross section at the center position in the width direction W of the multilayer ceramic capacitor 1 is exposed. Thereafter, the cross-sections of the first base electrode layer 50A disposed on the first end surface LS1 and the second base electrode layer 50B disposed on the second end surface LS2 are observed using a scanning electron microscope (SEM). and performs image binarization processing. In this process, software that can binarize the image is used to adjust the binarization range so that the glass portion and the non-glass portion are clearly separated, and the result of the binarization process is obtained. At this time, it is preferable to perform the binarization process on the first base electrode layer 50A and the second base electrode layer 50B in a range of 30 μm×30 μm or more. After performing the binarization process, parts other than the first base electrode layer 50A and the second base electrode layer 50B are excluded from the range specification, and the parts of the first base electrode layer 50A and the second base electrode layer 50B are Read the result of binarization processing for only The result of the area ratio of the glass portion to the entire specified range obtained as a result of this binarization processing is defined as the amount of glass.

Note that the size of the glass domains in the first base electrode layer 50A and the second base electrode layer 50B after the baking process is preferably 60 μm ² or less. This makes it easier to ensure moisture resistance reliability.

The size of the glass domains in the first base electrode layer 50A and the second base electrode layer 50B is measured by the following method. First, the multilayer ceramic capacitor 1 is polished in the width direction W so that the LT cross section at the center position in the width direction W of the multilayer ceramic capacitor 1 is exposed. Thereafter, the cross-sections of the first base electrode layer 50A disposed on the first end surface LS1 and the second base electrode layer 50B disposed on the second end surface LS2 are observed using a scanning electron microscope (SEM). and performs image binarization processing. In this process, software that can binarize the image is used to adjust the binarization range so that the glass portion and the non-glass portion are clearly separated, and the result of the binarization process is obtained. At this time, it is preferable to perform the binarization process on the first base electrode layer 50A and the second base electrode layer 50B in a range of 30 μm×30 μm or more. After performing the binarization process, parts other than the first base electrode layer 50A and the second base electrode layer 50B are excluded from the range specification, and the parts of the first base electrode layer 50A and the second base electrode layer 50B are Read the result of binarization processing for only Based on the result of this binarization process, the area of each glass portion is calculated. The maximum value of the area of this glass portion is defined as the size of the glass domain.

According to the multilayer ceramic capacitor 1 of this embodiment, in addition to the above (1), the following effects are achieved.

(2) The first glass layer 80A of this embodiment is arranged not only around the first region LS1E but also on the dielectric layer 20 in the first region LS1E, and is arranged on the dielectric layer 20 in the first region LS1E. 80B is arranged not only around the second region LS2E but also on the dielectric layer 20 within the second region LS2E. This enhances the effect of suppressing insulation deterioration of the laminate 10 due to intrusion of moisture from the outside.

(3) The first internal electrode layer 31 of this embodiment penetrates the first glass layer 80A and is joined to the first base electrode layer 50A, and the second internal electrode layer 32 It penetrates through the glass layer 80B and is joined to the second base electrode layer 50B. Thereby, electrical conduction between the internal electrode layer 30 and the external electrode 40 can be increased while suppressing insulation deterioration of the laminate 10 due to infiltration of moisture from the outside.

(4) The first plating layer 70A of this embodiment is arranged to cover the first divided region 90A in addition to the first end surface side base electrode layer 51A and the first side surface side base electrode layer 52A. The second plating layer 70B is arranged to cover the second divided region 90B in addition to the second end surface side base electrode layer 51B and the second side surface side base electrode layer 52B. This further improves the board mountability of the multilayer ceramic capacitor 1.

<Third embodiment>
A multilayer ceramic capacitor 1 according to a third embodiment of the present invention will be described below. In the following description, the same components as in the second embodiment are given the same reference numerals, and detailed description will be omitted. FIG. 10 is a sectional view of the multilayer ceramic capacitor 1 of this embodiment, and is a sectional view corresponding to FIG. 7 of the second embodiment. FIG. 11 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 10, taken along the line XI-XI. FIG. 12 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 10, taken along line XII-XII.

The multilayer ceramic capacitor 1 of this embodiment differs from the first and second embodiments in the region where the first glass layer 80A and the second glass layer 80B are provided.

In the second embodiment, the first glass layer 80A was arranged not only around the first region LS1E but also on the dielectric layer 20 in the first region LS1E. In this embodiment, the first glass layer 80A further continuously covers from the periphery of the first region LS1E to at least a portion of the first divided region 90A. More specifically, the first glass layer 80A extends continuously from the periphery of the first region LS1E of the laminate 10 to the portion of the laminate 10 where the first side-side base electrode layer 52A is provided. It is covered with. The first plating layer 70A includes a first glass layer 80A formed in the first divided region 90A in addition to the first end surface side base electrode layer 51A and the first side surface side base electrode layer 52A. arranged to cover. Further, in the second embodiment, the second glass layer 80B was arranged not only around the second region LS2E but also on the dielectric layer 20 in the second region LS2E. In this embodiment, the second glass layer 80B further continuously covers from the periphery of the second region LS2E to at least a portion of the second divided region 90B. More specifically, the second glass layer 80B extends continuously from the periphery of the second region LS2E of the laminate 10 to the portion of the laminate 10 where the second side base electrode layer 52B is provided. It is covered with. The second plating layer 70B includes a second glass layer 80B formed in the second divided region 90B in addition to the second end surface side base electrode layer 51B and the second side surface side base electrode layer 52B. arranged to cover.

The first glass layer 80A and the second glass layer 80B may be formed by applying or dipping a glass coating solution and then applying heat treatment. Alternatively, the first glass layer 80A and the second glass layer 80B may be formed by a sputtering method. Alternatively, the first glass layer 80A and the second glass layer 80B may be formed from a glass component contained in the conductive paste that becomes the first base electrode layer 50A and the second base electrode layer 50B. Furthermore, the first glass layer 80A and the second glass layer 80B may be formed by combining these methods. For example, the first glass layer 80A and the second glass layer 80B arranged between the first base electrode layer 50A and the second base electrode layer 50B and the laminate 10 are included in the conductive paste. The first glass layer 80A and the second glass layer 80B arranged in the first divided region 90A and the second divided region 90B may be formed of a glass component by a method using a glass coating solution or a sputtering method. may be formed.

Note that the amount of glass contained in the first base electrode layer 50A and the second base electrode layer 50B after the baking process is preferably 18% or less.

Note that the size of the glass domains in the first base electrode layer 50A and the second base electrode layer 50B after the baking process is preferably 60 μm ² or less. This makes it easier to ensure moisture resistance reliability.

Note that the lengths of the first divided region 90A and the second divided region 90B in this embodiment are measured by cross-sectional observation using an SEM, as in the first embodiment. For example, the length of the first divided region 90A on the first side surface TS1 side in the LT cross-sectional view shown in FIG. 10 is the length indicated by the broken line indicated by the symbol 90A in FIG. The distance along the interface between the first glass layer 80A and the first plating layer 70A from the point where the base electrode layer is interrupted on the side to the point where the base electrode layer is interrupted on the first side surface TS1 side. be. The lengths of the first divided region 90A and the second divided region 90B at other positions are also measured by the same method.

In this embodiment, the conditions of the plating process are adjusted so that plating is also formed on the first divided region 90A and the second divided region 90B. In the first divided region 90A and the second divided region 90B, the first glass layer 80A and the second glass layer 80B are exposed, but since the exposed regions are not large, plating By adjusting the conditions, plating can also be formed on the first divided region 90A and the second divided region 90B.

Note that, as shown in FIGS. 10 to 12, the first glass layer 80A of this embodiment is arranged on all four side surfaces TS1, TS2, WS1, and WS2. The first glass layer 80A is arranged so as to cover the four ridgeline portions E3 located between adjacent side surfaces. Further, the second glass layer 80B is arranged on all four side surfaces TS1, TS2, WS1, and WS2. The second glass layer 80B is arranged to cover the four ridgeline portions E3 located between adjacent side surfaces.

FIG. 13 is an external perspective view showing the multilayer ceramic capacitor 1 of the third embodiment before forming the first plating layer 70A and the second plating layer 70B.

The first side surface base electrode layer 52A of this embodiment is arranged on all four side surfaces TS1, TS2, WS1, and WS2. Further, the first side surface base electrode layer 52A is arranged to cover the first glass layer 80A that covers the four ridgeline portions E3 located between adjacent side surfaces. Further, the second side surface side base electrode layer 52B is arranged on all four side surfaces TS1, TS2, WS1, and WS2. Furthermore, the second side surface side base electrode layer 52B is arranged so as to cover the second glass layer 80B that covers the four ridgeline portions E3 located between adjacent side surfaces.

This expands the range in which the external electrodes 40 are formed, and further improves the board mounting properties of the multilayer ceramic capacitor 1.

FIG. 14 is an external perspective view showing a modification of the multilayer ceramic capacitor of the third embodiment before forming the first plating layer and the second plating layer.

In this modification, the first side surface side base electrode layer 52A is arranged on all four side surfaces TS1, TS2, WS1, and WS2. However, the first side surface side base electrode layer 52A is not arranged on the four ridgeline portions E3 located between adjacent side surfaces. Further, the second side surface side base electrode layer 52B is arranged on all four side surfaces TS1, TS2, WS1, and WS2. However, the second side surface base electrode layer 52B is not arranged on the four ridgeline portions E3 located between adjacent side surfaces.

In the case of the configuration of such a modified example, it is possible to improve the board mountability of the multilayer ceramic capacitor 1 and to increase the effect of suppressing the occurrence of cracks in the multilayer body 10.

According to the multilayer ceramic capacitor 1 of this embodiment, in addition to the above (1) to (4), the following effects are achieved.

(5) The first glass layer 80A of the present embodiment continuously covers from the periphery of the first region LS1E to at least a part of the first divided region 90A, and the second glass layer 80B covers the first divided region 90A. It continuously covers from the periphery of the second region LS2E to at least a portion of the second divided region 90B. This enhances the effect of suppressing insulation deterioration of the laminate 10 due to intrusion of moisture from the outside. Note that by adopting the configuration (6) below, the effect of suppressing insulation deterioration of the laminate 10 due to infiltration of moisture from the outside is further enhanced; however, for example, if the first glass layer 80A is Even in a configuration in which the second glass layer 80B extends halfway into the second divided region 90B, the effect of suppressing insulation deterioration of the laminate 10 due to intrusion of moisture from the outside is enhanced.

(6) The first glass layer 80A of the present embodiment extends from the periphery of the first region LS1E of the laminate 10 to the portion of the laminate 10 where the first side base electrode layer 52A is provided. The second glass layer 80B continuously covers the area from the periphery of the second region LS2E of the laminate 10 to the portion of the laminate 10 where the second side base electrode layer 52B is provided. cover. This further enhances the effect of suppressing insulation deterioration of the laminate 10 due to intrusion of moisture from the outside.

(7) The first plating layer 70A of the present embodiment includes, in addition to the first end-side base electrode layer 51A and the first side-side base electrode layer 52A, the first plating layer 70A formed in the first divided region 90A. The second plating layer 70B covers the second divided region 90B in addition to the second end-side base electrode layer 51B and the second side-side base electrode layer 52B. The second glass layer 80B is disposed so as to cover the second glass layer 80B formed in the second glass layer 80B. Thereby, it is possible to further enhance the effect of suppressing insulation deterioration of the multilayer body 10 due to the intrusion of moisture from the outside, and to further improve the board mountability of the multilayer ceramic capacitor 1.

(8) The first glass layer 80A of this embodiment is arranged on all four side surfaces TS1, TS2, WS1, and WS2, and covers the four ridgeline portions E3 located between the adjacent side surfaces. The second glass layer 80B is arranged on all four side surfaces TS1, TS2, WS1, and WS2, and covers the four ridgeline portions E3 located between each adjacent side surface. It is located. This further enhances the effect of suppressing insulation deterioration of the laminate 10 due to intrusion of moisture from the outside.

(9) The first side surface base electrode layer 52A of this embodiment is arranged on all four side surfaces TS1, TS2, WS1, and WS2, and the first glass layer 80A covers the four ridgeline portions E3. The second side surface base electrode layer 52B is placed on all four side surfaces TS1, TS2, WS1, and WS2, and the second glass layer 80B covers the four ridgeline portions E3. is arranged to cover. Thereby, the board mountability of the multilayer ceramic capacitor 1 can be further improved.

(10) The first side surface side base electrode layer 52A of this embodiment is arranged on all four side surfaces TS1, TS2, WS1, and WS2, and is not arranged on the four ridgeline portions E3, The second side surface side base electrode layer 52B is arranged on all the four side surfaces TS1, TS2, WS1, and WS2, and is not arranged on the four ridgeline portions E3. Thereby, it is possible to improve the board mounting properties of the multilayer ceramic capacitor 1 and to increase the effect of suppressing the occurrence of cracks in the multilayer body 10.

Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in FIGS. 1 to 14. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure, as shown in FIGS. 15A, 15B, and 15C.

The multilayer ceramic capacitor 1 shown in FIG. 15A is a double-layered multilayer ceramic capacitor 1, and includes a first end surface as an internal electrode layer 30 in addition to a first internal electrode layer 33 and a second internal electrode layer 34. A floating internal electrode layer 35 that is not drawn out to either LS1 or second end surface LS2 is provided. The multilayer ceramic capacitor 1 shown in FIG. 15B is a triple-structured multilayer ceramic capacitor 1 including a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 15C has a quadruple structure including a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. This is a multilayer ceramic capacitor 1. In this manner, by providing the floating internal electrode layer 35 as the internal electrode layer 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into a plurality of parts. As a result, a plurality of capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component is reduced, and the multilayer ceramic capacitor 1 can have a high withstand voltage. Note that it goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-connection structure of four or more units.

Note that the multilayer ceramic capacitor 1 may be of a two-terminal type with two external electrodes, or may be of a multi-terminal type with a large number of external electrodes.

The present invention is not limited to the configuration of the embodiments described above, and can be modified and applied as appropriate without changing the gist of the present invention. It goes without saying that each embodiment is merely an example, and that configurations shown in different embodiments can be partially replaced or combined. In the second embodiment and subsequent embodiments, descriptions of common matters with the first embodiment are omitted, and only different points are explained. In particular, similar effects due to similar configurations are not mentioned sequentially before the embodiments.

1 Multilayer ceramic capacitor 10 Laminated body 11 Inner layer part 11E Counter electrode part (capacitor effective part)
12 First side surface side outer layer portion 13 Second side surface side outer layer portion LS1 First end surface LS1E First region LS2 Second end surface LS2E Second region TS1 First side surface TS2 Second side surface WS1 Third Side surface WS2 Fourth side surface 20 Dielectric layer 30 Internal electrode layer 31 (311, 312, 313, 314, 314) First internal electrode layer 31A First opposing portion 31B First extraction portion 32 (321, 322, 323, 324, 325) Second internal electrode layer 32A Second opposing portion 32B Second extension portion 40 External electrode 40A First external electrode 40B Second external electrode 50A First base electrode layer 51A First End face side base electrode layer 52A First side face side base electrode layer 50B Second base electrode layer 51B Second end face side base electrode layer 52B Second side face side base electrode layer 70A First plating layer 71A First end face Side plating layer 72A First side plating layer 73A First connection plating layer 70B Second plating layer 71B Second end side plating layer 72B Second side side plating layer 73B Second connection plating layer 80A First Glass layer 80B Second glass layer 90A First divided region 90B Second divided region E1, E2, E3 Ridge line L Length direction W Width direction T Lamination direction

Claims (8)

It includes a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and has a first side surface and a second side surface facing each other in the lamination direction, and a third side surface facing each other in the width direction orthogonal to the lamination direction. A laminate including a side surface and a fourth side surface, and a first end surface and a second end surface facing each other in the length direction perpendicular to the lamination direction and the width direction;
a first external electrode disposed on the first end surface side;
a second external electrode disposed on the second end surface side;
A multilayer ceramic capacitor having
The plurality of internal electrode layers have a plurality of first internal electrode layers drawn out to the first end surface and a plurality of second internal electrode layers drawn out to the second end surface,
The first external electrode has a first base electrode layer and a first plating layer disposed on the first base electrode layer,
The second external electrode has a second base electrode layer and a second plating layer disposed on the second base electrode layer,
A first internal electrode layer located closest to the first side surface among the plurality of first internal electrode layers and a second side surface closest to the second side surface among the plurality of first internal electrode layers on the first end surface. A region sandwiched between the first internal electrode layer located on the side is defined as a first region;
a second internal electrode layer located closest to the first side surface among the plurality of second internal electrode layers on the second end surface; and a second internal electrode layer located closest to the first side surface among the plurality of second internal electrode layers; When a region sandwiched between the second internal electrode layer located on the side is defined as a second region,
A first glass layer is arranged on the first end surface so as to surround at least a first region,
A second glass layer is disposed on the second end surface so as to surround at least the second region,
The first base electrode layer includes a first end surface side base electrode layer that covers at least a portion of the first internal electrode layer and the first glass layer exposed on the first end surface; The first end surface side base electrode layer is a first side surface side base that is separated by a first dividing region and covers a part of the first end surface side of at least one of the four side surfaces. and an electrode layer;
The second base electrode layer includes a second end surface side base electrode layer that covers at least a portion of the second internal electrode layer and the second glass layer exposed on the second end surface; The second end surface side base electrode layer is a second side surface side base electrode layer that is separated by a second dividing area and covers a part of the second end surface side of at least one side surface among the four side surfaces. an electrode layer;
The first glass layer continuously covers from the periphery of the first region to at least a portion of the first divided region,
The second glass layer continuously covers from the periphery of the second region to at least a portion of the second divided region,
The first glass layer and the second glass layer are arranged apart from each other, and in the region between the first side-side base electrode layer and the second side-side base electrode layer, the dielectric of the laminate is The body layers are exposed on the outer surface,
The first glass layer continuously covers from the periphery of the first region of the laminate to a portion of the laminate where the first side base electrode layer is provided,
The second glass layer is a laminated ceramic that continuously covers from the periphery of the second region of the laminate to a portion of the laminate where the second side base electrode layer is provided. capacitor. The first glass layer is arranged not only around the first region but also on the dielectric layer in the first region,
2. The multilayer ceramic capacitor according to claim 1, wherein the second glass layer is disposed not only around the second region but also on the dielectric layer within the second region. The first internal electrode layer penetrates the first glass layer and is joined to the first base electrode layer,
3. The multilayer ceramic capacitor according to claim 2, wherein the second internal electrode layer penetrates the second glass layer and is joined to the second base electrode layer. The first plating layer is arranged to cover the first divided region in addition to the first end surface side base electrode layer and the first side surface side base electrode layer,
The second plating layer is arranged to cover the second divided region in addition to the second end-side base electrode layer and the second side-side base electrode layer. 3. The multilayer ceramic capacitor according to any one of 3. The first plating layer covers the first glass layer formed in the first divided region in addition to the first end-side base electrode layer and the first side-side base electrode layer. It is located in
The second plating layer covers the second glass layer formed in the second divided region in addition to the second end-side base electrode layer and the second side-side base electrode layer. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the multilayer ceramic capacitor is arranged in a . The first glass layer is disposed on all of the four side surfaces and is disposed so as to cover the four ridgeline portions located between each adjacent side surface,
Any one of claims 1 to 5, wherein the second glass layer is disposed on all of the four side surfaces and is disposed to cover four ridgeline portions located between each adjacent side surface . The multilayer ceramic capacitor according to item 1 . The first side surface base electrode layer is arranged on all the four side surfaces and is arranged so as to cover the first glass layer that covers the four ridgeline parts,
7. The second side surface base electrode layer is disposed on all of the four side surfaces and is disposed to cover the second glass layer that covers the four ridgeline portions. The listed multilayer ceramic capacitor. The first side-side base electrode layer is disposed on all of the four side surfaces and is not disposed on the four ridgeline portions,
7. The multilayer ceramic capacitor according to claim 6 , wherein the second side surface base electrode layer is arranged on all of the four side surfaces, and is not arranged on the four ridgeline portions.

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