JP7434685B2 - Printed circuit board and its manufacturing method - Google Patents

Description

The present invention relates to a printed circuit board and a method for manufacturing the same.

As electronic devices in the IT field, including mobile phones, become lighter, thinner, and smaller, technology to insert electronic components such as ICs, active elements, or passive elements into substrates is required to meet the technical demands. Recently, various techniques have been developed to embed components within a board.

Various cavity structures are formed to insert various components into the substrate. As a result, various processing techniques are required. There is also a need for technology to prevent damage to circuits due to processing.

US Patent No. 7,886,433

SUMMARY OF THE INVENTION An object of the present invention is to provide a printed circuit board that can precisely process a cavity structure without damaging circuitry during the process of forming the cavity structure into which an electronic element is inserted, and a method for manufacturing the same.

A printed circuit board according to an embodiment of the present invention includes a first insulating layer, a circuit pattern formed on the first insulating layer and exposed on one side of the first insulating layer, and laminated on one side of the first insulating layer, a second insulating layer having a through-hole cavity region formed therein exposing a circuit pattern; one side interposed between the first insulating layer and the second insulating layer and the other side protruding from the bottom of the cavity region; an insulator pattern formed along the boundary of the region.

Further, a method for manufacturing a printed circuit board according to an embodiment of the present invention includes the steps of forming a circuit pattern on one surface of a first insulating layer, setting a boundary of a cavity region on the first insulating layer, and forming a circuit pattern along the boundary. forming an insulating pattern; forming a protective layer covering the cavity region; forming a second insulating layer on one side of the first insulating layer; and removing the second insulating layer along the insulating pattern. forming a cavity region; and removing the protective layer to expose the circuit pattern.

FIG. 1 is a diagram for explaining a printed circuit board according to an embodiment of the present invention. FIG. 2 is an enlarged view of a cavity area of a printed circuit board according to an embodiment of the present invention. FIG. 2 is an enlarged view of a cavity area of a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 3 is a diagram for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG. 7 is a diagram for explaining a printed circuit board according to another embodiment of the present invention.

Embodiments of the printed circuit board, electronic device package, and manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings. Drawing numerals are given and duplicate explanations thereof will be omitted.

In addition, terms such as "first" and "second" used below are merely identification symbols for distinguishing between the same or corresponding components, and the same or corresponding components are the first, second, etc. is not limited by the terms.

Furthermore, in the contact relationship between each component, "coupling" does not mean only when each component is in direct physical contact, but when another structure is interposed between each component, It is used as a concept that covers cases where each component is in contact with another configuration.

<Printed circuit boards and electronic device packages>
FIG. 1 is a diagram for explaining a printed circuit board according to an embodiment of the present invention, and FIGS. 2 and 3 are enlarged views of a cavity area of the printed circuit board according to an embodiment of the present invention. be.

Referring to FIGS. 1 and 2, a printed circuit board according to an embodiment of the present invention includes a first insulating layer 10, a circuit pattern 15, a second insulating layer 20, and an insulator pattern 40.

The first insulating layer 10 electrically insulates the circuit pattern 15 formed on the inner or outer layer. The first insulating layer 10 may be made of a resin material. The first insulating layer 10 may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide (PI), and may be formed of prepreg (PPG) or a build-up film. can.

The circuit pattern 15 is formed on the first insulating layer 10 and is made of a metal such as copper that can transmit electrical signals. The circuit pattern 15 may be formed on one side, the other side, or inside the first insulating layer 10. For example, the circuit pattern 15 includes a via that penetrates the first insulating layer 10 and connects one surface of the first insulating layer 10 to the other surface, and a via that is formed on one surface or the other surface of the first insulating layer 10 and connected to the via. The pad may include:

Referring to FIGS. 1 and 2, in this embodiment, a circuit pattern 16 having a structure embedded inside the first insulating layer 10 is formed on one surface of the first insulating layer 10. For example, the embedded circuit pattern 16 may have a circuit structure of an embedded trace substrate in which minute circuits are embedded in the substrate. Since the upper surface of the embedded circuit pattern 16 is substantially the same as one surface of the first insulating layer 10, the upper surface of the embedded circuit pattern 16 is exposed through one surface of the first insulating layer 10. It can be a structure. The fine circuit pattern 16 of the embedded trace structure can also correspond to a fine pad of an electronic element inserted into the cavity region C.

The second insulating layer 20 is stacked on one surface of the first insulating layer 10 to electrically insulate the circuit pattern 15, and has a structure in which a portion thereof is penetrated to form a cavity region C.

The second insulating layer 20 may be formed of a material similar to that of the first insulating layer 10 in the form of prepreg (PPG), a build-up film, etc., and may be different from the first insulating layer 10. It may be formed using a different material or a different method.

A through hole 22 is formed in the second insulating layer 20 to expose the embedded circuit pattern 16 . An electronic element is inserted into the cavity region C formed by the through hole 22, and the inserted electronic element can be connected to the embedded circuit pattern 16.

Referring to FIGS. 1 and 2, a second insulating layer 20 in which a through hole 22 is formed is laminated on one surface of the first insulating layer 10, one surface of the first insulating layer 10 serves as a bottom, and the second insulating layer A cavity region C can be formed in which the wall surfaces of the 20 through holes 22 serve as side walls.

Further, a third insulating layer 30 is formed on the second insulating layer 20, and through holes 22 and 32 that continuously penetrate the second insulating layer 20 and the third insulating layer 30 are formed to deeply deepen the cavity region C. It can also be formed.

At this time, a conductive post 35 penetrating the second insulating layer 20 and the third insulating layer 30 and connecting to the circuit pattern 15 may be further included. For example, posts 35 made of copper may be coupled to pads 17 of circuit pattern 15 . By using the conductive posts 35, it is possible to easily electrically connect to other substrates in a package with a POP (package on the package) structure.

Meanwhile, the cavity region C may have a shape that becomes narrower as it approaches the first insulating layer 10 . When the through holes 22 and 32 are formed in the second insulating layer 20 or the third insulating layer 30 by laser or drilling, the boundary B of the cavity region C is formed in a structure close to a right angle, as shown in FIG. . That is, the inner wall of the cavity region C may be formed into a vertical wall shape.

On the other hand, when forming the through holes 22', 32' in the second insulating layer 20 or the third insulating layer 30 by sandblasting, the boundary B of the cavity region C is inclined as shown in FIG. be done. That is, the inner wall of the cavity region C may be formed so as to become narrower as it goes downward.

Also, referring to FIG. 1, the other surface of the first insulating layer 10 or one surface of the third insulating layer 30 serves as an outer layer of the printed circuit board, and solder resist layers 50 and 60 may be further formed thereon. A part of the conductive post 35 or the circuit pattern 15 is exposed through the opening of the solder resist layers 50 and 60, and can be electrically connected to the outside.

The insulator pattern 40 has a structure in which one side is interposed between the first insulating layer 10 and the second insulating layer 20, and the other side extends into the cavity region C and protrudes from the bottom surface of the cavity region C. The insulator pattern 40 is formed on one surface of the first insulating layer 10 and extends into the cavity region C, so that it has a shape protruding from the bottom surface of the cavity region C.

Referring to FIGS. 2 and 3, one end of the insulator pattern 40 is located between the first insulating layer 10 and the second insulating layer 20, and the other end is located above the bottom surface of the cavity region C. can be located in The insulator pattern 40 may be formed on one surface of the first insulating layer 10 along the boundary B of the cavity region C. Specifically, the insulator pattern 40 is arranged at a position where the boundary B of the cavity region C (a virtual plane extending the wall surfaces of the through holes 22 and 32, which are the inner walls of the cavity) intersects with one surface of the first insulating layer 10. be able to. The insulator pattern 40 formed along the boundary B of the cavity region C has a closed roof structure, and a portion of the first insulating layer 10 and the circuit pattern 15 may be exposed from the inside. For example, when the cavity region C is formed in the shape of a hexahedron, the insulator pattern 40 is formed in the shape of a square frame on the first insulating layer 10, and from inside the square frame, the first insulating layer serving as the bottom of the cavity region C is formed. 10 and the embedded circuit pattern 16 will be exposed.

Meanwhile, referring to FIG. 12, the insulator pattern 40' may be formed to cover at least a portion of the circuit pattern 15. For example, a portion of the insulator pattern 40' may have a structure in which it contacts the upper surface of the embedded circuit pattern 16.

At this time, the insulator pattern 40 may be formed of photosensitive resin so that the insulator pattern 40 can be selectively and easily formed on one surface of the first insulating layer 10 . For example, the photosensitive resin can be selectively applied to one surface of the first insulating layer 10 along the boundary B of the cavity region C, and then cured to easily form the insulating pattern 40.

Furthermore, the insulator pattern 40 may be formed of a different material from that of the second insulating layer 20. For example, the insulating pattern 40 may be formed of a material having higher wear resistance or toughness than the second insulating layer 20 or the third insulating layer 30 in which the through holes 22 and 32 are formed. Accordingly, when the through holes 22 and 32 are formed in the second insulating layer 20 or the third insulating layer 30 by a sandblasting process, the insulating pattern 40 can serve as a stopper during processing. Specific details regarding the sandblasting and stopper functions will be described later.

<Manufacturing method of printed circuit board>
4 to 11 are diagrams for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention.

A method for manufacturing a printed circuit board according to an embodiment of the present invention includes forming a circuit pattern 15 on a first insulating layer 10, forming an insulating pattern 40, and forming a protective layer 45. The method includes forming a second insulating layer 20, forming a cavity region C, and removing a protective layer 45.

In the step of forming the circuit pattern 15 on the first insulating layer 10 , the circuit pattern 15 is formed on one surface of the first insulating layer 10 . The circuit pattern 15 may be formed on the other surface or inside the first insulating layer 10. The circuit pattern 15 includes an embedded circuit pattern 16, and the embedded circuit pattern 16 may have a circuit structure of an embedded trace substrate in which a fine circuit is embedded in the substrate. The embedded trace structure's fine circuitry can also be applied to the fine pads of electronic devices.

Referring to FIG. 4, a first insulating layer 10 and a circuit pattern 15 may be formed on both sides of a carrier substrate 5 having a release layer. For example, a metal layer can be formed by plating and a patterning process can be performed by selective etching. Further, the circuit pattern 15 can be formed by applying a conductive metal material onto the release layer of the carrier substrate 5 and then performing a patterning process. For the patterning process, a tenting method, an MSAP method (Modified Semi-Additive Process), an SAP method (Semi-Additive Process), or the like can be used.

After the circuit pattern 15 is formed on the carrier substrate 5, the first insulating layer 10 is pressure-bonded and laminated on the carrier substrate 5, so that the circuit pattern 15 can be embedded in the first insulating layer 10. At this time, the first insulating layer 10 may be a semi-cured prepreg. Alternatively, the first insulating layer 10 in which the circuit pattern 15 is embedded can be formed by applying an insulating resin to the carrier substrate 5.

Meanwhile, the circuit pattern 15 may be additionally formed inside or on the other surface of the first insulating layer 10 stacked on the carrier substrate 5. At this time, the circuit pattern 15 located on the carrier substrate 5 may have a buried structure covered by the first insulating layer 10.

Referring to FIG. 5, when the first insulating layer 10 on which the circuit pattern 15 is formed is separated from the carrier substrate 5, the circuit pattern 15 has an embedded circuit pattern 16 exposed on one surface of the first insulating layer 10. Can be done. When a seed layer is formed on one surface of the first insulating layer 10 in the carrier substrate 5, the circuit pattern 16 embedded in one surface of the first insulating layer 10 can be exposed by removing the seed layer by etching. Can be done.

In the step of forming the insulating pattern 40, a boundary B of the cavity region C is set on the first insulating layer 10, and the insulating pattern 40 is formed along the boundary B. At this time, the insulating pattern 40 may be formed of a material different from that of the second insulating layer 20. For example, the insulating pattern 40 may be formed of a material with higher wear resistance or toughness than the second insulating layer 20 or the third insulating layer 30 that will be laminated later. Accordingly, when the through holes 22 and 32 are formed in the second insulating layer 20 or the third insulating layer 30 by a sandblasting process, the insulating pattern 40 can serve as a stopper during processing.

Referring to FIG. 6, the insulator pattern 40 may be formed on the boundary B of the cavity region C on one surface of the first insulating layer 10. Specifically, a boundary B (a virtual surface on which the cavity inner wall is formed) of the cavity region C is set, and the insulator pattern 40 is arranged at a position where the boundary B and one surface of the first insulating layer 10 intersect. can. The insulator pattern 40 formed along the boundary B of the cavity region C has a closed roof structure, and a portion of the first insulating layer 10 and the circuit pattern 15 may be exposed from the inside. For example, when the cavity region C is formed in a hexahedral shape, a square frame-shaped insulator pattern 40 is formed on the first insulating layer 10, and the first insulating layer 10 serving as the bottom of the cavity region C is formed from inside the square frame. One side of the circuit pattern 15 and the circuit pattern 15 are exposed.

At this time, in order to selectively and easily form the insulating pattern 40 on one surface of the first insulating layer 10, the insulating pattern 40 may be formed of photosensitive resin. For example, the insulator pattern 40 can be easily formed by selectively coating a photosensitive resin on one surface of the first insulating layer 10 along the boundary B of the cavity region C and curing it.

In the step of forming the protective layer 45, a temporary protective layer 45 is formed to protect the bottom of the cavity region C in a subsequent process of processing the cavity region C. For example, the protective layer 45 can cover the bottom of the cavity region C and protect the embedded circuit pattern 16. The protective layer 45 may be formed of a material different from that of the circuit pattern 15 .

Referring to FIG. 7, a protective layer 45 of an insulating material may be deposited on one side of the first insulating layer 10 to cover the bottom of the cavity region C. Referring to FIG. At this time, it is preferable that the protective layer 45 overlaps the insulating pattern 40 formed at the boundary B of the cavity region C, and covers the bottom of the cavity region C without any gap. The protective layer 45 can effectively prevent damage to the embedded circuit pattern 16 in the process of processing the cavity region C, which will be described later. In particular, since the fine circuit pattern 16 of the embedded trace structure has a very small thickness and width, even a small error during processing can cause significant damage. Therefore, by covering the circuit pattern 15 in the cavity region C with the protective layer 45, reliability and efficiency during manufacturing of the printed circuit board can be improved.

In the step of forming the second insulating layer 20, the second insulating layer 20 is formed on one surface of the first insulating layer 10. The second insulating layer 20 may be formed of a material similar to that of the first insulating layer 10 in the form of prepreg (PPG), a build-up film, etc., and may be different from the first insulating layer 10. It may be formed using a different material or a different method.

Referring to FIG. 8 , a second insulating layer 20 in which an insulating pattern 40 and a protective layer 45 are embedded may be stacked on one surface of the first insulating layer 10 . Then, a third insulating layer 30 can be further stacked on the second insulating layer 20. At this time, conductive posts 35 may be further formed to penetrate through the second insulating layer 20 and the third insulating layer 30 and connect to the circuit pattern 15. For example, the posts 35 made of copper may be coupled to the pads of the circuit pattern 15.

In the step of forming the cavity region C, the second insulating layer 20 is removed along the insulator pattern 40 to form the cavity region C. That is, the second insulating layer 20 is removed along the boundary B of the set cavity region C.

Specifically, by forming the through hole 22 in the second insulating layer 20, a cavity region C having a concave groove structure into which an electronic device or the like can be inserted and arranged is formed. When the third insulating layer 30 is formed on the second insulating layer 20, the through holes 22 and 32 can be formed to continuously penetrate the second insulating layer 20 and the third insulating layer 30. By exposing the protective layer 45 through the through holes 22 and 32, it is possible to electrically connect the exposed buried circuit pattern 16 and the electronic element after the protective layer 45 is removed, which will be described later. .

At this time, the cavity region C can be processed by sandblasting to selectively remove the second insulating layer 20.

Referring to FIG. 9, when processing the cavity region C, the insulator pattern 40 may serve as a stopper to limit the depth of processing. For example, the cavity region C is processed by a sandblasting process, and the insulator pattern 40 that serves as a stopper in the sandblasting process has higher wear resistance or toughness than the second insulating layer 20 or the third insulating layer 30. It can be made of any material.

Sandblasting is a processing method that prepares or cuts the surface of a material by spraying an abrasive material from a nozzle. In the past, sand was injected as an abrasive, hence the name sandblasting, but now various particles can be used as an abrasive, such as ceramic powders such as alumina (aluminum oxide) or silicon carbide, glass beads, and plastic powders. . There are two types of sandblasting: wet sandblasting, in which abrasives and water are mixed and then sprayed through a nozzle; and dry sandblasting, in which only the abrasive is sprayed through a nozzle using air. There is sandblasting (air blast).

In this embodiment, a processing prevention layer 70 is formed to selectively cover the unprocessed region of the third insulating layer 30, and the second insulating layer 20 and the third insulating layer 30 are processed by sandblasting to form the insulating pattern 40. and expose the upper part of the protective layer 45. At this time, since the insulating pattern 40 is made of a material with high wear resistance or high toughness, the insulating pattern 40 is less likely to be abraded or cut by sandblasting compared to the second insulating layer 20 and the third insulating layer 30. Thereby, even if the sandblasting process is sufficiently performed until the protective layer 45 is exposed from the central portion of the cavity region C, the boundary B portion of the cavity region C can be prevented from being damaged.

In the step of removing the protective layer 45, the protective layer 45 is removed to expose the embedded circuit pattern 16. The protective layer 45 can be removed by an easy chemical or physical method depending on the material.

Referring to FIG. 10, the protective layer 45 made of an insulating material may be removed from the first insulating layer 10. Referring to FIG.

Referring to FIG. 11, the other surface of the first insulating layer 10 or one surface of the third insulating layer 30 serves as an outer layer of the printed circuit board, and solder resist layers 50 and 60 may be further formed thereon. A part of the conductive post 35 or the circuit pattern 15 is exposed through the opening of the solder resist layers 50 and 60, and can be electrically connected to the outside.

Although one embodiment of the present invention has been described above, a person having ordinary knowledge in the technical field will be able to add or change constituent elements without departing from the idea of the present invention described in the claims. The present invention can be modified and changed in various ways by adding, deleting, adding, etc., and these are also within the scope of the rights of the present invention.

C Cavity region 10 First insulating layer 15 Circuit pattern 16 Embedded circuit pattern 20 Second insulating layer 22, 32 Through hole 30 Third insulating layer 40 Insulator pattern 45 Protective layer 50, 60 Solder resist layer

Claims (12)

a first insulating layer;
a circuit pattern embedded in the first insulating layer, the top surface of which is exposed on the top surface of the first insulating layer, and the side surfaces covered by the first insulating layer;
a second insulating layer laminated on one surface of the first insulating layer and having a penetrated cavity region that exposes the circuit pattern;
a third insulating layer formed on the second insulating layer and having the cavity region formed therein;
an insulator pattern, one side of which is interposed between the first insulating layer and the second insulating layer, the other side of which protrudes from the bottom surface of the cavity region, and is formed along the boundary of the cavity region;
including;
The insulating pattern is formed in a frame shape on the first insulating layer, and from the inside of the frame-shaped insulating pattern, the one surface of the first insulating layer that becomes the bottom of the cavity region, and the embedded pattern are formed on the first insulating layer. the circuit pattern is exposed ;
Side surfaces of the second insulating layer and the third insulating layer on the side of the cavity region are formed to be inclined, so that the cavity region has a structure that becomes narrower as it approaches the first insulating layer.
printed circuit board. The printed circuit board according to claim 1, wherein a portion of the first insulating layer and the circuit pattern are exposed in a region surrounded by the insulating pattern. The insulator pattern is
The printed circuit board according to claim 1 or 2, wherein the second insulating layer is made of a different material. The insulator pattern is
The printed circuit board according to claim 3, wherein the printed circuit board is made of a material having higher wear resistance or toughness than the second insulating layer. The printed circuit board according to claim 3, wherein the insulator pattern is formed of photosensitive resin. The printed circuit board according to any one of claims 1 to 5 , further comprising a conductive post formed to penetrate the second insulating layer and the third insulating layer and connected to the circuit pattern. The printed circuit board according to any one of claims 1 to 6 , wherein the insulator pattern covers at least a portion of the circuit pattern. forming a circuit pattern on one surface of the first insulating layer;
setting a boundary of a cavity region on the first insulating layer and forming an insulator pattern along the boundary;
forming a protective layer covering the cavity area;
forming a second insulating layer on one surface of the first insulating layer;
removing the second insulating layer along the insulating pattern to form the cavity region;
removing the protective layer to expose the circuit pattern;
A method of manufacturing a printed circuit board, including: In the step of forming the insulator pattern,
9. The method of manufacturing a printed circuit board according to claim 8 , wherein the insulator pattern is arranged on a boundary of the cavity region. Forming the insulator pattern includes:
10. The method of manufacturing a printed circuit board according to claim 9 , further comprising selectively applying and curing a photosensitive resin on the boundary of the cavity region. Forming the cavity region includes:
The method of manufacturing a printed circuit board according to any one of claims 8 to 10 , including the step of selectively removing the second insulating layer by sand blasting. The sandblasting step includes:
12. The method of manufacturing a printed circuit board according to claim 11 , further comprising forming a processing prevention layer that selectively covers an unprocessed region of the second insulating layer.

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