JP7441282B2 - semiconductor equipment - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are examples of semiconductor devices. Display devices (liquid crystal display devices, light emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic equipment, etc. may be said to have semiconductor devices. .

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.

2. Description of the Related Art Technologies for constructing transistors using semiconductor thin films are attracting attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a display device using a transistor having a channel formation region using zinc oxide or In-Ga-Zn oxide as an oxide semiconductor has been disclosed (see Patent Document 1 and Patent Document 2). ).

Furthermore, in recent years, a technique for manufacturing an integrated circuit of a memory device using a transistor including an oxide semiconductor has been disclosed (see Patent Document 3). Furthermore, not only memory devices but also arithmetic devices and the like have been manufactured using transistors including oxide semiconductors.

Japanese Patent Application Publication No. 2007-123861 Japanese Patent Application Publication No. 2007-96055 Japanese Patent Application Publication No. 2011-119674

By the way, as electronic devices become more sophisticated, smaller, and lighter, integrated circuits become more highly integrated and the size of transistors becomes smaller. Accordingly, the process rules for manufacturing transistors are becoming smaller year by year, from 45 nm to 32 nm to 22 nm. Along with this, transistors including oxide semiconductors are also required to have good electrical characteristics as designed in a fine structure.

An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a large on-current. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with small variations in electrical characteristics within the plane of a substrate. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high productivity. Alternatively, an object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. Note that issues other than these will naturally become clear from the description, drawings, claims, etc., and it is possible to extract issues other than these from the description, drawings, claims, etc. It is.

One embodiment of the present invention includes a first conductor, a first insulator on the first conductor, a second conductor on the first insulator, a first conductor, and a first insulator. an oxide having a region in contact with a side surface of the second conductor, a second insulator on the oxide, and a third conductor on the second insulator, The second insulator has a region facing the first conductor, the first insulator, and the side surface of the second conductor through an oxide, and the third conductor has an oxide and a region facing the side surfaces of the second conductor. The semiconductor device has a first conductor, a first insulator, and a region facing side surfaces of the second conductor with a second insulator interposed therebetween.

Further, in the above aspect, the first conductor, the first insulator, and the second conductor are covered with a third insulator, the third insulator has an opening, and the first conductor, the first insulator, and the second conductor are The second insulator and the third conductor may be formed to fill the opening.

Further, in the above aspect, the oxide has a region in contact with the top surface of the second conductor, and the second insulator has a region overlapping with the top surface of the second conductor via the oxide. , the third conductor may have a region that overlaps with the upper surface of the second conductor via the oxide and the second insulator.

Further, in the above aspect, the film thickness of the first insulator may be 1 nm or more and 100 nm or less.

Further, in the above embodiment, the oxide may include a metal oxide.

According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a large on-current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with small variations in electrical characteristics within a substrate surface can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a high degree of freedom in design can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become obvious from the description, drawings, claims, etc., and effects other than these can be extracted from the description, drawings, claims, etc. It is.

1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 1 is a cross-sectional view illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 1 is a circuit diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. 1 is a block diagram and a circuit diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. 2A and 2B are a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. FIG. 1 is a block diagram showing a semiconductor device according to one embodiment of the present invention. 1 is a circuit diagram showing a semiconductor device according to one embodiment of the present invention. FIG. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. A flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component. 1 is a diagram illustrating an electronic device according to one embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways and that the form and details thereof can be changed in various ways without departing from the spirit and scope thereof. Ru. Therefore, the present invention should not be construed as being limited to the contents described in the following embodiments.

In addition, in the drawings, the size, thickness of layers, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally reduced due to treatments such as etching, but these are sometimes omitted for ease of understanding. In addition, in the drawings, the same reference numerals are used for the same parts or parts having similar functions in different drawings, and repeated description thereof may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

Further, in order to facilitate understanding of the invention, particularly in top views (also referred to as "plan views") and perspective views, descriptions of some components may be omitted. In addition, some hidden lines may be omitted.

Further, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by replacing "first" with "second" or "third" as appropriate. Furthermore, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Furthermore, in this specification and the like, words indicating placement such as "above" and "below" are used for convenience in order to explain the positional relationship between structures with reference to the drawings. Further, the positional relationship between the structures changes as appropriate depending on the direction in which each structure is depicted. Therefore, the words and phrases are not limited to those explained in the specification, and can be appropriately rephrased depending on the situation.

Furthermore, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases where the angle is between -5° and 5° are also included. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Moreover, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case where the angle is 85° or more and 95° or less is also included. Moreover, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Further, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a channel formation region is provided between the source and the drain via the channel formation region. It is something that can pass current through. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.

Furthermore, the functions of the source and drain may be interchanged when transistors with different polarities are used, or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain may be used interchangeably.

Note that the channel length in a transistor refers to, for example, the region where the semiconductor (or the part of the semiconductor where current flows when the transistor is on) and the gate electrode overlap, or the length of the source (in the region where the channel is formed). The distance between the source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in a region where a channel is formed.

Furthermore, in this specification, etc., a silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and a silicon nitride oxide film refers to a film whose composition contains more nitrogen than oxygen. refers to a membrane with a large amount of

Furthermore, in this specification and the like, metal oxide refers to a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a channel formation region of a transistor, the metal oxide is sometimes called an oxide semiconductor. That is, when a metal oxide has at least one of an amplification effect, a rectification effect, and a switching effect, the metal oxide can be called a metal oxide semiconductor (metal oxide semiconductor), or OS for short. Moreover, when describing an OS FET or an OS transistor, it can be referred to as a transistor including a metal oxide or an oxide semiconductor.

Further, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

Further, in this specification and the like, it may be described as CAAC (C-Axis Aligned Crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration.

In addition, in this specification, etc., CAC-OS or CAC-metal oxide means that a part of the material has a conductive function, a part of the material has an insulating function, and the entire material has a semiconductor function. It has the function of Note that when CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, the conductive function is the function of flowing electrons (or holes) that become carriers, and the insulating function is the function of flowing electrons (or holes) that become carriers. This is a function that does not allow electrons (or holes) to flow. A switching function (on/off function) can be imparted to CAC-OS or CAC-metal oxide by making the conductive function and the insulating function act complementary to each other. By separating the functions of CAC-OS or CAC-metal oxide, the functions of both can be maximized.

Furthermore, in this specification and the like, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in a material, a conductive region and an insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. Further, the conductive regions may be observed to be connected in a cloud-like manner with the periphery blurred.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. Furthermore, the component having a narrow gap acts complementary to the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current, and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

Furthermore, in this specification and the like, the terms "film" and "layer" can be used interchangeably. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

Further, in this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer. Further, the term "conductor" can be replaced with a conductive film or a conductive layer. Further, the term "semiconductor" can be translated as a semiconductor film or a semiconductor layer.

Further, transistors shown in this specification and the like are field-effect transistors, unless otherwise specified. Further, transistors shown in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as "Vth") is assumed to be greater than 0V, unless specified otherwise.

(Embodiment 1)
<Configuration example 1 of semiconductor device>
A configuration example of a semiconductor device including a transistor 10 according to one embodiment of the present invention will be described below with reference to FIG.

FIG. 1A is a top view of a semiconductor device including a transistor 10. Further, FIG. 1(B) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1(A). Further, FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1(A). Here, the portion indicated by the dashed-dotted line A1-A2 and the portion indicated by the dashed-dotted line A3-A4 are orthogonal to each other. In the top view of FIG. 1A, some elements are omitted for clarity.

A semiconductor device of one embodiment of the present invention includes a transistor 10, an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as interlayer films over a substrate (not shown). 176, an insulator 178, and an insulator 180. The semiconductor device also includes a conductor 185 and a conductor 200 that are electrically connected to the transistor 10 and function as wiring, and a conductor 190 and a conductor 195 that function as a plug.

Conductor 185 is formed within an opening provided in insulator 105 . Here, the height of the top surface of the conductor 185 and the height of the top surface of the insulator 105 are preferably approximately the same. Note that although the conductor 185 is shown as having a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, the conductor 185 may have a laminated structure of two or more layers.

Conductor 190 is formed within an opening provided in insulator 110 . The bottom surface of the conductor 190 is provided so as to have a region in contact with the top surface of the conductor 185. Here, the height of the top surface of the conductor 190 and the height of the top surface of the insulator 110 are preferably approximately the same. Note that although the conductor 190 is shown as having a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, the conductor 190 is made of a material that suppresses the permeation of impurities such as hydrogen and water, and oxygen, in contact with the inner wall of the opening provided in the insulator 110, and on the conductor, It may be a laminated structure of two or more layers in which a conductor is made of a material having higher conductivity than the conductor.

The conductor 195 is formed in an opening that is provided in the insulator 175 , the insulator 176 , the insulator 178 , and the insulator 180 and reaches the upper surface of the conductor 140 . Here, the height of the top surface of the conductor 195 and the height of the top surface of the insulator 180 are preferably approximately the same. Note that although the conductor 195 is illustrated as having a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. A conductor made of a material that suppresses the permeation of impurities such as hydrogen and water and oxygen is formed in contact with the inner wall of the opening provided in the body 178 and the insulator 180, and a conductor is formed on the conductor. It may be a laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the above conductor is formed.

The conductor 200 is formed on the insulator 180 so as to have a region in contact with the upper surface of the conductor 195. Note that although the conductor 200 is shown as having a single-layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, the conductor 200 may have a laminated structure of two or more layers.

[Transistor 10]
As shown in FIG. 1B, the transistor 10 includes a conductor 120 and an oxide 150 disposed on an insulator 110, an insulator 130 disposed on the conductor 120, and an oxide 150 disposed on the insulator 110. A conductor 140 is disposed thereon, an insulator 160 is disposed on the oxide 150, and a conductor 170 is disposed on the insulator 160. Here, the oxide 150 is provided so as to have a region in contact with the side surfaces of the conductor 120, the insulator 130, and the conductor 140. Further, the insulator 160 is provided so as to have a region facing the side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 interposed therebetween. Further, the conductor 170 is provided so as to have a region facing the side surfaces of the conductor 120, the insulator 130, and the conductor 140 with the oxide 150 and the insulator 160 interposed therebetween.

As shown in FIGS. 1B and 1C, an insulator 175 is provided over the conductor 120, the insulator 130, and the conductor 140 so as to cover them. The insulator 175 is provided with an opening whose inner wall partially overlaps the side surface of the conductor 120 , insulator 130 , and conductor 140 , and an oxide 150 is provided along the inner wall of the opening. An insulator 160 is provided above, and a conductor 170 is provided above the insulator 160 so as to fill the opening. Here, as shown in FIG. 1B, the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175. Note that although the oxide 150 is shown as having a single layer structure in FIG. 1B, one embodiment of the present invention is not limited to this. For example, the oxide 150 may have a laminated structure of two or more layers.

In the transistor 10, the conductor 120 has a function as either a source electrode or a drain electrode, and the conductor 140 has a function as the other source electrode or drain electrode, and the conductor 140 has a function as the other of the source electrode or the drain electrode. The overlapping region functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode.

As described above, the transistor 10 according to one embodiment of the present invention includes a conductive layer (conductor 120) that functions as either a source electrode or a drain electrode, and an insulating layer (conductor 120) that has a region in contact with an oxide that functions as a channel formation region. It has a structure in which an insulator 130) and a conductive layer (conductor 140) functioning as the other of the source electrode or the drain electrode are laminated in order from the bottom. That is, in the transistor 10, the direction in which carriers (electrons or holes) flow (channel length direction) is substantially perpendicular to the substrate surface. With the transistor 10 having this configuration, the channel length of the transistor 10 is defined by the thickness of the insulator 130 sandwiched between the source electrode and the drain electrode. Therefore, the channel length of the transistor 10 can be controlled by the thickness of the insulator 130 when it is formed. For example, the channel length of the transistor 10 can be arbitrarily controlled within a range of 1 nm or more and 100 nm or less. Therefore, a plurality of fine transistors can be manufactured within the substrate surface with higher precision than when the channel length is formed using a lithography method or the like.

Note that in the transistor 10, the oxide 150 that functions as a channel formation region is preferably a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). A transistor using a metal oxide in a channel formation region has extremely low leakage current (off current) in a non-conducting state, and thus can provide a semiconductor device with low power consumption. Furthermore, since metal oxides can be formed into films using sputtering methods or the like, they can be used for transistors included in highly integrated semiconductor devices.

On the other hand, in a transistor using a metal oxide for a channel formation region, the electrical characteristics tend to fluctuate due to impurities or oxygen vacancies in the metal oxide, and reliability may deteriorate. Furthermore, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons, which are carriers, may be generated. Therefore, a transistor in which a metal oxide containing oxygen vacancies is used in a channel formation region tends to have normally-on characteristics. For this reason, it is preferable that oxygen vacancies in the metal oxide be reduced as much as possible.

In particular, if oxygen vacancies exist at the interface between the channel forming region of the oxide 150 and the insulator 160 functioning as a gate insulator, the electrical characteristics of the transistor 10 are likely to fluctuate, and reliability may deteriorate. There is.

Therefore, it is preferable that the insulator 160 in contact with the oxide 150 contains more oxygen (also referred to as excess oxygen) than the oxygen that satisfies the stoichiometric composition. In other words, excess oxygen in the insulator 160 diffuses into the channel formation region of the oxide 150, so that oxygen vacancies in the channel formation region can be reduced.

Furthermore, it is preferable that the transistor 10 be covered with an insulator having barrier properties that prevent impurities such as water or hydrogen from entering. An insulator with barrier properties has the ability to suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( _N2O , NO, NO2 _, etc.), and copper atoms. It is an insulator using an insulating material that has (the impurities mentioned above are difficult to pass through). Further, it is preferable to use an insulating material that has a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate).

For example, the transistor 10 is provided over an insulator 102 having barrier properties. Further, an insulator 178 having barrier properties is provided over the transistor 10. With the structure in which the insulator 102 and the insulator 178 are disposed above and below the transistor 10, the transistor 10 can be sandwiched between the insulators having barrier properties. With this structure, impurities such as hydrogen and water can be suppressed from entering the transistor 10 from the lower layer of the insulator 102 and from the upper layer of the insulator 178. Alternatively, oxygen contained in the insulator 130 and the insulator 160 can be suppressed from diffusing into the lower layer of the insulator 102 and the upper layer of the insulator 178. Thereby, oxygen contained in the insulator 130 and the insulator 160 can be efficiently supplied to the channel formation region of the oxide 150.

A detailed structure of a semiconductor device including the transistor 10 according to one embodiment of the present invention will be described below.

The insulator 102 and the insulator 178 preferably function as a barrier film that prevents impurities such as water or hydrogen from entering the transistor 10 from outside the insulator. Therefore, the insulator 102 and the insulator 178 suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( _N2O , NO, _NO2, etc.), and copper atoms. It is preferable to use an insulating material that has the function of preventing the impurities from passing through. Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate).

For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 102 and the insulator 178. Thereby, impurities such as hydrogen and water can be suppressed from diffusing inside the insulator (toward the transistor 10 side). Alternatively, oxygen contained in the insulator 130 and the like can be suppressed from diffusing outside the insulator 102 and the insulator 178.

Further, for example, as the insulator 102 and the insulator 178, an insulator such as aluminum oxide, hafnium oxide, or silicon nitride can be used in a single layer or in a stacked layer.

Furthermore, it is preferable that the insulators 100, 105, 110, 175, 176, and 180, which function as interlayer films, have a lower dielectric constant than the insulators 102 and 178. By using a material with a relatively low dielectric constant for the insulator, for example, parasitic capacitance occurring between wirings can be reduced.

For example, as the insulator 100, insulator 105, insulator 110, insulator 175, insulator 176, and insulator 180, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide Insulators such as lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba,Sr)TiO ₃ (BST) can be used in a single layer or in a stacked layer. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulator. Note that it is preferable that the concentration of impurities such as hydrogen and water in the film of each of the above-mentioned insulators is reduced as much as possible.

Further, in the transistor 10, the insulator 130 physically and electrically isolates the conductor 120 functioning as one of the source electrode or the drain electrode and the conductor 140 functioning as the other source electrode or the drain electrode. Has a function. The thickness of the insulator 130 is preferably 1 nm or more and 100 nm or less. As described above, the side surface of the insulator 130 is in contact with the channel formation region of the transistor 10 that the oxide 150 has. Therefore, as the insulator 130, it is preferable to use an oxide insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region is formed in the insulator 130. By providing such an insulator containing excess oxygen in contact with the oxide 150, oxygen vacancies in the channel formation region of the oxide 150 can be reduced, and the reliability of the transistor 10 can be improved.

Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material from which some oxygen is released by heating. An oxide from which oxygen is desorbed by heating is an oxide whose amount of desorbed oxygen in terms of oxygen atoms is 1.0×10 ¹⁴ atoms/cm ² or more, preferably 3 by TDS (Thermal Desorption Spectroscopy) analysis. It is an oxide film having a density of .0×10 ¹⁵ atoms/cm ² or more. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower.

Note that while it is better for the insulator 130 to contain as much oxygen as possible, it is preferable that the insulator 130 contains as little hydrogen, water, and the like as possible. This is because hydrogen, water, and the like can be a factor that changes the electrical characteristics of the transistor 10. Therefore, it is important that the concentration of hydrogen, water, etc. that can become impurities for the transistor 10 is reduced as much as possible not only in the oxide 150 that functions as a channel formation region but also in the insulator 130 that is in contact with the oxide 150. preferable.

Further, for the oxide 150 that functions as a channel formation region of the transistor 10, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide used for the channel forming region, it is preferable to use one with a band gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced.

The oxide 150 may have a laminated structure of two or more layers using oxides having different atomic ratios of metal atoms. For example, when the oxide 150 has a two-layer structure consisting of an oxide 150a (first layer) and an oxide 150b (second layer), in the metal oxide used for the oxide 150b, It is preferable that the atomic ratio of the element M is larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 150a. Further, in the metal oxide used for the oxide 150b, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 150a. Further, in the metal oxide used for the oxide 150a, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 150b.

When the oxide 150 has the above structure, the oxide 150a mainly functions as a channel formation region of the transistor 10. Here, defect levels are more likely to be formed at the interface between the insulator 160 and the oxide 150b made of different materials than at the interface between the oxide 150a and the oxide 150b made of materials with similar compositions. The defect level can become a trap level that causes variations in the electrical characteristics of the transistor 10 and deterioration of reliability. However, by having the oxide 150b on the oxide 150a, the defect level is can be separated from Thereby, the transistor 10 can provide good electrical characteristics and reliability.

Furthermore, by providing the oxide 150b over the oxide 150a, diffusion of impurities from above the oxide 150b into the channel formation region included in the oxide 150a can be suppressed.

As described above, a transistor in which a metal oxide is used in a channel formation region has extremely small leakage current in a non-conducting state, and thus can provide a semiconductor device with low power consumption. Furthermore, since metal oxides can be formed into films using sputtering methods or the like, they can be used for transistors included in highly integrated semiconductor devices.

For example, as the oxide 150, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium) , hafnium, tantalum, tungsten, or one or more selected from magnesium, etc.) may be used. Further, as the oxide 150, an In--Ga oxide or an In--Zn oxide may be used.

The conductor 120 and the conductor 140 function as a source electrode or a drain electrode of the transistor 10. As shown in FIGS. 1(B) and 1(C), the conductor 120 and the conductor 140 are provided above and below with the insulator 130 in between. For the conductor 120 and the conductor 140, for example, a conductor such as tantalum nitride, tungsten, titanium nitride, or the like can be used. Note that although the conductor 120 and the conductor 140 are shown as having a single layer structure in FIG. 1, they may have a laminated structure of two or more layers.

For example, when the conductor 120 and the conductor 140 have a two-layer structure, a metal such as tungsten is used for the first layer (second layer) of the conductor 120 (conductor 140), and A conductor having a function of suppressing oxygen permeation, such as titanium nitride or tantalum nitride, may be used for the second layer (first layer) of 140). With this configuration, as described above, when the insulator 130 sandwiched between the conductor 120 and the conductor 140 contains excess oxygen, the first layer of the conductor 120 (conductor 140) is removed from the insulator 130. Mixing of oxygen into the (second layer) is reduced, and an increase in the electrical resistance value of the first layer (second layer) of the conductor 120 (conductor 140) can be suppressed.

Although not shown in FIG. 1, a structure may be adopted in which an insulator such as aluminum oxide having a function of suppressing permeation of oxygen is formed on the conductor 120 (below the conductor 140). For example, a structure may be employed in which a conductor such as tantalum nitride, tungsten, or titanium nitride is used as the conductor 120 and the conductor 140, and an insulator such as aluminum oxide is laminated on the conductor 120 (below the conductor 140). With this structure, the mixing of oxygen from the insulator 130 into the conductors 120 and 140 can be reduced, and an increase in the electrical resistance values of the conductors 120 and 140 can be suppressed. Furthermore, since the amount of oxygen mixed into the conductor 120 and the conductor 140 is reduced, more oxygen can be supplied to the oxide 150. Note that when a sputtering method is used to form a film of aluminum oxide on the conductor 120 (under the conductor 140), aluminum oxide containing excess oxygen can be formed as a film. The excess oxygen may be provided to the insulator 130. Furthermore, the oxygen supplied to insulator 130 may be able to be supplied to oxide 150.

Further, the conductor 120 or the conductor 140 may react with the oxide 150. As a result, although not shown in FIG. 1, a region in which the region becomes n-type and has an increased number of carriers may be formed at the interface between the oxide 150 and the conductor 120 or 140. This region may contribute to increasing the drain current of transistor 10.

The insulator 160 functions as a gate insulator of the transistor 10. Insulator 160 is preferably placed in contact with the top surface of oxide 150. The insulator 160 is preferably formed using an insulator that releases oxygen when heated. For example, the insulator 160 has an oxygen desorption amount of 1.0×10 ¹⁴ atoms/cm ² or more, preferably 3 An oxide film having a density of .0×10 ¹⁵ atoms/cm ² or more is preferable. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower.

By providing an insulator from which oxygen is released by heating as the insulator 160 in contact with the upper surface of the oxide 150, oxygen can be efficiently supplied to the channel formation region of the oxide 150. Further, similarly to the insulator 130, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 160 is reduced. The thickness of the insulator 160 is preferably 1 nm or more and 20 nm or less. Note that although the insulator 160 is shown as having a single layer structure in FIG. 1, it may have a laminated structure of two or more layers.

The conductor 170 functions as a gate electrode of the transistor 10. For the conductor 170, for example, metal such as tungsten can be used. Note that although the conductor 170 is shown as having a single layer structure in FIG. 1, it may have a laminated structure of two or more layers.

For example, when the conductor 170 has a three-layer structure, a conductive oxide is used as the first layer of the conductor 170, titanium nitride is used as the second layer of the conductor 170, and titanium nitride is used as the third layer of the conductor 170. It is preferable to use a metal such as tungsten. Note that when the conductor 170 has a three-layer structure as described above, the first layer of the conductor 170 is arranged along the upper surface of the insulator 160, and the second layer of the conductor 170 is arranged along the upper surface of the insulator 160. It is preferable that the conductor 170 is disposed along the upper surface of the first layer, and the third layer of the conductor 170 is formed so as to fill the remaining space where the conductor 170 is provided. Further, the heights of the top surfaces of the first layer of the conductor 170, the second layer of the conductor 170, and the third layer of the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175.

Examples of the conductive oxide that can be used in the first layer of the conductor 170 include metal oxides that can be used as the oxide 150. In particular, among In-Ga-Zn oxides, metal atomic ratios of [In]:[Ga]:[Zn]=4:2:3 to 4.1, which have high conductivity, and values in the vicinity thereof Preferably, metal oxides are used. By using such a metal oxide in the first layer of the conductor 170, it is possible to reduce the mixing of oxygen into the second and third layers of the conductor 170 from below the first layer of the conductor 170, and to prevent oxidation. This can suppress an increase in the electrical resistance values of the second and third layers of the conductor 170.

Further, by forming the conductive oxide that can be used as the first layer of the conductor 170 using a sputtering method, oxygen can be added to the insulator 160 and oxygen can be supplied to the oxide 150. becomes possible. Thereby, oxygen vacancies in the channel formation region of the oxide 150 can be reduced.

For the second layer of the conductor 170, for example, a metal nitride such as titanium nitride can be used, as described above. By using a metal nitride in the second layer of the conductor 170, an impurity such as nitrogen may be added to the first layer of the conductor 170 to improve the conductivity of the first layer of the conductor 170. Furthermore, for the third layer of the conductor 170, a metal such as tungsten can be used, for example. By using a low resistivity material such as tungsten, the electrical resistance value of the conductor 170 can be lowered.

Further, for example, when the conductor 170 has a two-layer structure, the first layer may be a metal nitride such as titanium nitride, and the second layer may be a metal such as tungsten.

Although not shown in FIG. 1, an insulator having a function of suppressing oxygen permeation may be formed between the insulator 175 and the insulator 176. For example, as the insulator, an insulator such as aluminum oxide may be formed. With this configuration, it is possible to reduce the mixing of oxygen into the conductor 170 from above the insulator such as aluminum oxide, and to suppress oxidation of the conductor 170.

Further, the conductor 170 having a function as a gate electrode has an opening provided in the insulator 175 so as to have a region that partially overlaps with the side surfaces of the conductor 120, the insulator 130, and the conductor 140. 150 and an insulator 160 (see FIGS. 1(A) and 1(B)). When a mask is used to form a gate electrode, the smaller the gate electrode formation size, the higher the alignment accuracy of the mask is required. However, in the transistor 10 according to one embodiment of the present invention, the mask for forming the gate electrode No alignment is required. Therefore, compared to the case where a mask is used to form the gate electrode, it is possible to form a fine gate electrode with high precision, and the productivity is excellent.

As described above, in the transistor 10, the conductor 120 has a function as either a source electrode or a drain electrode, and the conductor 140 has a function as the other source electrode or drain electrode. A region of 150 overlapping with insulator 130 functions as a channel forming region, insulator 160 functions as a gate insulator, and conductor 170 functions as a gate electrode. Therefore, in the transistor 10, the length of the oxide 150 (that is, the thickness of the insulator 130) in the region sandwiched between the conductor 120 and the conductor 140 and in contact with the insulator 130 is equal to the channel length of the transistor 10. Equivalent to. With this configuration, in the transistor 10, the channel length can be controlled by controlling the film thickness of the insulator 130 at the time of film formation, and the channel length can be finely adjusted to several nanometers or less, which is difficult to manufacture using lithography. can be converted into In addition, since the channel length can be controlled by the thickness of the insulator 130 when it is formed, there is no need for precision in resist dimension variations, which is required when forming the channel length using lithography, and it is easy to adjust the device width within the substrate surface. It is possible to suppress processing variations between the two. That is, the transistor 10 according to one embodiment of the present invention is a transistor with a high degree of freedom in design, and transistors with a plurality of fine channel lengths can be manufactured with high precision within the substrate surface. Furthermore, since a plurality of transistors can be manufactured within the substrate plane with small processing variations, variations in electrical characteristics between elements can be reduced compared to a case where the channel length is formed using a lithography method.

Further, in addition to the channel length described above, the transistor 10 according to one embodiment of the present invention includes a conductor 120 and a conductor 140 that function as a source electrode or a drain electrode, which are provided above and below with an insulator 130 in between. It is characterized by the fact that By forming a structure in which a conductor having a function as a source electrode and a conductor having a function as a drain electrode are laminated in a direction perpendicular to the substrate surface as described above with the insulator 130 interposed therebetween, , it is possible to reduce the area occupied in the substrate plane by a conductor having a function as a source electrode or a drain electrode. Thereby, each transistor 10 can be miniaturized. Further, since each transistor 10 can be miniaturized, a semiconductor device including the transistor 10 can be highly integrated.

As described above, in the transistor 10 according to one embodiment of the present invention, a conductor that becomes one of the source electrode or the drain electrode, an insulator, and a conductor that becomes the other of the source electrode or the drain electrode are formed in order. By using the "type transistor structure", a plurality of transistors having extremely fine channel lengths can be easily manufactured with high precision. Further, a transistor with small variations in electrical characteristics between elements within the plane of the substrate can be manufactured. Further, transistors can be miniaturized. Further, a semiconductor device including the transistor can be highly integrated.

Note that as transistor miniaturization progresses and the channel length becomes shorter, Vth in the Vg (gate potential) - Id (drain current) characteristic of the transistor decreases (negatively shifts), and the subthreshold swing value (S value) decreases. The so-called "short channel effect," which is a problem such as an increase in off-state current, becomes more likely to become apparent. However, as described above, in the transistor 10 according to one embodiment of the present invention, a metal oxide can be used for the oxide 150 having the channel formation region. Therefore, compared to, for example, a transistor using Si in the channel formation region, short channel effects are less likely to occur, and off-state current can be significantly reduced. That is, the transistor 10 according to one embodiment of the present invention can have good electrical characteristics even when miniaturization is advanced. Note that details of the metal oxide will be explained later in <Components of Semiconductor Device>.

The conductor 190 (conductor 195) includes a conductor 120 (conductor 140) that functions as one (the other) of a source electrode or a drain electrode of the transistor 10, and a conductor 185 (conductor 185) that functions as a wiring. 200). For the conductor 190 (conductor 195), it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, although not shown in FIG. 1, the conductor 190 (conductor 195) may have a laminated structure, for example, it is provided in the insulator 110 (insulator 175, insulator 176, insulator 178, and insulator 180). A structure may be adopted in which a film of titanium, titanium nitride, etc. is formed in contact with the inner wall of the opening and the top surface (bottom surface) of the conductor 185 (conductor 200), and the conductive material is provided inside the film.

When the conductor 190 (conductor 195) has a laminated structure, the inner wall of the opening provided in the insulator 110 (insulator 175, insulator 176, insulator 178, and insulator 180) and the conductor 185 ( As the conductor in contact with the top surface (bottom surface) of the conductor 200), it is preferable to use a conductive material that has a function of suppressing the permeation of impurities such as hydrogen and water. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Further, the conductive material having the function of suppressing the permeation of impurities such as water or hydrogen may be used in a single layer or in a stacked layer. By using the conductive material, impurities such as hydrogen and water from a layer below (above) the insulator 110 (insulator 180) are suppressed from entering the oxide 150 through the conductor 190 (conductor 195). be able to.

As the conductor 185 (conductor 200) that functions as a wiring, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor may have a laminated structure, for example, a laminated layer of titanium, titanium nitride, and the above-mentioned conductive material.

The example of the structure of a semiconductor device including the transistor 10 according to one embodiment of the present invention has been described above. As described above, in one embodiment of the present invention, a plurality of transistors having a channel length of several nm or less, which is difficult to manufacture using a lithography method, can be manufactured accurately and easily within the plane of a substrate. I can do it. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements within the plane of a substrate can be manufactured. Further, in one embodiment of the present invention, a transistor can be manufactured that has a short channel length and has good electrical characteristics in which short channel effects are difficult to manifest. Further, in one embodiment of the present invention, a transistor can be manufactured with a fine element size including not only the channel length but also wiring and plugs. Further, in one embodiment of the present invention, the fine transistor described above can be manufactured, so that a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, the above semiconductor device can be manufactured with a high yield.

<Configuration example 2 of semiconductor device>
An example of the structure of a semiconductor device including the transistor 11 according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 shown in <Structure Example 1 of Semiconductor Device>, will be described below with reference to FIG.

FIG. 2A is a top view of a semiconductor device including the transistor 11. Further, FIG. 2(B) is a cross-sectional view of a portion indicated by a dashed line B1-B2 in FIG. 2(A). Further, FIG. 2(C) is a cross-sectional view of the portion indicated by the dashed line B3-B4 in FIG. 2(A). Here, the portion shown by the dashed-dotted line B1-B2 and the portion shown by the dashed-dotted line B3-B4 are orthogonal to each other. In the top view of FIG. 2A, some elements are omitted for clarity.

Note that in the semiconductor device shown in FIG. 2, structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> are given the same reference numerals. In addition, in the following, we will mainly explain the parts that are different from the semiconductor device explained in <Configuration Example 1 of Semiconductor Device>, and for other parts, we will refer to the contents explained in <Configuration Example 1 of Semiconductor Device>. It shall be possible.

As shown in FIGS. 2A and 2B, the semiconductor device shown in FIG. 2 has a conductor that functions as a source electrode or a drain electrode, and a plug that connects the conductor with upper and lower wirings. The semiconductor device shown in <Structure Example 1 of Semiconductor Device> has the transistor 11 provided facing each other with the conductor or the like sandwiching the oxide 150, the insulator 160, and the conductor 170. (See Figure 1.)

A semiconductor device of one embodiment of the present invention includes a transistor 11, an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as interlayer films over a substrate (not shown). 176, an insulator 178, and an insulator 180. Further, a conductor 185_1, a conductor 185_2, a conductor 200_1, and a conductor 200_2 are electrically connected to the transistor 11 and function as wiring, and a conductor 190_1, a conductor 190_2, a conductor 195_1, and a conductor 190_2 function as a plug. It has a conductor 195_2. Here, the conductor 185_1 and the conductor 185_2, the conductor 190_1 and the conductor 190_2, the conductor 195_1 and the conductor 195_2, and the conductor 200_1 and the conductor 200_2 are all the oxide 150, the insulator 160, and the conductor They are provided facing each other with 170 in between (see FIG. 2(B)).

The conductor 185_1 (conductor 185_2) is formed in an opening provided in the insulator 105. Here, the height of the top surface of the conductor 185_1 (conductor 185_2) and the height of the top surface of the insulator 105 are preferably approximately the same. Note that although the conductor 185_1 (conductor 185_2) is shown as having a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 185_1 (conductor 185_2) may have a laminated structure of two or more layers.

The conductor 190_1 (conductor 190_2) is formed in an opening provided in the insulator 110. The bottom surface of the conductor 190_1 (conductor 190_2) is provided so as to have a region in contact with the top surface of the conductor 185_1 (conductor 185_2). Here, the height of the top surface of the conductor 190_1 (conductor 190_2) and the height of the top surface of the insulator 110 are preferably approximately the same. Note that although the conductor 190_1 (conductor 190_2) is shown as having a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 190_1 (conductor 190_2) is a conductor made of a material that suppresses the permeation of impurities such as hydrogen and water, and oxygen, in contact with the inner wall of the opening provided in the insulator 110. It may be a laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed on the conductor.

The conductor 195_1 (conductor 195_2) is formed in an opening reaching the upper surface of the conductor 140_1 (conductor 140_2) provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180. Here, the height of the top surface of the conductor 195_1 (conductor 195_2) and the height of the top surface of the insulator 180 are preferably approximately the same. Note that although the conductor 195_1 (conductor 195_2) is illustrated as having a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 195_1 (conductor 195_2) , a conductor made of a material that suppresses the permeation of impurities such as hydrogen and water, and oxygen is formed in contact with the inner walls of the openings provided in the insulator 175, the insulator 176, the insulator 178, and the insulator 180. It may be a laminated structure of two or more layers in which a conductor made of a material having higher conductivity than the conductor is formed on the conductor.

The conductor 200_1 (conductor 200_2) is formed on the insulator 180 so as to have a region in contact with the upper surface of the conductor 195_1 (conductor 195_2). Note that although the conductor 200_1 (conductor 200_2) is shown as having a single-layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the conductor 200_1 (conductor 200_2) may have a laminated structure of two or more layers.

[Transistor 11]
As shown in FIG. 2B, the transistor 11 includes a conductor 120_1, a conductor 120_2, and an oxide 150 arranged over the insulator 110, and an insulator 130_1 arranged over the conductor 120_1. , an insulator 130_2 placed on the conductor 120_2, a conductor 140_1 placed on the insulator 130_1, a conductor 140_2 placed on the insulator 130_2, and an oxide 150 placed on the oxide 150. and a conductor 170 disposed on the insulator 160. Here, the conductor 120_1, the insulator 130_1, and the conductor 140_1 are opposed to each other with the oxide 150, the insulator 160, and the conductor 170 in between. It will be established as follows. Further, the oxide 150 is provided so as to have a region in contact with the mutually opposing side surfaces of the conductor 120_1, the insulator 130_1, and the conductor 140_1, and the conductor 120_2, the insulator 130_2, and the conductor 140_2. Further, the insulator 160 has a region facing the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) with the oxide 150 interposed therebetween. provided. Further, the conductor 170 is located in a region facing the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) via the oxide 150 and the insulator 160. It is provided so that it has.

As shown in FIG. 2(B) and FIG. 2(C), there is a layer on the conductor 120_1, the conductor 120_2, the insulator 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2 so as to cover them. An insulator 175 is provided. The insulator 175 is provided with an opening in which the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) partially overlap with the inner wall. An oxide 150 is provided along the inner wall, an insulator 160 is provided on the oxide 150, and a conductor 170 is provided on the insulator 160 so as to fill the opening. Here, as shown in FIG. 2B, the heights of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 are preferably approximately the same as the height of the top surface of the insulator 175. Note that although the oxide 150 is shown as having a single layer structure in FIG. 2B, one embodiment of the present invention is not limited to this. For example, the oxide 150 may have a laminated structure of two or more layers.

In the transistor 11, the conductor 120_1 has a function as one of a source electrode or a drain electrode, the conductor 140_1 has a function as the other of a source electrode or a drain electrode, and an insulator 130_1 of an oxide 150 The overlapping region functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode. Similarly, in the transistor 11, the conductor 120_2 has a function as either a source electrode or a drain electrode, and the conductor 140_2 has a function as the other source electrode or drain electrode. The region overlapping with the body 130_2 has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode.

That is, the transistor 11 includes one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductor 120_1 and conductor 140_1, conductor 120_2 and It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region of the oxide 150 overlapping with the insulator 130_1 and a region of the oxide 150 overlapping with the insulator 130_2). Alternatively, the transistor 11 includes a conductor 170 that functions as a gate electrode, an insulator 160 that functions as a gate insulator, and a conductor 120_1 and a conductor 140_1 that function as a source or drain electrode. A transistor including an oxide 150 (a region overlapping with the insulator 130_1) that functions as a channel formation region, a conductor 170 that functions as a gate electrode, and an insulator 160 that functions as a gate insulator. A transistor including a conductor 120_2 and a conductor 140_2 that function as a source electrode or a drain electrode, and an oxide 150 (a region overlapping with the insulator 130_2) that functions as a channel formation region. I can say that.

With the transistor 11 having the above configuration, the transistor 11 can output a larger drain current than the transistor 10 (see FIG. 1) included in the semiconductor device shown in <Configuration Example 1 of Semiconductor Device>. For example, a conductor 120_1 and a conductor 120_2 that function as either a source electrode or a drain electrode of the transistor 11 are electrically connected via a conductor 190_1, a conductor 185_1, a conductor 190_2, and a conductor 185_2. However, the case where the conductor 140_1 and the conductor 140_2, which function as the other of the source electrode or the drain electrode, are electrically connected via the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2. think. In this case, by applying a potential that turns on the transistor 11 to the conductor 170 that has a function as a gate electrode, the transistor 11 can be controlled to It is possible to output twice the drain current. Since the transistor 11 has the above-described electrical connection configuration, the transistor 11 occupies a smaller area than when two transistors 10 are simply installed together, and has a space equivalent to when two transistors 10 are installed together. Current output capability can be obtained.

Alternatively, the conductor 185_1 and the conductor 185_2 and the conductor 200_1 and the conductor 200_2 may not be electrically connected, and the two transistors forming the transistor 11 may be controlled independently. That is, the transistor 11 includes a conductor 170 that functions as a gate electrode, an insulator 160 that functions as a gate insulator, and a conductor 120_1 and a conductor 140_1 that function as a source electrode or a drain electrode. A transistor including an oxide 150 (a region overlapping with the insulator 130_1) that functions as a channel formation region, a conductor 170 that functions as a gate electrode, and an insulator 160 that functions as a gate insulator. A transistor consisting of a conductor 120_2 and a conductor 140_2 that function as a source electrode or a drain electrode, and an oxide 150 (a region overlapping with an insulator 130_2) that functions as a channel formation region is independently controlled. It is also possible to have a configuration in which

Note that in the transistor 11, the same material as the conductor 185 of the transistor 10 can be used for the conductor 185_1 (the conductor 185_2). Further, the same material as the conductor 190 of the transistor 10 can be used for the conductor 190_1 (conductor 190_2). Further, the same material as the conductor 120 of the transistor 10 can be used for the conductor 120_1 (the conductor 120_2). Further, the same material as the insulator 130 of the transistor 10 can be used for the insulator 130_1 (insulator 130_2). Further, the same material as the conductor 140 of the transistor 10 can be used for the conductor 140_1 (conductor 140_2). Further, the same material as the conductor 195 of the transistor 10 can be used for the conductor 195_1 (conductor 195_2). Further, the same material as the conductor 200 of the transistor 10 can be used for the conductor 200_1 (the conductor 200_2).

Regarding the configuration and effects of the semiconductor device including the transistor 11 other than those described above, the configuration and effects of the semiconductor device including the transistor 10 described in <Configuration Example 1 of Semiconductor Device> can be referred to.

In the above, a configuration example of a semiconductor device including the transistor 11 according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 10 shown in <Configuration Example 1 of Semiconductor Device>, has been described. As described above, in one embodiment of the present invention, a plurality of transistors having a channel length of several nm or less, which is difficult to manufacture using a lithography method, can be manufactured accurately and easily within the plane of a substrate. I can do it. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements within the plane of a substrate can be manufactured. Further, in one embodiment of the present invention, a transistor can be manufactured that has a short channel length and has good electrical characteristics in which short channel effects are difficult to manifest. Further, in one embodiment of the present invention, a transistor can be manufactured with a fine element size including not only the channel length but also wiring and plugs. Further, in one embodiment of the present invention, a transistor with a large on-state current can be manufactured despite being small. Further, in one embodiment of the present invention, the fine transistor described above can be manufactured, so that a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, the above semiconductor device can be manufactured with a high yield.

<Configuration example 3 of semiconductor device>
In the following, a semiconductor device according to one embodiment of the present invention that is different from the semiconductor device including the transistor 10 shown in <Structure Example 1 of a Semiconductor Device> and the semiconductor device including the transistor 11 shown in <Structure Example 2 of a Semiconductor Device> A configuration example of a semiconductor device including the transistor 12 will be described using FIG. 3.

FIG. 3A is a top view of a semiconductor device including the transistor 12. Further, FIG. 3(B) is a cross-sectional view of the portion shown by the dashed line C1-C2 in FIG. 3(A). Further, FIG. 3(C) is a cross-sectional view of the portion shown by the dashed line C3-C4 in FIG. 3(A). Here, the portion shown by the dashed-dotted line from C1-C2 and the portion shown by the dashed-dotted line from C3-C4 are orthogonal to each other. In the top view of FIG. 3A, some elements are omitted for clarity.

Note that in the semiconductor device shown in FIG. 3, structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device> are given the same reference numerals. ing. In addition, below, we will mainly explain the parts that are different from the semiconductor device described in <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device>, and other parts will be explained in <Configuration of Semiconductor Device The contents explained in Example 1> or <Configuration Example 2 of Semiconductor Device> can be taken into consideration.

As shown in FIGS. 3A and 3B, the semiconductor device shown in FIG. 3 has a conductor that functions as a source electrode or a drain electrode, and a plug that connects the conductor with upper and lower wirings. The semiconductor device shown in <Configuration Example 1 of Semiconductor Device> (see FIG. .) is different. Further, the oxide 150 is provided only in the region facing the side surface of the conductor 170 via the insulator 160 (oxide 150_1, oxide 150_2), and is not provided in the region overlapping the bottom surface of the conductor 170. This is different from the semiconductor device shown in <Configuration Example 2 of Semiconductor Device> (see FIG. 2) in that it is not.

A semiconductor device of one embodiment of the present invention includes a transistor 12, an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as interlayer films over a substrate (not shown). 176, an insulator 178, and an insulator 180. Further, a conductor 185_1, a conductor 185_2, a conductor 200_1, and a conductor 200_2 are electrically connected to the transistor 12 and function as wiring, and a conductor 190_1, a conductor 190_2, a conductor 195_1, and a conductor 190_2 function as a plug. It has a conductor 195_2. Here, the conductor 185_1, the conductor 190_1, the conductor 195_1, and the conductor 200_1, and the conductor 185_2, the conductor 190_2, the conductor 195_2, and the conductor 200_2 all refer to the insulator 160 and the conductor 170. They are provided so as to be sandwiched and face each other (see FIG. 3(B)).

Note that, in the semiconductor device shown in FIG. 3, the configuration can be applied to the conductor 185_1 (conductor 185_2), the conductor 190_1 (conductor 190_2), the conductor 195_1 (conductor 195_2), and the conductor 200_1 (conductor 200_2). Regarding this, the content explained in <Configuration Example 2 of Semiconductor Device> can be referred to.

[Transistor 12]
As shown in FIG. 3B, the transistor 12 includes a conductor 120_1, a conductor 120_2, an oxide 150_1, an oxide 150_2, and an insulator 160 arranged over the insulator 110, and an insulator 160 over the conductor 120_1. an insulator 130_1 placed on the conductor 120_2, an electric conductor 140_1 placed on the insulator 130_1, and a conductor 140_2 placed on the insulator 130_2. , and a conductor 170 disposed on the insulator 160. Here, the conductor 120_1 and the conductor 120_2, the insulator 130_1 and the insulator 130_2, the conductor 140_1 and the conductor 140_2, and the oxide 150_1 and the oxide 150_2 are all facing each other with the insulator 160 and the conductor 170 in between. It will be established as follows. Further, the oxide 150_1 (oxide 150_2) is the conductor 120_2 (conductor 120_1) of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2), It is provided so as to have a region in contact with the side surface facing the insulator 130_2 (insulator 130_1) and the conductor 140_2 (conductor 140_1). Further, the insulator 160 faces the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) via the oxide 150_1 (oxide 150_2). It is provided to have a region. The conductor 170 also connects the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) via the oxide 150_1 (oxide 150_2) and the insulator 160. It is provided so as to have a region facing the side surface of.

As shown in FIG. 3(B) and FIG. 3(C), there is a layer on the conductor 120_1, the conductor 120_2, the insulator 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2 so as to cover them. An insulator 175 is provided. The insulator 175 is provided with an opening in which the side surfaces of the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the conductor 140_1 (conductor 140_2) partially overlap with the inner wall. Oxide 150_1 and oxide 150_2 are provided along the inner wall (side surface), and cover the mutually facing side surfaces of oxide 150_1 and oxide 150_2 and the upper surface of insulator 110 between oxide 150_1 and oxide 150_2. An insulator 160 is provided, and a conductor 170 is provided on the insulator 160 so as to fill the opening. Here, as shown in FIG. 3B, the heights of the top surfaces of the oxide 150_1, the oxide 150_2, the insulator 160, and the conductor 170 are approximately the same as the height of the top surface of the insulator 175. is preferred. Note that although the oxide 150_1 (oxide 150_2) is shown as having a single-layer structure in FIG. 3B, one embodiment of the present invention is not limited to this. For example, the oxide 150_1 (oxide 150_2) may have a stacked structure of two or more layers.

In the transistor 12, the conductor 120_1 has a function as one of a source electrode or a drain electrode, the conductor 140_1 has a function as the other of a source electrode or a drain electrode, and an insulator 130_1 of an oxide 150_1 The overlapping region functions as a channel formation region, the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode. Similarly, in the transistor 12, the conductor 120_2 has a function as one of a source electrode or a drain electrode, the conductor 140_2 has a function as the other of a source electrode or a drain electrode, and The region overlapping with the body 130_2 has a function as a channel formation region, the insulator 160 has a function as a gate insulator, and the conductor 170 has a function as a gate electrode.

That is, the transistor 12 includes one gate electrode (conductor 170), one gate insulator (insulator 160), and two sets of source or drain electrodes (conductor 120_1 and conductor 140_1, conductor 120_2 and It can be said that the transistor includes a conductor 140_2) and two channel formation regions (a region of the oxide 150_1 overlapping with the insulator 130_1 and a region of the oxide 150_2 overlapping with the insulator 130_2). Alternatively, the transistor 12 includes a conductor 170 that functions as a gate electrode, an insulator 160 that functions as a gate insulator, and a conductor 120_1 and a conductor 140_1 that function as a source electrode or a drain electrode. A transistor including an oxide 150_1 (a region overlapping with the insulator 130_1) that functions as a channel formation region, a conductor 170 that functions as a gate electrode, and an insulator 160 that functions as a gate insulator. A transistor including a conductor 120_2 and a conductor 140_2 that function as a source electrode or a drain electrode, and an oxide 150_2 (a region overlapping with the insulator 130_2) that functions as a channel formation region. I can say that.

With the transistor 12 having the above configuration, the transistor 12 can output a larger drain current than the transistor 10 (see FIG. 1) included in the semiconductor device shown in <Configuration Example 1 of Semiconductor Device>. For example, a conductor 120_1 and a conductor 120_2 that function as either a source electrode or a drain electrode of the transistor 12 are electrically connected via a conductor 190_1, a conductor 185_1, a conductor 190_2, and a conductor 185_2. However, the case where the conductor 140_1 and the conductor 140_2, which function as the other of the source electrode or the drain electrode, are electrically connected via the conductor 195_1, the conductor 200_1, the conductor 195_2, and the conductor 200_2. think. In this case, by applying a potential at which the transistor 12 is turned on to the conductor 170 that functions as a gate electrode, the transistor 12 can be controlled to It is possible to output twice the drain current. Since the transistor 12 has the above-described electrical connection configuration, the transistor 12 occupies a smaller area than when two transistors 10 are simply installed together, and has a space equivalent to when two transistors 10 are installed together. Current output capability can be obtained.

Alternatively, a configuration may be adopted in which the two transistors forming the transistor 12 are controlled independently, without electrically connecting the conductor 185_1 and the conductor 185_2, and the conductor 200_1 and the conductor 200_2. That is, the transistor 12 includes a conductor 170 that functions as a gate electrode, an insulator 160 that functions as a gate insulator, and a conductor 120_1 and a conductor 140_1 that function as a source or drain electrode. A transistor including an oxide 150_1 (a region overlapping with the insulator 130_1) that functions as a channel formation region, a conductor 170 that functions as a gate electrode, and an insulator 160 that functions as a gate insulator. A transistor consisting of a conductor 120_2 and a conductor 140_2 that function as a source electrode or a drain electrode, and an oxide 150_2 (a region overlapping with an insulator 130_2) that functions as a channel formation region is independently controlled. It is also possible to have a configuration in which

Here, the transistor 12 included in the semiconductor device shown in FIG. 3 is different from the transistor 11 included in the semiconductor device shown in FIG. 2 in the shape of an oxide having a channel formation region. Specifically, the transistor 11 is connected to side surfaces of the conductor 120_1, the insulator 130_1, and the conductor 140_1, the conductor 120_2, the insulator 130_2, and the conductor 140_2 that face each other, and a part of the upper surface of the insulator 110. The transistor 12 has an oxide 150 that is in contact with the conductor 120_1, the insulator 130_1, and the conductor 140_1, and the oxide 150 that is in contact with the conductor 120_1, the insulator 130_1, and the conductor 140_1, which are in contact with the conductor 120_2, the insulator 130_2, and the conductor 140_2. The oxide 150_2 is in contact with the conductor 120_2, the insulator 130_2, and the side surface of the conductor 140_2 that faces the conductor 120_1, the insulator 130_1, and the conductor 140_1. That is, in the transistor 12, the oxide 150 of the transistor 11 is divided into two parts (oxide 150_1 and oxide 150_2) with the insulator 160 and the conductor 170 in between. different from. The oxide having the channel forming region has conductivity. Therefore, for example, when the two transistors forming the transistor 12 described above are controlled independently, leakage through the oxide can be suppressed between the two transistors. This makes it difficult for the other transistor to be affected by the operation (on operation, off operation) of one transistor constituting the transistor 12, and the operations of each transistor can be reliably controlled.

Note that in the transistor 12, the same material as the oxide 150 of the transistor 10 can be used for the oxide 150_1 (oxide 150_2). Further, the same material as the conductor 185 of the transistor 10 can be used for the conductor 185_1 (the conductor 185_2). Further, the same material as the conductor 190 of the transistor 10 can be used for the conductor 190_1 (conductor 190_2). Further, the same material as the conductor 120 of the transistor 10 can be used for the conductor 120_1 (conductor 120_2). Further, the same material as the insulator 130 of the transistor 10 can be used for the insulator 130_1 (insulator 130_2). Further, the same material as the conductor 140 of the transistor 10 can be used for the conductor 140_1 (conductor 140_2). Further, the same material as the conductor 195 of the transistor 10 can be used for the conductor 195_1 (conductor 195_2). Further, the same material as the conductor 200 of the transistor 10 can be used for the conductor 200_1 (the conductor 200_2).

In the semiconductor device including the transistor 12, configurations and effects other than those described above are explained in the semiconductor device including the transistor 10 described in <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device> The configuration and effects of a semiconductor device including the transistor 11 described above can be considered.

In the above description, the semiconductor device according to one embodiment of the present invention is different from the semiconductor device including the transistor 10 shown in <Structure Example 1 of a Semiconductor Device> or the semiconductor device including the transistor 11 shown in <Structure Example 2 of a Semiconductor Device>. A configuration example of a semiconductor device including the transistor 12 has been described. As described above, in one embodiment of the present invention, a plurality of transistors having a channel length of several nm or less, which is difficult to manufacture using a lithography method, can be manufactured accurately and easily within the plane of a substrate. I can do it. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements within the plane of a substrate can be manufactured. Further, in one embodiment of the present invention, a transistor can be manufactured that has a short channel length and has good electrical characteristics in which short channel effects are difficult to manifest. Further, in one embodiment of the present invention, a transistor can be manufactured with a fine element size including not only the channel length but also wiring and plugs. Further, in one embodiment of the present invention, a transistor with a large on-state current can be manufactured despite being small. Further, in one embodiment of the present invention, the fine transistor described above can be manufactured, so that a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, a semiconductor device that is highly integrated and has small leakage between adjacent transistors can be manufactured. Further, in one embodiment of the present invention, the above semiconductor device can be manufactured with a high yield.

<Modified example of semiconductor device>
Below, as a modification of the semiconductor device including the transistor 10 shown in <Structure Example 1 of Semiconductor Device>, a semiconductor device including the transistor 13 according to one embodiment of the present invention will be described with reference to FIG.

FIG. 4A is a top view of a semiconductor device including the transistor 13. Further, FIG. 4(B) is a cross-sectional view of a portion indicated by a dashed line D1-D2 in FIG. 4(A). Further, FIG. 4(C) is a cross-sectional view of a portion indicated by a dashed line D3-D4 in FIG. 4(A). Here, the portion shown by the dashed-dotted line D1-D2 and the portion shown by the dashed-dotted line D3-D4 are orthogonal to each other. In the top view of FIG. 4A, some elements are omitted for clarity.

In the semiconductor device shown in FIG. 4, structures having the same functions as the structures configuring the semiconductor devices shown in <Configuration Example 1 of Semiconductor Device> to <Configuration Example 3 of Semiconductor Device> are given the same reference numerals. ing. In addition, below, we will mainly explain the parts that are different from the semiconductor devices described in <Configuration Example 1 of Semiconductor Device> to <Configuration Example 3 of Semiconductor Device>, and other parts will be explained in <Configuration Example of Semiconductor Device The contents explained in Example 1 to <Configuration Example 3 of Semiconductor Device> can be referred to.

As shown in FIGS. 4B and 4C, the semiconductor device shown in FIG. The point is that the transistor 13 has a region that overlaps not only the side surfaces of the conductor 120, the insulator 130, and the conductor 140 but also a part of the top surface of the conductor 140 via the functional insulator 161. This is different from the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> (see FIG. 1).

A semiconductor device of one embodiment of the present invention includes a transistor 13, an insulator 100, an insulator 102, an insulator 105, an insulator 110, an insulator 175, and an insulator that function as interlayer films over a substrate (not shown). 176, an insulator 178, and an insulator 180. The semiconductor device also includes a conductor 185 and a conductor 200 that are electrically connected to the transistor 13 and function as wiring, and a conductor 190 and a conductor 195 that function as a plug.

In addition, in the semiconductor device shown in FIG. 4, regarding the configuration that can be applied to the conductor 185, the conductor 190, the conductor 195, and the conductor 200, the content explained in <Configuration Example 1 of the Semiconductor Device> may be referred to. can.

[Transistor 13]
As shown in FIG. 4B, the transistor 13 includes a conductor 120 and an oxide 151 disposed on the insulator 110, an insulator 130 disposed on the conductor 120, and an oxide 151 disposed on the insulator 110. A conductor 140 is disposed on the conductor 140, an insulator 161 is disposed on the oxide 151, and a conductor 171 is disposed on the insulator 161. Here, the oxide 151 is provided so as to have a region in contact with the side surfaces of the conductor 120, the insulator 130, and the conductor 140, and a part of the upper surface of the conductor 140. Further, the insulator 161 is provided so as to have a region that overlaps with the side surfaces of the conductor 120, the insulator 130, and the conductor 140, and a part of the upper surface of the conductor 140, with the oxide 151 interposed therebetween. Further, the conductor 171 has a region that overlaps the side surfaces of the conductor 120, the insulator 130, and the conductor 140 and a part of the upper surface of the conductor 140 via the oxide 151 and the insulator 161. established in

As shown in FIG. 4B, an insulator 175 is provided over the conductor 120, the insulator 130, and the conductor 140 so as to cover them. The insulator 175 is provided with an opening in which a portion of the inner wall overlaps the side surfaces of the conductor 120, the insulator 130, and the conductor 140, and a portion of the upper surface of the conductor 140, and an opening is formed along the inner wall of the opening. An oxide 151 is provided on the oxide 151, an insulator 161 is provided on the oxide 151, and a conductor 171 is provided on the insulator 161 so as to fill the opening. Here, as shown in FIG. 4B, the heights of the top surfaces of the oxide 151, the insulator 161, and the conductor 171 are preferably approximately the same as the height of the top surface of the insulator 175. Note that although the oxide 151 is shown as having a single layer structure in FIG. 4B, one embodiment of the present invention is not limited to this. For example, the oxide 151 may have a laminated structure of two or more layers.

In the transistor 13, the conductor 120 has a function as one of a source electrode or a drain electrode, and the conductor 140 has a function as the other of a source electrode or a drain electrode. The overlapping region functions as a channel formation region, the insulator 161 functions as a gate insulator, and the conductor 171 functions as a gate electrode.

Here, while the transistor 10 has a contact surface between the oxide 150 and the insulator 130 at only one location shown in FIG. The difference is that there are three locations in total, one location shown in FIG. 4(B) and two locations shown in FIG. 4(C). That is, the transistor 10 and the transistor 13 have a difference in the area of the region that can function as a channel formation region in the oxides (oxide 150 or oxide 151) that they each have (transistor 13 has a larger area than transistor 10). , the area of oxide that can function as a channel forming region is large). Therefore, the transistor 13 can output a larger drain current than the transistor 10 even though the element size is about the same as that of the transistor 10.

Further, the transistor 13 differs from the transistor 10 in that the conductor 171 functioning as a gate electrode has a region overlapping a part of the upper surface of the conductor 140. When the transistor 13 has this structure, a channel formation region (a region of the oxide 151 that overlaps with the insulator 130) can be surrounded by the conductor 171, as shown in FIG. 4C. Therefore, compared to the transistor 10, the transistor 13 can more reliably control the application of the gate electric field to the channel formation region. Therefore, the transistor 13 can reliably control carriers during operation (on operation, off operation), and can realize both a larger on-current and a smaller off-current than the transistor 10.

Note that in the transistor 13, the same material as the oxide 150 of the transistor 10 can be used for the oxide 151. Further, the same material as the insulator 160 of the transistor 10 can be used for the insulator 161. Further, the same material as the conductor 170 of the transistor 10 can be used for the conductor 171.

Regarding the structure and effects of the semiconductor device including the transistor 13 other than those described above, the semiconductor device including the transistor 10 described in <Configuration Example 1 of Semiconductor Device> and <Configuration Example 2 of Semiconductor Device> are explained. The structure and effects of the semiconductor device having the transistor 11 or the semiconductor device having the transistor 12 described in <Structure Example 3 of Semiconductor Device> can be taken into consideration.

The example of the structure of the semiconductor device including the transistor 13 according to one embodiment of the present invention has been described above as a modification of the semiconductor device including the transistor 10 shown in <Structure Example 1 of Semiconductor Device>. As described above, in one embodiment of the present invention, a plurality of transistors having a channel length of several nm or less, which is difficult to manufacture using a lithography method, can be manufactured accurately and easily within the plane of a substrate. I can do it. Further, in one embodiment of the present invention, a transistor with small variations in electrical characteristics between elements within the plane of a substrate can be manufactured. Further, in one embodiment of the present invention, a transistor with large on-state current can be manufactured. Further, in one embodiment of the present invention, a transistor with low off-state current can be manufactured. Further, in one embodiment of the present invention, a transistor can be manufactured that has a short channel length and has good electrical characteristics in which short channel effects are difficult to manifest. Further, in one embodiment of the present invention, a transistor can be manufactured with a fine element size including not only the channel length but also wiring and plugs. Furthermore, in one embodiment of the present invention, the fine transistor described above can be manufactured, so that a semiconductor device including the transistor can be highly integrated. Further, in one embodiment of the present invention, the above semiconductor device can be manufactured with a high yield.

An example of a semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device having the transistor 10, the transistor 11, the transistor 12, or the transistor 13 described above (see FIGS. 1 to 4). A semiconductor device according to one embodiment of the present invention can be used by appropriately combining the structures of the semiconductor devices described above.

<Components of semiconductor device>
Each component that can be applied to a semiconductor device (see FIGS. 1 to 4) including the transistor 10, the transistor 11, the transistor 12, or the transistor 13 according to one embodiment of the present invention will be described in detail below.

〔substrate〕
As the substrate, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator) substrate. Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there may be a substrate having a metal nitride, a substrate having a metal oxide, or the like. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.

Furthermore, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor on a flexible substrate, there is also a method in which a transistor is manufactured on a non-flexible substrate, the transistor is peeled off, and the transistor is transferred to a flexible substrate. In that case, a release layer may be provided between the non-flexible substrate and the transistor. Note that a sheet, film, or foil in which fibers are woven may be used as the substrate. Further, the substrate may have elasticity. Further, the substrate may have the property of returning to its original shape when it is no longer bent or stretched. Alternatively, it may have the property of not returning to its original shape. The substrate has a region having a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By making the substrate thinner, a semiconductor device including a transistor can be made lighter. Furthermore, by making the substrate thinner, it may have elasticity even when glass or the like is used, or it may have the property of returning to its original shape when it is no longer bent or stretched. Therefore, the impact applied to the semiconductor device on the substrate due to dropping or the like can be alleviated. That is, a durable semiconductor device can be provided.

As the flexible substrate, for example, metal, alloy, resin, glass, or fibers thereof can be used. It is preferable that the flexible substrate has a lower linear expansion coefficient, since deformation caused by the environment is suppressed. As the flexible substrate, for example, a material having a coefficient of linear expansion of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. In particular, aramid has a low coefficient of linear expansion, so it is suitable as a flexible substrate.

〔Insulator〕
Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.

Examples of the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), and the insulator 160 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, An insulator containing silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stacked layer. For example, the insulator 100, the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), and the insulator 160 may include silicon oxide, silicon oxynitride, or silicon nitride. preferable.

The concentration of impurities such as water, hydrogen, or nitrogen oxide in the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1, the insulator 130_2) is preferably reduced. For example, the amount of hydrogen desorbed from the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1, the insulator 130_2) is determined by thermal desorption spectroscopy (TDS). When the surface temperature of the film is in the range of 50°C to 500°C, the amount of desorption in terms of hydrogen molecules is per area of the insulator 105, insulator 110, or insulator 130 (or insulator 130_1, insulator 130_2). In terms of this, it may be 2×10 ¹⁵ molecules/cm ² or less, preferably 1×10 ¹⁵ molecules/cm ² or less, more preferably 5×10 ¹⁴ molecules/cm ² or less. Further, the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) are preferably formed using an insulator that releases oxygen when heated. By using the insulator for the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1, the insulator 130_2), the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1) , the insulator 130_2) to the oxide 150 (or the oxide 150_1, the oxide 150_2).

Moreover, it is preferable that the insulator 160 has an insulator with a high dielectric constant. For example, the insulator 160 may include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxide containing silicon and hafnium, etc. It is preferable to use a nitride or a nitride containing silicon and hafnium. Alternatively, the insulator 160 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Silicon oxide and silicon oxynitride are thermally stable, so by combining them with an insulator with a high relative dielectric constant, it is possible to create a layered structure with fewer defects that is thermally stable and has a high relative dielectric constant. .

The insulator 160 is preferably disposed in contact with the upper surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2). The insulator 160 is preferably formed using an insulator that releases oxygen when heated. By providing such an insulator 160 in contact with the upper surface of the oxide 150 (or oxide 150_1, oxide 150_2), oxygen can be effectively supplied to the oxide 150 (or oxide 150_1, oxide 150_2). can be supplied. Further, similarly to the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1, the insulator 130_2), it is preferable that the concentration of impurities such as water or hydrogen in the insulator 160 is reduced. . The thickness of the insulator 160 is preferably 1 nm or more and 20 nm or less, and may be approximately 1 nm thick, for example.

Preferably, the insulator 160 contains oxygen. For example, in temperature programmed desorption gas spectroscopy analysis (TDS analysis), the amount of oxygen molecules desorbed per area of the insulator 160 is measured at a surface temperature range of 100°C to 700°C or 100°C to 500°C. It is sufficient if it is converted to 1×10 ¹⁴ molecules/cm ² or more, preferably 2×10 ¹⁴ molecules/cm ² or more, more preferably 4×10 ¹⁴ molecules/cm ² or more.

It is preferable that the insulator 175, the insulator 176, and the insulator 180 have an insulator with a low dielectric constant. For example, the insulator 175, the insulator 176, and the insulator 180 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, etc. It is preferable to use silicon oxide, silicon oxide with pores, resin, or the like. Alternatively, the insulator 175, the insulator 176, and the insulator 180 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, or silicon oxide added with carbon and nitrogen. It is preferable to have a laminated structure of silicon oxide or silicon oxide having pores and a resin. Silicon oxide and silicon oxynitride are thermally stable, so by combining them with resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Note that the insulator 175, the insulator 176, and the insulator 180 are similar to the insulator 105, the insulator 110, the insulator 130 (or the insulator 130_1, the insulator 130_2), the insulator 160, etc. Preferably, the concentration of impurities such as water or hydrogen is reduced.

Further, as the insulator 102 and the insulator 178, it is preferable to use an insulator that has high barrier properties against impurities such as hydrogen and water and oxygen. By using the insulator for the insulator 102 and the insulator 178, hydrogen and water can be absorbed from the lower side (upper side) of the insulator 102 (insulator 178) into the transistor 10, transistor 11, transistor 12, or transistor 13. It is possible to suppress the contamination of impurities such as. Further, oxygen in the transistor 10, the transistor 11, the transistor 12, or the transistor 13 can be suppressed from diffusing below (above) the insulator 102 (the insulator 178). The insulator includes, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. It is preferable to use a single layer or a laminated layer.

For example, the insulator may be a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or Silicon nitride or the like may be used. Note that the insulator preferably includes aluminum oxide, hafnium oxide, or the like.

〔conductor〕
Conductor 120 (or conductor 120_1, conductor 120_2), conductor 140 (or conductor 140_1, conductor 140_2), conductor 185 (or conductor 185_1, conductor 185_2), conductor 190 (or , conductor 190_1, conductor 190_2), conductor 195 (or conductor 195_1, conductor 195_2), conductor 200 (or conductor 200_1, conductor 200_2), and conductor 170, such as aluminum or chromium. , copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Can be used. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Further, as the conductor, particularly the conductor 170, a conductive material containing oxygen and a metal element contained in a metal oxide applicable to the oxide 150 (or oxide 150_1, oxide 150_2) may be used. good. Further, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide 150 (or the oxide 150_1 or the oxide 150_2) can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed in from an external insulator or the like.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

Note that when an oxide is used for the channel formation region of the transistor, it is preferable to use a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined as the gate electrode. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.

Note that the conductor 185 (or the conductor 185_1, the conductor 185_2), the conductor 190 (or the conductor 190_1, the conductor 190_2), the conductor 195 (or the conductor 195_1, the conductor 195_2), and the conductor As the conductor 200 (or the conductor 200_1, the conductor 200_2), a conductive material with high embeddability, such as tungsten or polysilicon, may be used, for example. Further, a conductive material with high embeddability and a conductive barrier film such as titanium, titanium nitride, tantalum nitride, etc. may be used in combination.

[Oxide]
It is preferable to use a metal oxide as the oxide 150 (or the oxide 150_1, the oxide 150_2). However, instead of the oxide 150, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used as the semiconductor material. There are cases where it doesn't matter. A metal oxide that is preferably used for the oxide 150 (or oxide 150_1, oxide 150_2) according to one embodiment of the present invention will be described below.

Preferably, the metal oxide contains at least indium or zinc. In particular, it is preferable to include indium and zinc. Moreover, in addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, a case will be considered in which the metal oxide is InMZnO containing indium, element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above-mentioned elements may be combined.

By using the above metal oxide in a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Further, a transistor with good reliability can be realized.

A transistor using a metal oxide in a channel formation region has extremely small leakage current in a non-conducting state, so a semiconductor device with low power consumption can be provided. Furthermore, since metal oxides can be formed into films using sputtering methods or the like, they can be used for transistors included in highly integrated semiconductor devices.

Further, it is preferable to use a metal oxide with low carrier density for the channel formation region of the transistor. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be lowered to lower the defect level density. In this specification and the like, the term "high purity intrinsic" or "substantially high purity intrinsic" means that the impurity concentration is low and the defect level density is low. For example, the metal oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and 1×10 ⁻⁹ /cm 3 . cm ³ or more.

Further, since a metal oxide film that is highly pure or substantially pure has a low defect level density, the trap level density may also be low.

Furthermore, charges captured in the trap levels of metal oxides take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in a metal oxide with a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the metal oxide. Furthermore, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

Here, the influence of each impurity in the metal oxide will be explained.

When a metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon near the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are ×10 ¹⁸ atoms/cm ³ or less, preferably 2 × 10 ¹⁷ atoms/cm ³ or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, the metal may form a defect level in the metal oxide and generate carriers. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, when nitrogen is contained in a metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to become n-type. As a result, a transistor in which a metal oxide containing nitrogen is used in a channel formation region tends to have normally-on characteristics. Therefore, it is preferable that the metal oxide contains as little nitrogen as possible. For example, the nitrogen concentration in the metal oxide is determined by SIMS to be less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further Preferably it is 5×10 ¹⁷ atoms/cm ³ or less.

Furthermore, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used in a channel formation region tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the metal oxide be reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably 5×10 ¹⁸ atoms/cm It is less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using a metal oxide with sufficiently reduced impurities in a channel formation region of a transistor, stable electrical characteristics can be provided.

Below, CAC-OS will be explained in detail. CAC-OS is an example of a function or material structure that a metal oxide of a transistor according to one embodiment of the present invention can have.

CAC-OS is, for example, a structure of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In addition, in the following, in a metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The mixed state is also called mosaic or patch.

For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO among CAC-OS) is indium oxide (hereinafter, InO _X1 (X1 is a real number greater than 0), or indium zinc oxide (hereinafter In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)), and gallium. oxide (hereinafter referred to as GaO _X3 ( _X3 is a real number larger than ₀ )), or gallium zinc _oxide (hereinafter referred to as Ga ), _the material separates into _a mosaic _- like structure, and the mosaic-like _InO be.

In other words, CAC-OS is a composite metal oxide having a configuration in which a region whose main component is GaO _X3 and a region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 are mixed. Note that, in this specification, for example, the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than that in region 2.

Note that IGZO is a common name and may refer to one compound made of In, Ga, Zn, and O. As a typical example, it is expressed as InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1-x0) O ₃ (ZnO) _m0 (-1≦x0≦1, m0 is an arbitrary number) Examples include crystalline compounds.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to the material composition of metal oxides. CAC-OS is a material composition containing In, Ga, Zn, and O, with some regions observed as nanoparticles containing Ga as the main component and some nanoparticles containing In as the main component. This refers to a configuration in which regions observed in a shape are randomly distributed in a mosaic shape. Therefore, in CAC-OS, crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more types of films with different compositions. For example, a structure consisting of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

Note that it may be difficult to observe a clear boundary between a region where GaO _X3 is the main component and a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component.

In addition, instead of gallium, a metal selected from aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be used. When one or more types are included, CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element, and a region observed in the form of nanoparticles mainly composed of In. This refers to a configuration in which the regions observed in the image are randomly distributed in a mosaic pattern.

The CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. Furthermore, when forming the CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas is used as the film-forming gas. Bye. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation, the better. For example, the flow rate ratio of oxygen gas is set to 0% or more and less than 30%, preferably 0% or more and less than 10%.

CAC-OS is characterized by the fact that no clear peaks are observed when it is measured using a θ/2θ scan using the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. has. That is, it can be seen from the X-ray diffraction that no orientation in the a-b plane direction or the c-axis direction of the measurement region is observed.

Furthermore, in the electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), CAC-OS has a ring-shaped region with high brightness and a plurality of rings in the ring region. A bright spot is observed. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure with no orientation in the plane direction and the cross-sectional direction.

Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals that _GaO It can be confirmed that the region and the region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and have a mixed structure.

CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. In other words, CAC-OS has phase separation between a region where GaO _X3 is the main component and a region where _InX2 Zn _Y2 O _Z2 or _InO It has a mosaic-like structure.

Here, the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component is a region with higher conductivity than the region where GaO _X3 or the like is the main component. That is, carriers flow through the region where _InX2ZnY2OZ2 or _{InOX1 is} the main component, thereby exhibiting conductivity as _a metal oxide. Therefore, by distributing regions mainly composed of In _X2 Zn _Y2 O _Z2 or _InO can.

On the other hand, a region whose main component is GaO _X3 or the like has higher insulation than a region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 . That is, by distributing a region mainly composed of GaO _X3 or the like in the metal oxide, a transistor using the metal oxide can suppress leakage current and achieve good switching operation.

Therefore, when CAC-OS is used in a semiconductor device _such as _{a transistor} , the conductivity caused _{by In} This makes it possible to achieve both high on-current and low off-current.

Furthermore, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is optimally used in various semiconductor devices such as display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, processors, and electronic devices.

<Method for manufacturing semiconductor device>
An example of a method for manufacturing a semiconductor device including the transistor 10 according to one embodiment of the present invention will be described below with reference to FIGS. 5 to 10. 5 to 10, (A) in each figure is a top view of a semiconductor device having the transistor 10. In FIGS. Further, (B) in each figure is a cross-sectional view of the portion indicated by the dashed line A1-A2 in (A) of each figure. Further, (C) of each figure is a cross-sectional view of the portion indicated by the dashed line A3-A4 in (A) of each figure. In addition, in the method for manufacturing a semiconductor device having a transistor 10 described below, for specific materials of each component (substrate, insulator, conductor, oxide, etc.) that can be applied to the semiconductor device, see <Semiconductor Device Please take into account the contents explained in Component Elements.

First, a substrate (not shown) is prepared.

Next, an insulator 100 is formed on the substrate. The insulator 100 can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or ALD (Atomic Layer Deposition) method, etc. can be used.

The CVD method can be classified into plasma enhanced CVD (PECVD) that uses plasma, thermal CVD (TCVD) that uses heat, photo CVD (photo CVD) that uses light, etc. . Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

Further, the ALD method is also a film forming method that can reduce plasma damage to the object to be processed. Furthermore, since plasma damage does not occur during film formation in the ALD method, a film with fewer defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object, unlike film forming methods in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed by changing the flow rate ratio of source gases. Further, for example, in the CVD method and the ALD method, by changing the flow rate ratio of the raw material gas while forming the film, it is possible to form a film in which the composition changes continuously. When forming a film while changing the flow rate ratio of raw material gases, the time required for film formation is reduced because the time required for transportation and pressure adjustment, which is required when forming films using multiple film formation chambers, is eliminated. be able to. Therefore, it may be possible to improve the productivity of semiconductor devices.

In this embodiment, a silicon oxide film is formed as the insulator 100 by a CVD method. Note that as the insulator 100, for example, silicon oxynitride may be used instead of silicon oxide.

Next, an insulator 102 is formed on the insulator 100. The insulator 102 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is formed into a film as the insulator 102 by a sputtering method. Further, the insulator 102 may have a multilayer structure. For example, a structure may be adopted in which aluminum oxide is formed into a film by a sputtering method, and then aluminum oxide is formed into a film by an ALD method on the aluminum oxide. Alternatively, a structure may be adopted in which aluminum oxide is formed into a film by an ALD method, and then aluminum oxide is formed into a film by a sputtering method on the aluminum oxide.

Next, an insulator 105 is formed on the insulator 102. The insulator 105 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 105 by a CVD method. Note that as the insulator 105, for example, silicon oxynitride may be used instead of silicon oxide.

Next, an opening reaching the insulator 102 is formed in the insulator 105. Here, the opening includes, for example, a groove or a slit. Further, an area in which an opening is formed may be referred to as an opening. Although a wet etching method may be used to form the opening, it is preferable to use a dry etching method for fine processing. Further, it is preferable to select an insulator for the insulator 102 that functions as an etching stopper film when etching the insulator 105 to form an opening. For example, when a silicon oxide film is used for the insulator 105 forming the opening, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used for the insulator 102.

After forming the opening, a conductor that will become the conductor 185 is formed. Here, the conductor 185 has a laminated structure consisting of a conductor 185a (not shown) having a function of suppressing oxygen permeation and a conductor 185b (not shown) having higher conductivity than the conductor 185a. It is preferable that

The conductor that becomes the conductor 185a preferably includes a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. The conductor that becomes the conductor 185a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride, or a film in which titanium nitride is stacked on tantalum nitride, is formed by a sputtering method as the conductor 185a. By using such a metal nitride as the conductor 185a, even if a metal that easily diffuses, such as copper, is used as the conductor 185b (described later), the metal can be prevented from diffusing out from the conductor 185a. It can be prevented.

Next, a conductor that will become the conductor 185b is formed on the conductor that will become the conductor 185a. The conductor that becomes the conductor 185b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed into a film as the conductor that becomes the conductor 185b.

Next, by performing a chemical mechanical polishing (CMP) process, the conductor that will become the conductor 185a and a part of the conductor that will become the conductor 185b are removed, and the insulator 105 is exposed. As a result, the conductor that will become the conductor 185a and the conductor that will become the conductor 185b remain only in the opening. As a result, a conductor 185 including a conductor 185a and a conductor 185b having a flat upper surface can be formed (see FIG. 5). Note that part of the insulator 105 may be removed by the CMP process.

Next, an insulator 110 is formed over the insulator 105 and the conductor 185. The insulator 110 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 110 by a CVD method. Note that as the insulator 110, for example, silicon oxynitride may be used instead of silicon oxide.

Here, a first heat treatment may be performed. The first heat treatment may be performed, for example, at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed in an atmosphere of nitrogen gas or inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment is heat treatment in an atmosphere of nitrogen gas or inert gas, and then heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. You may do so. The first heat treatment can reduce impurities such as hydrogen and water contained in the insulator 110 and the insulator 105. Alternatively, in the first heat treatment, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use, for example, an apparatus having a power source that generates high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 110 and the insulator 105. be able to. Alternatively, after plasma processing containing an inert gas is performed using this apparatus, plasma processing containing oxygen may be performed in order to compensate for the desorbed oxygen.

Next, an opening reaching the conductor 185 is formed in the insulator 110. Although a wet etching method may be used to form the opening, it is preferable to use a dry etching method for fine processing.

After forming the opening, a conductor that will become the conductor 190 is formed. Here, the conductor 190 has a laminated structure consisting of a conductor 190a (not shown) having a function of suppressing oxygen permeation and a conductor 190b (not shown) having higher conductivity than this conductor 190a (not shown). It is preferable.

The conductor that becomes the conductor 190a preferably includes a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. A film of the conductor to become the conductor 190a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, a film of tantalum nitride is formed by a sputtering method as a conductor to become the conductor 190a.

Next, a conductor that will become the conductor 190b is formed over the conductor that will become the conductor 190a. The conductor can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, a titanium nitride film is formed as a conductor to become the conductor 190b by an ALD method, and a tungsten film is formed over the titanium nitride by a CVD method.

Next, by performing a CMP process, the conductor that will become the conductor 190a and a part of the conductor that will become the conductor 190b are removed to expose the insulator 110. As a result, the conductor that will become the conductor 190a and the conductor that will become the conductor 190b remain only in the opening. As a result, a conductor 190 including a conductor 190a and a conductor 190b having a flat upper surface can be formed (see FIG. 5). Note that a portion of the insulator 110 may be removed by the CMP process.

Next, a conductor 120a is formed on the insulator 110 and the conductor 190. The conductor 120a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the conductor 120a, for example, a conductor such as tantalum nitride, tungsten, titanium nitride, etc. can be used. Alternatively, for example, a structure may be adopted in which a tungsten film is formed and a conductor having a function of suppressing oxygen permeation, such as titanium nitride or tantalum nitride, is formed on the tungsten. With this configuration, it is possible to prevent tungsten from being oxidized by oxygen mixed in from above the conductor 120a and increasing the electrical resistance value.

Alternatively, the conductor 120a may be an oxide having conductivity, such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium containing titanium oxide. oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon, or indium gallium zinc oxide containing nitrogen, and on the oxide, aluminum, chromium, Materials containing one or more metal elements selected from copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc., or phosphorus. It is also possible to form a film of a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as silicide, or silicide such as nickel silicide.

The oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffused from the outside, and the electrical characteristics and reliability of the transistor 10 may be improved. Alternatively, even if titanium is used instead of the oxide, the same function may be obtained.

In this embodiment, a tungsten film is formed as the conductor 120a by a sputtering method.

Next, an insulator 130a is formed on the conductor 120a. The insulator 130a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 130a by a CVD method. Note that as the insulator 130a, for example, silicon oxynitride may be used instead of silicon oxide.

Here, a second heat treatment may be performed. The second heat treatment can use the conditions of the first heat treatment. Through the heat treatment, impurities such as hydrogen and water contained in the insulator 130a can be reduced. Additionally, oxygen can be supplied into the insulator 130a.

Alternatively, an ion implantation method in which ionized source gas is added after mass separation, an ion doping method in which ionized source gas is added without mass separation, or a plasma immersion ion implantation method is used to add the ionized source gas into the insulator 130a. Oxygen may be supplied to the

The insulator 130a can have excess oxygen by the above-described heat treatment, ion implantation method, or the like. The excess oxygen is supplied into the oxide 150 through later heat treatment or the like, and the electrical characteristics and reliability of the transistor 10 may be improved.

Next, a conductor 140a is formed on the insulator 130a (see FIG. 6). The conductor 140a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the conductor 140a, for example, a conductor such as tantalum nitride, tungsten, titanium nitride, etc. can be used. Alternatively, for example, a structure may be adopted in which a conductor such as titanium nitride or tantalum nitride that has a function of suppressing permeation of oxygen is deposited, and tungsten is deposited on the conductor. With this configuration, it is possible to prevent tungsten from being oxidized by oxygen mixed in from below the conductor 140a and increasing the electrical resistance value.

Alternatively, as the conductor 140a, a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc. A material containing one or more elements or a semiconductor with high electrical conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide is deposited on top of this. For example, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide. A structure in which an oxide, indium zinc oxide, indium tin oxide added with silicon, or indium gallium zinc oxide containing nitrogen may be formed.

The oxide may have a function of absorbing hydrogen in the oxide 150 and capturing hydrogen diffused from the outside, and the electrical characteristics and reliability of the transistor 10 may be improved. Alternatively, even if titanium is used instead of the oxide, the same function may be obtained.

In this embodiment, a tungsten film is formed as the conductor 140a by a sputtering method.

Next, using a lithography method or the like, the conductor 120a, the insulator 130a, and the conductor 140a are processed so that the conductor 120b, the insulator 130b, and a conductor 140b (see FIG. 7). Although a dry etching method or a wet etching method can be used for the formation, the dry etching method is particularly preferable because it is suitable for processing fine shapes. Due to this processing, a part of the insulator 110 may be removed.

Note that in the lithography method, the resist is first exposed to light through a mask. Next, a resist mask is formed by removing or leaving the exposed area using a developer. Next, by performing an etching process through the resist mask, a conductor, semiconductor, insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, writing is performed directly on the resist, so the above-mentioned resist exposure mask is not required. Note that the resist mask can be removed by performing dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment. I can do it.

Further, instead of a resist mask, a hard mask made of an insulator or a conductor may be used. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductor 140a, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask in a desired shape. can do. Etching of the conductor 120a, insulator 130a, and conductor 140a may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. After etching the conductor 120a, the insulator 130a, and the conductor 140a, the hard mask may be removed by an etching method. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

As the dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high frequency power source is applied to one electrode of the parallel plate electrodes. Alternatively, a configuration may be adopted in which a plurality of different high frequency power sources are applied to one electrode of a parallel plate type electrode. Alternatively, a configuration may be adopted in which a high frequency power source having the same frequency is applied to each of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which high frequency power sources having different frequencies are applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching device having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching device can be used.

Note that by performing a process such as the dry etching described above, impurities caused by etching gas or the like may adhere to or diffuse into the surfaces or insides of the conductor 120b, the insulator 130b, the conductor 140b, and the like. Examples of impurities include fluorine and chlorine.

Washing may be performed to remove the above impurities. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning may be performed in an appropriate combination.

Wet cleaning may be performed using an aqueous solution of oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

Next, an insulator 175 is formed over the insulator 110, the conductor 120b, the insulator 130b, and the conductor 140b. The insulator 175 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 175 by a CVD method. Note that as the insulator 175, for example, silicon oxynitride may be used instead of silicon oxide.

Next, the upper surface of the insulator 175 is flattened by removing a portion of the insulator 175 (see FIG. 8). The planarization can be performed by CMP processing, dry etching processing, or the like. In this embodiment, the upper surface of the insulator 175 is planarized by CMP processing. The top surface of the insulator 175 after the planarization process is preferably located above the top surface of the conductor 140b. Note that if the upper surface of the insulator 175 after being formed has flatness, the above-described flattening process may not be necessary.

Here, a third heat treatment may be performed. The conditions of the first heat treatment can be used for the third heat treatment. Through the heat treatment, impurities such as hydrogen and water contained in the insulator 175 can be reduced. Additionally, oxygen can be supplied into the insulator 175.

Next, the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are processed by lithography to form the opening 145 reaching the upper surface of the insulator 110, the conductor 120, the insulator 130, and the conductor 140. (See Figure 9.) Resist exposure in the lithography method may be performed using, for example, KrF excimer laser light, ArF excimer laser light, EUV light, etc. through a mask, or may be performed using liquid immersion technology. Alternatively, a method may be used in which a pattern is drawn directly on the resist using an electron beam or an ion beam without using a mask. Exposure using an electron beam or ion beam can draw a finer pattern on the resist than exposure using the above-mentioned light, and is therefore suitable for microfabrication. In this embodiment, resist exposure is performed using an electron beam.

As the etching process in the lithography method, a dry etching method or a wet etching method can be used. In this embodiment, after the above-described resist exposure with an electron beam and development, the insulator 175, conductor 140b, insulator 130b, and conductor 120b are etched using a dry etching method. Note that the inner wall (side surface) of the opening 145 formed by the etching process is preferably formed substantially perpendicular to the substrate surface. As the inner wall (side surface) of the opening 145 is formed at an angle closer to perpendicular to the substrate surface, the transistor 10 can be made smaller. Note that a part of the insulator 110 may be removed by the etching process.

Next, an oxide that will become the oxide 150 is formed on the inner wall of the opening 145 and on the insulator 175. The oxide film that becomes the oxide 150 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when forming an oxide to become the oxide 150 by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide to be formed can be increased. Furthermore, when forming the above oxide into a film by a sputtering method, the above-mentioned In--M--Zn oxide target can be used.

In addition, when forming an oxide film to become oxide 150 by a sputtering method, if the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type metal oxides are formed. A transistor using an oxygen-deficient metal oxide in a channel forming region can obtain relatively high field-effect mobility.

In this embodiment, the oxide 150 is formed by a sputtering method using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. To form a film. Note that the oxide to be the oxide 150 may be formed in accordance with the characteristics required for the oxide 150 of the transistor 10 by appropriately selecting the film formation conditions and the atomic ratio.

Note that, as described above, the oxide 150 may have a stacked structure of two or more layers. For example, when the oxide 150 has a two-layer structure consisting of an oxide 150a (not shown) and an oxide 150b (not shown) from the bottom, the oxide that becomes the oxide 150a is formed by sputtering. :Ga:Zn=4:2:4.1 [atomic ratio] Using an In-Ga-Zn oxide target, the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5%. The film may be formed with a ratio of 20% or less. Then, the oxide that becomes the oxide 150b is produced by a sputtering method using an In-Ga-Zn oxide target with In:Ga:Zn=1:3:4 [atomic ratio]. The film may be formed with a ratio of 70% or more, preferably 80% or more, more preferably 100%. When the oxide 150 has this structure, the oxide 150a mainly functions as a channel formation region of the transistor 10. By giving the oxide 150 this configuration, oxygen contained in the oxide that will become the oxide 150b can be supplied to the oxide that will become the oxide 150a through the fourth heat treatment or the like. Note that the fourth heat treatment is preferably performed after forming an oxide film to become the oxide 150b. As the conditions for the heat treatment, it is preferable to perform the treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and then continuously perform the treatment at a temperature of 400° C. for 1 hour in an oxygen atmosphere.

Alternatively, for example, when the oxide 150 has a two-layer structure consisting of an oxide 150a (not shown) and an oxide 150b (not shown) from the bottom, the oxide that becomes the oxide 150a is formed by sputtering. Using an In-Ga-Zn oxide target with In:Ga:Zn=1:3:4 [atomic ratio], the proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, more preferably The film may be formed with 100%. Then, the oxide that becomes the oxide 150b is produced by a sputtering method using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. The film may be formed with the proportion of oxygen contained in the film being 1% or more and 30% or less, preferably 5% or more and 20% or less. When the oxide 150 has this structure, the oxide 150b mainly functions as a channel formation region of the transistor 10. When the oxide 150 has this configuration, oxygen contained in the oxide that becomes the oxide 150a can be supplied to the oxide that becomes the oxide 150b through the fourth heat treatment or the like.

Further, when the oxide 150 has a three-layer structure consisting of an oxide 150a, an oxide 150b, and an oxide 150c (not shown) from the bottom, the oxide becomes the oxide 150a and the oxide becomes the oxide 150b. was formed under the above conditions, and the oxide 150c was formed using a sputtering method using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. The film may be formed using a sputtering gas in which the proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, and more preferably 100%. As described above, it is preferable to perform the fourth heat treatment after forming the oxide film to become the oxide 150b. When the oxide 150 has this structure, the oxide 150b mainly functions as a channel formation region of the transistor 10. By making the oxide 150 have this configuration, in addition to the oxygen contained in the oxide that becomes the oxide 150a, the oxygen contained in the oxide that becomes the oxide 150c also becomes the oxide 150b through subsequent heat treatment. Oxide can be supplied.

Next, an insulator that will become the insulator 160 is formed on the oxide that will become the oxide 150. The insulator that becomes the insulator 160 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as an insulator that becomes the insulator 160 by a CVD method. Note that as the insulator serving as the insulator 160, for example, silicon oxynitride may be used instead of silicon oxide.

Here, it is preferable to perform the fifth heat treatment. The conditions of the fourth heat treatment can be used for the fifth heat treatment. Through the heat treatment, the oxygen contained in the insulator that will become the insulator 160 (and the oxide that will become the oxide 150c if the oxide has a three-layer structure) is removed from the oxide that will become the oxide 150 (and the oxide that will become the oxide 150c). If it has a three-layer structure, it can be supplied to the oxide (which becomes the oxide 150b).

Next, a conductor that will become the conductor 170 is formed on the insulator that will become the insulator 160. The conductor that will become the conductor 170 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, after a titanium nitride film is formed as a conductor to become the conductor 170 by an ALD method, a tungsten film is further formed by a CVD method. Note that in the conductor 170, the thickness of tungsten is preferably thicker than the thickness of titanium nitride. Further, titanium nitride is preferably formed into a film along the inner wall of the opening 145 via the insulator 160, and the remaining space in the opening 145 is filled with tungsten. By forming the conductor to become the conductor 170 in this manner, the conductor 170 having a stacked structure of titanium nitride and tungsten can be formed later.

Next, the top surfaces of the conductor that will become the conductor 170, the insulator that will become the insulator 160, and the oxide that will become the oxide 150 are polished until the top surface of the insulator 175 is exposed. and oxide 150 is formed (see FIG. 10). The polishing can be performed by CMP processing or the like. Further, by dry etching the upper surfaces of the conductor that will become the conductor 170, the insulator that will become the insulator 160, and the oxide that will become the oxide 150 until the upper surface of the insulator 175 is exposed, the conductor 170, the insulator 160, and an oxide 150 may be formed. In this embodiment, the conductor 170, the insulator 160, and the oxide 150 are formed by CMP treatment. By the CMP process, the height of the top surface of the insulator 175 and the height of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 can be formed to be approximately the same (see FIG. 10). Note that a portion of the insulator 175 may be removed by the CMP process.

Next, an insulator 176 is placed on the top surface of the insulator 175, the oxide 150, the insulator 160, and the top surface of the conductor 170, an insulator 178 is placed on the insulator 176, and an insulator 180 is placed on the insulator 178. Each film is formed. The insulator 176, the insulator 178, and the insulator 180 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is deposited as the insulator 176 by a CVD method, aluminum oxide is deposited as the insulator 178 by a sputtering method, and silicon oxide is deposited as the insulator 180 by a CVD method. . Note that for the insulator 176 or the insulator 180, other than silicon oxide, for example, silicon oxynitride may be used. Further, for the insulator 178, other than aluminum oxide, for example, silicon nitride or hafnium oxide may be used.

Next, openings reaching the conductor 140 are formed in the insulator 180, the insulator 178, the insulator 176, and the insulator 175. Although a wet etching method may be used to form the opening, it is preferable to use a dry etching method for fine processing.

After forming the opening, a conductor that will become the conductor 195 is formed. Here, the conductor 195 has a laminated structure consisting of a conductor 195a (not shown) having a function of suppressing oxygen permeation and a conductor 195b (not shown) having higher conductivity than the conductor 195a. It is preferable that

The conductor serving as the conductor 195a preferably includes a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. A film of the conductor to become the conductor 195a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, a film of tantalum nitride is formed by a sputtering method as a conductor to become the conductor 195a.

Next, a conductor that will become the conductor 195b is formed over the conductor that will become the conductor 195a. The conductor can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, a titanium nitride film is formed as a conductor to become the conductor 195b by an ALD method, and a tungsten film is formed over the titanium nitride by a CVD method.

Next, by performing a CMP process, the conductor that will become the conductor 195a and a part of the conductor that will become the conductor 195b are removed, and the insulator 180 is exposed. As a result, the conductor that will become the conductor 195a and the conductor that will become the conductor 195b remain only in the opening. As a result, a conductor 195 including a conductor 195a and a conductor 195b having a flat upper surface can be formed. Note that part of the insulator 180 may be removed by the CMP process.

Next, a conductor that will become the conductor 200 is formed over the insulator 180 and the conductor 195. Here, the conductor 200 has a laminated structure consisting of a conductor 200a (not shown) having a function of suppressing oxygen permeation and a conductor 200b (not shown) having higher conductivity than the conductor 200a. It is preferable that

The conductor that becomes the conductor 200a preferably includes a conductive material that has a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. The conductor that becomes the conductor 200a can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride or a film in which titanium nitride is laminated on tantalum nitride is formed by a sputtering method as the conductor to become the conductor 200a. By using such a metal nitride as the conductor that becomes the conductor 200a, even if a metal that easily diffuses, such as copper, is used for the conductor 200b (described later), the metal will not pass through the conductor 200a and the conductor 195. , diffusion into the transistor 10 can be prevented.

Next, a conductor that will become the conductor 200b is formed on the conductor that will become the conductor 200a. The conductor that becomes the conductor 200b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed into a film as the conductor that becomes the conductor 200b.

Next, using a lithography method or the like, the conductor 200b and the conductor 200a are processed to have regions overlapping with the conductor 195, and the conductor 200a and the conductor 200a are placed on the insulator 180. A conductor 200 made of a conductor 200b can be formed. Note that a part of the insulator 180 may be removed by the processing.

Through the above steps, a semiconductor device including the transistor 10 according to one embodiment of the present invention can be manufactured (see FIG. 1).

As described above, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a plurality of transistors having a channel length of several nm or less, which is difficult to manufacture using a lithography method, can be manufactured accurately and easily within the plane of a substrate. Alternatively, according to one embodiment of the present invention, a semiconductor device can be manufactured that has a transistor with good electrical characteristics in which a short channel effect is difficult to manifest even though the channel length is small. Further, in one embodiment of the present invention, a semiconductor device including a transistor with a fine element size including not only the channel length but also wiring and plugs can be manufactured. Alternatively, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with a large on-state current can be provided. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device with small variations in electrical characteristics between elements within the plane of a substrate. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

As described above, the structure, method, etc. shown in this embodiment can be used in appropriate combination with the structure, method, etc. shown in other embodiments.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG.

[Storage device]
The memory device shown in FIG. 11 includes a transistor 3000, a transistor 2000, and a capacitor 1000.

The transistor 2000 is a transistor in which a channel is formed in a semiconductor layer containing a metal oxide. Since the transistor 2000 has a small off-state current, when the transistor 2000 is used in a memory device, stored contents can be retained for a long period of time. In other words, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In FIG. 11, a first wiring 3001 is electrically connected to the source of the transistor 3000, and a second wiring 3002 is electrically connected to the drain of the transistor 3000. Further, the third wiring 3003 is electrically connected to either the source or the drain of the transistor 2000, and the fourth wiring 3004 is electrically connected to the gate of the transistor 2000. The gate of the transistor 3000 and the other of the source or drain of the transistor 2000 are electrically connected to one of the electrodes of the capacitor 1000, and the fifth wiring 3005 is electrically connected to the other electrode of the capacitor 1000. It is connected.

The memory device shown in FIG. 11 has a characteristic that the potential of the gate of the transistor 3000 can be held, so that information can be written, held, and read as described below.

Writing and retaining information will be explained. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 becomes conductive, thereby making the transistor 2000 conductive. As a result, the potential of the third wiring 3003 is applied to the node FG electrically connected to the gate of the transistor 3000 and one of the electrodes of the capacitor 1000. That is, a predetermined charge is applied to the gate of the transistor 3000 (writing). Here, it is assumed that one of charges giving two different potential levels (hereinafter referred to as a low level charge and a high level charge) is provided. Thereafter, the potential of the fourth wiring 3004 is set to a potential at which the transistor 2000 is rendered non-conductive, thereby rendering the transistor 2000 non-conductive, thereby retaining charge at the node FG (retention).

When the off-state current of transistor 2000 is small, the charge on node FG is retained for a long period of time.

Next, reading information will be explained. When an appropriate potential (read potential) is applied to the fifth interconnect 3005 while a predetermined potential (constant potential) is applied to the first interconnect 3001, the second interconnect 3002 receives the charge held at the node FG. Takes a potential depending on the amount. This means that if the transistor 3000 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 3000 is different from the apparent threshold voltage V th_H when a low level charge is applied to the gate of the transistor 3000. This is because it becomes lower than the apparent threshold voltage V _{th_L} of V th_L. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 that is necessary to make the transistor 3000 conductive. Therefore, by setting the potential of the fifth wiring 3005 to the potential V ₀ between V _{th_H} and V _{th_L} , the charge applied to the node FG can be determined. For example, in writing, when a high level charge is applied to the node FG, the transistor 3000 becomes conductive when the potential of the fifth wiring 3005 becomes V ₀ (>V _{th_H} ). On the other hand, when a low-level charge is applied to the node FG, the transistor 3000 remains non-conductive even if the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, the information held in the node FG can be read.

<Structure of storage device>
A memory device of one embodiment of the present invention includes a transistor 3000, a transistor 2000, and a capacitor 1000, as shown in FIG. The transistor 2000 is provided above the transistor 3000, and the capacitor 1000 is provided above the transistor 3000 and the transistor 2000.

The transistor 3000 is provided on a substrate 311 and includes a semiconductor region 313 made up of a conductor 316, an insulator 315, and a part of the substrate 311, and a low resistance region 314a and a low resistance region 314b that function as a source region or a drain region. have

Transistor 3000 may be either a p-channel type or an n-channel type.

It is preferable that a semiconductor such as a silicon-based semiconductor be included in the region of the semiconductor region 313 where the channel is formed, the region in the vicinity thereof, the low resistance region 314a which becomes the source region or the drain region, the low resistance region 314b, etc. Preferably, it contains crystalline silicon. Alternatively, it may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A structure using silicon may be used in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 3000 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In addition to the semiconductor material applied to the semiconductor region 313, the low resistance region 314a and the low resistance region 314b are made of an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. Contains elements that

The conductor 316 that functions as a gate electrode is made of a semiconductor material such as silicon, a metal material, or an alloy containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A conductive material such as a metal oxide material or a metal oxide material can be used.

Note that since the work function is determined by the material of the conductor, Vth of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a layered layer for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

Note that the transistor 3000 illustrated in FIG. 11 is an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided to cover the transistor 3000.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. are used. Bye.

The insulator 322 may function as a planarization film that planarizes a step caused by the transistor 3000 or the like provided below. For example, the upper surface of the insulator 322 may be planarized by CMP processing or the like to improve flatness.

Further, as the insulator 324, it is preferable to use a film having barrier properties that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 3000 into a region where the transistor 2000 is provided.

As an example of a film having barrier properties against hydrogen, silicon nitride formed by a CVD method can be used, for example. Here, when hydrogen diffuses into a semiconductor element including a metal oxide such as the transistor 2000, the electrical characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 2000 and the transistor 3000. Specifically, the membrane that suppresses hydrogen diffusion is a membrane that releases a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, temperature programmed desorption gas analysis (TDS). For example, in TDS analysis, the amount of hydrogen desorbed from the insulator 324 is determined by the amount converted into hydrogen atoms per area of the insulator 324 when the surface temperature of the film is in the range of 50°C to 500°C. The amount may be 10×10 ¹⁵ atoms/cm ² or less, preferably 5×10 ¹⁵ atoms/cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the dielectric constant of the insulator 324. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

Furthermore, a conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 1000 or the transistor 2000 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 have a function as a plug or wiring. Further, for a conductor having a function as a plug or a wiring, a plurality of structures may be collectively given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

The material of each plug and wiring (conductor 328, conductor 330, etc.) is a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 11, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug or wiring. Note that the conductor 356 can be provided using the same material as the conductor 328 and the conductor 330.

Note that, for example, as with the insulator 324, it is preferable to use an insulator that has hydrogen barrier properties as the insulator 350. Further, the conductor 356 preferably includes a conductor having barrier properties against hydrogen. In particular, it is preferable to form the conductor 356 having hydrogen barrier properties in the opening of the insulator 350 having hydrogen barrier properties. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

Note that as the conductor having barrier properties against hydrogen, for example, tantalum nitride or the like may be used. Further, by stacking tantalum nitride and highly conductive tungsten, diffusion of hydrogen from the transistor 3000 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having hydrogen barrier properties be in contact with the insulator 350 having hydrogen barrier properties.

A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 11, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

Note that, for example, as with the insulator 324, it is preferable to use an insulator that has hydrogen barrier properties as the insulator 360. Further, the conductor 366 preferably includes a conductor having barrier properties against hydrogen. In particular, it is preferable to form the conductor 366 having barrier properties against hydrogen in the opening of the insulator 360 having barrier properties against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 11, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. Further, a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or wiring. Note that the conductor 376 can be provided using the same material as the conductor 328 and the conductor 330.

Note that, for example, as with the insulator 324, it is preferable to use an insulator that has hydrogen barrier properties as the insulator 370. Further, the conductor 376 preferably includes a conductor having barrier properties against hydrogen. In particular, it is preferable to form the conductor 376 having barrier properties against hydrogen in the opening of the insulator 370 having barrier properties against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 11, an insulator 380, an insulator 382, and an insulator 384 are stacked in this order. Further, a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 has a function as a plug or wiring. Note that the conductor 386 can be provided using the same material as the conductor 328 and the conductor 330.

Note that, for example, as with the insulator 324, it is preferable to use an insulator that has hydrogen barrier properties as the insulator 380. Further, the conductor 386 preferably includes a conductor having barrier properties against hydrogen. In particular, it is preferable to form the conductor 386 having barrier properties against hydrogen in the opening of the insulator 380 having barrier properties against hydrogen. With this structure, the transistor 3000 and the transistor 2000 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

On the insulator 384 and the conductor 386, the insulator 210, the insulator 100, the insulator 102, and the insulator 105 are provided in a laminated manner in this order. Any one of the insulator 210, the insulator 100, the insulator 102, and the insulator 105 is preferably a film that has barrier properties against oxygen and hydrogen.

For example, for the insulator 210 and the insulator 102, it is preferable to use a film having barrier properties that prevents hydrogen and impurities from diffusing from the substrate 311 or the region where the transistor 3000 is provided to the region where the transistor 2000 is provided. . Therefore, the same material as the insulator 324 can be used.

As an example of a film having barrier properties against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including a metal oxide such as the transistor 2000, the electrical characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 2000 and the transistor 3000. Specifically, the membrane that suppresses hydrogen diffusion is a membrane that releases a small amount of hydrogen.

Further, as a film having barrier properties against hydrogen, for example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, tantalum oxide, or the like for the insulator 210 and the insulator 102.

In particular, aluminum oxide has a high blocking effect of preventing the membrane from permeating both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the transistor manufacturing process. Further, release of oxygen from the oxide forming the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000.

Further, for example, the same material as the insulator 320 can be used for the insulator 100 and the insulator 105. Further, by using a material with a relatively low dielectric constant for the insulator, parasitic capacitance occurring between wirings can be reduced. For example, silicon oxide, silicon oxynitride, or the like can be used as the insulator 100 and the insulator 105.

Further, a conductor 218, a conductor (conductor 185) electrically connected to the transistor 2000, and the like are embedded in the insulator 210, the insulator 100, the insulator 102, and the insulator 105. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the capacitor 1000 or the transistor 3000. The conductor 218 can be provided using the same material as the conductors 328 and 330.

In particular, the insulator 210 and the conductor 218 in a region in contact with the insulator 102 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 3000 and the transistor 2000 can be reliably separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 3000 to the transistor 2000 can be suppressed.

A transistor 2000 is provided above the insulator 105 with an insulator 110 interposed therebetween. Note that for the structure of the transistor 2000, the transistor included in the semiconductor device described in the previous embodiment may be used. Further, the transistor 2000 illustrated in FIG. 11 is an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

An insulator 175, an insulator 176, and an insulator 178 are provided above the transistor 2000.

As the insulator 178, it is preferable to use a film having barrier properties against oxygen and hydrogen. Therefore, the same material as the insulator 102 can be used for the insulator 178. For example, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, tantalum oxide, or the like for the insulator 178.

In particular, aluminum oxide has a high blocking effect of preventing the membrane from permeating both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 2000 during and after the transistor manufacturing process. Further, release of oxygen from the oxide forming the transistor 2000 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 2000.

Further, an insulator 180 is provided on the insulator 178. The same material as the insulator 320 can be used for the insulator 180. Further, by using a material with a relatively low dielectric constant for the insulator, parasitic capacitance occurring between wirings can be reduced. For example, silicon oxide, silicon oxynitride, or the like can be used as the insulator 180.

Further, a conductor 246, a conductor 248, etc. are embedded in the insulator 110, the insulator 175, the insulator 176, the insulator 178, and the insulator 180.

The conductor 246 and the conductor 248 function as a plug or wiring that is electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000. The conductor 246 and the conductor 248 can be provided using the same material as the conductor 328 and the conductor 330.

A capacitive element 1000 is provided above the transistor 2000. Capacitive element 1000 includes a conductor 1100, a conductor 1200, and an insulator 1300.

Further, the conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or wiring that is electrically connected to the capacitor 1000, the transistor 2000, or the transistor 3000. The conductor 1100 has a function as an electrode of the capacitive element 1000. Note that the conductor 112 and the conductor 1100 can be formed at the same time.

The conductor 112 and the conductor 1100 include a metal containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride containing the above-mentioned elements. Tantalum, titanium nitride, molybdenum nitride, tungsten nitride), etc. can be used. Or, add indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or silicon oxide. Conductive materials such as indium tin oxide can also be applied.

Although FIG. 11 shows a configuration in which the conductor 112 and the conductor 1100 have a single layer structure, the present invention is not limited to this configuration, and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesiveness to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

Further, an insulator 1300 is provided as a dielectric of the capacitor 1000 over the conductor 112 and the conductor 1100. The insulator 1300 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like. It can be used as a laminated layer or a single layer.

For example, the insulator 1300 is preferably made of a material with high dielectric strength, such as silicon oxynitride. With this configuration, the dielectric breakdown resistance of the capacitor 1000 can be improved, and electrostatic breakdown of the capacitor 1000 can be suppressed.

A conductor 1200 is provided on the insulator 1300 so as to overlap with the conductor 1100. Note that the conductor 1200 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Moreover, when forming other structures such as conductors at the same time, low resistance metal materials such as Cu (copper) and Al (aluminum) may be used.

An insulator 1500 is provided on the conductor 1200 and the insulator 1300. Insulator 1500 can be provided using the same material as insulator 320. Further, the insulator 1500 may function as a flattening film that covers the uneven shape below it.

The above is a description of a configuration example of a memory device to which a semiconductor device according to one embodiment of the present invention is applied. By using this structure, in a semiconductor device using a transistor including a metal oxide, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including a metal oxide with a large on-state current can be provided. Alternatively, a transistor including a metal oxide with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

As described above, the structure, method, etc. shown in this embodiment can be used in appropriate combination with the structure, method, etc. shown in other embodiments.

(Embodiment 3)
In this embodiment, a transistor using a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied, with reference to FIGS. 12 and 13. A NOSRAM will be explained as an example of a storage device. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Note that in the following, a memory device using an OS transistor, such as a NOSRAM, may be referred to as an OS memory.

NOSRAM uses a memory device (hereinafter referred to as "OS memory") in which an OS transistor is used as a memory cell. The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor has an extremely small off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

<<NOSRAM1600>>
FIG. 12 shows an example of the configuration of NOSRAM. NOSRAM 1600 shown in FIG. 12 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multilevel NOSRAM that stores multilevel data in one memory cell.

The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, a plurality of word lines RWL, a plurality of bit lines BL, and a plurality of source lines SL. Word line WWL is a write word line, and word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (8-value) data.

The controller 1640 centrally controls the entire NOSRAM 1600, and writes data WDA[31:0] and reads data RDA[31:0]. Controller 1640 processes external command signals (eg, chip enable signals, write enable signals, etc.) to generate control signals for row driver 1650, column driver 1660, and output driver 1670.

Row driver 1650 has the function of selecting a row to access. Row driver 1650 includes a row decoder 1651 and a word line driver 1652.

Column driver 1660 drives source line SL and bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.

DAC1663 converts 3-bit digital data into analog voltage. The DAC 1663 converts the 32-bit data WDA[31:0] into an analog voltage every 3 bits.

The write driver 1662 has the function of precharging the source line SL, making the source line SL electrically floating, selecting the source line SL, and inputting the write voltage generated by the DAC 1663 to the selected source line SL. It has a function of precharging the bit line BL, a function of making the bit line BL electrically floating, and the like.

The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672. ADC1672 has a function of converting analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data by the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.

<Memory cells 1611 to 1614>
FIG. 13A is a circuit diagram showing a configuration example of the memory cell 1611. The memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, word line RWL, bit line BL, and source line SL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is composed of, for example, a p-channel type Si transistor. Capacitive element C61 is a holding capacitor for holding the voltage of node SN. Node SN is a data holding node, and here corresponds to the gate of transistor MP61.

Since the write transistor of the memory cell 1611 is composed of the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

In the example of FIG. 13(A), the bit line is a common bit line for writing and reading, but as shown in FIG. 13(B), a writing bit line WBL and a reading bit line RBL may be provided. good.

Other configuration examples of memory cells are shown in FIGS. 13(C) to 13(E). 13(C) to FIG. 13(E) show an example in which a write bit line and a read bit line are provided, but as shown in FIG. 13(A), the bit line is shared for writing and reading. may be provided.

A memory cell 1612 shown in FIG. 13C is a modification of the memory cell 1611, in which the read transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

The memory cell 1613 shown in FIG. 13D is a 3T-type gain cell, and is electrically connected to the word line WWL, word line RWL, bit line WBL, bit line RBL, source line SL, and wiring PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. OS transistor MO62 is a write transistor. Transistor MP62 is a read transistor, and transistor MP63 is a selection transistor.

A memory cell 1614 shown in FIG. 13E is a modification of the memory cell 1613, in which the read transistor and the selection transistor are changed to n-channel transistors (MN62, MN63). The transistor MN62 and the transistor MN63 may be OS transistors or Si transistors.

The OS transistors provided in the memory cells 1611 to 1614 may be transistors without a bottom gate or may be transistors with a bottom gate.

Since data is rewritten by charging and discharging the capacitive element C61, the NOSRAM 1600 has no restrictions on the number of rewrites in principle, and data can be written and read with low energy. Furthermore, since it is possible to hold data for a long time, the refresh frequency can be reduced.

When the semiconductor device described in the above embodiment is used for the memory cell 1611, memory cell 1612, memory cell 1613, and memory cell 1614, the transistor 2000 is used as the OS transistor MO61 and the OS transistor MO62, and the transistor 3000 is used as the transistor MP61 and the transistor MN62. Can be used. As a result, the area occupied by the transistor when viewed from above can be reduced, so that the memory device according to this embodiment can be further highly integrated. Therefore, the storage capacity per unit area of the storage device according to this embodiment can be increased.

The structure shown in this embodiment can be used in combination with the structures shown in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, a DOSRAM will be described as an example of a memory device to which an OS transistor according to one embodiment of the present invention is applied, with reference to FIGS. 14 and 15. DOSRAM (registered trademark) is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) and 1C (capacitance) type memory cells. Like NOSRAM, OS memory is also applied to DOSRAM.

<<DOSRAM1400>>
FIG. 14 shows an example of the configuration of a DOSRAM. The DOSRAM 1400 shown in FIG. 14 includes a controller 1405, a row circuit 1410, a column circuit 1415, and a memory cell and sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420").

The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 has a global sense amplifier array 1416 and an input/output circuit 1417. Global sense amplifier array 1416 includes a plurality of global sense amplifiers 1447. The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and a global bit line GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which a memory cell array 1422 is stacked on a sense amplifier array 1423. Global bit line GBLL and global bit line GBLR are stacked on memory cell array 1422. The DOSRAM 1400 employs a hierarchical bit line structure in which local bit lines and global bit lines are layered.

The memory cell array 1422 has N (N is an integer of 2 or more) local memory cell arrays 1425<0> to 1425<N-1>. FIG. 15A shows a configuration example of the local memory cell array 1425. Local memory cell array 1425 includes multiple memory cells 1445, multiple word lines WL, multiple bit lines BLL, and multiple bit lines BLR. In the example of FIG. 15A, the structure of the local memory cell array 1425 is an open bit linear type, but it may be a folded bit linear type.

FIG. 15B shows an example of the circuit configuration of the memory cell 1445. The memory cell 1445 includes a transistor MW1, a capacitor CS1, and a terminal B1. Transistor MW1 has a function of controlling charging and discharging of capacitive element CS1. The gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitive element CS1. The second terminal of the capacitive element CS1 is electrically connected to the terminal B1. A constant potential (for example, a low power supply potential) is input to the terminal B1.

Transistor MW1 may be a transistor with a bottom gate. When the transistor MW1 is a transistor having a bottom gate, for example, the bottom gate of the transistor MW1 may be electrically connected to the gate, source, or drain of the transistor MW1.

The sense amplifier array 1423 has N local sense amplifier arrays 1426<0> to 1426<N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has the function of precharging the bit line pair, the function of amplifying the potential difference between the bit line pair, and the function of holding this potential difference. The switch array 1444 has a function of selecting a bit line pair and making conductive between the selected bit line pair and the global bit line pair.

Here, the bit line pair refers to two bit lines that are simultaneously compared by a sense amplifier. A global bit line pair refers to two global bit lines that are compared simultaneously by a global sense amplifier. A bit line pair can be referred to as a pair of bit lines, and a global bit line pair can be referred to as a pair of global bit lines. Here, bit line BLL and bit line BLR form a bit line pair. Global bit line GBLL and global bit line GBLR form a global bit line pair. Hereinafter, they will also be referred to as bit line pairs (BLL, BLR) and global bit line pairs (GBLL, GBLR).

(controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 has a function of determining an operation mode by performing a logical operation on a command signal input from the outside, and a function of generating control signals for the row circuit 1410 and column circuit 1415 so that the determined operation mode is executed. , has a function of holding an address signal input from the outside, and a function of generating an internal address signal.

(Row circuit 1410)
Row circuit 1410 has the function of driving MC-SA array 1420. Decoder 1411 has a function of decoding address signals. The word line driver circuit 1412 generates a selection signal that selects the word line WL of the row to be accessed.

Column selector 1413 and sense amplifier driver circuit 1414 are circuits for driving sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting a bit line of a column to be accessed. A selection signal from column selector 1413 controls switch array 1444 of each local sense amplifier array 1426. A plurality of local sense amplifier arrays 1426 are independently driven by control signals from the sense amplifier driver circuit 1414.

(Column circuit 1415)
Column circuit 1415 has a function of controlling input of data signal WDA[31:0] and a function of controlling output of data signal RDA[31:0]. Data signal WDA[31:0] is a write data signal, and data signal RDA[31:0] is a read data signal.

Global sense amplifier 1447 is electrically connected to the global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying the potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Writing and reading data to and from the global bit line pair (GBLL, GBLR) is performed by the input/output circuit 1417.

An outline of the write operation of the DOSRAM 1400 will be explained. Data is written to the global bit line pair by input/output circuit 1417. Data on global bit line pairs is held by global sense amplifier array 1416. The data on the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address. Local sense amplifier array 1426 amplifies and holds written data. In the designated local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and writes the data held in the local sense amplifier array 1426 to the memory cells 1445 of the selected row.

An overview of the read operation of the DOSRAM 1400 will be explained. One row of local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL of the target row is brought into a selected state, and the data of the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data. Switch array 1444 writes the data in the column specified by the address among the data held in local sense amplifier array 1426 to the global bit line pair. Global sense amplifier array 1416 detects and holds data on global bit line pairs. Data held by global sense amplifier array 1416 is output to input/output circuit 1417. With this, the read operation is completed.

Since data is rewritten by charging and discharging the capacitive element CS1, the DOSRAM 1400 has no restrictions on the number of rewrites in principle, and data can be written and read with low energy. Furthermore, since the circuit configuration of the memory cell 1445 is simple, it is easy to increase the capacity.

Transistor MW1 is an OS transistor. Since the OS transistor has an extremely small off-state current, leakage of charge from the capacitive element CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is much longer than that of a DRAM using Si transistors. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, by using the DOSRAM 1400 as a frame memory, the power consumption of the display controller IC and source driver IC can be reduced.

Since the MC-SA array 1420 has a stacked structure, the bit lines can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance becomes smaller, and the storage capacitance of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the driving load when accessing the DOSRAM 1400 is reduced, so that the energy consumption of the display controller IC and source driver IC can be reduced.

The structure shown in this embodiment can be used in combination with the structures shown in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, an FPGA (field programmable gate array) will be described as an example of a semiconductor device to which a transistor in which a metal oxide is used in a channel formation region (OS transistor) according to one embodiment of the present invention is applied. . In the FPGA of this embodiment, OS memory is applied to the configuration memory and registers. Here, such an FPGA is referred to as an "OS-FPGA."

The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with extremely low off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

FIG. 16(A) shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 16A is capable of NOFF (normally off) computing that executes context switching using a multi-context structure and fine-grained power gating for each PLE. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

The programmable area 3115 has two input/output blocks (IOB) 3117 and a core (Core) 3119. IOB3117 has multiple programmable input/output circuits. The core 3119 includes multiple logic array blocks (LAB) 3120 and multiple switch array blocks (SAB) 3130. LAB3120 has multiple PLE3121. FIG. 16(B) shows an example in which the LAB 3120 is configured with five PLEs 3121. As shown in FIG. 16C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and to LABs 3120 in four (up, down, left and right) directions via the SAB 3130.

SB3131 will be described with reference to FIGS. 17(A) to 17(C). Data, datab, signals context[1:0], and word[1:0] are input to the SB 3131 shown in FIG. 17(A). data and datab are configuration data, and data and datab have a complementary relationship in logic. The number of contexts of the OS-FPGA 3110 is 2, and the signal context[1:0] is a context selection signal. The signal word[1:0] is a word line selection signal, and each wiring to which the signal word[1:0] is input is a word line.

SB3131 has PRS (programmable routing switch) 3133[0] and PRS3133[1]. PRS3133[0] and PRS3133[1] have a configuration memory (CM) that can store complementary data. In addition, when PRS3133[0] and PRS3133[1] are not distinguished, they are called PRS3133. The same applies to other elements.

FIG. 17(B) shows an example of the circuit configuration of PRS3133[0]. PRS3133[0] and PRS3133[1] have the same circuit configuration. PRS3133[0] and PRS3133[1] differ in input context selection signal and word line selection signal. Signal context[0] and signal word[0] are input to PRS3133[0], and signal context[1] and signal word[1] are input to PRS3133[1]. For example, in SB3131, when the signal context[0] becomes “H”, PRS3133[0] becomes active.

PRS3133[0] includes a CM3135 and a Si transistor M31. Si transistor M31 is a pass transistor controlled by CM3135. The CM3135 includes a memory circuit 3137 and a memory circuit 3137B. The memory circuit 3137 and the memory circuit 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit 3137B includes a capacitor CB31, an OS transistor MOB31, and an OS transistor MOB32.

OS transistor MO31, OS transistor MO32, OS transistor MOB31, and OS transistor MOB32 may have a bottom gate. For example, when the OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 have bottom gates, each of these bottom gates may be electrically connected to a power supply line that supplies a fixed potential. .

The gate of Si transistor M31 is node N31, the gate of OS transistor MO32 is node N32, and the gate of OS transistor MOB32 is node NB32. Node N32 and node NB32 are charge retention nodes of CM3135. OS transistor MO32 controls the conduction state between node N31 and the signal line for signal context[0]. OS transistor MOB32 controls the conduction state between node N31 and low potential power supply line VSS.

The logic of data held by the memory circuit 3137 and the memory circuit 3137B is complementary. Therefore, either OS transistor MO32 or OS transistor MOB32 becomes conductive.

An example of the operation of PRS3133[0] will be described with reference to FIG. 17(C). Configuration data has already been written to PRS3133[0], node N32 of PRS3133[0] is "H", and node NB32 is "L".

While the signal context[0] is "L", the PRS3133[0] is inactive. During this period, even if the input terminal of PRS3133[0] transitions to "H", the gate of Si transistor M31 is maintained at "L", and the output terminal of PRS3133[0] is also maintained at "L".

PRS3133[0] is active while signal context[0] is "H". When the signal context[0] transitions to “H”, the gate of the Si transistor M31 transitions to “H” according to the configuration data stored in the CM3135.

When the input terminal changes to "H" while PRS3133[0] is active, the gate potential of the Si transistor M31 increases due to boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. do. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving ability, and the gate of the Si transistor M31 becomes floating.

In the PRS 3133 having a multi-context function, the CM 3135 also has a multiplexer function.

FIG. 18 shows a configuration example of the PLE 3121. The PLE 3121 includes an LUT (lookup table) block 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to select and output data according to inputs inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.

PLE 3121 is electrically connected to a power supply line for potential VDD via a power switch 3127. The on/off state of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 in each PLE 3121, fine-grained power gating is possible. The fine-grained power gating function allows power gating of PLEs 3121 that are not used after context switching, so standby power can be effectively reduced.

To implement NOFF computing, register block 3124 is configured with non-volatile registers. A non-volatile register in the PLE 3121 is a flip-flop (hereinafter referred to as "OS-FF") that includes an OS memory.

The register block 3124 includes an OS-FF 3140[1] and an OS-FF 3140[2]. The signal user_res, the signal load, and the signal store are input to the OS-FF3140[1] and the OS-FF3140[2]. Clock signal CLK1 is input to OS-FF3140[1], and clock signal CLK2 is input to OS-FF3140[2]. FIG. 19A shows a configuration example of the OS-FF 3140.

The OS-FF 3140 includes an FF 3141 and a shadow register 3142. The FF 3141 includes a node CK, a node R, a node D, a node Q, and a node QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node and node Q is a data output node. Node Q and node QB have a complementary relationship in logic.

The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes the backed up data back to the nodes Q and QB according to the signal load.

The shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, a Si transistor M37, a Si transistor MB37, a memory circuit 3143, and a memory circuit 3143B. The memory circuit 3143 and the memory circuit 3143B have the same circuit configuration as the memory circuit 3137 of the PRS3133. The memory circuit 3143 includes a capacitive element C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. Node N36 and node NB36 are the gates of OS transistor MO36 and OS transistor MOB36, and are charge retention nodes, respectively. Node N37 and node NB37 are the gates of Si transistor M37 and Si transistor MB37.

OS transistor MO35, OS transistor MO36, OS transistor MOB35, and OS transistor MOB36 may have a bottom gate. For example, when OS transistor MO35, OS transistor MO36, OS transistor MOB35, and OS transistor MOB36 have bottom gates, these bottom gates may be electrically connected to a power supply line that supplies a fixed potential, respectively. .

An example of the operating method of the OS-FF 3140 will be described with reference to FIG. 19(B).

(Backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data of the FF 3141. The node N36 becomes "L" when the data of the node Q is written, and the node NB36 becomes "H" when the data of the node QB is written. After that, power gating is performed and power switch 3127 is turned off. Although the data of nodes Q and QB of the FF 3141 are lost, the shadow register 3142 retains the backed up data even if the power is turned off.

(Recovery)
Turn on the power switch 3127 to supply power to the PLE 3121. Thereafter, when the "H" signal load is input to the OS-FF 3140, the shadow register 3142 writes back the backed up data to the FF 3141. Since the node N36 is "L", the node N37 is maintained at "L", and since the node NB36 is "H", the node NB37 becomes "H". Therefore, node Q becomes "H" and node QB becomes "L". In other words, the OS-FF 3140 returns to the state at the time of backup operation.

By combining fine-grained power gating and the backup/recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.

Errors that can occur in memory circuits include soft errors caused by incidence of radiation. Soft errors are secondary cosmic errors that occur when alpha rays emitted from materials that make up memory or packages, or primary cosmic rays that enter the atmosphere from space, cause a nuclear reaction with the nuclei of atoms in the atmosphere. This is a phenomenon in which a transistor is irradiated with linear neutrons and electron-hole pairs are generated, resulting in malfunctions such as inversion of data held in memory. OS memory using OS transistors has high soft error resistance. Therefore, by installing an OS memory, a highly reliable OS-FPGA 3110 can be provided.

The structure shown in this embodiment can be used in combination with the structures shown in other embodiments as appropriate.

(Embodiment 6)
In this embodiment, an example of a CPU including a semiconductor device according to one embodiment of the present invention, such as the above-described storage device, will be described.

<CPU configuration>
A semiconductor device 5400 shown in FIG. 20 includes a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422. The power management unit 5421 includes a power controller 5402 and a power switch 5403. The peripheral circuit 5422 includes a cache 5404 having a cache memory, a bus interface (BUS I/F) 5405, and a debug interface (Debug I/F) 5406. The CPU core 5401 includes a data bus 5423, a control unit 5407, a PC (program counter) 5408, a pipeline register 5409, a pipeline register 5410, an arithmetic logic unit (ALU) 5411, and a register file ( Register File) 5412. Data is exchanged between the CPU core 5401 and peripheral circuits 5422 such as the cache 5404 via a data bus 5423.

The semiconductor device (cell) can be applied to many logic circuits including the power controller 5402 and the control device 5407. In particular, it can be applied to all logic circuits that can be constructed using standard cells. As a result, a compact semiconductor device 5400 can be provided. Furthermore, a semiconductor device 5400 that can reduce power consumption can be provided. Further, it is possible to provide a semiconductor device 5400 that can improve operating speed. Further, it is possible to provide a semiconductor device 5400 that can reduce fluctuations in power supply voltage.

A p-channel Si transistor and a transistor whose channel formation region includes the metal oxide (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment are used in a semiconductor device (cell). By applying the semiconductor device (cell) to the semiconductor device 5400, a small-sized semiconductor device 5400 can be provided. Furthermore, a semiconductor device 5400 that can reduce power consumption can be provided. Further, it is possible to provide a semiconductor device 5400 that can improve operating speed. In particular, manufacturing costs can be kept low by using only p-channel type Si transistors.

A control device 5407 controls the operations of a PC 5408, a pipeline register 5409, a pipeline register 5410, an ALU 5411, a register file 5412, a cache 5404, a bus interface 5405, a debug interface 5406, and a power controller 5402. It has the ability to decode and execute instructions included in programs such as applications.

The ALU 5411 has a function of performing various arithmetic operations such as arithmetic operations and logical operations.

The cache 5404 has a function of temporarily storing frequently used data. PC5408 is a register that has the function of storing the address of the next instruction to be executed. Although not shown in FIG. 20, the cache 5404 is provided with a cache controller that controls the operation of the cache memory.

Pipeline register 5409 is a register that has a function of temporarily storing instruction data.

The register file 5412 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing by the ALU 5411, and the like.

The pipeline register 5410 is a register that has a function of temporarily storing data used in the arithmetic processing of the ALU 5411 or data obtained as a result of the arithmetic processing of the ALU 5411.

The bus interface 5405 functions as a data path between the semiconductor device 5400 and various devices external to the semiconductor device 5400. The debug interface 5406 functions as a signal path for inputting instructions to the semiconductor device 5400 for controlling debugging.

The power switch 5403 has a function of controlling the supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400. The various circuits described above each belong to several power domains, and whether or not a power supply voltage is supplied to the various circuits belonging to the same power domain is controlled by the power switch 5403. Further, the power controller 5402 has a function of controlling the operation of the power switch 5403.

The semiconductor device 5400 having the above configuration can perform power gating. The flow of power gating operation will be explained using an example.

First, the CPU core 5401 sets the timing for stopping the supply of power supply voltage in the register of the power controller 5402. Next, the CPU core 5401 sends a command to the power controller 5402 to start power gating. Next, various registers and cache 5404 included in semiconductor device 5400 start saving data. Next, the supply of power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 is stopped by the power switch 5403. Next, by inputting an interrupt signal to the power controller 5402, supply of power supply voltage to various circuits included in the semiconductor device 5400 is started. Note that the power controller 5402 may be provided with a counter, and the timing at which supply of the power supply voltage is started may be determined using the counter, instead of depending on the input of the interrupt signal. The various registers and cache 5404 then begin returning data. Execution of instructions in controller 5407 then resumes.

Such power gating can be performed on the entire processor or on one or more logic circuits that make up the processor. Furthermore, the power supply can be stopped even for a short period of time. Therefore, power consumption can be reduced spatially or temporally with fine granularity.

When performing power gating, it is preferable that the information held by the CPU core 5401 and peripheral circuits 5422 can be saved in a short period of time. By doing so, the power can be turned on and off in a short period of time, which increases the power saving effect.

In order to save the information held by the CPU core 5401 and the peripheral circuit 5422 in a short period of time, it is preferable that the flip-flop circuit can save data within the circuit (referred to as a backup-capable flip-flop circuit). Further, it is preferable that the SRAM cell can save data within the cell (referred to as a backup-capable SRAM cell). A flip-flop circuit or an SRAM cell that can be backed up preferably has a transistor containing a metal oxide (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, since the transistor has a low off-state current, a flip-flop circuit or SRAM cell capable of backup can retain information even without power supply for a long period of time. Furthermore, because the transistor has a high switching speed, flip-flop circuits and SRAM cells that can be backed up may be able to save and restore data in a short period of time.

An example of a flip-flop circuit that can be backed up will be described using FIG. 21.

A semiconductor device 5500 shown in FIG. 21 is an example of a flip-flop circuit that can be backed up. The semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, a third memory circuit 5503, and a read circuit 5504. The semiconductor device 5500 is supplied with the potential difference between the potential V1 and the potential V2 as a power supply voltage. One of the potentials V1 and V2 is at a high level, and the other is at a low level. Hereinafter, a configuration example of the semiconductor device 5500 will be described using as an example a case where the potential V1 is at a low level and the potential V2 is at a high level.

The first memory circuit 5501 has a function of holding data when a signal D including data is input during a period when a power supply voltage is supplied to the semiconductor device 5500. Then, during a period when the power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 5501 outputs a signal Q including the held data. On the other hand, the first memory circuit 5501 cannot hold data during a period when the power supply voltage is not supplied to the semiconductor device 5500. That is, the first memory circuit 5501 can be called a volatile memory circuit.

The second memory circuit 5502 has a function of reading and storing (or saving) data held in the first memory circuit 5501. The third storage circuit 5503 has a function of reading and storing (or saving) the data held in the second storage circuit 5502. The read circuit 5504 has a function of reading data held in the second memory circuit 5502 or the third memory circuit 5503 and storing it in the first memory circuit 5501 (or returning it).

In particular, the third memory circuit 5503 has a function of reading and storing (or saving) the data held in the second memory circuit 5502 even during a period when the power supply voltage is not supplied to the semiconductor device 5500. have

As shown in FIG. 21, the second memory circuit 5502 includes a transistor 5512 and a capacitor 5519. The third memory circuit 5503 includes a transistor 5513, a transistor 5515, and a capacitor 5520. The read circuit 5504 includes a transistor 5510, a transistor 5518, a transistor 5509, and a transistor 5517.

The transistor 5512 has a function of charging and discharging the capacitor 5519 with charge according to the data held in the first memory circuit 5501. It is preferable that the transistor 5512 can rapidly charge and discharge charges to and from the capacitor 5519 according to the data held in the first memory circuit 5501. Specifically, the transistor 5512 preferably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in a channel formation region.

A conductive state or a non-conductive state of the transistor 5513 is selected according to the charge held in the capacitor 5519. The transistor 5515 has a function of charging and discharging the capacitor 5520 with charge according to the potential of the wiring 5544 when the transistor 5513 is conductive. The transistor 5515 preferably has extremely low off-state current. Specifically, the transistor 5515 preferably includes a metal oxide (preferably an oxide containing In, Ga, and Zn) in the channel formation region.

To specifically explain the connection relationship between each element, one of the source and drain of the transistor 5512 is connected to the first memory circuit 5501. The other of the source and drain of the transistor 5512 is connected to one electrode of the capacitor 5519, the gate of the transistor 5513, and the gate of the transistor 5518. The other electrode of capacitive element 5519 is connected to wiring 5542. One of the source and drain of the transistor 5513 is connected to a wiring 5544. The other of the source and drain of transistor 5513 is connected to one of the source and drain of transistor 5515. The other of the source and drain of the transistor 5515 is connected to one electrode of the capacitor 5520 and the gate of the transistor 5510. The other electrode of capacitive element 5520 is connected to wiring 5543. One of the source and drain of the transistor 5510 is connected to a wiring 5541. The other of the source and drain of transistor 5510 is connected to one of the source and drain of transistor 5518. The other of the source and drain of transistor 5518 is connected to one of the source and drain of transistor 5509. The other of the source and drain of the transistor 5509 is connected to one of the source and drain of the transistor 5517 and the first memory circuit 5501. The other of the source and drain of the transistor 5517 is connected to a wiring 5540. Further, although the gate of the transistor 5509 is connected to the gate of the transistor 5517 in FIG. 21, the gate of the transistor 5509 does not necessarily have to be connected to the gate of the transistor 5517.

The transistor exemplified in the previous embodiment can be applied to the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can retain information for a long period of time without power supply. Since the transistor 5515 has good switching characteristics, the semiconductor device 5500 can perform high-speed backup and recovery.

The structure shown in this embodiment can be used in combination with the structures shown in other embodiments as appropriate.

(Embodiment 7)
In this embodiment, one embodiment of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 22 and 23.

<Semiconductor wafers, chips>
FIG. 22A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a "semiconductor wafer") can be used. A plurality of circuit areas 712 are provided on the substrate 711. A semiconductor device according to one embodiment of the present invention or the like can be provided in the circuit region 712.

Each of the plurality of circuit regions 712 is surrounded by an isolation region 713. A separation line (also referred to as a “dicing line”) 714 is set at a position overlapping the separation region 713. By cutting the substrate 711 along the separation line 714, a chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 22(B) shows an enlarged view of the chip 715.

Further, a conductive layer, a semiconductor layer, or the like may be provided in the isolation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, electro-static discharge (ESD) that may occur during the dicing process can be alleviated, and a decrease in yield due to the dicing process can be prevented. Further, the dicing process is generally performed while supplying pure water in which carbon dioxide gas and the like are dissolved to lower the resistivity to the cutting part for the purpose of cooling the substrate, removing chips, preventing static electricity, and the like. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Therefore, the production cost of semiconductor devices can be reduced. Furthermore, productivity of semiconductor devices can be improved.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIGS. 23(A) and 23(B). Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic components have multiple standards, names, etc., depending on the direction in which the terminal is taken out, the shape of the terminal, etc.

An electronic component is completed by combining the semiconductor device shown in the above embodiment mode and components other than the semiconductor device in an assembly process (post-process).

The post-process will be explained using the flowchart shown in FIG. 23(A). In the pre-process, after a semiconductor device or the like according to one embodiment of the present invention is formed on the substrate 711, a "back surface grinding step" is performed in which the back surface of the substrate 711 (the surface on which the semiconductor device or the like is not formed) is ground (step S721). ). By making the substrate 711 thinner by grinding, it is possible to downsize the electronic component.

Next, a "dicing process" is performed to separate the substrate 711 into a plurality of chips 715 (step S722). Then, a "die bonding process" is performed to bond the separated chips 715 onto individual lead frames (step S723). For bonding the chip 715 and the lead frame in the die bonding process, an appropriate method is selected depending on the product, such as bonding with resin or bonding with tape. Note that the chip 715 may be bonded onto an interposer substrate instead of the lead frame.

Next, a "wire bonding process" is performed to electrically connect the leads of the lead frame and the electrodes on the chip 715 using thin metal wires (step S724). Silver wire, gold wire, etc. can be used as the thin metal wire. Further, as the wire bonding, for example, ball bonding or wedge bonding can be used.

The wire-bonded chip 715 is subjected to a "sealing process (molding process)" in which it is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, and the wires that connect the chip 715 and the leads can be protected from mechanical external forces, and the electrical characteristics can be prevented from deteriorating due to moisture, dust, etc. (deterioration in reliability) can be reduced.

Next, a "lead plating process" is performed to plate the leads of the lead frame (step S726). The plating treatment prevents the leads from rusting, making it possible to more reliably solder them later when mounting them on a printed circuit board. Next, a "forming process" for cutting and molding the lead is performed (step S727).

Next, a "marking process" is performed in which a printing process (marking) is performed on the surface of the package (step S728). Then, the electronic component is completed through an "inspection process" (step S729) to check whether the external shape is good or not, whether there are malfunctions, etc.

Furthermore, a schematic perspective view of the completed electronic component is shown in FIG. 23(B). FIG. 23B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. The electronic component 750 shown in FIG. 23(B) has leads 755 and a chip 715. The electronic component 750 may include a plurality of chips 715.

The electronic component 750 shown in FIG. 23(B) is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined and electrically connected to each other on the printed circuit board 752, thereby completing a board (mounted board 754) on which the electronic components are mounted. The completed mounting board 754 is used for electronic devices and the like.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 8)
<Electronic equipment>
A semiconductor device according to one embodiment of the present invention can be used in various electronic devices. FIG. 24 shows a specific example of an electronic device using a semiconductor device according to one embodiment of the present invention.

FIG. 24(A) is an external view showing an example of an automobile. The automobile 2980 has a body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The car 2980 also includes an antenna, a battery, and the like.

The information terminal 2910 shown in FIG. 24B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. The information terminal 2910 also includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A notebook personal computer 2920 shown in FIG. 24C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The notebook personal computer 2920 also includes an antenna, a battery, and the like inside the housing 2921.

A video camera 2940 shown in FIG. 24(D) includes a housing 2941, a housing 2942, a display portion 2943, an operation switch 2944, a lens 2945, a connecting portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the casing 2941, and the display section 2943 is provided in the casing 2942. The video camera 2940 also includes an antenna, a battery, and the like inside the housing 2941. The casing 2941 and the casing 2942 are connected by a connecting part 2946, and the angle between the casing 2941 and the casing 2942 can be changed by the connecting part 2946. Depending on the angle of the casing 2942 with respect to the casing 2941, the orientation of the image displayed on the display section 2943 can be changed and the display/non-display of the image can be switched.

FIG. 24(E) shows an example of a bangle-type information terminal. The information terminal 2950 includes a housing 2951, a display section 2952, and the like. Furthermore, the information terminal 2950 includes an antenna, a battery, and the like inside the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display section 2952 includes a display panel using a flexible substrate, it is possible to provide the information terminal 2950 that is flexible, lightweight, and easy to use.

FIG. 24(F) shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display section 2962, a band 2963, a buckle 2964, an operation switch 2965, an input/output terminal 2966, and the like. The information terminal 2960 also includes an antenna, a battery, and the like inside the housing 2961. Information terminal 2960 can run various applications such as mobile telephony, e-mail, text viewing and creation, music playback, Internet communication, computer games, etc.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. Further, the display section 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, by touching an icon 2967 displayed on the display section 2962, an application can be started. In addition to setting the time, the operation switch 2965 can have various functions such as turning on and off the power, turning on and off wireless communication, executing and canceling silent mode, and executing and canceling power saving mode. . For example, the functions of the operation switch 2965 can be set using an operating system built into the information terminal 2960.

Further, the information terminal 2960 is capable of performing short-range wireless communication according to communication standards. For example, by communicating with a headset capable of wireless communication, it is also possible to make hands-free calls. Furthermore, the information terminal 2960 is equipped with an input/output terminal 2966, and can directly exchange data with other information terminals via a connector. Further, charging can also be performed via the input/output terminal 2966. Note that the charging operation may be performed by wireless power supply without using the input/output terminal 2966.

For example, a storage device using the semiconductor device of one embodiment of the present invention can retain control information, control programs, and the like for the electronic device described above for a long period of time. By using a semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be achieved.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

10: transistor, 11: transistor, 12: transistor, 13: transistor, 100: insulator, 102: insulator, 105: insulator, 110: insulator, 112: conductor, 120: conductor, 120_1: conductor , 120_2: conductor, 120a: conductor, 120b: conductor, 130: insulator, 130_1: insulator, 130_2: insulator, 130a: insulator, 130b: insulator, 140: conductor, 140_1: conductor , 140_2: conductor, 140a: conductor, 140b: conductor, 145: opening, 150: oxide, 150_1: oxide, 150_2: oxide, 150a: oxide, 150b: oxide, 150c: oxide, 151: oxide, 160: insulator, 161: insulator, 170: conductor, 171: conductor, 175: insulator, 176: insulator, 178: insulator, 180: insulator, 185: conductor, 185_1: conductor, 185_2: conductor, 185a: conductor, 185b: conductor, 190: conductor, 190_1: conductor, 190_2: conductor, 190a: conductor, 190b: conductor, 195: conductor, 195_1: conductor, 195_2: conductor, 195a: conductor, 195b: conductor, 200: conductor, 200_1: conductor, 200_2: conductor, 200a: conductor, 200b: conductor, 210: insulator, 218: conductor, 246: conductor, 248: conductor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator , 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator , 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator , 386: conductor, 711: board, 712: circuit area, 713: separation area, 714: separation line, 715: chip, 750: electronic component, 752: printed board, 754: mounting board, 755: lead, 1000: Capacitive element, 1100: Conductor, 1200: Conductor, 1300: Insulator, 1400: DOSRAM, 1405: Controller, 1410: Row circuit, 1411: Decoder, 1412: Word line driver circuit, 1413: Column selector, 1414: Sense Amplifier driver circuit, 1415: Column circuit, 1416: Global sense amplifier array, 1417: Input/output circuit, 1420: Memory cell and sense amplifier array, 1422: Memory cell array, 1423: Sense amplifier array, 1425: Local memory cell array, 1426: Local sense amplifier array, 1444: Switch array, 1445: Memory cell, 1446: Sense amplifier, 1447: Global sense amplifier, 1500: Insulator, 1600: NOSRAM, 1610: Memory cell array, 1611: Memory cell, 1612: Memory cell, 1613: Memory cell, 1614: Memory cell, 1640: Controller, 1650: Row driver, 1651: Row decoder, 1652: Word line driver, 1660: Column driver, 1661: Column decoder, 1662: Write driver, 1663: DAC, 1670 : output driver, 1671: selector, 1672: ADC, 1673: output buffer, 2000: transistor, 2910: information terminal, 2911: housing, 2912: display section, 2913: camera, 2914: speaker section, 2915: operation switch, 2916: External connection section, 2917: Microphone, 2920: Laptop personal computer, 2921: Housing, 2922: Display section, 2923: Keyboard, 2924: Pointing device, 2940: Video camera, 2941: Housing, 2942: Housing , 2943: Display section, 2944: Operation switch, 2945: Lens, 2946: Connection section, 2950: Information terminal, 2951: Housing, 2952: Display section, 2960: Information terminal, 2961: Housing, 2962: Display section, 2963: band, 2964: buckle, 2965: operation switch, 2966: input/output terminal, 2967: icon, 2980: car, 2981: car body, 2982: wheel, 2983: dashboard, 2984: light, 3000: transistor, 3001: Wiring, 3002: Wiring, 3003: Wiring, 3004: Wiring, 3005: Wiring, 3110: OS-FPGA, 3111: Controller, 3112: Word driver, 3113: Data driver, 3115: Programmable area, 3117: IOB, 3119: Core , 3120: LAB, 3121: PLE, 3123: LUT block, 3124: Register block, 3125: Selector, 3126: CM, 3127: Power switch, 3128: CM, 3130: SAB, 3131: SB, 3133: PRS, 3133 [ 0]: PRS, 3133[1]: PRS, 3135: CM, 3137: Memory circuit, 3137B: Memory circuit, 3140: OS-FF, 3140[1]: OS-FF, 3140[2]: OS-FF, 3141: FF, 3142: Shadow register, 3143: Memory circuit, 3143B: Memory circuit, 3188: Inverter circuit, 3189: Inverter circuit, 5400: Semiconductor device, 5401: CPU core, 5402: Power controller, 5403: Power switch, 5404 : cache, 5405: bus interface, 5406: debug interface, 5407: control device, 5408: PC, 5409: pipeline register 5410: pipeline register, 5411: ALU, 5412: register file, 5421: power management unit, 5422: Peripheral circuit, 5423: Data bus, 5500: Semiconductor device, 5501: Memory circuit, 5502: Memory circuit, 5503: Memory circuit, 5504: Readout circuit, 5509: Transistor, 5510: Transistor, 5512: Transistor, 5513: Transistor, 5515 : Transistor, 5517: Transistor, 5518: Transistor, 5519: Capacitive element, 5520: Capacitive element, 5540: Wiring, 5541: Wiring, 5542: Wiring, 5543: Wiring 5544 Wiring

Claims (5)

a semiconductor layer having a channel forming region;
a first insulating layer having a region functioning as a gate insulating film;
a first conductive layer having a region functioning as a gate electrode;
a second conductive layer having a region functioning as either a source electrode or a drain electrode;
a second insulating layer above the second conductive layer;
a third conductive layer having a region functioning as the other of the source electrode or the drain electrode above the second insulating layer;
The semiconductor layer has a region in contact with a side surface of the second conductive layer, a region in contact with a side surface of the second insulating layer, and a region in contact with a side surface of the third conductive layer,
The first conductive layer has a region sandwiched between the first insulating layers,
The semiconductor layer has a region in contact with the upper surface of the third conductive layer,
The first insulating layer has a region that overlaps with the upper surface of the third conductive layer via the semiconductor layer,
A semiconductor device , wherein the first conductive layer has a region that overlaps with an upper surface of the third conductive layer via the semiconductor layer and the first insulating layer . In claim 1,
In the semiconductor device, the channel length direction of the channel forming region is perpendicular or substantially perpendicular to the substrate surface in a cross-sectional view. In claim 1,
In the semiconductor device, when viewed in cross section, the channel length direction of the channel forming region is in a direction of 60° or more and 120° or less with respect to the substrate surface. In any one of claims 1 to 3,
The semiconductor device, wherein the second insulating layer has a thickness of 1 nm or more and 100 nm or less. In any one of claims 1 to 4 ,
A semiconductor device, wherein the semiconductor layer includes a metal oxide.

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