JP7499799B2 - Gaming Machines - Google Patents

Description

The present invention relates to a gaming machine that executes games.

Patent document 1 describes an enclosed gaming machine (a controlled gaming machine).

JP 2019-122874 A

In recent years, many similar gaming machines have been proposed, and there is a demand for innovative gaming machines.

Therefore, the objective of the present invention is to provide an innovative gaming machine.

The present invention employs the following solutions to solve the above problems. Note that the solutions and the wording in parentheses below are merely examples, and the present invention is not limited thereto. The present invention can be an invention that includes at least one of the invention-specific matters shown in the solutions below. Furthermore, each invention-specific matter shown in the solutions below can be made into a lower-level concept by adding an element that limits the invention-specific matter, and can also be made into a higher-level concept by removing an element that limits the invention-specific matter.

[First technical feature: generating error-related commands outside the area used]
Solution A1: The gaming machine of this solution comprises a game control means for controlling the execution of a game, and a memory means for storing information required for the execution of a game within a usage area provided in a memory area, and for storing information not required for the execution of a game outside an area provided separately from the usage area, wherein the game control means executes a judgment regarding an error using information outside the area during the execution of a game, generates result information indicating the result of the judgment and stores it outside the area, while using information from the usage area to refer to the result information outside the area, generates notification information (e.g., a sub-command) for notifying the outside of the result of the judgment, and stores it in the usage area (e.g., a sub-command buffer).

The gaming machine of this solution has the following configuration.
(1) A game control means (main control board) is provided. The game control means includes, for example, a main control CPU.

(2) A storage means is provided. The storage means includes storage areas such as ROM and RWM, and the storage area includes an outside area (an area separate from the use area) in addition to the use area. The use area stores information required for playing the game (e.g., program code, data tables, flags, commands, etc.). The outside area stores information not required for playing the game (e.g., program code, data tables, flags, commands, etc.).

(3) The game control means executes error-related determinations (e.g., occurrence or cancellation of an error) outside the area. When any determination is made regarding an error, result information (e.g., information set in a sub-command buffer in the usage area) is generated and stored outside the area.

(4) On the other hand, the game control means only generates notification information in the usage area by referencing result information outside the area, and does not perform error determination in the usage area.

This solution eliminates the need to store the amount of information (amount of program code) required to determine errors in the used area, which reduces the amount of information in the used area. As a result, a novel gaming machine can be provided.

Solution A2: The gaming machine of this solution is any of the solutions described above, characterized in that the gaming control means uses information outside the area to make judgments regarding multiple types of errors, generates the result information for each type and stores it outside the area, adding up the number of pieces of result information and storing it, and when referring to the outside area using information in the usage area, does not execute the process of generating the notification information if the number of pieces of result information stored is 0.

The present solution adds the following features:
(1) The game control means uses information outside the area to make judgments regarding multiple types of errors (e.g., switch abnormality error, door open error, magnetic detection error, radio wave detection error, etc.). When any judgment is made regarding any type of error, result information is generated for each type of error and stored outside the area, and at this time the number of pieces of result information is also stored. Conversely, if no judgment is made regarding all types of errors (e.g., if it is not determined that all types of errors have occurred or been released), no result information is generated, and the number of pieces of result information stored is 0.

(2) Then, when the game control means uses the information in the used area to refer to the outside area, if the number of pieces of result information outside the area is zero, the game control means does not execute the process of generating notification information. This is because the number of pieces of result information outside the area being zero means that the result of the error determination will not be notified to the outside, and therefore there is no need to generate notification information.

This solution makes it possible to further simplify the logic used when referencing areas outside the area of use, thereby further reducing the amount of information in the area of use (amount of program code used). As a result, it is possible to provide a more innovative gaming machine.

[Second Technical Feature: Configuration with Reduced Interrupt Processing Code]
Solution B1: The gaming machine of this solution is a gaming machine equipped with a game control means for controlling the execution of a game, and the game control means is characterized in that when it transitions to main loop processing after the initialization processing at power-on is completed, it sets the game control means to an interrupt-disabled state and executes all processing within the main loop processing, and after completion of the processing, sets the game control means to an interrupt-enabled state only for the period from the end of the main loop processing back to the beginning.

The gaming machine of this solution has the following configuration.
(1) A game control means (main control board) is provided. The game control means includes, for example, a main control CPU.

(2) When the power supply of the gaming machine is turned on, the game control means executes an initialization process (e.g., a CPU initialization process). When the initialization process is completed, the game control means moves to a main loop process, and enters a state in which the processes included in the main loop are executed in a loop.
(3) At this time, the game control means executes logic in which the entire main loop process is surrounded by an interrupt disable command and an interrupt enable command. That is, when the game control means transitions to the main loop process, it executes all processes in an interrupt disabled state. The interrupt enabled state is set only for the period when the main loop process returns from the end to the beginning after the execution of all processes is completed.

According to this solution, there is no room to execute another process (e.g., an interrupt process) while all processes are being executed within the main loop, so there is no need to consider how to handle the occurrence of another process during the main loop process or the return from it (e.g., preserving the contents in temporary storage), which reduces the amount of code in the program as a whole. Conversely, since no process that is executed in an interrupt-enabled state is provided within the main loop process, the amount of code in the main loop process can also be reduced. As a result, a more innovative gaming machine can be provided.

Solution B2: The gaming machine of this solution is any of the solutions described above, in which the gaming control means does not execute the process of saving and restoring registers related to the main loop process when an interrupt process that occurs during the execution of the main loop process is executed.

The present solution adds the following features:
(1) During execution of the main loop processing, an interrupt processing (e.g., a timer interrupt processing, a power outage warning interrupt processing) occurs.
(2) When an interrupt process is being executed, the process of saving and restoring registers related to the main loop process is not executed.

This solution makes it possible to omit the process of saving registers when an interrupt occurs in the main loop process, or the process of restoring registers when returning to the main loop process, thereby reducing the amount of program code. As a result, a more innovative gaming machine can be provided.

[Third Technical Feature: Configuration of Checksum Calculation Process Using Specific Instructions]
Solution C1: The gaming machine of this solution is equipped with a game control means for controlling the execution of a game, and a memory means having a memory area capable of storing information relating to the game, and the game control means is characterized in that it executes a checksum calculation process for a specified range by executing a single instruction based on the starting address and number of areas of the range specified in the memory area.

The gaming machine of this solution has the following configuration.
(1) A game control means (main control board) is provided. The game control means includes, for example, a main control CPU.
(2) A storage unit is provided. The storage unit includes storage areas such as a ROM and a RWM.

(3) The game control means executes a checksum calculation process. The checksum calculation process can be executed, for example, when the power is turned off and when the power is turned on (when the power is restored).

(4) The game control means then specifies the range of memory areas for which the checksum is to be calculated by their starting address and the number of areas (e.g., the number of consecutive addresses from the starting address), and executes a single command (e.g., an ADDIR command, an ADDIRS command) to perform the checksum calculation process.

This solution makes it possible to minimize the number of commands used to execute the checksum calculation process (to one), and therefore minimize the time required to execute the process by not executing multiple commands. As a result, it is possible to provide a more innovative gaming machine.

Solution C2: The gaming machine of this solution is any of the solutions described above, characterized in that the gaming control means executes a single command to calculate the checksum of a first range based on a first start address and a first number of areas of the first range specified in the memory area, and then executes a single command to calculate the checksum of a second range based on a second start address and a second number of areas of a different second range.

The present solution adds the following features:
(1) When executing a checksum calculation process for a first range in a memory area, a first start address and the first number of areas for the first range are specified, and a single command is executed.
(2) When a checksum calculation process for a second range is to be executed in a storage area, a second start address and the number of second ranges are specified, and a single command is executed.

According to this solution, when there are multiple ranges (e.g., areas in use and outside areas) within a memory area for which checksums are to be calculated, the calculation process can be performed simply by specifying the starting address and number of areas for each range and executing a single command for each. Therefore, even when checksums are calculated separately for multiple ranges (areas in use, outside areas), the overall processing time can be minimized. As a result, a more innovative gaming machine can be provided.

Solution C3: The gaming machine of this solution is any of the solutions described above (e.g., solution C2), characterized in that the gaming control means is capable of executing different commands for the first range of processing and the second range of processing.

The present solution adds the following features:
That is, in the checksum calculation process in the first range, a specific command can be executed, and in the checksum calculation process in the second range, a special command can be executed.

With this solution, even though different commands are executed for the first and second ranges for which the checksum is calculated, a single command is executed for both, so the processing time can still be minimized.

Solution C4: The gaming machine of this solution is any of the solutions described above, characterized in that the gaming control means stores the checksum calculation result in the memory area during the initialization process executed when the power is turned on, and stores the result of the process of taking the two's complement of the checksum calculation result in the memory area during the interrupt process executed when the power is turned off.

The present solution adds the following features:
(1) The checksum calculation process is performed during the initialization process when the power is turned on and during the interrupt process when the power is turned off.
(2) In the initialization process when the power is turned on, the checksum calculation result is stored in a memory area (e.g., RWM).
(3) In the interrupt process when the power is turned off, the sign of the checksum calculation result is inverted and saved in a storage area (for example, RWM).

According to this solution, the processing time required when the power is turned off is longer than when the power is turned on because the processing to obtain the two's complement is performed, but it is still possible to minimize the processing time required for both the initialization processing when the power is turned on and the interrupt processing when the power is turned off. As a result, a more innovative gaming machine can be provided.

[Fourth technical feature: Configuration of code reduction in variation pattern selection 2 processing]
Solution D1: The gaming machine of this solution comprises a game control means for controlling the execution of a game, and a memory means having a memory area capable of storing information relating to a game, wherein the memory means has a table area in which first data and second data, each having a different number of bits, are set as a pair, and the game control means reads the pair of first data and second data from the table area into a pair of a first register and a second register, and then executes an instruction to divide the value of the first register by a predetermined value, store the quotient in the first register, and store the remainder in a third register, thereby generating the second data by the pair of the third register and the second register.

The gaming machine of this solution has the following configuration.
(1) A game control means (main control board) is provided. The game control means includes, for example, a main control CPU.
(2) A storage unit is provided. The storage unit includes storage areas such as a ROM and a RWM.

(3) In the memory area of the memory means, a table area is set with a data configuration in which first data (e.g., a mode number that is an element that determines the pattern of variation of the patterns) and second data (e.g., a comparison value that is compared with a random number value) are paired. For example, the first data is less than 1 byte, while the second data is larger than 1 byte, and when these are paired, the data structure is 2 bytes in total. Note that multiple pairs of first data and second data are provided in the table area.

(4) The game control means executes a predetermined command (e.g., an LDIN command) and reads a set of first and second data (e.g., data in the table area at the address specified by the contents of the HL register) from the table area into a pair of a first and second register (e.g., register pair AE). At this time, the set of first and second data fits exactly into the pair of 2-byte registers.

(5) The game control means executes a specific command (e.g., DIV D, A, 16), divides the value in the first register by a predetermined value (e.g., 16), stores the quotient in the first register (e.g., the A register), and stores the remainder in a third register (e.g., the D register).

(6) As a result of (5) above, second data (e.g., a comparison value to be compared with the random value) is generated in the pair of the third register and the second register (e.g., register pair DE). At the same time, the first data (e.g., mode number data), which is the quotient of the division, is shifted to the right within the first register (e.g., A register) and set while remaining in the first register.

According to this solution, for a set of first data and second data read from a table area into a pair of a first register and a second register, the "separation of the first data and the second data" and "right shift of the first data" contained therein can be executed with a single instruction, and accordingly the second data can be generated by another pair of a third register and a second register. This makes it possible to minimize the amount of program code required to execute a selection process using a set of data in the table area. As a result, a more innovative gaming machine can be provided.

Solution D2: The gaming machine of this solution is a gaming machine characterized in that, in any of the solutions described above, the gaming control means further executes a process of returning a value associated with the contents stored in the first register as a selection result based on the result of comparing the acquired random number value with the generated second data.

The present solution adds the following features:
The game control means compares the generated second data with the acquired random number value, and returns a selection result based on the result. At this time, the selection result is the content stored in the first register, that is, the value associated with the first data (for example, the value indicated by the address of the table area).

According to this solution, when returning the selection result, there is no need to execute the process of reading the first data from the table area again, which reduces the amount of program code. As a result, a more innovative gaming machine can be provided.

[Fifth technical feature: Configuration of the calculation timing of the base, the role ratio and the consecutive role ratio]
Solution E1: The gaming machine of this solution is equipped with a game control means for controlling the execution of a game, and has multiple types of performance that can be calculated in relation to the game, and is characterized in that the game control means repeatedly executes timer interrupt processing during control, and is capable of executing only one of multiple calculation processes that calculate the multiple types of performance during one timer interrupt processing.

The gaming machine of this solution has the following configuration.
(1) A game control means (main control board) is provided. The game control means includes, for example, a main control CPU.
(2) The game has a plurality of types of performance that can be calculated with respect to a game. The plurality of types of performance include, for example, a base value, a role ratio, a consecutive role ratio, and the like.

(3) The game control means repeatedly executes timer interrupt processing during control. At this time, there are multiple calculation processes that calculate multiple types of performance, but only one of the calculation processes can be executed during one timer interrupt processing.

According to this solution, even if there are multiple types of performance for a gaming machine and multiple calculation processes for calculating each of them, by not executing multiple processes within a single timer interrupt process, it is possible to minimize the time required for the process of calculating the gaming machine's performance. As a result, it is possible to provide a more innovative gaming machine.

Solution E2: The gaming machine of this solution is any of the solutions described above, characterized in that the gaming control means, during execution of one timer interrupt process, determines one of the calculation processes that can be executed within the current timer interrupt process based on the priority set for the multiple calculation processes.

The present solution adds the following features:
(1) Priorities are set in advance for the multiple calculation processes. For example, the order of priority is the calculation process of the base value, the calculation process of the role ratio, and the calculation process of the continuous role ratio.
(2) Even if the conditions for executing multiple calculation processes are met during the current timer interrupt process, only the calculation process with the highest priority is executed without executing multiple calculation processes.

According to this solution, even if a situation arises where multiple types of performance must be calculated due to certain conditions, the processing time can be minimized by executing only one of the calculation processes based on the priority. As a result, a more innovative gaming machine can be provided.

The present invention makes it possible to provide an innovative gaming machine.

FIG. 2 is a block diagram of a managed gaming machine. A diagram showing a memory map of the memory area used by the main control board 30 (main control CPU 31). 13 is a flowchart showing an example of a procedure for CPU initialization processing (1/2). 13 is a flowchart showing an example of a procedure for CPU initialization processing (2/2). FIG. 13 is a diagram showing a program for an interrupt waiting main loop process (1). 13 is a flowchart showing an example of a procedure for an interrupt waiting main loop process (2); FIG. 13 is a diagram showing a program for an interrupt waiting main loop process (2). 13 is a flowchart illustrating an example of a procedure for an interrupt waiting main loop process in a comparative example. FIG. 13 is a diagram illustrating a program of an interrupt waiting main loop process in a comparative example. FIG. 13 is a diagram showing a program for other random number update processing in the comparative example. FIG. 13 is a diagram illustrating a program for timer interrupt processing. FIG. 13 is a diagram showing a program for a save process when power is turned off. 13 is a flowchart illustrating an example of a procedure for a timer interrupt process. 13 is a flowchart showing an example of a procedure for a save process when a power supply is turned off (1/2). 13 is a flowchart showing an example of a procedure for a save process when a power supply is turned off (2/2). FIG. 13 is a diagram showing a program for a checksum calculation process in a comparative example. FIG. 13 is a diagram illustrating a program for checksum verification processing in a comparative example. FIG. 4 is a diagram showing a program for a checksum calculation process according to the present embodiment. FIG. 11 is a diagram showing a program for a checksum confirmation process according to the present embodiment. FIG. 11 is a diagram showing a verification result of the reduction in processing time according to the present embodiment. FIG. 13 is a diagram showing a program for managing the state of a used area; 13 is a flowchart illustrating an example of a procedure for state management processing. FIG. 13 is a diagram showing a program for error checking processing stored outside the area (1/5). FIG. 13 is a diagram showing a program for error checking processing stored outside the area (2/5). FIG. 13 is a diagram showing a program for error checking processing stored outside the area (3/5). FIG. 4 is a diagram showing a program for error checking processing stored outside the area (4/5). FIG. 5 is a diagram showing a program for error checking processing stored outside the area (5/5). FIG. 13 is a diagram showing an example of the configuration of an error management processing table 1 (1/2). FIG. 2 is a diagram showing an example of the configuration of an error management processing table 1 (2/2). FIG. 13 is a diagram illustrating an example of the configuration of an error management processing table 2. 13 is a flowchart showing an example of a procedure for an error checking process (1/7). 13 is a flowchart showing an example of a procedure for an error checking process (2/7). 13 is a flowchart showing an example of a procedure for an error checking process (3/7). 13 is a flowchart showing an example of a procedure for an error checking process (4/7). 13 is a flowchart showing an example of a procedure for an error checking process (5/7). 13 is a flowchart showing an example of a procedure for an error checking process (6/7). 13 is a flowchart showing an example of a procedure for an error checking process (7/7). 13 is a flowchart showing an example of a procedure for a variation pattern determination process. A figure showing a program for the variation pattern selection 2 process of the comparative example. 13 is a flowchart showing an example of a procedure for a variation pattern selection 2 process in a comparative example. A diagram showing the program relationship of the variation pattern selection 2 process in this embodiment. FIG. 13 is a diagram showing allocation using the table “D_MOD_SEL_07”. 13 is a flowchart showing an example of a procedure for the variation pattern selection 2 process of this embodiment. 13 is a flowchart showing an example of a procedure for a performance display monitor display process (1/3). 13 is a flowchart showing an example of a procedure for a performance display monitor display process (2/3). 13 is a flowchart showing an example of a procedure for a performance display monitor display process (3/3). A diagram showing a program for the undetermined prize ball counter addition process. A figure showing a program for executing confirmation of special game management phases, etc. A diagram showing a program for updating the consecutive prize ball counter, etc. FIG. 13 is a diagram showing a program for a calculation management buffer setting process after a base value is calculated. FIG. 13 is a diagram showing a program for allocating processes based on an estimated management buffer. A figure showing a program for the calculation management buffer setting process after calculating the role ratio. A figure showing a program for the calculation management buffer setting process after calculating the ratio of consecutive reels. FIG. 13 is a diagram showing the program for calculating the base value (1/2). FIG. 13 is a diagram showing the program for calculating the base value (2/2). FIG. 13 is a diagram showing the time required to calculate various performance values. FIG. 13 is a diagram showing a correspondence relationship between calculation flags and processes to be executed in another example.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a controlled gaming machine.
The managed gaming machine 100 is equipped with a managed gaming machine game board 10 and a managed gaming machine frame 20, and is an enclosed gaming machine that circulates a certain number of gaming balls within a single machine, eliminating the need for gaming balls to be used in games or for directly paying out gaming balls to players. The managed gaming machine 100 becomes playable by connecting it to a dedicated unit (IC card unit) dedicated to the managed gaming machine.

The managed gaming machine game board 10 is equipped with a game board (acrylic board), a pattern display device (special pattern display device, normal pattern display device), a winning/ball passing detection mechanism (various switches), a windmill, game nails, other performance devices (movable body for performance, LCD display, information display device, speaker, lamp), a winning display device, a device that changes the direction of the ball falling (movable member, cover member), etc.

The managed gaming machine frame 20 is equipped with gaming balls, a launching device, a power supply, a ball polishing device, a gaming ball circulation device, a device for displaying the number of gaming balls, etc., a glass panel, a nighttime monitoring device, other devices for performances, an iron ball detection device, a front decoration, a counting switch, etc.

In the managed gaming machine 100, the front ornament of the managed gaming machine frame 20 can be set to an open state. When the front ornament is set to an open state, the front ornament and the glass plate are opened, and the managed gaming machine game board 10 arranged behind the glass plate is exposed.

[Overview of managed gaming machines]
The overview of the managed gaming machine is as follows:
(1) The managed gaming machine 100 belongs to the same classification as a pachinko machine, and a player plays the game by shooting gaming balls onto the surface of the managed gaming machine gaming board 10.
(2) The controlled gaming machine 100 is structurally incapable of having an upper or lower tray, and the player cannot directly touch the gaming balls.
(3) The managed gaming machine 100 circulates the minimum number of gaming balls required for launch within the managed gaming machine 100, and a launching device, a ball polishing device, and a gaming ball circulation device are provided along the circulation path.
(4) The launching device has the same launching capabilities as current gaming machines and may be bottom-launching or top-launching.
(5) The ball polishing device has a cassette containing abrasive cloths for removing dirt from game balls, which are replaced at regular intervals.
(6) The number of game balls played and the number of acquired game balls are managed and displayed as numerical data in the management gaming machine 100 (frame control board 50).
(7) When the game ends, the number of game balls managed by the managed gaming machine 100 (frame control board 50) can be transferred to a dedicated unit and managed by pressing the counting switch 54 (counting button).

The managed gaming machine game board 10 is equipped with a main control board 30 (game control means) and a presentation control board 40 (presentation control means).
The main control board 30 has a main control CPU 31, and controls the contents related to the progress of the game (or the execution of the game). The presentation control board 40 has a presentation control CPU 41, and controls the contents related to the presentation of the game. The main control board 30 can communicate with the presentation control board 40 and the frame control board 50. The presentation control board 40 can communicate with the main control board 30, but this communication is only one-way from the main control board 30 to the presentation control board 40, and no two-way communication is performed.

The main control board 30 is connected to a winning port switch 32, an out switch 33, a first board magnetic detection sensor 34, a second board magnetic detection sensor 35, a radio wave detection sensor 36, and a performance display monitor 37. The main control board 30 is also connected to a door opening switch 38. The winning port switch 32 includes switches such as a winning port, a large winning port, and a normal winning port (general winning port) corresponding to normal and special patterns. The out switch 33 is arranged in the out passage. A game ball shot into the game area (board) flows down the game area and enters the winning port or the out port, but in either case, it is guided to the out passage and detected by the out switch 33. For example, when the glass door is open, the door opening switch 38 detects the opening of the glass door, and when the inner frame is open, it detects the opening of the inner frame, and outputs a door opening signal (error signal) to the main control board 30. The door opening switch 38 may be configured with two switches, one for the glass door and one for the inner frame, or it may be configured with one switch that serves both the glass door and the inner frame.

The first board magnetic detection sensor 34, the second board magnetic detection sensor 35, and the radio wave detection sensor 36 are error (fraud) detection sensors. The first board magnetic detection sensor 34 and the second board magnetic detection sensor 35 are installed, for example, at different positions on the managed gaming machine game board 10, and when they detect a magnetism of a predetermined strength or more near their respective positions, they output a magnetic detection signal to the main control board 30. The radio wave detection sensor 36 is installed, for example, on the managed gaming machine game board 10, and when they detect a radio wave of a predetermined strength or more near their respective positions, they output a radio wave detection signal to the main control board 30.

The performance display monitor 37 is a display device that displays the performance of the managed gaming machine 100, and has, for example, multiple 7-segment LEDs. The performance display monitor 37 displays the base value, the role ratio, and the consecutive role ratio as performance under specified conditions. Furthermore, if the managed gaming machine 100 has settings, the performance display monitor 37 displays the setting values. Additionally, the performance display monitor 37 can also display code information for errors that have occurred in the managed gaming machine 100.

The performance control board 40 is connected to a liquid crystal display 42, a speaker 43, and a lamp 44. The performance control board 40 (performance control CPU 41) receives commands (sub-commands) sent from the main control board 30, determines the content of the performance based on the received commands, and executes the performance using the liquid crystal display 42, the speaker 43, and the lamp 44.

The managed gaming machine frame 20 is equipped with a frame control board 50. The frame control board 50 has a frame control CPU 51 and controls the contents related to the number of game balls. The frame control board 50 can communicate with the main control board 30. A subtraction sensor 52, a foul ball sensor 53, a counting switch 54, a display device for the number of game balls, etc. 55, a touch sensor 56, and a front decoration opening switch 57 are connected to the frame control board 50.

When the frame control board 50 (frame control CPU 51) receives a prize ball number command (request for the number of acquired game balls) from the main control board 30, it adds the number of prize balls included in the prize ball number command to the number of game balls, and displays it on the game ball number display device 55. When the subtraction sensor 52 detects the launch of a game ball, the frame control board 50 subtracts one from the number of game balls, and displays it on the game ball number display device 55. When the foul ball sensor 53 detects the passage of a game ball, the frame control board 50 adds one to the number of game balls, and displays it on the game ball number display device 55. When the counting switch 54 is pressed, the frame control board 50 transmits the counted number of balls to a dedicated unit not shown, subtracts the counted number of balls from the number of game balls, and displays the number of game balls after subtraction on the game ball number display device 55. When the frame control board 50 receives information on the number of loaned balls from a dedicated unit (not shown), it adds the number of loaned balls to the number of game balls and displays the sum as the number of game balls on the game ball number display device 55. Note that a foul ball (returned ball) is a game ball that has been launched by the launching device but has returned without reaching the game area.

The touch sensor 56 detects from a change in capacitance that the player's body is touching a grip unit (launch handle, ball launcher) not shown, and outputs the detection signal to the frame control board 50. In addition, the front decoration opening switch 57 outputs a door opening signal (error signal) to the frame control board 50 when the front decoration of the managed gaming machine frame 20 is in the open state.

FIG. 2 is a diagram showing a memory map of a memory area used by the main control board 30 (main control CPU 31).
The memory area used by the main control board 30 (main control CPU 31) includes a memory area (0000H to 2FFFH) allocated to ROM and a memory area (F000H to F3FFH) allocated to RAM (RWM).

The area from addresses 0000H to 0BFFH (first area) is an area capable of storing the program code (program) of the usage area. The program code of the usage area is the first information required to execute the game (to control the progress of the game).

The area from addresses 0000H to 0BFFH (first area) stores the program code (first information) in the used area, and special program code (special information), which is a portion of the program code (second information) that is not required to play the game.

The area from address 0C00H to 0FFFH is unused.

The area from address 1000H to 1BFFH (first area) is an area capable of storing program data (data) of the usage area. The program data of the usage area is the first information required for playing a game.
The area from addresses 1000H to 1BFFH (first area) stores program data (first information) in the used area, and special program data (special information), which is a portion of the program data (second information) that is not required for playing the game.

The area from address 1C00H to 1FFFH is unused.

The area from address 2000H to 2FFFH (second area) is an area capable of storing program code and program data outside the area, and is an area separate from the area in use. The program code and program data outside the area is second information that is not required for the execution of the game (for example, related to processing for performing tests defined by gaming machine regulations, or processing related to the performance display monitor). Furthermore, in this embodiment, one of the technical features is that the processing for determining whether an error has occurred and whether it has been cleared is executed outside the area. This technical feature will be described in further detail below.

The area from address 2000H to 2FFFH (second area) stores non-special program code and non-special program data (non-special information), which is the remaining information from the program code and program data (second information) that is not required for playing the game.

The area from address 3000H to EFFFH is unused.

The area from addresses F000H to F1FFH is used as a work area for the used area and a stack RWM.
The area from address F200H to F3FFH is used as an external work area and stack RWM.
These areas are used as areas that are used temporarily when a program in the used area is being executed or when a program outside the area is being executed, or as stack areas for temporarily saving data.

The area from address F400H to FFFFH is unused.

In addition to the use area and outside area, the memory area of the ROM may also have an area in which arbitrary data such as the program title and version is stored, and a program management area in which information required for the main control board 30 (main control CPU 31) to execute the program is stored.

In this way, the ROM and RAM (storage means having a memory area) of this embodiment have a use area (first area) capable of storing program code and program data (first information) required to execute a game, and an outside area (second area) capable of storing program code and program data (second information) not required to execute a game.

Here, the used area is the area in which the capacity available for controlling the progress of the game is determined by the gaming machine rules, and the outside area is the area that is not included in the calculation of the available capacity.

The main control board 30 (main control CPU 31) controls the managed gaming machine 100 based on the program code and program data (first information) required to execute the game and the program code and program data (second information) not required to execute the game (game control means).

The usage area (first area) stores program code and program data (first information) that are required to play the game, and special program code and special program data (special information), which are part of the program code and program data (second information) that are not required to play the game.

Outside the area (second area), non-special program code and non-special program data (non-special information), which are the remaining information from the program code and program data (second information) that is not required for playing the game, are stored.

Special program codes and special program data (special information) are information that differs between different types of machines with different game content, and non-special program codes and non-special program data (non-special information) are information that is common to all types of machines with different game content.

For this reason, when changing the specifications of a gaming machine, it is necessary to change the special program code and special program data. On the other hand, there is no need to change the non-special program code and non-special program data, even when changing the specifications of a gaming machine.

The special program code/special program data (special information) includes information regarding at least one of the processes for calculating the base, a determination process for determining whether or not to calculate the base based on the game status, and a confirmation process for confirming the value of the number of winning balls. Either the determination process or the confirmation process may be non-special program code/non-special program data (non-special information).

In this embodiment, due to the performance of the main control board 30 (main control CPU 31), even if the same command (program code) is used, the processing speed may differ between when it is used in the use area and when it is used outside the area. For example, when the LDQ command (special load command) is used in the use area, the processing speed is faster, but when the LDQ command is used outside the area, the processing speed is not faster. For this reason, the LD command (normal load command), which has a slow processing speed, must be used outside the area. The reason for this is that when the LDQ command is used outside the area, it is necessary to add the saving, resetting, and restoring processes of the stack pointer and Q register, which actually slows down the processing speed.
For this reason, in this embodiment, the processing speed is faster when processing is performed on the used area than when processing is performed on the outside of the area.

The main control board 30 (main control CPU 31) can execute the processing of the usage area (first processing) required to execute the game by using (executing) the program code and program data stored in the usage area (first area) (first processing execution means).

In addition, the main control board 30 (main control CPU 31) can execute processing outside the area (second processing) that is not necessary for playing the game by using (executing) the program code and program data stored outside the area (second area) (second processing execution means).
The above is an example of the configuration for controlling the managed gaming machine 100.

Next, the control processing executed by the main control board 30 (main control CPU 31) will be described. Note that the following description will be given assuming that the main control board 30 executes the processing.

[CPU Initialization (Main) Processing in the Main Control Unit]
When the managed gaming machine 100 is powered on, the main control board 30 starts a CPU initialization process. The CPU initialization process is a process for preparing the initial state of the managed gaming machine 100 by restoring the gaming state (so-called power recovery) based on the backup information saved at the time of the previous power cut, or conversely, clearing the backup information. The CPU initialization process is also positioned as a main process (main control program) for ensuring stable gaming operation of the managed gaming machine 100 after adjusting the initial state.

3 and 4 are flowcharts showing an example of a procedure for CPU initialization processing.
Step S230: The main control board 30 executes a process to set the stack area base address.
Step S231: The main control board 30 executes a process to set an address in the built-in register setting table.
Step S232: The main control board 30 executes a process of loading the upper byte of the built-in register address and the number of set data.
Step S233: The main control board 30 executes a process of setting the built-in register (FFxxH).
Step S234: The main control board 30 executes a process of loading the upper byte of the built-in register address and the number of set data.
Step S235: The main control board 30 executes a process of setting the built-in register (FFxxH) and the launch permission signal.
Step S236: The main control board 30 executes a process of setting the upper byte of the working area start address in the Q register.
Step S237: The main control board 30 executes a process to acquire the state of the input support at the time of power-on.
Step S238: The main control board 30 executes a process to wait for the sub-control to start (wait for the performance control board to start) and to confirm that the power supply of the main control board is stable.

Step S239: The main control board 30 executes a process of outputting a RAM access permission value to the RWM access protection register.
Step S240: The main control board 30 executes a process to check the settings and clear the fraud detection state.
Step S241: The main control board 30 executes a process to call a checksum verification process.

Step S242: The main control board 30 executes a process to confirm whether the checksum is normal or not.
As a result, if it is confirmed that the checksum is normal (Yes), the main control board 30 executes step S243. On the other hand, if it is not confirmed that the checksum is normal (No), the main control board 30 proceeds to the external connector (2) and executes step S246 (FIG. 4).

Step S243: The main control board 30 executes a process to check whether the RWM clear switch has been pressed. The RWM clear switch (not shown) is connected to the main control board 30.
As a result, if it is confirmed that the RWM clear switch has been pressed (Yes), the main control board 30 proceeds to the external connector (3) and executes step S247 (FIG. 4). On the other hand, if it is not confirmed that the RWM clear switch has been pressed (No), the main control board 30 executes step S244.

Step S244: The main control board 30 executes initial settings when power is restored.
Step S245: The main control board 30 executes a transition check for setting confirmation processing.
After completing the processing of step S245, the main control board 30 proceeds to external connector (1) and executes step S253 (FIG. 4).

Step S246: The main control board 30 executes a process to call an out-of-area check process.
Step S247: The main control board 30 executes a work area initialization process.

Step S248: The main control board 30 executes a process to check whether or not there is an RWM abnormality.
As a result, if it is confirmed that there is an RWM abnormality (Yes), the main control board 30 executes step S249. On the other hand, if it is not confirmed that there is an RWM abnormality (No), the main control board 30 executes step S250.

Step S249: The main control board 30 executes a process to set the RWM abnormal state designation value. Next, the main control board 30 executes step S252.

Step S250: The main control board 30 executes a process to check whether or not the setting change conditions have been met.
As a result, if it is confirmed that the setting change condition is satisfied (Yes), the main control board 30 executes step S251. On the other hand, if it is not confirmed that the setting change condition is satisfied (No), the main control board 30 executes step S252.

Step S251: The main control board 30 executes a process to set the setting switching state designation.
Step S252: The main control board 30 executes a process of updating the gaming machine status flag.
Step S253: The main control board 30 executes a process to call the power-on setting process.
Step S254: The main control board 30 executes a process to set a frame command waiting state.
Step S255: The main control board 30 executes a process to reset the daisy chain.
Step S256: The main control board 30 executes a process to prohibit interrupts (interrupt prohibit command).
Step S257: The main control board 30 executes a process to call the initial value random number update process.
Step S259: The main control board 30 executes a process for calling a sub-command transmission process.
Step S260: The main control board 30 executes a process to permit an interrupt (interrupt permission command).
After completing the process of step S259, the main control board 30 returns to the process of step S256 and continues the process, thereby starting the main loop process.

[Second Technical Feature: Configuration with Reduced Interrupt Processing Code]
Here, the second technical feature of this embodiment will be described with a number of examples. Note that although there are first to fifth technical features of this embodiment, the order of the features has been changed for convenience of description. Therefore, the first technical feature and the third and subsequent technical features will be described after the second technical feature.

[Problem of the second technical feature]
The present invention is directed to reducing the program capacity (amount of code) of the used area. This object is also applicable to pachinko machines other than the managed gaming machine 100, as long as the memory means has a used area and an outside area.

[Solution Means According to Second Technical Feature]
In this embodiment, in order to reduce the main program capacity, the program code in the interrupt process is reduced. The interrupt wait main loop process (1) in FIG. 4 constitutes one of the means for solving this problem.

[Details of interrupt waiting main loop processing (1)]
That is, the interrupt waiting main loop process (1) is a process in which the main control board 30 loops through the portion (symbol ML) enclosed by the dotted line frame in Fig. 4. In this embodiment, all processes executed in the interrupt waiting main loop process (1), that is, the initial value random number update process (step S257) and the subcommand transmission process (step S259), are enclosed by an interrupt prohibition command (step S256) and an interrupt permission command (step S260). Therefore, the interrupt permission state in the interrupt waiting main loop process (1) is the period from the execution of the interrupt permission command (step S260) to the execution of the command to return from the end of the program to the beginning until the execution of the interrupt prohibition command (step S256).

Figure 5 shows the program for the interrupt waiting main loop process (1). This program corresponds to the main loop portion (the portion enclosed by the dotted line) in the flowchart in Figure 4. The program (code) for the interrupt waiting main loop process (1) is as follows:

"CPUINIT_80:" is a label indicating the start (first address) of the interrupt waiting main loop process (1).

[Waiting for interrupt main loop processing]
"DI" is an instruction to disable interrupts. This causes the interrupts to be disabled when the interrupt wait main loop process (1) starts.

[Initial value random number update process]
"CALLF INI_RND" is a process for calling an initial value random number update process. This process executes a process for randomly updating the initial values of various software random numbers.

[Subcommand transmission process]
"CALLF SBC_OUT" is a process for calling a subcommand transmission process, which executes a process for outputting a subcommand stored in the subcommand buffer to a port.

"EI" is an instruction to enable interrupts, which enables interrupts.
"JR CPUINIT_80" is a command to jump to the top address of the interrupt waiting main loop process (1).

[Interrupt enabled state period]
Due to the specifications of the EI instruction, immediately after execution, no interrupt occurs and the next instruction is executed. Therefore, the possibility of an interrupt occurring in the interrupt waiting main loop process (1) is limited to immediately after the execution of the "JR CPUINIT_80" instruction.

On the other hand, in the interrupt waiting main loop processing (1), no registers are used before or after executing "JR CPUINIT_80". Therefore, even if the register values are rewritten during an interrupt processing that occurs in an enabled state, there is no problem for the interrupt waiting main loop processing (1) side, and there is no need to consider how to save and restore the registers on the interrupt processing side.

[Waiting for interrupt main loop processing (2)]
6 is a flowchart showing an example of the procedure of the interrupt waiting main loop process (2). In this embodiment, such an interrupt waiting main loop process (2) can also be adopted. Below, the points that differ from the interrupt waiting main loop process (1) in FIG. 4 will be described.

Step S258: The main control board 30 executes a process to call the main command analysis process.

Next, FIG. 7 shows the program for the interrupt waiting main loop processing (2). This program corresponds to the flowchart in FIG. 6. Below, we will explain the differences from the program in FIG. 5. The program (code) for the interrupt waiting main loop processing (2) is as follows:

[Main command analysis process]
"CALLF PY_CMDA" is a process for calling a main command analysis process. In this process, a process for analyzing a command (main command) transmitted from the frame control board 50 is executed.

Similarly, in the interrupt waiting main loop processing (2), all processing is executed in interrupt disabled state, so no registers are used in interrupt enabled state.

Comparative Example
8 is a flowchart showing an example of a procedure for an interrupt waiting main loop process in a comparative example. For comparison with this embodiment, an example is given in which the interrupt waiting main loop process includes a process that is executed in an interrupt enabled state.

Step S141: As in the present embodiment, an interrupt disable command is executed to disable interrupts.
Step S142: Execute the initial value random number update process similar to that of this embodiment.
Step S143: The same main command analysis process as in this embodiment is executed.
Step S144: A sub-command transmission process is executed similarly to the present embodiment.
Step S146: As in this embodiment, an interrupt permission command is executed, and the interrupt permission state is established from the next process execution.

Step S147: In the comparative example, other random number update processing is executed. In this processing, the software random numbers that are not involved in determining the winning symbol (reach group determination random numbers, reach mode determination random numbers, variation pattern determination random numbers, etc.) are updated.

Figure 9 is a diagram showing a program for the interrupt waiting main loop processing of the comparative example. This program corresponds to the flowchart of Figure 8. Below, we will explain the differences from the program for the interrupt waiting main loop processing (2) of this embodiment (Figure 7). The program (code) for the interrupt waiting main loop processing of the comparative example is as follows.

In FIG. 9, "CALLF SBC_OUT" executes a process to call the subcommand transmission process. Next, the EI command is executed to set the interrupt enabled state. The program code up to this point is the same as in this embodiment, but the following process is different.

"CALLF ETC_RND" is a process that calls other random number update processes. This process is executed in an interrupt enabled state. The reason why the other random number update processes are not in an interrupt disabled state is to make the interrupt disabled period as short as possible. In other words, if the other random number update processes were also in an interrupt disabled state, the interrupt disabled period in the main loop processing would become longer, and there would be less time to adequately execute the timer interrupt processing.

Figure 10 is a diagram showing a program for other random number update processing in a comparative example. In the comparative example, the following program is executed in an interrupt enabled state. The program (code) for other random number update processing in the comparative example is as follows:

"ETCRND:" is a label that indicates the start of the other random number update process.

[Special symbol reach mode determination random number update process]
"LD A,R" is an instruction to set the value of the R register.
"LDQ HL, (LOW R_RND_TZ_MOD)" is a command to load a random number for determining a special symbol reach mode.
"ADDWB HL, A" and "INC HL" are commands for updating the special symbol reach mode determination random number.
"LD BC, @RND_MOD_MAX+1" is a command to set the upper limit of the random number for determining the special symbol reach mode.

[Points where interrupts are expected to occur]
The program code continues, but assume that a timer interrupt occurs between [1] and [2] below.
[1] "DIV HL, BC" is a command to divide the update result by the upper limit value of the random number for determining the special symbol reach mode.
[2] "LDQ (LOW R_RND_TZ_MOD), BC" is a command to save the remainder in the special symbol reach mode determination random number.

[Saving and restoring registers on the interrupt processing side]
Even if an interrupt occurs between [1] and [2] above, after returning, the other random number update processing will continue, but it can be seen that the BC register is used in addition to the A register during the processing. Therefore, if the value of the BC register changes during the timer interrupt processing and the processing returns, the value of the BC register saved in the special symbol reach mode determination random number in [2] and the BC register set as a result of the calculation in [1] will be completely unrelated values.
Therefore, on the timer interrupt processing side, it is necessary to save the BC register and the like at the start of processing, and to restore the BC register and the like at the end of the timer interrupt processing.

The program code follows below.
[Special pattern variation pattern random number update process]
"LD DE, @RND_PAT_MAX * 256 + LOW R_RND_TZ__PAT" is a command to set the upper limit value of the special pattern variation pattern random number and the lower byte of the address of the special pattern variation pattern random number.
"RST COUNTUP" is a process for calling the count-up process.
"RET" is an instruction to return to the main loop process waiting for an interrupt from the caller.

[Comparison between this embodiment and a comparative example]
The present embodiment and a comparative example will be compared in terms of a program below.
11 is a diagram showing a timer interrupt processing program. Here, we will explain the part where the comparison result is clear. The timer interrupt processing program (code) is as follows:

"TMR_IPT:" is a label that indicates the start of timer interrupt processing.

[Register save processing]
"PUSH GPR" is an instruction to save the AF, BC, DE, and HL registers.
As shown in the figure as "Comparative Example: Required/Present Embodiment: Not Required," the present embodiment differs in that this process is required in the program of the comparative example, but is completely unnecessary.

[Dynamic port output processing]
"CALLF DYM_OUT" is a process for calling a dynamic port output process.
(Omitted)

[Safety device activation management phase setting process]
"CALLEX E_SFSET" is a process for calling a safety device activation management phase setting process.

[Register recovery process]
"POP GPR" is an instruction to restore the HL, DE, BC, and AF registers.
As shown in the figure as "Comparative Example: Required/Present Embodiment: Not Required," the present embodiment differs in that this process is required in the program of the comparative example, but is completely unnecessary.

[Interrupt permission process]
"TMR_IPT_30" is a label indicating the start of interrupt permission processing.
"EI" is an instruction to enable interrupts.
The "RETI" instruction returns to the state before the interrupt occurred.

As is clear from the above comparison, in the comparative example, it is necessary to save the registers at the start of the interrupt processing, restore the registers at the end, and then execute the process of restoring them before the interrupt occurs, whereas in this embodiment, there is no need to execute these processes. Therefore, it is possible to reduce the amount of program code by that amount. More specifically, the "PUSH GPR" instruction and the "POP GPR" instruction are unnecessary. Since these are both 2 bytes, in this embodiment, it is possible to reduce the amount of code used for timer interrupt processing by a total of 4 bytes compared to the comparative example.

Figure 12 shows the program for the backup process when the power is turned off. Here too, we will focus on the parts where the results of the comparison are clear and explain them. The program (code) for the backup process when the power is turned off is as follows:

"PRFPROC:" is a label that indicates the start of the backup process when the power is turned off.

[Power off warning signal detection confirmation process]
"PUSH AF" is an instruction to save the AF register. As shown in the figure as "Comparative Example: Necessary/Present Embodiment: Not Required," the program of the comparative example requires execution of the present embodiment, but is not required in the present embodiment.
"JIBIT Z, @IN3_PWF_POS, (LOW @IN3_PRT), PRFPROC_10" is a command to branch to "PRFPROC_10" if the power-off warning signal bit of input port 3 is 0.
"POP AF" is an instruction to restore the AF register, and as shown in the figure as "Comparative Example: Necessary/Present Embodiment: Not Required," the program of the comparative example requires execution of this embodiment, but is not required in this embodiment.
The "EI" instruction enables interrupts.
The "RETI" command returns to the state before the save process occurred when the power was turned off.

[Output port clear processing]
"PRFPROC_10:" is a label indicating the start of the output port clear process.
“OUT (LOW @OT1_PRT), @OT1_LCE_BIT” is a command to output a launch enable signal to output port 1.
"LDF HL, D_OUT_PRT" is a command to set the address of the output port address table.
"LD B, @PRT_CLR_LOP" is a command to set the output port initialization loop counter.
"XOR A, A" is a command to set [00H].
(The rest is omitted.)

As is clear from the above comparison, in the comparative example, the registers are saved at the start of the save process when the power is turned off, and when the power off warning signal bit of input port 3 is no longer 0 (the power is no longer turned off), it is necessary to execute a process to restore the registers in preparation for returning to the program address before the power off interrupt occurred, whereas in this embodiment, it is not necessary to execute such a process. Therefore, the amount of program code can be reduced accordingly. More specifically, the "PUSH AF" command and the "POP AF" command are no longer necessary. Since these are both 1 byte, in this embodiment, it is possible to reduce the amount of code used for the save process when the power is turned off by a total of 2 bytes compared to the comparative example.

[Comparison with a flowchart]
Fig. 13 is a flowchart showing an example of a procedure for timer interrupt processing. The flowchart in Fig. 13 partially corresponds to the program in Fig. 11. In Fig. 13, the procedures that need to be executed in the comparative example but do not need to be executed in this embodiment are indicated by dotted lines.

[Steps not required in this embodiment]
As described above, in this embodiment, the register save process (step S300) is not necessary, so the process starts with the dynamic port output process (step S302).

Step S302: The main control board 30 executes dynamic port output processing. In this processing, port output is performed on a common basis in order to control the lighting of each lamp mounted on the performance display monitor 37 or an integrated display board (not shown) using a dynamic lighting method. Specifically, the main control board 30 clears the output port, and then outputs the generated common output data to the port output buffer for the common corresponding to the selected common. The output contents are the contents set in the previous timer interrupt.

The data output to the port output buffer for each common is output to the port one common at a time in this dynamic port output process in sequence each time a timer interrupt process occurs. For example, the data stored for common 1 is output to the port in the timer interrupt process executed next, and the data stored for common 2 is output to the port in the timer interrupt process executed after that, and so on, with the data stored in the port output buffer for each common being processed one by one in sequence. As a result, the lamps that make up the specified display mode (modes for displaying changing or stopped patterns, displaying the number of operation memories, displaying the game status, etc.) and the performance display monitor 37 are driven in sequence on a common basis, and lighting is controlled by the dynamic lighting method.

Step S303: The main control board 30 executes port input processing. In this processing, in order to accurately obtain the latest switch state based on the input port information, the main control board 30 stores in the input port on detection flag the logical product of the input value of the various switch signals from the parallel I/O port and the inverted result value of the previous input value. As a result, the value (ON/OFF) of the input port on detection flag makes it possible to grasp the accurate input state based on the changes in the various switch signals since the previous time. The various switch signals include a winning detection signal from the winning slot switch 32, and detection signals from the fraud detection switches (first board magnetic detection sensor 34, second board magnetic detection sensor 35, radio wave detection sensor 36, etc.).

Step S303a: The main control board 30 checks whether the gaming machine status flag is "00H (playable state)" or not.

As a result, if it is confirmed that the gaming machine status flag is "00H (playable state)" (Yes), the main control board 30 executes step S304. On the other hand, if it is not confirmed that the gaming machine status flag is "00H (playable state)" (No), the main control board 30 executes step S303b.

The reason for performing this type of judgment processing is to prevent normal game-related processing from being executed when settings are being changed, settings are being checked, etc. Furthermore, by not executing normal game-related processing within the timer interrupt processing when settings are being changed, settings are being checked, etc., the load on the program of the main control board 30 can be reduced.

Step S303b: The main control board 30 checks whether the gaming machine status flag is "03H or higher (fatal error state)."

As a result, if it is confirmed that the gaming machine status flag is "03H or higher (fatal error state)" (Yes), the main control board 30 executes step S318 without executing step S303c. On the other hand, if it is not confirmed that the gaming machine status flag is "03H or higher (fatal error state)" (No), the main control board 30 executes step S303c.

The reason for this judgment process is to prevent the system from transitioning to a state in which settings are being changed or checked if a fatal error condition occurs.

Step S303c: The main control board 30 executes a setting change process (setting-related process). By executing this process, the main control board 30 can execute a setting-related process including at least one of a setting change process executed when changing a setting value or a setting confirmation process executed when confirming a setting value (setting-related process execution means). The setting-related process includes processes executed during a setting change or setting confirmation. Then, when the setting change process is completed, the main control board 30 executes step S318. The reason for moving to step S318 is to output an external signal (security signal) in the external information management process.

By executing such processing, the main control board 30 can restrict the execution of at least a portion of the setting-related processing and the base-related processing while one of the processing is being executed (restriction means). In other words, when the setting is being changed or confirmed (step S303a: Yes), the main control board 30 can prevent the execution of at least a portion of the base-related processing (steps S304 to S317, particularly step S308).

Step S304: The main control board 30 executes a timer update process (special information continuous transmission process execution means). In this process, the main control board 30 executes a process (subtraction process, etc.) to update counters of various timers used in the game (timers that manage the change time and stop time of the patterns, the opening and closing time of the electric role, etc.), various timers for external information, timers for security signal output, etc.

Step S305: The main control board 30 executes an initial value random number update process. The content of the process is the same as the initial value random number update process of the interrupt wait main loop process (step S257 in FIG. 4).

Step S306: The main control board 30 executes a winning symbol random number update process. In this process, the main control board 30 updates the counter values for generating various random numbers for the lottery of special symbols and normal symbols. The value of each counter is incremented in the counter area of the RAM, and each loops within a specified range. The various random numbers include, for example, a winning symbol random number.

Step S307: The main control board 30 executes switch management processing. In this processing, it determines the events that have occurred during play based on the winning detection signal from the winning slot switch 32, among the switch signals input in the previous port input processing (step S303), and executes processing according to each of the events that have occurred.

Step S308: The main control board 30 executes an addition number calculation process (base-related process execution means). The addition number calculation process is a base-related process. This process is a process for the use area. In this process, the main control board 30 checks the game status and the state of the winning slot switch 32 and the out switch 33, and calculates the "value to be added to the RAM outside the area (additions such as the number of winning balls and outs generated in 4 ms)" for the base calculation. Specifically, the main control board 30 executes a process to determine the values of the number of shot balls A (normal out addition number), the number of shot balls B (total out addition number), and the number of acquired balls (normal prize ball addition number).

Step S309, Step S310: The main control board 30 executes special game management processing and normal game management processing. These processes are intended to specifically progress the game on the managed gaming machine 100.

In the special game management process (step S309), the main control board 30 controls the execution of an internal lottery corresponding to the first special pattern or the second special pattern, determines the variable display or stationary display by the first special pattern display device and the second special pattern display device (not shown), and controls the operation of the first variable winning device and the second variable winning device (not shown) according to the display results.

In addition, in the normal game management process (step S310), the main control board 30 determines the variable display and stop display by the normal pattern display device (not shown), and controls the operation of the variable start winning device (not shown) according to the display result.

Step S311: The main control board 30 executes a status management process. In this process, the main control board 30 checks whether an error state such as an abnormality in the winning frequency or a base abnormality has occurred. If an error state is detected, the main control board 30 notifies the arcade's hall computer of the abnormality by outputting a security signal and by sending a specified error command to the performance control board 40. Note that in this process, the main control board 30 may also execute error processing related to door opening and fraud detection (magnets, radio waves, vibrations, etc.).

Step S312: The main control board 30 executes the winning port switch process. In this process, if the input port on detection flags stored based on the winning detection signal input from the winning port switch 32 in the previous port input process (step S303) are ON, the prize ball control counters for each are updated by incrementing them by 1.

Step S313: The main control board 30 executes the payout control management process. In this process, the main control board 30 first checks whether the payout command buffer is empty (whether the payout command to be sent is set), and if it is not empty (the payout command is set), it sends the various payout commands output to the payout command buffer to the frame control board 50. For example, the payout command indicating the startup mode when the power is turned on is set during the CPU initialization process and output to the payout command buffer, and the payout command indicating this startup mode is sent in this process. On the other hand, if the payout command buffer is empty, it proceeds to a process for instructing the payout of prize balls. The main control board 30 checks whether the prize ball control counter is not 0, and if the prize ball control counter is not 0, it sends a prize ball-designated payout command indicating the number of prize balls corresponding to this counter to the frame control board 50.

In particular, when the power is turned on, if the payout command set during the CPU initialization process is sent normally, the main control board 30 uses this as an opportunity to turn on the launch permission signal. Specifically, the main control board 30 clears the payout command buffer that was output when the power was turned on, and turns on the launch permission signal by setting a specific bit of the output port. This allows the launch of game balls after confirming normal operation after power is turned on, and this launch permission signal is sent to the frame control board 50, making it possible to launch game balls.

In addition, the main control board 30 outputs a prize ball content command that transmits the content of the number of prize balls to the performance control board 40 in the payout control management process. When a winning detection signal is input from the winning port switch 32 corresponding to the first variable winning device or the second variable winning device (not shown), a prize ball content command corresponding to the first profit (e.g., 15 game balls) is generated. Note that generating a command means storing the command in a sub-command transmission buffer (same below). In addition, when a winning detection signal is input from the winning port switch 32 corresponding to the normal winning port (not shown), a prize ball content command corresponding to the second profit (e.g., 10 game balls) is generated. The prize ball content command is transmitted to the performance control board 40 in the sub-command transmission process (step S259 in FIG. 4) of the interrupt waiting main loop process.

Step S315: The main control board 30 executes a test signal management process. This process can be an out-of-area process. In this process, the main control board 30 generates various test signals that indicate its own internal state (e.g., normal symbol game management state, special symbol game management state, launch position designation state, big win, small win, probability fluctuation function in operation, time reduction function in operation, etc.) and stores these in the port output request buffer. These test signals make it possible to test the internal state, for example, outside the main control board 30.

Step S316: The main control board 30 executes an LED display setting process. In this process, the main control board 30 executes a process to generate common output data for controlling the lighting of LEDs included in the normal symbol display device, normal symbol operation memory lamp, first special symbol display device, second special symbol display device, first special symbol operation memory lamp, second special symbol operation memory lamp, game status display device, etc. (not shown). Note that the process related to the performance display monitor 37 is executed in the performance display monitor control process.

More specifically, the main control board 30 generates drive signals as common output data to light up each lamp in a corresponding manner based on the changing and stopping display of the patterns, the number of operation memories, the game status display, etc., determined in the special game management process (step S309) and the normal game management process (step S310).

Step S317: The main control board 30 executes a solenoid data setting process. In this process, the main control board 30 combines (combines) the drive signals and test signals of the normal electric role solenoid (not shown), the first large prize opening solenoid, and the second large prize opening solenoid, which are generated in the special game management process (step S309) and the normal game management process (step S310), and stores them in the port output buffer. After this, the main control board 30 executes a solenoid data port output process. In this process, the main control board 30 checks whether a value is stored in each output buffer (port output buffer), and if a value is stored, outputs the port. For example, it outputs the drive signals of each solenoid stored in the port output buffer to the port. In this case, each drive signal is sent to the corresponding solenoid, and each solenoid performs an operation according to the drive signal.

Step S318: Next, the main control board 30 executes an external information management process. In this process, the main control board 30 stores in the port output request buffer external information signals (e.g., winning ball information, door opening information, number of pattern determination information, jackpot information, starting gate information, security signals, etc.) to be output to the hall computer of the game center via a dedicated unit (not shown).
In the external information management process, when "settings are being changed or settings are being confirmed" or the like, an external signal (security signal) is output.

Here, a security signal is a signal that is output when some abnormal condition occurs or when the system transitions to a setting change state or setting confirmation state.

The main control board 30 refers to the value stored in the gaming machine status flag (gaming machine status information) and decides whether or not to transmit a security signal (special information transmission process execution means). For example, if the gaming machine status flag stores a value (00H) corresponding to a playable state, it decides not to transmit a security signal, and if it stores a value (01H to 05H) other than the value (00H) corresponding to a playable state, it decides to transmit a security signal.

Step S319: The main control board 30 executes the performance display monitor control process (base-related process execution means). The performance display monitor control process is a base-related process. This process is outside the area. In this process, the main control board 30 executes processes such as switching the display contents of the performance display monitor 37, calculating the base value, the role ratio, and the continuous role ratio as performance, and generating a drive signal for displaying the calculated base value, the role ratio, and the continuous role ratio on the performance display monitor 37 as common output data. Details of the process will be described later.

[Steps not required in this embodiment]
As described above, in this embodiment, the register restoration process (step S320) is not necessary.

Step S321: The main control board 30 executes a safety device activation management phase setting process. In this process, a safety device activation management phase is set. The safety device is activated when the number of payouts in one day reaches a specified number, and the managed gaming machine 100 stops playing (stops playing).

Step S322: The main control board 30 executes the interrupt permission process. By permitting interrupts here, it becomes possible for other interrupts to occur while the next step or subsequent steps of the timer interrupt process are being executed. In this way, multiple interrupts are permitted in the timer interrupt process.

When the above steps are performed, the main control board 30 ends the timer interrupt process and returns to the main loop process waiting for an interrupt. As described above, the interrupt-enabled state does not occur while the register is in use in the main loop process waiting for an interrupt, so there is no need to consider any special measures for the register when returning.

Figures 14 and 15 are flowcharts showing an example of the procedure for the evacuation process when the power is turned off. This flowchart partially corresponds to the program in Figure 12. This process is executed by the main control board 30 (main control CPU 31).

[Steps not required in this embodiment]
As described above, in this embodiment, the register save process (step S270) indicated by the dotted line in the figure is not necessary, and the process starts with the power cut warning signal detection confirmation process (step S280).

[Power off warning signal detection confirmation process]
Step S280: The main control board 30 executes a process to confirm (reconfirm) whether the power off warning signal is ON.
As a result, when it is confirmed that the power-off warning signal is ON (Yes), the main control board 30 executes step S282. On the other hand, when it is not confirmed that the power-off warning signal is ON (No), the main control board 30 executes step S281.

Step S281: The main control board 30 executes a process to permit an interrupt.
When the processing of step S281 is completed, the main control board 30 returns to the address before the interrupt.

[Steps not required in this embodiment]
As described above, in this embodiment, even if the power is no longer off and the state returns to the state before the interrupt, the register restoration process (step S272) indicated by the dotted line in the figure is not required.

Step S282: The main control board 30 executes a process of outputting a launch permission signal to output port 1.
Step S283: The main control board 30 executes a process to set the address in the output port address table.
Step S284: The main control board 30 executes a process to set an output port initialization loop counter.
Step S285: The main control board 30 executes a process of setting [00H] in the A register.
Step S286: The main control board 30 executes a process to load the contents of the target address.
Step S287: The main control board 30 executes a process of outputting [00H] to the output port.
Step S288: The main control board 30 executes a process to increment the HL register.

Step S289: The main control board 30 executes a process to check whether the loop is to continue (i.e., whether the processes from step S286 to step S288 are to be executed again).
As a result, if it is confirmed that the loop is to continue (Yes), the main control board 30 executes step S286. On the other hand, if it is not confirmed that the loop is to continue (No), the main control board 30 proceeds to the external connector (1) and executes step S290 (FIG. 15).

Step S290: The main control board 30 executes a process to call the checksum calculation process.
Step S291: The main control board 30 executes a process of outputting a RAM access prohibition value to the RWM access protection register.
Step S292: The main control board 30 executes a process of setting the power off warning signal confirmation setting value.

Step S293: The main control board 30 executes a process to check whether the power off warning signal is on or not.
As a result, if it is confirmed that the power-off warning signal is on (Yes), the main control board 30 executes step S292. On the other hand, if it is not confirmed that the power-off warning signal is on (No), the main control board 30 executes step S294.

Step S294: The main control board 30 executes a process to decrement the HL register.

Step S295: The main control board 30 executes a process to check whether the second zero flag is 0 or not.
As a result, when it is confirmed that the second zero flag is 0 (Yes), the main control board 30 executes step S293. On the other hand, when it is not confirmed that the second zero flag is 0 (No), the main control board 30 executes a process of jumping to address [0000H].

[Third Technical Feature: Configuration of Checksum Calculation Process Using Specific Instructions]
Here, a third technical feature of this embodiment will be described. The third technical feature is a configuration in which specific instructions are used in the checksum calculation process (step S290 in FIG. 15) executed in the save process when the power is turned off, and the checksum confirmation process (step S241 in FIG. 3) executed in the CPU initialization process.

[Problem of the third technical feature]
The present invention aims to reduce the time required to calculate a checksum when the power is turned off and to confirm the checksum when the power is turned on again.
That is, in a gaming machine such as the managed gaming machine 100, the backup check data and checksum are checked when the power is turned on, and if any abnormality is found (including the first time the machine is started), all RWMs are cleared.
At this time, the backup check data and checksum settings are created and saved during the backup process when the power is turned off. However, because the power supply has already been cut off, the calculation and confirmation of the checksum must both be completed in the shortest possible time.

[Checksum calculation method]
The checksum is calculated by subtracting the entire used area excluding the two bytes of the stack area from the used RWM outside the area, and taking the lowest byte of the result. For example, if the RWM values to be calculated are 1, 2, 3, and 4, the result is 0-1-2-3-4=-10.
Since the checksum is an unsigned 1-byte integer (0 to 255), the value stored in the RWM will be -10 + 256 = 246.

After extensive research, the inventors of the present invention discovered that by using specific commands in the checksum calculation process, the process can be completed in an extremely short time. The specific commands are the ADDIR command and the ADDIRS command that can be executed by the main control board 30 (main control CPU 31). By using these commands in the checksum calculation process, the processing time (number of states) can be minimized. Below, the third technical feature will be explained in comparison with a comparative example.

[Comparative Example Checksum Calculation Process]
Fig. 16 is a diagram showing a program of a checksum calculation process of a comparative example. In the comparative example, the configuration does not use the specific command used in this embodiment. In the program code of Fig. 16, the numbers in parentheses added to each line indicate the number of internal clocks (number of states) required for the main control CPU 31 to execute the command. The program (code) of the checksum calculation process of the comparative example is as follows:

"E_CLSUM_01:" is a label indicating the start of the checksum calculation process.
(Omitted)

[Used area checksum calculation process]
(1) "XOR A, A" is an instruction to set [00H] in the A register. The number of states is 1.
(3) "LD HL, @RM_RAMADR" is a command to set the start address of the working area in the HL register. The number of states is 3.
(3) "LD BC, @CHK_ARE" is a command to set the number of checksum calculation areas in the BC register. The number of states is 3.

[Loop processing]
"E_CLSUM_10:" is a label indicating the start address of the loop processing.
(2) "SUB A, (HL)" is an instruction to calculate the RWM checksum of the address currently set in the HL register. The number of states is 2.
(1) "INC HL" is an instruction to increment the HL register and set the next RWM address. The number of states is 1.
(2) "DEC BC" is an instruction to subtract 1 from the number of checksum calculation areas. When the checksum calculation area is completely calculated, the BC register becomes 0. The number of states is 2.
(3/2) "JR NTZ, E_CLSUM_10" is an instruction that branches to the beginning if the checksum calculation area has not been completely calculated and the loop continues. The number of states is 3 in the case of branching and 2 in the case of not branching.

[Out-of-area checksum calculation process]
(2) "LDQ HL, LOW @RM_EXTADR" is a command to set the start address of the outside work area in the HL register. The number of states is 2.
(2) "LD B, @EXD_USE_ERW" is an instruction to set the number of RWM areas outside the area to the B register. The number of states is 2.

"E_CLSUM_20:" is a label indicating the start address of the loop processing.
(2) "SUB A, (HL)" is an instruction to calculate the RWM checksum of the address currently set in the HL register. The number of states is 2.
(1) "INC HL" is an instruction to increment the HL register and set the next RWM address. The number of states is 1.
(3/2) "DJNZ E_CLSUM_20" is an instruction that branches to the beginning if the loop continues when the RWM usage area outside the area has not been calculated (the B register is subtracted and is not 0). The number of states is 3 in the case of branching and 2 in the case of not branching.

[Sum check buffer setting process]
(3) "LDQ (LOW R_ERW_SUM), A" is a command to save the calculation result in the sum check buffer. The number of states is 3.

[Number of states required for checksum calculation process in comparative example]
From the above, for example, if the RWM of the used area to be checked is 510 bytes, and the RWM outside the area is 170 bytes, the total number of states required to calculate the checksum is 1+3+3+(510-1)*(2+1+2+3)+(2+1+2+2)+2+2+(170-1)*(2+1+3)+(2+1+2)+2=5112. Therefore, if the internal system clock of the main control CPU 31 is 16 MHz, the execution time for the checksum calculation process in the comparative example is 0.3195 ms.

[How to check the checksum]
The method for checking the checksum is to check whether the lowest byte of the result of subtracting the entire area of the used area excluding the 2 bytes of the stack area from the used RWM outside the area is 0. For example, if the RWM values are 1, 2, 3, and 4 and 246 is saved as the checksum, the result is 1 + 2 + 3 + 4 + 246 = 256, and the lowest byte is 0, so in this case it can be confirmed that the checksum has been saved correctly.

[Comparative Example Checksum Verification Process]
17 is a diagram showing a program for checksum confirmation processing of a comparative example. Here again, the comparative example is configured not to use the specific command used in this embodiment. Also, in the program code of FIG. 17, the numbers in parentheses added to each line indicate the number of states. The program (code) for checksum confirmation processing of the comparative example is as follows:

"E_CKSUM_01:" is a label indicating the start of the checksum verification process.
(Omitted)

[Used area checksum calculation process]
(1) "XOR A, A" is an instruction to set [00H] in the A register. The number of states is 1.
(3) "LD HL, @RM_RAMADR" is a command to set the start address of the working area in the HL register. The number of states is 3.
(3) "LD BC, @CHK_ARE" is a command to set the number of checksum calculation areas in the BC register. The number of states is 3.

"E_CKSUM_10:" is a label indicating the start address of the loop processing.
(2) "ADD A, (HL)" is a command to calculate the RWM checksum of the address currently set in the HL register. The number of states is 2.
(1) "INC HL" is an instruction to increment the HL register and set the next RWM address. The number of states is 1.
(2) "DEC BC" is an instruction to subtract 1 from the number of checksum calculation areas. The BC register, which calculates all checksum calculation areas, becomes 0. The number of states is 2.
(3/2) "JR NTZ, E_CKSUM_10" is an instruction that branches to the beginning if the checksum calculation area has not been completely calculated and the loop continues. The number of states is 3 in the case of branching and 2 in the case of not branching.

[Out-of-area checksum calculation process]
(2) "LDQ HL, LOW @RM_EXTADR" is a command to set the start address of the outside work area in the HL register. The number of states is 2.
(2) "LD B, @EXD_USE_ERW" is an instruction to set the number of RWM areas outside the area to the B register. The number of states is 2.

"E_CKSUM_20:" is a label indicating the start address of the loop processing.
(2) "ADD A, (HL)" is a command to calculate the RWM checksum of the address currently set in the HL register. The number of states is 2.
(1) "INC HL" is an instruction to increment the HL register and set the next RWM address. The number of states is 1.
(3/2) "DJNZ E_CKSUM_20" is an instruction that branches to the beginning if the loop continues when the RWM usage area outside the area has not been calculated (the B register is subtracted and is not 0). The number of states is 3 in the case of branching and 2 in the case of not branching.

"E_CKSUM_30" is a label that indicates the start of the checksum result flag setting process. The process of determining whether the checksum is abnormal is performed by referencing the checksum result flag (R_ERW_BRS) from the used area, but the program is omitted here.

[Checksum result flag setting process]
(3) "LDQ (LOW R_ERW_BRS), A" is an instruction to save a value to the checksum result flag. The number of states is 3.

[Number of states required for checksum verification process in comparative example]
As a result, the total number of states required to calculate the checksum in the checksum verification process when power is turned on is 5112, the same as when power is turned off. Therefore, the execution time for the checksum verification process in the comparative example is also 0.3195 ms.

[Checksum calculation process of this embodiment]
FIG. 18 is a diagram showing a program of the checksum calculation process of this embodiment. In this embodiment, the ADDIR instruction and the ADDIRS instruction are used to calculate and confirm the checksum. The ADDIR instruction and the ADDIRS instruction are instructions to calculate the sum of the RWM of the number of bytes specified by the BC register (B register for the ADDIRS instruction) from the start address specified by the HL register. Since there is no instruction to calculate the difference instead of the sum, when setting the value of the checksum buffer in the save process at the time of power off, the sum is first calculated and then the two's complement is taken (the sign is inverted). Below, the same instructions as in the comparative example will be omitted, and the explanation will be centered on the instructions unique to this embodiment. The program (code) of the checksum calculation process of this embodiment is as follows.

"E_CLSUM_01:" is a label indicating the start of the checksum calculation process.
(Omitted)

[Used area checksum calculation process]
(1) “XOR A, A”: Same as the comparative example.
(3) “LD HL, @RM_RAMADR”: Same as the comparative example.
(3) "LD BC, @CHK_ARE" Same as the comparative example.
(3) "ADDIR" is a block search command. Specifically, it calculates the sum of RWMs from the start address (@RM_RAMADR) to the number of bytes specified by the number of checksum calculation areas (@CHK_ARE). Here, the number of states per byte added is 3.

[Out-of-area checksum calculation process]
(2) "LDQ HL, LOW @RM_EXTADR": Same as the comparative example.
(2) “LD B, @EXD_USE_ERW”: Same as the comparative example.
(3) "ADDIRS" is a block search command. Specifically, it calculates the sum of RWMs from the start address (@RM_EXTADR) to the number of bytes specified by the number of checksum calculation areas (@EXD_USE_ERW). Here, the number of states per byte added is 3.

[Sum check buffer setting process]
(2) "NEG" is an instruction to set a two's complement number. The number of states is 2.
(3) "LDQ (LOW R_ERW_SUM), A" is an instruction to save a value in the checksum buffer. The number of states is 3.

[Number of States Required for Checksum Calculation Processing in This Embodiment]
From the above, if the RWM of the used area to be checked is 510 bytes and the RWM outside the area is 170 bytes, as in the comparative example, the total number of states required to calculate the checksum in this embodiment is 1 + 3 + 3 + 510 * 3 + 2 + 2 + 170 * 3 + 2 + 3 = 2056. Therefore, if the internal system clock of the main control CPU 31 is 16 MHz, the processing time will be reduced to 0.1285 ms in this embodiment.

Similarly, the checksum verification process will be described below.
19 is a diagram showing a program for the checksum confirmation process of this embodiment. The program (code) for the checksum confirmation process of this embodiment is as follows.

"E_CLSUM_01:" is a label indicating the start of the checksum verification process.
(Omitted)

[Used area checksum calculation process]
(1) “XOR A, A”: Same as the comparative example.
(3) “LD HL, @RM_RAMADR”: Same as the comparative example.
(3) "LD BC, @CHK_ARE": Same as the comparative example.
(3) "ADDIR" is a block search command (referred to as a block search because it is a checksum check when power is turned on). Specifically, it calculates the sum of the RWMs for the number of bytes specified by the number of checksum calculation areas (@CHK_ARE) from the start address (@RM_RAMADR). The number of states per byte added is 3.

[Out-of-area checksum calculation process]
(2) "LDQ HL, LOW @RM_EXTADR": Same as the comparative example.
(2) “LD B, @EXD_USE_ERW”: Same as the comparative example.
(3) "ADDIRS" is a block search command. Specifically, it calculates the sum of RWMs from the start address (@RM_EXTADR) to the number of bytes specified by the number of checksum calculation areas (@EXD_USE_ERW). The number of states per byte added is 3.

[Checksum result flag setting process]
(3) "LDQ (LOW R_ERW_BRS), A" is an instruction to save a value to the checksum result flag. The number of states is 3.

[Number of states required for checksum verification processing in this embodiment]
From the above, the total number of states required to calculate the checksum in the checksum verification process of this embodiment is 1 + 3 + 3 + 510*3 + 2 + 2 + 170*3 + 3 = 2054. Because there is no need to use the NEG instruction to invert the sign, the number of states is 2 fewer than when the power is turned off, and the processing time is reduced to 0.128375 ms.

[Verification results of the third technical feature]
20 is a diagram showing the verification results of the reduction in processing time according to this embodiment. The following advantages are evident from the verification results in FIG.
(1) The processing time for checksum calculation can be improved by approximately 59.78% compared to the comparative example.
(2) The processing time for the checksum verification process can be improved by approximately 59.82% compared to the comparative example.
(3) Overall, the time required to calculate the checksum can be reduced to approximately 1/2.5.
(4) This allows the system to transition to the main loop processing more quickly when the power is turned on.
(5) In particular, when the power is turned off, the checksum calculation can be completed reliably before the power supply is completely cut off, improving the reliability of the save process.
(6) The same usefulness can be obtained even when the managed gaming machine 100 is a slot machine.

[First technical feature: Configuration for generating commands outside the area when an error occurs or is cleared]
Next, a first technical feature of this embodiment will be described.

[Problem of the second technical feature]
The present invention is directed to reducing the program capacity (amount of code) of the used area. This object is also applicable to pachinko machines other than the managed gaming machine 100, as long as the memory means has a used area and an outside area.

[Solution Means According to First Technical Feature]
In this embodiment, a program stored outside the area is executed to determine whether an error has occurred or been cleared. If it is determined that an error has occurred or been cleared outside the area, a subcommand is generated and saved in the RWM outside the area. If a subcommand is saved in the RWM outside the area, the program stored in the area of use is configured to read it and set a subcommand buffer in the area of use.

The reason why the sub-command buffer is not set even if an error has occurred or been released outside the area is as follows. That is, since the sub-command buffer is located within the RWM of the area in use, it cannot be written to by a program outside the area. Also, handle detection does not fall under fraud prevention measures, but is related to game execution, so it is necessary to perform detection in the area in use.

The outline of the program configuration is that a state management process is configured on the usage area side, and an error checking process module is placed outside the area and called and executed. The outside-area error checking process determines whether various errors have occurred or been cleared, and the result of the determination is saved in the RWM outside the area as a subcommand (for reference from the usage area), before returning to the caller. On the usage area side, if it is confirmed that a subcommand has been saved outside the area, it will set the subcommand again in the RWM of the usage area.

[Used area status management process]
Fig. 21 is a diagram showing a program for managing the state of used areas. The program (code) for managing the state is as follows: Note that in the program code in Fig. 21, the numbers in parentheses on each line indicate the number of bytes used.

"STC_PRC:" is a label that indicates the start of the state management process.

[Error checking process]
(2) "CALLEX E_CKERR" is a process for calling an error checking process outside the area. The code size here is 2 bytes.
In the outside-area error confirmation process, subcommands related to the error are set in the outside-area RWM. After this process is completed, the following program clears the winning abnormality error flag (R_ERR_FLG). In this way, the winning abnormality error flag is cleared in the status management process immediately after it is set, but before it is cleared, the subcommand is set, the game stop request flag is set, and the fraud detection 1 information bit timer is set.

[Error flag clear processing]
(2) "CLRQ (LOW R_ERR_FLG)" is a command to clear the winning error flag. The code size here is 2 bytes.

[Subcommand request counter confirmation process]
In the following program, the subcommand set in the RWM outside the area is read out in the error checking process, and the subcommand set process (SBCMDST) is called.
(3) "LD HL, R_ERW_SBC" is a command to set the address of the subcommand request counter in the HL register. The code size here is 3 bytes.
(1) "LD B, (HL)" is an instruction to load the contents of the target address specified by the HL register. Specifically, it loads the number of subcommands set outside the area. The code size here is 1 byte.
(2) "JR TZ, STC_PRC_20" is an instruction to branch to label "STC_PRC_20" if the second zero flag is 1. Specifically, branching occurs when the number of loaded subcommands is 0. The amount of code here is 2 bytes.

"STC_PRC_10:" is a label indicating the start of the sub-command set processing.
[Subcommand set processing]
(2) "INLD DE, (HL)" is an instruction to load a subcommand. Specifically, it loads the preceding command and the following command from the subcommand request buffer (R_ERW_SCD). The subcommand request buffer is located immediately after the subcommand request counter, and the INLD instruction updates the HL register while loading the value of the subcommand request buffer into the DE register. The amount of code here is 2 bytes.
(1) "RST SBCMDST" is a process that calls the subcommand set process. Here, a subcommand is set in the subcommand buffer. Note that all subcommands set outside the area are set to not allow addition (bit 0 of the E register is set to "1"). This is to omit clearing the A register in the area of use (such as "XOR A, A"). The code size here is 1 byte.

[Loop count determination process]
(2) "DJNZ STC_PRC_10" is an instruction to branch to the beginning "STC_PRC_10" if not all subcommands have been set (B register is not subtracted to 0) and the loop continues. In other words, if not all subcommands set outside the area have been read, the loop returns to the beginning. The amount of code here is 2 bytes.

"STC_PRC_20:" is a label indicating the start of the game board error state flag update process.
[Game board error status flag update process]
If the outside-area error confirmation process determines that there is a fatal abnormality that requires game play to be stopped (an error is determined), the outside-area game stop request flag will be set to a value indicating game play stop (@YUG_HNF, 06H).
In the following program for the use area, this value is ORed with the game board error status flag (R_YUG_ERR) in the use area. Note that the possible values for the game board error status flag are either "00H" or "06H".
(3) "LD A, (R_ERW_YER)" is a command to load a game stop request flag. The code size here is 3 bytes.
(3) "ORQ (LOW R_YUG_ERR), A" is a command to OR the game stop request flag with the game board error state flag. The code size here is 3 bytes.

[Handle detection signal confirmation process]
(2) "LDQ A, (LOW R_IN1_PRT)" is an instruction to load the input port 1 status flag. The code size here is 2 bytes.
(2) "AND A, @IN1_HDL_BIT" is an instruction to perform a logical AND operation on the input port 1 status flag and the handle detection signal. The code size here is 2 bytes.
(3) "RCPQ Z, A, (LOW R_HDL_STS)" is an instruction to compare with the handle status and return to the caller if the zero flag is 1. The amount of code here is 3 bytes.

[Handle detection specification command set processing]
Handle detection is not an anti-fraud measure, so it must be checked in the area of use.
In the following program, if the handle detection signal does not change, it returns to the caller, and if the handle detection signal changes, it sends a subcommand. Note that it is possible that detection/non-detection may change in a short period of time due to chattering, but even in that case, the subcommand is sent and the program on the performance control board 40 (performance control CPU 41) side decides whether to take action or not.
(2) "LDQ (LOW R_HDL_STS), A" is an instruction to save to the handle status (update the status). The code size here is 2 bytes.
(3) "LD DE, @CMD_STS_HDL" is a command to set the handle detection specification (@CMD_STS_HDL) of the subcommand. The code size here is 3 bytes.
(1) "RST SBCMDST" is a process for calling a subcommand set process. The code size here is 1 byte.
(1) "RET" is an instruction to return to the caller. The code size is 1 byte.

Figure 22 is a flowchart showing an example of the procedure for status management processing. This flowchart corresponds to the program in Figure 21. This processing is executed by the main control board 30 (main control CPU 31).

Step S500: The main control board 30 executes a process that calls the out-of-area error checking process. This causes the main control board 30 to execute the out-of-area error checking process and then return to this process.

Step S501: The main control board 30 clears the error flag.
Step S502: The main control board 30 loads the sub-command request counter.
Step S503: The main control board 30 checks whether the value of the loaded sub-command request counter is 0 or not.
As a result, if it is confirmed that the loaded value is 0 (Yes), the main control board 30 executes step S507. On the other hand, if it is not confirmed that the loaded value is 0 (No), the main control board 30 executes step S504.

Step S504: The main control board 30 loads the sub-commands. The sub-commands are those stored in the RWM outside the area.
Step S505: The main control board 30 executes a process for calling a sub-command set process. In this process, the main control board 30 sets a sub-command buffer in the usage area.
Step S506: The main control board 30 checks whether all subcommands have been set (sets subcommand buffers corresponding to all subcommands outside the loaded area). If it is confirmed that all subcommands have been set (Yes), the main control board 30 executes step S507. On the other hand, if it is still not confirmed that all subcommands have been set (No), the main control board 30 executes step S504 and continues the loop.

Step S507: The main control board 30 loads the game stop request flag.
Step S508: The main control board 30 performs a logical OR operation on the game board error state flag and the game stop request flag.
Step S509: The main control board 30 loads the input port 1 status flag.
Step S510: The main control board 30 performs a logical AND operation on the input port 1 status flag and the handle detection signal.
Step S511: The main control board 30 checks whether the value of step S510 matches the handle status. If it is confirmed that the value matches the handle status (the handle detection signal does not change) (Yes), the main control board 30 returns to the caller. On the other hand, if it is not confirmed that the value matches the handle status (the handle detection signal has changed) (No), the main control board 30 executes step S512.
Step S512: The main control board 30 updates the handle status.
Step S513: The main control board 30 sets the sub-command "handle detection designation."
Step S514: The main control board 30 executes a process for calling a sub-command set process. In this process, the main control board 30 sets a sub-command of "specify handle detection" in the sub-command buffer.
Once the above steps are completed, the main control board 30 returns to the caller.

[Summary of state management processing]
As described above, the amount of program code in the usage area is 35 bytes (FIG. 21) (15 steps in the flow chart), which makes it possible to suppress an increase in program capacity. Although the handle detection signal is processed in the usage area, for simplification, there is no detection timer, and the logic is set to send sub-commands only at the on-edge/off-edge of the signal, which makes it possible to suppress an increase in the amount of code.

[Out-of-area error checking process]
Figures 23 to 27 are diagrams showing the error confirmation processing program stored outside the area. As mentioned above, since the occurrence or release of an error is not judged in the used area, a considerable amount of program necessary for processing is stored outside the area. The error confirmation processing program (code) is as follows. Unless otherwise omitted, the programs in Figures 23 to 27 are a series.

"E_CKERR:" is a label indicating the start of the error checking process.
"JP E_CKERR_01" is an instruction to jump to the address with the label "E_CKERR_01".
(Omitted)

In this embodiment, when calling an external module (E_CKERR:) from the used area, the CALLEX command is used, but if the address of the callee is between 2000H and 20FFH, 2 bytes of code are required, otherwise 4 bytes are required. For this reason, the label of the callee module and the jump command to the module body are arranged from 2000H onwards, and the program of the body of each module is written after that. This allows up to 86 external modules to be called with a 2-byte CALLEX command.
The above "JP E_CKERR_01" is a two-byte jump command for this purpose. The address of the jump destination does not have to be between 2000H and 20FFH, so the address of the label "E_CKERR_01" is written at a subsequent address.

[Initialization process]
The initialization process is called by the command "JP E_CKERR_01."
"E_CKERR_01:" is a label indicating the start of the initialization process.
"LD Q, HIGH @RM_EXTADR" is a command to set the upper byte of the start address of the outside work area.
In this embodiment, the bank of the register set is changed from "bank 0" to "bank 1" by the CALLEX instruction, and the bank is changed from "bank 1" to "bank 0" by the RETEX instruction. The Q register of bank 0 and the Q register of bank 1 are functionally equivalent, but their values are independent of each other. For example, even if a value of F0H is set in the Q register of bank 0, the value of the Q register of bank 1 does not change.
As described above, the RWM of the storage means is implemented with 4 kilobytes from F000H to F3FFH, but F000H to F1FFH is used as the RWM in the used area, and F300H to F3FFH is used as the RWM outside the area (see the memory map in FIG. 2). Also, F200H to F2FFH is unused.
At this time, the Q register for outside the area (assumed to be "bank 1") is set to F3H. This makes it possible to use instructions using the Q register for the RWMs from F300H to F3FFH. Program code outside the area is not subject to any regulatory restrictions, but using shorter code will help prevent execution times from increasing, so it is desirable to shorten the code outside the area as well.

[Subcommand request counter clear processing]
"CLRQ (LOW R_ERW_SBC)" is a command to clear the subcommand request counter. This command initializes the number of subcommands set outside the area.

[Loop setting process 1]
In the loop setting process 1, the address of the table used in the loop for checking errors and the number of loops are set. Since the handle detection is performed in the use area, the errors judged here are five types: "switch abnormality", "door open", "display magnetic error 1", "display magnetic error 2" and "radio wave error". Note that the type of error may differ depending on the model (display type).
"LD HL, D_ETB_ER1" is a command to set the address of the error management processing table 1. The error management processing table 1 will be described later.
"LD B, @D_ETB_ER1_NUM" is a command to set the number of status items.

[Monitoring target signal bit data determination process]
"E_CKERR_10:" is a label indicating the start of the monitoring target signal bit data determination process.
"LDIN DE, (HL)" is an instruction to load the address of the input port status flag.
"LD A, (DE)" is an instruction to load the contents of the loaded target address into the A register.
"LD C,0" is an instruction to set 0 to the C register.
"AND A, (HL)" is a command to perform a logical AND with the bit data to be monitored. In other words, the above command first sets 0 to the C register, and this command sets all bits other than the target bit to 0.
"JR Z,E_CKERR_20" is an instruction to branch if the zero flag is one.
"INC C" is an instruction to increment the C register. In other words, if the target bit is 0, the above instruction branches to "E_CKERR_20", otherwise this instruction sets the C register to 1. As a result, if an error is detected, 1 is set to the C register, and if no error is detected, 0 is set to the C register.

[Monitoring target status current value processing]
The monitor target status current value process is called when the zero flag is 1 in the "JR Z,E_CKERR_20" command above.
"E_CKERR_20:" is a label indicating the start of the current monitoring target status value processing. The current monitoring target status value processing includes the following current monitoring target status value update processing and current monitoring target status value determination processing.

[Monitoring target status current value update process]
"INLD DE, (HL)" is a command to load the address of the previous value of the monitored status.
"LD A, (DE)" is a command to load the contents of the target address. Here, the above command loads the address of the previous value of the monitored status, and this command loads the previous value into the A register.
"CP A, C" is a command to compare the A register with the C register. Here, the previous value of the monitoring target status and the current value of the monitoring target status are set, and the zero flag is updated.
"LD (DE), C" is a command to save the contents of the target address. Here, the current value of the monitored status is saved to the previous value of the monitored status.
"INC DE" is a command to increment the DE register. That is, 1 is added to the DE register, which points to the previous value of the monitored status, so that the DE register points to the address of the monitoring timer for the error.
"INC HL" is an instruction to increment the HL register. Here, 1 is added to the HL register, which points to the table, so that it points to the address of the monitoring timer value for the error.

[Monitoring target status current value judgment process]
"JR Z, E_CKERR_30" is an instruction to branch if the zero flag is 1. Here, the zero flag set by the previous "CP A, C" instruction is checked, and if the zero flag is set (Z), that is, if the previous value of the monitored status and the current value of the monitored status match, it branches to the address of "E_CKERR_30". On the other hand, if the zero flag is reset (NZ), the following occurs.
"LD A, (HL)" is a command to load the contents of the target address. In this case, the error monitoring timer value is loaded.
"LD (DE), A" is a command to save the contents of a target address. In this case, the watchdog timer is saved.

[Monitoring timer value determination process]
The monitoring timer value determination process is called when the previous value of the monitoring target status and the current value of the monitoring target status match.
"E_CKERR_30:" is a label indicating the start of the monitoring timer value determination process.
In this embodiment, an error is officially determined to have occurred when an error state continues for a certain period of time or more. Similarly, an error is officially determined to have been cleared when an error cleared state continues for a certain period of time or more. Therefore, a process of setting and subtracting a timer is required to determine the occurrence and cancellation of an error. In this process, a timer is set and subtracted.

[Monitoring timer value determination process 1]
"INC HL" is an instruction to increment the HL register.
"LD A, (DE)" is an instruction to load the contents of a target address.
"JT Z, A, E_CKERR_40" is an instruction to branch if the zero flag is 1. Here, if the watchdog timer is zero, branch to "E_CKERR_40". Note that decrementing the watchdog timer is performed by the following process.
"DEC A" is an instruction to subtract 1 from the timer value. That is, if the watchdog timer is not zero in the above instruction, 1 is subtracted from the watchdog timer.
"LD (DE), A" is an instruction to save the contents of the target address. Here, the watchdog timer value is updated.

[Monitoring timer value determination process 2]
"JT NZ, A, E_CKERR_40" is an instruction to branch if the zero flag is 0. The above "DEC A" instruction subtracts 1 from the timer value, and as a result, if the monitoring timer is not 0, it will still branch to "E_CKERR_40". The processing of "E_CKERR_40" will be described later.
On the other hand, if the monitoring timer changes from 1 to 0, the process proceeds to the following error flag determination process 1.

[Error Flag Judgment Process 1]
"INC DE" is an instruction to increment the DE register.
"LD A, (DE)" is an instruction to load the contents of a target address.
"CP A, C" is an instruction to compare the A register with the C register.
"JR Z,E_CKERR_40" is an instruction to branch if the zero flag is one.
"LD A, C" is a command to set the current status value.
"LD (DE), A" is an instruction to save the contents of the target address.
"EX DE,HL" is an instruction to exchange the DE register and the HL register.
In this way, when the monitoring timer changes from 1 to 0, the error flag (current error state) is compared again with the current value of the monitored status in error flag judgment process 1. If the error flag and the current value of the monitored status match as a result, the process branches to "E_CKERR_40".
On the other hand, if the error flag and the current value of the monitoring target status do not match, the current value of the monitoring target status is saved in the error flag, and the process proceeds to the subcommand setting process 1 described below.

[Subcommand setting process 1]
Subcommand setting process 1 is a process that sets a subcommand when it is determined that an error has occurred or been released. However, since it is not possible to call a subcommand setting process in the area of use from a process outside the area, or to rewrite the subcommand buffer in the area of use, a temporary subcommand is set in the RWM (buffer) outside the area. This makes it possible to refer to the set subcommand from the area of use.
"LDQ HL, LOW R_ERW_SBC" is a command to set the address of the sub-command request counter in the HL register.
"INC (HL)" is a command to increment the subcommand request counter in the HL register by one.
"LD A, (HL)" is an instruction to load the contents of the target address. Here, the sub-command request counter value of the HL register after increment is loaded into the A register.
"ADDWB HL, A" is an instruction to add the A register to the HL register.
"ADDWB HL, A" is an instruction to add the A register to the HL register, which means that the counter value is added to the HL register twice.
"LD (HL), @CMD_STS_HED" is a command to save a state designation preceding command in the contents of the target address. Here, a command (85H) common to all error occurrences and cancellations is saved as the preceding command.
"DEC HL" is an instruction to decrement the HL register. In this case, the HL register is decremented by 1, so that it points to the address of the subsequent command.
"LD A, C" is a command to set the current value of the monitoring target status.
[Current Status Value Judgment Process 1]
"ADD A, A" is an instruction to add a value to the A register.
"ADD A, (DE)" is a command to add a subcommand to the current value of the monitoring target status. That is, the subcommand is calculated by multiplying the current value of the monitoring target status set by the above "LD A, C" command and adding the subsequent command value.
"LD (HL), A" is a command to save the contents of the target address. Here, the subsequent command is saved in the HL register.
The reason for doubling the current monitoring target status value is to match the format of the command requested by the subcommand set process (SBCMDST). For example, the subsequent command will be any of 00H to 7FH, but the value set in the E register when calling the subcommand set process is twice the subsequent command plus the addition permission flag (0: addition permission, 1: addition permission not permission), so it is necessary to add twice the current monitoring target status value.

[RWM rewrite process]
The following RWM rewrite process is a process for rewriting the RWM when an error occurs.
"EX DE,HL" is an instruction to exchange the DE register and the HL register.
"JT Z,C,E_CKERR_40" is an instruction to branch if the zero flag is 1. Here, it is determined whether an error has occurred or has been cleared, and if the error has been cleared, it branches to "E_CKERR_40".
"LD E, (HL+1)" is a command to load the lower byte of the RAM address to be set when an error occurs. Here, the lower byte of the RWM to be rewritten when an error occurs is loaded.
"JR TZ, E_CKERR_40" is an instruction to branch if the second zero flag is 1. Here, if the loaded value is 0, it is determined that the RWM is not to be rewritten when an error occurs, and the program branches to "E_CKERR_40".
On the other hand, if the loaded value is not 0 and the RWM is to be rewritten, the following occurs.
"LD A, (HL+2)" is a command to load setting data for when an error occurs. Here, data for rewriting is loaded.
"LD (DE), A" is an instruction to save the loaded data to the contents of the target address.

[Loop end process decision 1 process]
In the following loop end process decision 1 process, 3 is added to the table address to carry out the process related to the next error, and if the loop has not ended, the process returns to "E_CKERR_10".
"E_CKERR_40:" is a label indicating the start of loop end process determination 1 process.
"ADDWB HL, 003H" is an instruction to add [003H] to the HL register.
[Loop end decision 1]
"DJNZ E_CKERR_10" is an instruction to branch if the loop continues. Here, if the loop has not ended as described above, the flow returns to "E_CKERR_10".

[Program from loop setting process 2 to loop end decision process 2]
In the following loop setting process 2 to loop end judgment process 2, winning abnormality errors are checked and sub-commands are set. In comparison with the loop process that checks for switch abnormalities, etc., the difference here is that "error cancellation is not judged only when an error occurs" and "there is no timer, and if an error occurs, a sub-command, etc. is immediately set."

[Loop setting process 2]
"LD HL, D_ETB_ER2" is a command to set the address of the error management processing table 2. The contents of the error management processing table 2 will be described later.
"LD B, @D_ETB_ER2_NUM" is a command to set the number of status items.

[Error Flag Judgment Process 2]
“E_CKERR_50:” is a label indicating the start of the error flag determination process 2.
"LD A, (R_ERR_FLG)" is an instruction to load the error flag.
"AND A, (HL)" is a command to perform a logical AND operation on the error flag and the bit data to be monitored.
"JR Z, E_CKERR_60" is an instruction to branch to "E_CKERR_60" if the zero flag is 1.
"LD A, 01H" is a command to set [01H] in the A register.

"E_CKERR_60:" is a label indicating the branch destination address of the "JR Z, E_CKERR_60" instruction.
"INC HL" is an instruction to increment the HL register.
"LDIN DE, (HL)" is a command to load the address of the error occurrence flag.

[Error occurrence flag update process]
"LD (DE), A" is a command to save an error occurrence flag in the contents of the target address.
[Status current value determination process]
"JT Z,A,E_CKERR_70" is an instruction that branches to "E_CKERR_70" if the zero flag is 1.
"EX DE,HL" is an instruction to exchange the DE register and the HL register.

[Subcommand setting process 2]
"LDQ HL, LOW R_ERW_SBC" is a command to set the address of the sub-command request counter in the HL register.
"INC (HL)" is a command to increment the sub-command request counter by one.
"LD A, (HL)" is a command to load the contents of the target address. In this case, the value of the subcommand request counter is loaded into the A register.
"ADDWB HL, A" is an instruction to add the A register to the HL register.
"ADDWB HL, A" is an instruction to add the A register to the HL register (second time).
"LD (HL), @CMD_STS_HED" is a command to save the state designation preceding command (@CMD_STS_HED) in the contents of the target address.
"DEC HL" is an instruction to decrement the HL register.
"LD A, (DE)" is an instruction to load the contents of a target address. In this case, the contents of the DE register are loaded into the A register.
"LD (HL), A" is an instruction to save the contents of a target address. In this example, the contents of the A register are saved to the HL register.
"EX DE,HL" is an instruction to exchange the DE register and the HL register.

[Setting target RAM address confirmation process when an error occurs]
"LD E, (HL+1)" is a command to load the lower byte of the RAM address to be set when an error occurs.
"JR TZ, E_CKERR_70" is an instruction to branch to "E_CKERR_70" if the second zero flag is 1.
"LD A, (HL+2)" is a command to load setting data when an error occurs.
"LD (DE), A" is an instruction to save the contents of a target address. Here, the contents of the A register are saved to the contents of the DE register.

"E_CKERR_70:" is a label indicating the branch destination address of the instruction "JR Z, E_CKERR_70".
"ADDWB HL, 003H" is an instruction to add [003H] to the HL register.

[Loop End Determination 2]
"DJNZ E_CKERR_50" is an instruction to branch to "E_CKERR_50" if the loop continues.

[Error Flag Judgment Process 3]
In the following error flag determination process 3, a timer is set for outputting the fraud detection 1 information. Specifically, when it is determined that an error related to winning has occurred, or when it is determined that any of the following has occurred: a switch abnormality, a board magnetic error 1, a board magnetic error 2, or a radio wave error, one second is saved in the fraud detection 1 information bit timer.

"LD A, (R_ERR_FLG)" is an instruction to load the error flag into the A register.
"ORQ A, (LOW R_ERW_SEF)" is an instruction to perform a logical OR operation on the switch error flag and the A register.
"ORQ A, (LOW R_ERW_M1F)" is a command to perform a logical OR operation on the disk magnetic error 1 flag and the A register.
"ORQ A, (LOW R_ERW_M2F)" is a command to perform a logical OR operation on the disk magnetic error 2 flag and the A register.
"ORQ A, (LOW R_ERW_D1F)" is a command to perform a logical OR on the radio error 1 flag and the A register.
"JT Z,A,E_CKERR_80" is an instruction to branch to "E_CKERR_80" if the zero flag is 1.

[Fraud detection 1 information bit timer set process]
"LDQ (LOW R_ERW_I1T), @TMR_HLD_SEC" is a command to save the fraud detection information 1 retention time in the fraud detection 1 information bit timer.

"E_CKERR_80:" is a label indicating the branch destination address when the zero flag is 1 in the above "JT Z,A,E_CKERR_80" instruction.
"RETEX" is a command to return to the caller.

[Table configuration outside the area]
28 and 29 are diagrams showing examples of the configuration of the error management processing table 1. As shown in FIG.
“D_ETB_ER1:” is a label indicating the start address of the error management processing table 1.
"DWR_IN1_PRT" is a label indicating the address of the input port 1 status flag.
"DB @IN1_SWE_BIT" is the switch abnormality signal bit data.
"DWR_ERW_SEO" is the address of the previous switch status value.
"DB @TMR_CHK_SWI" is the switch abnormality monitoring timer value.
"DB LOW @CMD_ERR_SWI" is a subcommand (switch error designation).
"DB 0" is the RAM address to be set when an error occurs when a switch error is specified.
"DB 0" is the setting data for when a switch error is specified. Therefore, when a switch error is specified, the game is not stopped.

"DWR_IN1_PRT" is the address of the input port 1 status flag.
"DB @IN1_DRE_BIT" is the door open switch signal bit data.
"DWR_ERW_DEO" is the address of the previous door open status value.
"DB @TMR_CHK_DOR" is the door monitoring timer value.
"DB LOW @CMD_ERR_BDR" is a subcommand (door open error designation).
"DB 0" is the RAM address to be set when a door open error occurs.
"DB 0" is the setting data for when an error occurs when a door open error is specified. Therefore, when a door open error is specified, the game is not stopped.

"DWR_IN1_PRT" is the address of the input port 1 status flag.
"DB @IN1_M1E_BIT" is the signal bit data of the disk surface magnetic detection sensor 1.
"DWR_ERW_M1O" is the address of the previous value of the status of the disc surface magnetic detection sensor 1.
"DB @TMR_CHK_MAG" is the magnetic monitoring timer value.
"DB LOW @CMD_ERR_MG2" is a subcommand (designation of board magnetic error 2).
"DB LOW R_ERW_YER" is the RAM address to be set when an error occurs when disk magnetic error 2 is specified.
"DB @YUG_HNF" is setting data for when an error occurs when board magnetic error 2 is specified. When board magnetic error 2 is specified, the game is stopped.

"DWR_IN1_PRT" is the address of the input port 1 status flag.
"DB @IN1_M2E_BIT" is the disk surface magnetic detection sensor 2 signal bit data.
"DWR_ERW_M2O" is the previous value of the status of the disc surface magnetic detection sensor 2.
"DB @TMR_CHK_MAG" is the magnetic monitoring timer value.
"DB LOW @CMD_ERR_MG3" is a subcommand (designating board magnetic error 3).
"DB LOW R_ERW_YER" is the RAM address to be set when an error occurs when disk magnetic error 3 is specified.
"DB @YUG_HNF" is setting data for when an error occurs when board magnetic error 3 is specified. When board magnetic error 3 is specified, the game is stopped.

"DWR_IN0_PRT" is the address of the input port 0 status flag.
"DB @IN0_D1E_BIT" is 1-bit data from the radio wave detection sensor.
"DWR_ERW_D1O" is the previous value of the radio wave detection sensor 1 status.
"DB @TMR_CHK_DEN" is the radio wave monitoring timer value.
"DBLOW @CMD_ERR_DE1" is a subcommand (specifying radio error 1).
"DB 0" is the RAM address to be set when an error occurs when radio error 1 is specified.
"DB 0" is the setting data for when an error occurs when radio error 1 is specified. Therefore, when radio error 1 is specified, the game is not stopped.

"@D_ETB_ER1_NUM EQU ($ - D_ETB_ER1)/9" is the number of status items.

[Error Management Processing Table 2]
FIG. 30 is a diagram showing an example of the configuration of the error management process table 2.
“D_ETB_ER2:” is a label indicating the start address of the error management processing table 2.
"DB @ERF_IL1_BIT" is one error bit data for an illegal win.
"DWR_ERW_FS1" is the illegal winning 1 error flag.
"DB LOW @CMD_ERR_FS1" is a subcommand (specifying the occurrence of an illegal winning error 1).
"DB LOW R_ERW_YER" is the RAM address to be set when an error occurs when the occurrence of illegal winning error 1 is specified.
"DB @YUG_HNF" is setting data for when an error occurs when the occurrence of an illegal winning error 1 is specified. When the occurrence of an illegal winning error 1 is specified, the game is stopped.

"DB @ERF_IL3_BIT" is the illegal winning 3 error bit data.
"DWR_ERW_FS3" is the illegal winning 3 error flag.
"DB LOW @CMD_ERR_FS3" is a subcommand (specifying the occurrence of illegal winning error 3).
"DB 0" is the RAM address to be set when an error occurs when an illegal winning error 3 occurs.
"DB 0" is the setting data for when an error occurs when the occurrence of an improper winning error 3 is specified. Therefore, when the occurrence of an improper winning error 3 is specified, the game is not stopped.

"DB @ERF_FDN_BIT" is the normal power abnormality error bit data.
"DWR_ERW_FDN" is a normal power abnormality error flag.
"DB LOW @CMD_ERR_FDN" is a subcommand (specifying the occurrence of a normal power abnormality error).
"DB 0" is the RAM address to be set when an error occurs when a normal power abnormality error occurs.
"DB 0" is the setting data for when an error occurs when a normal power abnormal winning error occurs. Therefore, when a normal power abnormal winning error occurs, the game is not stopped.

"@D_ETB_ER2_NUM EQU ($ - D_ETB_ER2)/6" is the number of status items.

Figures 31 to 37 are flowcharts showing an example of the procedure for error confirmation processing. The flowcharts in Figures 31 to 37 correspond to the programs in Figures 23 to 27. The error confirmation processing is executed outside the area by the main control board 30 (main control CPU 31).

Step S400: The main control board 30 sets the upper byte of the outside area work area in the Q register.
Step S401: The main control board 30 clears the sub-command request counter.
Step S402: The main control board 30 sets the address of the error management processing table 1.
Step S403: The main control board 30 sets the number of status items.
Step S404: The main control board 30 loads the address of the input port status flag.
Step S405: The main control board 30 loads the contents of the target address.
Step S406: The main control board 30 sets the C register to 0.
Step S408: The main control board 30 performs a logical AND operation on the contents of the target address and the monitored bit.
Step S409: The main control board 30 checks whether the zero flag is 1 (has no abnormality occurred?). As a result, if it is confirmed that the zero flag is 1 (Yes), the main control board 30 executes step S411. On the other hand, if it is not confirmed that the zero flag is 1 (No), the main control board 30 executes step S410.

Step S410: The main control board 30 increments the C register (sets the C register to 1).
Step S411: The main control board 30 loads the address of the previous status value.
Step S412: The main control board 30 loads the contents of the target address.
Step S413: The main control board 30 compares the loaded contents with the C register and updates the zero flag.
Step S414: The main control board 30 saves the C register (current status value) to the target address.
Step S415: The main control board 30 increments the DE register (sets the timer address).
Step S416: The main control board 30 increments the HL register (points to the address of the timer value).

[Figure 32: External connector (2) and onwards]
Step S417: The main control board 30 checks whether the zero flag is 1. As a result, if it is confirmed that the zero flag is 1 (Yes), the main control board 30 executes step S420. On the other hand, if it is not confirmed that the zero flag is 1 (No), the main control board 30 executes step S418.
Step S418: The main control board 30 loads the timer value.
Step S419: The main control board 30 saves the timer value in the timer.
Step S420: The main control board 30 increments the HL register.
Step S421: The main control board 30 loads the timer.
Step S422: The main control board 30 checks whether the timer value is 0. If the main control board 30 checks that the timer value is 0 (Yes), it moves to the external connector (4) and executes step S446 (FIG. 34). On the other hand, if it cannot check that the zero flag is 1 (No), the main control board 30 executes step S423.

Step S423: The main control board 30 decrements the timer value by one.
Step S424: The main control board 30 checks whether the timer value after subtraction is not 0. As a result, if it is confirmed that the timer value is not 0 (Yes), the main control board 30 proceeds to the external connector (4) and executes step S446 (FIG. 34). On the other hand, if it is not confirmed that the timer value is not 0 (No), the main control board 30 executes step S425.

Step S425: The main control board 30 increments the DE register (sets the address of the error flag).
Step S426: The main control board 30 loads the error flag.
Step S427: The main control board 30 checks whether the error flag and the current status value match. If they match (Yes), the main control board 30 moves to the external connector (4) and executes step S446 (FIG. 34). On the other hand, if they cannot match (No), the main control board 30 executes step S428.

Step S428: The main control board 30 saves the current status value in the error flag.
Step S429: The main control board 30 exchanges the DE register and the HL register.

[Figure 33: External connector (3) and onwards]
Step S430: The main control board 30 sets the address of the sub-command request counter in the HL register.
Step S431: The main control board 30 increments the sub-command request counter by one.
Step S432: The main control board 30 loads the sub-command request counter.
Step S433: The main control board 30 increments the sub-command request counter value twice in the HL register.
Step S434: The main control board 30 saves the state designation preceding command (85H) in the subcommand request buffer.
Step S435: The main control board 30 decrements the HL register by 1.
Step S436: The main control board 30 sets the current status value.
Step S437: The main control board 30 doubles the current status value.
Step S438: The main control board 30 adds the subsequent command value to twice the current status value.
Step S439: The main control board 30 saves the addition result in the sub-command request buffer.
Step S440: The main control board 30 exchanges the DE register and the HL register.

[Figure 34: External connector (5) and onwards]
Step S441: The main control board 30 checks whether the current status value is 0. As a result, if it is confirmed that the current status value is 0 (Yes), the main control board 30 executes step S446. On the other hand, if it is not confirmed that the current status value is 0 (No), the main control board 30 executes step S442.
Step S442: The main control board 30 loads the lower byte of the RAM address to be set when an error occurs.
Step S443: The main control board 30 checks whether the loaded value is 0. As a result, if it is confirmed that the loaded value is 0 (Yes), the main control board 30 executes step S446. On the other hand, if it is not confirmed that the loaded value is 0 (No), the main control board 30 executes step S444.

Step S444: The main control board 30 loads the setting data for when an error occurs.
Step S445: The main control board 30 saves to the target RAM address.
Step S446: The main control board 30 adds 3 to the HL register.
Step S447: The main control board 30 checks whether the loop continues. If it is confirmed that the loop continues (Yes), the main control board 30 moves to the external connector (1) and executes step S404 (FIG. 31). On the other hand, if it is not confirmed that the loop continues (No), the main control board 30 moves to the external connector (6) and executes step S448 (FIG. 35).

[Figure 35: External connector (6) and onwards]
Step S448: The main control board 30 sets the address of the error management processing table 2.
Step S449: The main control board 30 sets the number of status items.
Step S450: The main control board 30 loads the error flag.
Step S451: The main control board 30 performs a logical AND operation on the error flag and the monitored bit.
Step S452: The main control board 30 checks whether the zero flag is 1 (has no abnormality occurred?). If it is confirmed that the zero flag is 1 (Yes), the main control board 30 executes step S454. On the other hand, if it is not confirmed that the zero flag is 1 (No), the main control board 30 executes step S453.

Step S453: The main control board 30 sets the A register to 1.
Step S454: The main control board 30 increments the HL register (points to the address of the error occurrence flag).
Step S455: The main control board 30 loads the address of the error occurrence flag.
Step S456: The main control board 30 saves the A register as an error occurrence flag.
Step S457: The main control board 30 checks whether the zero flag is 1 (no abnormality has occurred). If it is confirmed that the zero flag is 1 (Yes), the main control board 30 proceeds to the external connector (9) and executes step S472 (FIG. 36). On the other hand, if it is not confirmed that the zero flag is 1 (No), the main control board 30 executes step S458.

Step S458: The main control board 30 exchanges the DE register and the HL register.
Step S459: The main control board 30 sets the address of the sub-command request counter in the HL register.
Step S460: The main control board 30 increments the sub-command request counter by one.

[Figure 36: External connector (7) and onwards]
Step S461: The main control board 30 loads the sub-command request counter.
Step S462: The main control board 30 increments the sub-command request counter value twice in the HL register.
Step S463: The main control board 30 saves the state designation precedence command (85H) in the subcommand request buffer.
Step S464: The main control board 30 decrements the HL register by 1.
Step S465: The main control board 30 loads the subsequent commands.
Step S466: The main control board 30 saves the subsequent command in the sub-command request buffer.
Step S467: The main control board 30 exchanges the DE register and the HL register.
Step S468: The main control board 30 loads the lower byte of the RAM address to be set when an error occurs.
Step S469: The main control board 30 checks whether the loaded value is 0. As a result, if it is confirmed that the value is 0 (Yes), the main control board 30 executes step S472. On the other hand, if it is not confirmed that the value is 0 (No), the main control board 30 executes step S470.

Step S470: The main control board 30 loads the setting data for when an error occurs.
Step S471: The main control board 30 saves the loaded contents to the target RAM address.
Step S472: The main control board 30 adds 3 to the HL register.
Step S473: The main control board 30 checks whether the loop continues. If it is confirmed that the loop continues (Yes), the main control board 30 moves to the external connector (8) and executes step S450 (FIG. 35). On the other hand, if it is not confirmed that the loop continues (No), the main control board 30 moves to the external connector (10) and executes step S474 (FIG. 37).

[Figure 37: External connector (10) and onwards]
Step S474: The main control board 30 loads the error flag.
Step S475: The main control board 30 performs a logical OR on the loaded error flag and the switch error flag.
Step S476: The main control board 30 performs a logical OR on the loaded error flag and the board magnetic 1 error flag.
Step S477: The main control board 30 performs a logical OR on the loaded error flag and the board magnetic 2 error flag.
Step S478: The main control board 30 performs a logical OR on the loaded error flag and the radio wave error flag.

Step S479: The main control board 30 checks whether the zero flag is 1 (has the above error not occurred?). As a result, if it is confirmed that the zero flag is 1 (the above error has not occurred) (Yes), the main control board 30 returns to the caller. On the other hand, if it is not confirmed that the zero flag is 1 (the above error has not occurred) (No), the main control board 30 executes step S480.
Step S480: The main control board 30 sets a timer value in the fraud detection 1 information bit timer.
When the above procedure is completed, the main control board 30 returns to the caller.

[Summary of the first technical feature]
According to the program configuration of the state management process and error checking process as described above, an increase in the amount of code in the usage area and data area can be suppressed.

[Fourth technical feature: Configuration of code reduction in variation pattern selection 2 processing]
Next, a fourth technical feature of the present embodiment will be described. The fourth technical feature is a configuration for suppressing an increase in the amount of code used in the variation pattern selection 2 process.

[Outline of the fourth technical feature]
The variation pattern selection 2 process is a module that is called in the process of determining the variation pattern of the special symbol, and in order to control the contents related to the progress (execution) of the game, it is necessary to place the program in the usage area. First, an overview of the variation pattern determination process will be described.

[Outline of the fluctuation pattern determination process]
38 is a flowchart showing an example of a procedure for a variation pattern determination process. This flowchart is executed by the main control board 30 (main control CPU 31).
Step S600: The main control board 30 sets the table addresses by state and by stopping symbols. The table addresses set here are for specifying the location of the table master that is the basis for finally determining the variation pattern (selected by random number lottery) in the subsequent procedures. In this embodiment, the processing is common for both a miss and a jackpot, but the location of the table (table address) used to determine the variation pattern is specified by the table stored in the ROM for the current game state and the stopping symbols.

Step S601: The main control board 30 acquires an offset value by activation memory number. This offset value can be acquired from an offset value table by activation memory number based on the first special pattern activation memory number counter value if the current target pattern is the first special pattern, or the second special pattern activation memory number counter value if the current target pattern is the second special pattern. Note that the offset value by activation memory number may be configured as a table acquired based on the counter value that is the sum of the activation memory number of the first special pattern and the activation memory number of the second special pattern.

Step S602: The main control board 30 sets the first stage selection table from the acquired offset value for each number of operation memories. The "first stage selection table" here is a table that uses the fluctuation group determination random number in particular out of the three random numbers related to determining the fluctuation pattern (fluctuation group determination random number, fluctuation mode determination random number, and fluctuation pattern determination random number) to draw the "fluctuation group," which is the first category of the fluctuation pattern.

Step S603: The main control board 30 loads the variable group determination random number from the random number memory area of the RWM.
Step S604: The main control board 30 executes the first stage variation group determination process (variation pattern selection 1 process). This process performs the first category lottery (variation group lottery) of the variation pattern using the variation group determination random number as described above, and sets the obtained variation group designation offset value as a return value.

Step S606: The main control board 30 sets the "second stage selection table" using the previously returned value, the fluctuation mode selection offset. The "second stage selection table" here is a table that uses a fluctuation mode determination random number to draw the "fluctuation mode," which is the second category of the fluctuation pattern.

Step S607: The main control board 30 loads the variation mode determination random number from the RWM random number memory area.
Step S608: The main control board 30 executes the second stage fluctuation mode determination process (fluctuation pattern selection 2 process in this embodiment). This process uses the fluctuation mode determination random number as described above to perform a second category lottery for the fluctuation pattern (lottery for the fluctuation mode), and sets the acquired fluctuation mode designation offset (pattern selection offset) value as a return value. The fluctuation mode designation offset (pattern selection offset) acquired here specifies the address of the fluctuation pattern selection table used in the final third stage fluctuation pattern determination process. The specific contents of the process will be described later in comparison with a comparative example.

Step S609: The main control board 30 sets the third stage selection table (variation pattern selection table) using the return value of the variation mode designation offset (pattern selection offset). Specifically, it designates the table address in ROM indicated by the value of the variation mode designation offset as described above.

Step S610: When the table address is specified, the main control board 30 loads the fluctuation pattern determination random number.
Step S611: The main control board 30 executes the third stage fluctuation pattern determination process. In this process, the main control board 30 selects the corresponding fluctuation pattern number from the above-mentioned "third stage selection table (fluctuation pattern selection table by fluctuation mode)" based on the fluctuation pattern determination random number. The main control board 30 also sets the selected fluctuation pattern number to the return value. The fluctuation pattern number selected here represents the unique fluctuation pattern that is ultimately performed in the fluctuation (the time from the start of the fluctuation to the occurrence of the notice, until the tenpai, the reach state, the reach fluctuation time, and the fluctuation state until the final stop display), and the total fluctuation time (the number of fluctuation seconds) in the fluctuation is uniquely determined from this fluctuation pattern number.

Step S612: The main control board 30 generates a variation pattern command from the variation pattern number selected as the return value. The generated variation pattern command is sent to the performance control board 40 in the sub-command sending process. The performance control board 40 can then determine the variation pattern information of the corresponding variation from the received variation pattern command, and can select a variation performance pattern.

[Problem of the second technical feature]
As described above, it is desirable to suppress an increase in the amount of program usage (amount of code) of the area used in the variation pattern selection 2 process.
Generally, consider a case where data A and data B are paired in a data table configuration, with data A ranging from 0 to 10 and data B ranging from 0 to 4000. In this case, if data A and data B are normally recorded in a table, one byte is required to record data A, two bytes are required to record data B, for a total of three bytes.
Here, if we consider another "data C" composed of data A x 4096 + data B, the range of data C is 0 to 53960, so with this composition, it can be written as 2-byte data.

For example, the table read in the variation pattern 2 selection process (HPT_MOD) of this embodiment contains 16-bit data consisting of 4-bit mode number data and 12-bit comparison value data. When handling such table data, the following configuration can be considered as a comparative example.

[Data processing configuration of comparative example]
In the comparative example, a set of mode number data and comparison value data is first read from the table data as 16-bit data, and comparison value data is generated by setting the upper 4 bits to 0. Then, the comparison value data is compared with a random value, and if the condition is satisfied, data is read from the table again, and this time the upper 4 bits are made valid.

Specifically, when calling the variation pattern selection 2 process in the comparative example, the mode selection offset is set in the A register and a random value is set in the BC register. In this process, the mode number data is ultimately set in the A register and the pattern selection offset in the B register. For this reason, in this process, after loading the comparison value data and mode number data from the table, the mode number data portion in the upper bytes is masked and the comparison value data portion is extracted. Then, if the random value value is less than the comparison value, the comparison value (the upper 4 bits) and mode number data are loaded again and the mode number is extracted by shifting it 4 bits to the right. In the comparative example, the amount of code used is 22 bytes.

Figure 39 is a diagram showing a program for the variation pattern selection 2 process of the comparative example. The program (code) of the comparative example is as follows. Note that the numbers in parentheses on each line of the program code in Figure 39 indicate the number of bytes used.

"HPT_MOD:" is a label indicating the start of the variation pattern selection 2 process.
[Mode selection table address selection process]
(2) "LDF HL, D_MOD_SEL" is a command to set the address of the mode selection table. The code size here is 2 bytes.
(1) "RST WORDSEL" is a process for calling a word data selection process. The code size here is 1 byte.

"HPT_MOD_10:" is a label indicating the start of the comparison value acquisition process.
[Comparison value acquisition process]
(2) "LDIN AE, (HL)" is an instruction to load a comparison value and mode number data and increment the table address by 2. The code size here is 2 bytes.
(2) "AND A, 00FH" is an instruction to logically AND the A register with [00FH]. The code size here is 2 bytes.
(1) "LD D, A" is an instruction to set the extracted value (A register) to the D register. The code size here is 1 byte.

[Mode Determination Processing]
(2) "CP BC,DE" is an instruction to compare the random number in the BC register with the comparison value in the DE register. The code size here is 2 bytes.
(2) "JR C, HPT_MOD_20" is an instruction to branch to "HPT_MOD_20" if the carry flag is 1. The amount of code here is 2 bytes.

[Table update process]
(1) "INC HL" is an instruction to increment the table address indicated by the HL register by 1 and update it to the next data block. The code size here is 1 byte.
(2) "JR HPT_MOD_10" is an instruction to jump to "HPT_MOD_10." The amount of code here is 2 bytes.

"HPT_MOD_20:" is a label indicating the start of the pattern selection offset setting process.
[Pattern selection offset setting process]
(1) "LD B, (HL)" is an instruction to load the contents of the target address indicated by the HL register into the B register. The code size here is 1 byte.
[Mode number data setting process]
(1) "DEC HL" is an instruction to subtract 1 from the table address of the HL register. The code size here is 1 byte.
(1) "LD A, (HL)" is an instruction to load the contents of the target address indicated by the HL register. The code size here is 1 byte.
(3) "SRL A, 4" is an instruction to calculate mode number data by shifting the A register 4 bits to the right. The code size here is 3 bytes.
(1) "RET" is an instruction to return to the caller. The code size here is 1 byte.

Figure 40 is a flowchart showing an example of the procedure for the variation pattern selection 2 process in the comparative example. This flowchart corresponds to the program in Figure 39. For the sake of convenience, it is assumed here that the main control board in the comparative example executes the process.

Step S700: The main control board sets the address of the mode selection table in the HL register.
Step S701: The main control board executes a process for calling a word data selection process.
Step S702: The main control board loads the comparison value and mode number data, and increments the HL register by 2.
Step S703: The main control board performs a logical AND operation on the A register and [0FH], and extracts the upper 4 bits of the comparison value.
Step S704: The main control board sets the A register to the D register.
Step S705: The main control board compares the random number value (BC register) with the comparison value (DE register).
Step S706: The main control board checks whether the carry flag is 1 (is the random number value less than the comparison value?). If it is confirmed that the carry flag is 1 (Yes), the main control board executes step S708. On the other hand, if it is not confirmed that the carry flag is 1 (No), the main control board executes step S707.
Step S707: The main control board increments the HL register by 1 and executes step S702.

Step S708: The main control board loads the pattern selection offset into the B register.
Step S709: The main control board decrements the HL register by one.
Step S710: The main control board loads the upper byte data of the comparison value and the mode number.
Step S711: The main control board shifts the content of the A register to the right by 4 bits and extracts the mode number.
Once the above steps are completed, the main control board returns to the caller.

[Configuration of the variation pattern selection 2 process of this embodiment]
Next, the configuration of the variation pattern selection 2 process of this embodiment will be described.
In this embodiment, as in the comparative example, when calling the variation pattern selection 2 process, the mode selection offset is set in the A register and the random number is set in the BC register. In this embodiment, the mode number data is set in the A register and the pattern selection offset is set in the B register. The amount of code used in the variation pattern selection 2 process of this embodiment is 16 bytes.

Figure 41 is a diagram showing the program relationships of the variation pattern selection 2 process of this embodiment. In Figure 41, (A) shows the program body, and (B) shows the table specified by the HL register. In the program code in Figure 41, the numbers in parentheses added to each line indicate the number of bytes used.

"HPT_MOD" is a label indicating the start of the variation pattern selection 2 process.
[Mode Selection Table Address Selection Process]
(2) "LDF HL, D_MOD_SEL" is a command to set the address of the mode selection table. The code size here is 2 bytes.
(1) "RST WORDSEL" is a process for calling a word data selection process. The code size here is 1 byte.

"HPT_MOD_10:" is a label indicating the start of the comparison value acquisition process.
[Comparison value acquisition process]
(2) "LDIN AE, (HL)" is an instruction to load a comparison value and mode number data and add 2 to the table address. Here, the comparison value and mode number are loaded from the table into the AE register, while adding 2 to the table address. As a result, the upper 4 bits of the A register are set to the mode number, the lower 4 bits are set to the upper byte of the comparison value, and the E register is set to the lower byte of the comparison value. The amount of code here is 2 bytes.
(1) "INC HL" is an instruction to increment the HL register. Since the table address indicates the pattern selection offset, 1 is added to the table address indicated by the HL register, and the table address is made to point to the next comparison value and mode number. The code size here is 1 byte.

[Mode number data setting process]
(3) "DIV D, A, 16" is an instruction to calculate the mode number. The "DIV D, A, 16" instruction executes "separation of the mode number and comparison value" and "right shift of the mode number" with a single instruction. In other words, this is a process in which the A register is divided by 16, and the quotient (mode number data) is set in the A register, and the remainder (high-order byte of the comparison value) is set in the D register. As a result, the comparison value with the random number is set in the DE register (comparison value data is generated). The amount of code here is 3 bytes.

[Mode Determination Processing]
(2) "CP BC,DE" is an instruction to compare the contents of the random number in the BC register with the comparison value in the DE register. Here, the random number (BC register) is compared with the comparison value (DE register) and the carry flag is set. For example, if the value of the DE register is 3368, the carry flag is set (C) if the value of the BC register is between 0 and 3367, and is reset (NC) if it is 3368 or greater. The amount of code here is 2 bytes.
(2) "JR NC, HPT_MOD_10" is an instruction to branch to "HPT_MOD_10" if the carry flag is 0. Here, the carry flag set above is checked, and if it is reset (NC), it returns to "HPT_MOD_10". Since the HL register points to the next comparison value and mode number, the next value can be loaded by the LDIN instruction at the return destination. The amount of code here is 2 bytes.

[Pattern selection offset setting process]
(1) "DEC HL" is an instruction to decrement the HL register. That is, the table address advanced by the above "INC HL" instruction is decremented by 1, and the table address is returned to the pattern selection offset. The code amount here is 1 byte.
(1) "LD B, (HL)" is an instruction to load the contents of the target address. Here, the B register is overwritten with the pattern selection offset. The amount of code here is 1 byte.
(1) "RET" is an instruction to return to the caller. The code size here is 1 byte.
The mode number data is held in the state set in the A register in the mode number data setting process, and there is no need to read the value from the table again and process it as in the comparative example.

[Table configuration example]
In the mode selection table address selection process, the address of a table in which comparison values, mode number data, and pattern selection offsets are written is set in the HL register according to the mode selection offset (A register) set at the time of calling. (B) in Figure 41 is an example of the table configuration.
"D_MOD_SEL_07:" is a label indicating the top of the table.
"DW 3368 + 1000H * 004H" is a composite value of the comparison value and the mode number data.
"DB @D_PAT_SEL_10" is the pattern selection 10 offset.
"DW 3868 + 1000H * 005H" is a composite value of the comparison value and the mode number data.
"DB @D_PAT_SEL_11" is the pattern selection 11 offset.
"DW @STP + 1000H * 006H" is a composite value of the comparison value and the mode number data.
"DB @D_PAT_SEL_12" is the pattern selection 12 offset.

[Allocation using a table]
Fig. 42 is a diagram showing allocation using the table "D_MOD_SEL_07". That is, when the table (B) in Fig. 41 is selected, the following allocation is performed according to the random number value set in the BC register. Note that the random number set when the process is called has 4093 possible values from 0 to 4092.
If the acquired random number is between 0 and 3367, the mode number data will be 04H and the pattern selection offset will be "10 (@D_PAT_SEL_10)."
If the acquired random number is between 3368 and 3867, the mode number data will be 05H and the pattern selection offset will be "11 (@D_PAT_SEL_11)."
If the acquired random number value is 3868 or greater, the mode number data becomes 06H, and the pattern selection offset becomes "12 (@D_PAT_SEL_12)."

Fig. 43 is a flowchart showing an example of the procedure of the variation pattern selection 2 process of this embodiment. This flowchart corresponds to the program (A) in Fig. 41. The variation pattern selection 2 process is executed by the main control board 30 (main control CPU 31).
Step S800: The main control board 30 sets the address of the mode selection table in the HL register.
Step S801: The main control board 30 executes a process to call the word data selection process.
Step S802: The main control board 30 loads the comparison value and mode number data, and increments the HL register by 2.
Step S803: The main control board 30 increments the HL register by 1.
Step S804: The main control board 30 divides the A register by 16, and sets the quotient (mode number data) in the A register and the remainder (comparison value) in the D register.
Step S805: The main control board 30 compares the random number value (BC register) with the comparison value (DE register).
Step S806: The main control board 30 checks whether the carry flag is 0 (is the random number value equal to or greater than the comparison value?). If it is confirmed that the carry flag is 0 (Yes), the main control board 30 executes step S802. On the other hand, if it is not confirmed that the carry flag is 0 (No), the main control board 30 executes step S807.

Step S807: The main control board 30 subtracts 1 from the HL register.
Step S808: The main control board 30 loads the pattern selection offset into the B register.
When the above procedure is completed, the main control board 30 returns to the caller.

[Summary of the fourth technical feature]
As described above, in this embodiment, the amount of program code for the variation pattern selection 2 process can be reduced by 6 bytes compared to the comparative example. Therefore, an increase in program capacity can be suppressed.

[Fifth technical feature: Configuration of calculation timing of base, role ratio and continuous role ratio]
Next, a fifth technical feature of the present embodiment will be described. The fifth technical feature is a configuration related to the timing of executing the process for calculating the performance of the managed gaming machine 100.

[Problem of the fifth technical feature]
The performance of the managed gaming machine 100 includes a base value, a role ratio, and a consecutive role ratio. The process of calculating these performance values is executed by the performance display monitor control process (E_SHYMT) during the timer interrupt process. At this time, it is desired to suppress the calculation time of the base, role ratio, and consecutive role ratio from becoming long.

[Outline of the fifth technical feature]
Since the time required to end the timer interrupt process is limited, the configuration is such that two or more processes for calculating the base value, the role ratio, and the consecutive role ratio are not executed in one timer interrupt process. Note that the base value, the role ratio, and the consecutive role ratio are calculated when the following conditions are met.

The base value will be calculated when either "a" or "b" below is met.
When the total number of outs in the section reaches 299 (first time only) or 60,000, the timing for starting display of the "current base value"

The role ratio will be calculated when the above "A" and "B" are not met, and the following "C" to "E" are met.
C When the base value was calculated in the previous timer interrupt D When the "undetermined prize ball" was added to the "continuous prize ball counter" E When a prize ball was generated in the current timer interrupt

The continuous feature ratio is calculated when the above conditions "A" to "E" are not met and the following condition "F" is met.
F. When the ratio of the special feature was calculated at the previous timer interruption

[Performance monitor display process]
Figures 44 to 46 are flowcharts showing an example of the procedure of the performance monitor display process. The performance monitor display process is a module (step S319 in Figure 13) that is called and executed during timer interrupt processing. The configuration that is the fifth technical feature of this embodiment is incorporated into the performance monitor display process, so the performance monitor display process will be described below. The performance monitor display process is executed by the main control board 30 (main control CPU 31).

Step S900: The main control board 30 checks whether or not the game is allowed to be played. If the game is not allowed to be played (No), the main control board 30 goes to the external connector (2) and executes step S917 (FIG. 45). On the other hand, if the game is allowed to be played (Yes), the main control board 30 executes step S901.
Step S901: The main control board 30 executes the process of calculating the current number of outs.
Step S902: The main control board 30 executes a process for confirming the operation of the reels.
Step S903: The main control board 30 executes the process of calculating the number of prize balls this time.
Step S904: The main control board 30 executes the total prize ball counter update process.
Step S905: The main control board 30 executes a bonus prize ball counter update process.
Step S906: The main control board 30 executes the undetermined prize ball counter update process.
Step S907: The main control board 30 checks whether or not a big win or a small win is occurring. As a result, if it is confirmed that a big win or a small win is occurring (Yes), the main control board 30 executes step S908. On the other hand, if it is not confirmed that a big win or a small win is occurring (No), the main control board 30 executes step S911.

Step S908: The main control board 30 checks whether or not a jackpot is occurring. As a result, if it is confirmed that a jackpot is occurring (Yes), the main control board 30 executes step S909. On the other hand, if it is not confirmed that a jackpot is occurring (No), the main control board 30 moves to the external connector (1) and executes step S912 (Figure 45).

Step S909: The main control board 30 saves the "next feature ratio calculation designated value" in the calculation management buffer.
Step S910: The main control board 30 adds the undetermined prize ball counter to the continuous prize ball counter.
Step S911: The main control board 30 clears the undetermined prize ball counter.

[Figure 45: Connector (1) and onwards]
Step S912: The main control board 30 checks whether or not it is during normal play. As a result, if it is confirmed that it is during normal play (Yes), the main control board 30 executes step S913. On the other hand, if it is not confirmed that it is during normal play (No), the main control board 30 executes step S915.

Step S913: The main control board 30 executes the normal prize ball counter update process.
Step S914: The main control board 30 executes normal out counter update processing.
Step S915: The main control board 30 executes the total out counter update process.
Step S916: The main control board 30 checks whether the total out counter is equal to or greater than the comparison value. The comparison value is 299 (first time only) or 60,000. As a result, if it is confirmed that the total out counter is equal to or greater than the comparison value (Yes), the main control board 30 executes step S919. On the other hand, if it is not confirmed that the total out counter is equal to or greater than the comparison value (No), the main control board 30 executes step S917.

Step S917: The main control board 30 executes a performance display timer update process.
Step S918: The main control board 30 checks whether it is the display start timing of the base value (current). The performance display monitor 37 of the managed gaming machine 100 switches between the display of the "current base value", the "base value of the previous section", the "base value of the section before last", and the "base value of the section three times before" approximately every five seconds. At this time, the timing at which the display is switched from the "base value of the third section" to the "current base value" is the display start timing, so this is checked. As a result, if it is confirmed that it is the display start timing of the current base value (Yes), the main control board 30 executes step S919. On the other hand, if it is not confirmed that it is the display start timing (No), the main control board 30 moves to the external connector (3) and executes step S922 (FIG. 46).

Step S919: The main control board 30 executes a base value calculation process.
Step S920: The main control board 30 executes a process of updating the base value.
Step S921: The main control board 30 saves the "next feature ratio calculation designated value" in the calculation management buffer.

[Figure 46: External connector (3) and onwards]
Step S922: The main control board 30 checks whether the current number of prize balls is other than 0. As a result, if it is confirmed that the current number of prize balls is other than 0 (Yes), the main control board 30 executes step S926. On the other hand, if it is not confirmed that the current number of prize balls is other than 0 (No), the main control board 30 executes step S923.

Step S923: The main control board 30 loads the calculation management buffer.
Step S924: The main control board 30 checks whether the loaded calculation management buffer is the "next role ratio calculation designated value". As a result, if it is confirmed that it is the "next role ratio calculation designated value" (Yes), the main control board 30 executes step S926. On the other hand, if it is not confirmed that it is the "next role ratio calculation designated value" (No), the main control board 30 executes step S925.

Step S925: The main control board 30 checks whether the loaded calculation management buffer is the "next consecutive feature ratio calculation designated value". As a result, if it is confirmed that it is the "next consecutive feature ratio calculation designated value" (Yes), the main control board 30 executes step S928. On the other hand, if it is not confirmed that it is the "next consecutive feature ratio calculation designated value" (No), the main control board 30 executes step S930.

Step S926: The main control board 30 executes a role ratio calculation process.
Step S927: The main control board 30 saves the "next consecutive feature ratio calculation designated value" in the calculation management buffer.
Step S928: The main control board 30 executes a continuous feature ratio calculation process.
Step S929: The main control board 30 clears the calculation management buffer.
Step S930: The main control board 30 executes an identification segment data setting process.
Step S931: The main control board 30 executes ratio segment data setting processing.
When the above procedure is completed, the main control board 30 returns to the caller.

[Summary of the fifth technical feature]
As described above, in the performance display monitor display process, there are a base value calculation process (step S919) for performance values, a feature ratio calculation process (step S926), and a continuous feature ratio calculation process (step S928), but no more than two of these processes are executed in one timer interrupt process.

In more detail, the base value needs to be calculated when the total number of outs in the section reaches 299 (first time only) or 60,000, and when the display of the current base value starts. The feature ratio needs to be calculated when a prize ball occurs, and the consecutive feature ratio needs to be calculated when a prize ball occurs and when an undetermined prize ball is added to the prize balls subject to the consecutive feature ratio.

However, in the performance display monitor display process of this embodiment, even if there are cases where multiple calculations are required simultaneously (conditions are met) for the base value, feature ratio, and continuous feature ratio, the priority is set as "base value > feature ratio > continuous feature ratio". Therefore, even if two or more calculations are required, only the one with the highest priority will be calculated according to the priority order. Therefore, the remaining calculations that require calculation will be calculated during the next or subsequent timer interrupt processing.

Below, we will explain the program that is related to the fifth technical feature of the performance display monitor display process of this embodiment.

[Undetermined prize ball counter addition process]
Figure 47 is a diagram showing the program of the undetermined prize ball counter addition process (step S906 in Figure 44). In this embodiment, the current consecutive prize ball count (R_ERW_PRN) is added to the undetermined prize ball counter (R_ERW_MTS). The "current consecutive prize ball count" is the total number of prize balls acquired by winning the large prize slot (when the consecutive prize ball is activated) during the current timer interrupt process.

The program for the undetermined prize ball counter increment process is as follows. Note that the numbers in parentheses attached to each line in the program code in Figure 47 are added for ease of explanation.

"E_SHYMT_30:" is a label indicating the start of the undetermined prize ball counter addition process.
(Omitted)

[Undetermined prize ball counter update process]
[1] "LDQ A, (LOW R_ERW_PRN)" is a command to load the number of consecutive prize balls this time. Here, the number of consecutive prize balls this time is loaded.
[2] "LDQ HL, (LOW R_ERW_MTS+0)" is a command to load the undetermined prize ball counter +0. Here, the lower 2 bytes of the undetermined prize ball counter are loaded. Since the managed gaming machine 100 of this embodiment is a specification that combines so-called one-type and two-type games, the prize balls obtained by winning into the large prize winning hole may be during a small win, and whether or not the number of prize balls is included in the number of consecutive role ratio calculations is not determined until a big win occurs. Therefore, in this embodiment, regardless of whether or not a big win occurs, the number of prize balls obtained by winning into the large prize winning hole is always added to the undetermined prize balls once.
[3] "ADDWB HL, A" is a command to add the A register to the HL register. Here, the sum of the undetermined prize ball counter and the number of consecutive prize balls this time is calculated.
[4] "LDQ (LOW R_ERW_MTS+0), HL" is a command to save the undetermined prize ball counter +0. Here, the calculation result is saved in the lower two bytes of the current consecutive prize ball count. If an overflow occurs in [3], the carry flag is set, and if not, it is reset.
[5] "LDQ A, (LOW R_ERW_MTS+2)" is a command to load the undetermined prize ball counter +2. Here, the most significant byte of the undetermined prize ball counter is loaded.
[6] "ADC A,0" is a command to add the carry flag to the third byte of the undetermined prize ball counter. Here, the sum of "the most significant byte of the undetermined prize ball counter + 0 + carry flag" is calculated. In other words, if the carry flag is set, 1 is added to the most significant byte of the undetermined prize ball counter.
[7] "LDQ (LOW R_ERW_MTS+2), A" is a command to save to the undetermined prize ball counter + 2. Here, the result calculated in [6] is saved as the most significant byte of the new undetermined prize ball counter.

[Checking special game management phases, etc.]
In the performance display monitor display process of this embodiment, the game state of the gaming machine and the value of the undetermined prize ball counter are confirmed, and it is determined whether or not to transfer to the prize balls subject to the consecutive feature ratio. This corresponds to the contents performed in steps S907 to S909 in FIG.

48 is a diagram showing a program for executing confirmation of the special game management phase, etc. The same will be explained below.
[1] "LD A, (R_TOK_PHS)" is a command to load a special game management phase.
[2] "JCP C, A, @SHT_PRE, E_SHYMT_42" is a command to compare with the small win/big win opening wait state designation value and branch if the carry flag is 1. Here, the value of the special game management phase is checked, and if it is neither a small win nor a big win, it branches to "E_SHYMT_42".
[3] "LD A, (R_BIG_FLG)" is an instruction to load the condition unit active flag.
[4] "JCP NZ, A, @TZ___BHT, E_SHYMT_43" is a command to compare with the special symbol jackpot information and branch if the zero flag is 0. Here, the value of the condition device operation flag is checked, and if it is not a jackpot, it branches to "E_SHYMT_43".
[5] "JTQ NZ, (LOW R_ERW_MTS+2), E_SHYMT_41" is an instruction to branch if the undetermined prize ball counter +2 is other than 0.
[5] "JTWQ Z, (LOW R_ERW_MTS+0), E_SHYMT_43" is an instruction to branch if the undetermined prize ball counter +0, +1 is 0.
In the two upper [5], if the game state is a jackpot, the value of the undetermined prize ball counter is checked. If the value of the undetermined prize ball counter is not 0, the process after "E_SHYMT_41" is performed, and if it is 0, the process branches to "E_SHYMT_43".

"E_SHYMT_41:" is a label indicating the branch destination address of the above [5].
[6] "LDQ (LOW R_ERW_TSK), @EXD_TSK_YKH" is a command to save the next feature ratio calculation designated value in the calculation management buffer. Here, the "next feature ratio calculation designated value" is saved in the calculation management buffer.
The reason why the "next feature ratio calculation designated value" is saved here instead of the "next consecutive feature ratio calculation designated value" is that it is considered that the "next feature ratio calculation designated value" may already be set in the calculation management buffer at this time.

[Continuous bonus ball counter update process]
In the performance display monitor display process of this embodiment, the process of transferring the prize balls of the undetermined prize ball counter to the continuous feature prize ball counter (steps S905, S910, S911, etc. in FIG. 44) is performed. Hereinafter, these will be described as the continuous feature prize ball counter update process.

49 is a diagram showing a program for updating the consecutive bonus ball counter, etc. The same will be explained.
[Continuous feature prize ball counter update process]
[1] "LDQ HL, (LOW R_ERW_RYS+0)" is a command to load the consecutive prize ball counter +0.
[2] "LDQ DE, (LOW R_ERW_MTS+0)" is a command to load the undetermined prize ball counter +0. In the above [1] and [2], the lower 2 bytes of the continuous prize ball counter and the undetermined prize ball counter are loaded.
[3] "ADD HL, DE" is a command to add the undetermined prize ball counter to the continuous prize ball counter.
[4] "LDQ (LOW R_ERW_RYS+0), HL" is a command to save the consecutive prize ball counter +0. The sum is calculated in [3] above, and the lower 2 bytes of the consecutive prize ball counter are saved in [4].
[5] "LDQ A, (LOW R_ERW_RYS+2)" is a command to load the consecutive prize ball counter +2.
[6] "LDQ HL, LOW R_ERW_MTS+2" is a command to set the address of the undetermined prize ball counter +2. In the above [5], the upper byte of the consecutive prize ball counter is loaded, and in [6], the address of the upper byte of the undetermined prize ball counter is set.
[7] "ADC A, (HL)" is a command to add the third byte of the undetermined prize ball counter and the carry flag to the third byte of the continuous prize ball counter.
[8] "LDQ (LOW R_ERW_RYS+2), A" is a command to save to the consecutive prize ball counter +2. In the above [7], the sum of the most significant byte of the consecutive prize ball counter, the most significant byte of the undetermined prize ball counter, and the carry flag is calculated, and in [8], the result is saved.

"E_SHYMT_42:" is a label indicating the start of the undetermined prize ball counter clearing process.
[Undetermined prize ball counter clearing process]
[9] "CLRWQ (LOW R_ERW_MTS+0)" is a command to clear the undetermined prize ball counter +0.
[10] "CLRQ (LOW R_ERW_MTS+2)" is a command to clear the undetermined prize ball counter +2. The above [9] and [10] clear the undetermined prize ball counter. This clearing is also performed when the game state is neither a big win nor a small win.

[Calculation management buffer setting process after base value calculation]
In the performance display monitor control process of this embodiment, when the base value is calculated, the process of saving the next feature ratio calculation designated value in the calculation management buffer (steps S926 and S927 in FIG. 46) is performed. Hereinafter, this will be described as the calculation management buffer setting process after the base value is calculated.

50 is a diagram showing a program for the calculation management buffer setting process after the base value is calculated.
[Calculation management buffer update process 1]
“E_SHYMT — 57:” is a label indicating the start of calculation management buffer update process 1 .
"LDQ (LOW R_ERW_TSK), @EXD_TSK_YKH" is a command to save the next winning ratio calculation designated value in the calculation management buffer.
"JP E_SHYMT_90" is a command to jump to "E_SHYMT_90".

[Process allocation based on calculation management buffer]
In the performance display monitor control process of this embodiment, if the base value is not calculated, the calculation management buffer (R_ERW_TSK) is checked and processing is allocated (steps S922, S923, S924, S925, S926, etc. in FIG. 46). Specifically, if the ratio of the reels is calculated, it branches to "E_SHYMT_70", and if the ratio of the continuous reels is calculated, it branches to "E_SHYMT_80". If neither is performed, it branches to "E_SHYMT_90". Below, this process will be described as processing allocation based on the calculation management buffer.

51 is a diagram showing a program for allocating processes based on the calculation management buffer.
"E_SHYMT_60:" is a label indicating the start of processing.
[If the base is not calculated, check whether the ratio of the reels and the ratio of consecutive reels are to be calculated.]
[1] "JTQ NZ, (LOW R_ERW_PAY), E_SHYMT_70" is an instruction to branch if the current number of prize balls is other than 0. Here, if the current number of prize balls (R_ERW_PAY) is not 0, branch to E_SHYMT_70.
[2] "LDQ A, (LOW R_ERW_TSK)" is a command to load the computation management buffer.
[2] "JCP Z, A, @EXD_TSK_YKH, E_SHYMT_70" is a command that compares with the next reel ratio calculation designated value and branches if the zero flag is 1.
In the two [2] above, if the calculation management buffer is the next role ratio calculation designated value (@EXD_TSK_YKH(1)), it branches to "E_SHYMT_70".
[3] "CP A, @EXD_TSK_RYH" is a command to compare with the next consecutive role ratio calculation designated value. Here, the calculation management buffer is compared with the next consecutive role calculation designated value (@EXD_TSK_RYH (2)).
[4] "JP Z, E_SHYMT_80" is an instruction to branch if the zero flag is 1. Here, if there is a match in [3] above, branch to "E_SHYMT_80".
"JP E_SHYMT_90" is an instruction to branch to "E_SHYMT_90". If there is no match in the above [3], branch to "E_SHYMT_90" here.

[Calculation management buffer setting process after calculating the role ratio]
52 is a diagram showing a program for setting the calculation management buffer after calculating the ratio of the reels. In this process, when the ratio of the reels is calculated, the calculation management buffer saves the next consecutive reels ratio calculation designated value.
"E_SHYMT_72:" is a label indicating the start of processing.
"LDQ (LOW R_ERW_YAK), A" is a command to save to the bonus ratio buffer.
"LDQ (LOW R_ERW_TSK), @EXD_TSK_RYH" is a command to save the next linked calculation designated value in the calculation management buffer.
"JP E_SHYMT_90" is a command to jump to "E_SHYMT_90".

[Calculation management buffer setting process after calculating the continuous role ratio]
53 is a diagram showing a program of the calculation management buffer setting process after the consecutive feature ratio calculation. In this process, when the feature ratio is calculated, the calculation management buffer is cleared.
"E_SHYMT_82:" is a label indicating the start of processing.
"LDQ (LOW R_ERW_REN), A" is a command to save to the continuous feature ratio buffer.
"CLRQ (LOW R_ERW_TSK)" is a command to clear the computation management buffer.

[Summary of the fifth technical feature]
As described above, it is possible to prevent the calculation time of the performance values (base value, reel ratio, and continuous reel ratio) during timer interrupt processing from becoming long, and also to minimize the delay in calculation.

[Verification by number of states]
The usefulness of this embodiment has been made clear above, but an additional verification based on the number of states will be performed below.

[Number of states required to calculate base value]
54 and 55 are diagrams showing the program for calculating the base value. In the program code, the number to the left of an instruction indicates the number of states (number of clocks) required to execute the instruction. When two types of numbers are written, the left one indicates the number of states when branching is performed, and the right one indicates the number of states when branching is not performed.

"E_SHYMT_50:" is a label indicating the start of processing.
[Divisor setting register update process]
1. "XOR A, A" is an instruction to set [00H] to the A register.
5 "LDQ BC, (LOW R_ERW_TJS)" is a command to load the normal prize ball counter.
4 "LDQ HL, (LOW R_ERW_TJO)" is an instruction to load the normal out counter.
3/2 "JR TZ, E_SHYMT_54" is an instruction to branch to "E_SHYMT_5" if the second zero flag is 1.
5 “OUT (LOW @DIVB32_+0), HL” is a command to output to the lowest address of the divisor setting register +0.
2. "CLR HL" is an instruction to set [0000H] to the HL register.
5 "OUT (LOW @DIVB32_+2), HL" is a command to output to the lowest address of the divisor setting register +2.

[Dividend setting register update process]
The following is an instruction to calculate 200 times the normal number of winning balls.
1. "LD A, C"
4. "MUL HL, A, 200"
1 "EX DE,HL"
1. "LD A, B"
4. "MUL HL, A, 200"
2. "ADDWB HL,D"
1 "LD A, E"

3 “OUT (LOW @DIVA32_+0), A” is a command to output to the lowest address of the dividend setting register+0.
5 "OUT (LOW @DIVA32_+1), HL" is a command to output to the lowest address of the dividend setting register +1.
4 “OUT (LOW @DIVA32_+3), 0” is a command to output 0 to the lowest address of the dividend setting register +3.

[Base value division waiting process]
2. "LD B,2" is an instruction to set 2 in the B register.
"E_SHYMT_51:" is a label indicating the start of processing.
3/2 "DJNZ E_SHYMT_51" is an instruction to branch to "E_SHYMT_51:" if the loop continues.
[Division result confirmation process]
2. "LD A,100" is an instruction to set 100 in the A register.
5 “IN HL, (LOW @DIV32__+2)” is a command to input the lowest address of the division result register +2.
3/2 "JR NTZ, E_SHYMT_54" is an instruction to branch to "E_SHYMT_54" if the second zero flag is 0.
5 "IN HL, (LOW @DIV32__)" is a command to input the lowest address of the division result register.
4. "CP HL, 100*2" is a command to check the first and second bytes of the division result.
3/2 "JR NC, E_SHYMT_54" is an instruction to branch to "E_SHYMT_54" if the carry flag is 0.
1. "LD A,L" is an instruction to set the result of a division.
2. "SRL A" is an instruction to calculate a value by shifting one bit to the right.
2. "ADC A,0" is an instruction that adds the carry flag to calculate the base calculation value.

"E_SHYMT_54:" is a label indicating the start of processing.
[Base calculation value update process]
2. "LDQ HL, LOW R_ERW_BAS" is a command to set the address of the base calculation value.
2 "LD (HL), A" is an instruction to save the contents of the target address.

As a result, the divisor setting register update process requires 1+5+4+2+5+2+5=24 states (assuming the out counter is not normally 0 and no branch is taken at "JRTZ, E_SHYMT_54").

The dividend setting register update process requires 1+4+1+1+4+2+1+3+5+4=26 states.

The base value division wait process requires 2 + 3 + 2 = 7 states.

The division result confirmation process requires 2+5+2+5+4+2+1+2+2=25 states (the base calculation result is 0 to 99.5%, and no branching is performed at the two JR instructions).
The base estimate update process requires 2+2=4 states.
Therefore, the total number of states required to calculate the base value and store the result is 24+26+7+25+4=86 states.

[Number of states required to calculate the ratio of roles]
The ratio of the reels is calculated in the same manner as the base value, but the total number of states required to save the result is 81.

[Number of states required to calculate the ratio of consecutive features]
The successive feature ratio is calculated in the same manner as the base value, but the total number of states required to save the result is 81 states.

[Verification based on processing time]
FIG. 56 is a diagram showing the time required to calculate various performance values.
Assume that the internal system clock of the main control CPU 31 is 16 MHz. In this case, one state = 1/16 millionth of a second, so the time required to calculate the base value, etc. is as follows:
The base value calculation requires a processing time of 5.375 μs for 86 states.
The reel ratio calculation has a processing time of 5.0625 μs for 81 states.
The calculation of the ratio of consecutive features requires a processing time of 5.0625 μs for 81 states.
Therefore, if the base value, feature ratio, and continuous feature ratio are all calculated, 248 states (15.5 μs) are required, but if only one is calculated during one timer interrupt processing as in this embodiment, the maximum number of states is 86 (5.375 μs).

[Alternative plan]
Next, another method for reducing the calculation processing time will be described.
In another proposal, a base value calculation flag, a role ratio calculation flag, and a continuous role ratio calculation flag are prepared, and the flags are set when calculation is necessary, and reset when calculation is performed. If multiple flags are set, only the one with the highest priority is calculated. This proposal also provides the same usefulness as the present embodiment, but the program becomes slightly more complicated. A more detailed explanation will be given below.

[Various flags]
Alternatively, the following flags are used:
The following flags are reset when the RWM is initialized, and the current status is maintained when the power is turned on (when the power is restored).
Base value calculation flag Reel ratio calculation flag Continuous reel ratio calculation flag These flags may be separate RWMs or separate bits in the same RWM.

[Flag setting trigger]
When the following conditions are met, the corresponding flag is set. If the flag is already set, it will remain set.
"Base value calculation flag"
The base value calculation flag is set in the following cases:
・ When the display of the current base value starts due to the change in the display content of the base value ・ When the total number of outs reaches a predetermined value (60,000, 299 only for the first time) "Ratio calculation flag for the special feature"
The reel ratio calculation flag is set in the following cases.
・ When a winning ball occurs, the "Continuous feature ratio calculation flag"
The consecutive feature ratio calculation flag is set in the following cases.
When a winning ball occurs When an undetermined winning ball is added to the winning balls subject to the consecutive prize ratio

[Process to be performed]
FIG. 57 is a diagram showing the correspondence between the calculation flag and the process to be executed in another example.
Depending on the state of the base value calculation flag, etc., the process to be executed within the timer interrupt process is determined as shown in Fig. 57. When a calculation is performed, the corresponding flag is reset.

The present invention is not limited to the above-described embodiment, and can be practiced in various modified forms. For example, the above-described embodiment can be modified as follows.
(1) Although the above has been explained in the case of the managed gaming machine 100, the present invention can also be applied to existing pachinko machines that do not have the configuration of the managed gaming machine 100.
(2) The above-described programs and flowcharts are merely examples, and the present invention is not limited to them.

(3) The present invention can also be applied to slot machines. That is, the present invention can also be applied to slot machines that include a main control board that controls the execution and stopping of games, and a medal count control board that controls the payout of medals.
In this case, the main control board transmits information on the number of medals consumed in a game and the number of medals won in a game to the medal count control board, which calculates the difference in the number of medals.The medal count control board then transmits the calculated difference in the number of medals information to the main control board, and the main control board may set a game stop state based on the received difference in the number of medals information.
The main control board may transmit information on the number of medals won in a game to the medal count control board, and the medal count control board may calculate the difference in number based on the information on the number of medals won in a game and the information on the number of medals consumed in a game. The medal count control board may then transmit the calculated difference in number information to the main control board, and the main control board may set a game stop state based on the received difference in number information.

REFERENCE SIGNS LIST 10 Managed gaming machine game board 20 Managed gaming machine frame 30 Main control board 32 Winning port switch 33 Out switch 34 First board magnetic detection sensor 35 Second board magnetic detection sensor 36 Radio wave detection sensor 37 Performance display monitor 38 Door opening switch 40 Performance control board 50 Frame control board 100 Managed gaming machine

Claims (2)

A gaming machine including a game control means for controlling the execution of a game and a presentation control means for controlling the content related to the presentation of the game,
The game control means includes:
This gaming machine is characterized in that when it transitions to main loop processing after completing initialization processing at power-on, it puts itself into an interrupt-disabled state and executes all processing within the main loop processing , including at least the processing of sending commands to the presentation control means , and after completion of the processing, puts itself into an interrupt-enabled state only during the period from the end of the main loop processing back to the beginning. 2. The gaming machine according to claim 1,
The game control means includes:
A gaming machine characterized in that, when an interrupt process that occurs during execution of the main loop process is executed, the process of saving and restoring registers related to the main loop process is not executed.

Images