JP7500382B2 - Load drive system and method thereof, railway vehicle and operation method thereof - Google Patents

Description

The present invention relates to a load drive system that enables smooth restart of a free run, a railway vehicle equipped with the system, a load drive method, and a railway vehicle operation method that applies the system.

In systems that use a motor as a drive source, the motor may continue to rotate even when the power is off. For example, this may occur when a train is coasting or when an electric vehicle has the accelerator off. This state is called free-running, and the technology for restarting a motor in a free-running state is called free-running restart. In free-running restart, the rotor position or rotational speed of the motor is estimated, and the inverter is controlled based on this estimated value. If there is an error in the estimated speed value, a torque shock will occur and the ride will become uncomfortable, so high estimation accuracy is required. Therefore, a technology has been disclosed that suppresses torque pulsation by removing the offset error that causes torque shock from the three-phase AC current (for example, Patent Document 1).

The motor control device in Patent Document 1 is equipped with a filter section that does not pass certain frequency components of the three-phase AC current input from the motor's three-phase AC current detection circuit to the current conversion section. It is also proposed to use a high-pass filter that changes the passband according to the motor rotation speed as the filter section. As a result, the offset error superimposed on the three-phase AC current is removed, thereby suppressing torque pulsation.

To detect the motor rotation speed that is the reference for the pass band, a resolver can be provided, or it can be estimated from the three-phase AC current flowing through the motor as in Reference 1, with the latter being preferable from a cost perspective. However, in a free-run restart, no three-phase AC current flows until the restart begins, and the motor rotation speed is unknown. As a result, the pass band of the filter cannot be set, and the offset error of the three-phase AC current cannot be removed. If a free-run restart is started in this state, an error occurs in the estimated motor rotation speed due to the offset error of the three-phase AC current. As a result, restarting at a motor rotation speed based on an inaccurate estimate generates a torque shock, which causes vibration and noise.

JP 2009-273302 A

The object of the present invention was made in consideration of the above problems, and its purpose is to provide a load drive system that can reduce torque shock that causes vibration and noise by suppressing the current offset error during free running and restarting at an estimated motor rotation speed.

The present invention, which solves the above problems, is a load drive system that drives an inverter load, comprising an inverter and an inverter control circuit that controls the switching of the inverter, and is equipped with an inverter frequency calculation circuit that calculates the inverter frequency, which is the drive frequency that drives the load, a current detection circuit that detects the current flowing through the load, multiple frequency filters that receive the detected current as an input, and a selection circuit that selects the output of the multiple frequency filters, where the inverter control circuit shorts the terminals of the load, the selection circuit selects one output of the multiple frequency filters based on the band and output of each of the multiple frequency filters, and the inverter frequency calculation circuit calculates the inverter frequency based on the selected selected output.

The present invention provides a load drive system that can reduce torque shocks that cause vibrations and noise by suppressing current offset errors during free-running and restarting the motor at an accurately estimated rotation speed.

1 is a configuration diagram of a load driving system according to a first embodiment of the present invention. FIG. 2 is an internal configuration diagram of an inverter frequency calculation circuit. FIG. 11 is a waveform diagram showing a free-run restart. FIG. 11 is a waveform diagram relating to the first to third HPFs. 4 is a flowchart of a selection circuit. FIG. 11 is a configuration diagram of a main part of a load driving system according to a second embodiment. FIG. 13 is a waveform comparison diagram when there is no phase overflow detection unit. FIG. 13 is a waveform comparison diagram when a phase overflow detection unit is included. FIG. 11 is an explanatory diagram relating to current and past values of a phase difference. FIG. 11 is a configuration diagram of a load driving system according to a third embodiment.

Each embodiment of the present invention will be explained below using the drawings.

FIG. 1 is a configuration diagram of a load driving system according to a first embodiment. Each component will be described below. A motor 1 serves as a driving source for the load driving system. An inverter 2 receives a DC voltage _Ecf , converts the DC voltage to an AC voltage using a switching element, and applies the AC voltage to the motor 1. A capacitor 3 is provided to smooth the DC voltage _Ecf . A current detection circuit 4 is a section for detecting the U-phase current _iu , V-phase current _iv , and W-phase current _iw of the motor 1, and the respective detected values are _iuf , _ivf , and _iwf .

The high-pass filter (HPF) group 5 includes a first HPF 5a, a second HPF 5b, and a third HPF 5c, and the detection values i _uf , i _vf , and i _wf are input to each of the first to third HPFs. The selection circuit 6 selects one of the outputs of the first HPF 5a to the third HPF 5c as a selected output. The selected outputs for the U phase, V phase, and W phase are represented by i _us , i _vs , and i _ws , respectively. The high-pass filter (HPF) group 5 illustrated in the first to third embodiments may also be referred to as a frequency filter (bandpass filter) 5 as a higher-level concept.

The inverter frequency calculation circuit 7 calculates the inverter frequency ω _inv based on i _us , i _vs , and i _ws . Figure 2 shows the internal configuration of the inverter frequency calculation circuit 7. The inverter frequency calculation circuit 7 is composed of a current phase calculation unit 7a and a PLL unit 7b. First, in the current phase calculation unit 7a, the α-axis current i _α and the β-axis current i _β are calculated by the three-phase/two-phase conversion unit 7a1, and the current phase θ _i is calculated by the arctangent function 7a2.

Here, the current phase _θi is equivalent to the phase of the current vector defined by i _us , i _vs , and i _ws , so the rate of change of the current phase _θi coincides with the frequencies of i _us , i _vs , and i _ws . Next, in the PLL unit 7b, the phase difference Δθ, the inverter frequency ω _inv , and the PLL output phase θ _PLL are calculated by a PLL (Phase Locked Loop) consisting of a PI control unit 7b1 and an integration unit 7b2. Due to the stability of the PLL, θ _PLL is synchronized with θ _i , so the rate of change of θ _PLL , i.e., the inverter frequency ω _inv , coincides with the frequencies of i _us , i _vs , and i _ws .

When the restart signal g _on is low, the inverter control circuit 8 turns off all of the gate signals g ₁ to g ₆ to stop switching of the inverter 2. When g _on is high, the inverter control circuit 8 shorts the terminals of the motor 1 for a certain period by turning on the gate signals g ₁ , g ₃ , and g ₅ of the upper arms of the U-phase, V-phase, and W-phase, or the gate signals g ₂ , g ₄ , and g ₆ of the lower arms. After that, the gate signals g ₁ to g ₆ are determined based on PWM control so that the fundamental frequency of the output voltage of the inverter 2 becomes the inverter frequency ω _inv . The above are the components of the first embodiment.

Now let us explain free-run restart. Figure 3 shows the waveforms during free-run restart. Until time _t1 , the restart signal g _on is low, and gate signals g ₁ to g ₆ are off. Of g ₁ to g ₆ , Figure 3 only shows gate signals g ₁ and g ₂ for the upper and lower arms of the U phase. Since all switching elements of the inverter 2 are off, i _u , i _v , and i _w are all zero, and the torque of the motor 1 is also zero, but the drive frequency ω _r of the motor 1 is not necessarily zero due to inertia or an external load.

Free-run restart is a technique for restarting the inverter when the drive frequency _ωr is unknown, and in order to smoothly raise the torque of the motor 1, it is necessary to start PWM control by the inverter control circuit 8 with the drive frequency _ωr and the inverter frequency _ωinv in a state where they are matched. Therefore, it is necessary to estimate the drive frequency _ωr by some means and set it as the initial value of the inverter frequency _ωinv . To estimate the drive frequency _ωr during free-run restart, after g _on changes to High at time t ₁ in Figure 3, the inverter control circuit 8 turns on g ₂ , g ₄ , and g ₆ to short the terminals of the motor 1.

As a result, for example, when (1) motor 1 is a magnet motor, or (2) motor 1 is an induction motor and the rotor has residual magnetic flux, _iu flows at the same frequency as the drive frequency _ωr . Since _iu contains an offset _iofs according to the residual magnetic flux phase at time _t1 , if a signal after removing the effect of _iofs by the HPF is input to the inverter frequency calculation circuit 7, the inverter frequency _ωinv will converge to the drive frequency _ωr . The time when this convergence is completed is set to _t2 , and PWM control by the inverter control circuit 8 is started at this timing, allowing the torque of motor 1 to rise smoothly. This is the outline of the coast restart.

The issue of free-run restart will now be explained. To remove i _ofs using an HPF, an HPF with a passband of the frequency of i _u, i.e., the drive frequency ω _r, is required. However, the drive frequency ω _r is unknown at time t ₁ in Figure 3, and the passband cannot be set at that time.

Therefore, the offset i _ofs is not removed, and an error occurs between the drive frequency ω _r and the inverter frequency ω _inv . Due to this frequency error, even if a variable passband based on the inverter frequency ω _inv is provided, i _ofs is not removed in the end, which causes further frequency error. In this way, the passband of the HPF for removing i _ofs cannot be set unless the drive frequency ω _r is known, but there is a contradiction in that the offset i _ofs must be removed before estimating the drive frequency ω _r . This is an issue when restarting a free-running system.

In the present invention, a frequency filter 5 and a selection circuit 6 are provided as a section for matching the drive frequency _ωr and the inverter frequency _ωinv without being affected by i _ofs even when the drive frequency _ωr is unknown, and the operating principle of these is described below. The frequency filter 5 is a generic term for the HPF group 5 that includes the first HPF 5a to the third HPF 5c. Figure 4 shows waveform diagrams related to the first HPF 5a to the third HPF 5c. The passbands ω _HPF1 to ω _HPF3 of the first HPF 5a to the third HPF 5c have a relationship of "ω _HPF1 < ω _HPF2 < ω _HPF3 ", and it is assumed that ω _HPF2 is closest to the drive frequency _ωr . In the first HPF 5a, an offset remains in the HPF output because "ω _HPF1 < ω _r ".

For this reason, _θi shown in Fig. 2 is distorted as shown at A in Fig. 4, and an error occurs between the drive frequency _ωr and the inverter frequency _ωinv . In the second HPF 5b, since "ω _HPF2 ≒ _ωr ", no offset i _ofs remains in the HPF output, and the drive frequency _ωr and the inverter frequency _ωinv match. In the third HPF 5c, since "ω _HPF3 > _ωr ", the HPF output becomes zero, _θi shown in Fig. 2 becomes zero as shown at B in Fig. 4, and the inverter frequency _ωinv also becomes zero. In order to select an appropriate HPF, the selection circuit 6 operates according to the flowchart shown in Fig. 5.

In step S1, an HPF whose output is equal to or greater than the threshold value i _th is selected. In HPFs whose passband is equal to or less than _ωr , such as the first HPF 5a and second HPF 5b shown in Fig. 4, the output is non-zero and they are selected in step S1. In step S2, of the HPFs selected in step S1, the HPF with the largest band is selected. In other words, the second HPF 5b is selected from the two options of the first HPF 5a and the second HPF 5b. In this way, the selection circuit 6 utilizes the following property shown in Fig. 4.

(1) In an HPF whose passband exceeds the drive frequency _ωr , the output becomes zero.
(2) In an HPF whose passband is below the drive frequency _ωr , the output is non-zero.
(3) The higher the passband of the HPF, the more the offset i _ofs can be removed.

In step S1, the HPFs corresponding to (1) above are excluded, and the HPFs corresponding to (2) are left. In step S2, among the HPFs corresponding to (2), the HPFs corresponding to (3) are selected. Through these steps, it is possible to select an HPF having a passband equal to or lower than the drive frequency _ωr and closest to the drive frequency _ωr . Therefore, it is possible to converge the inverter frequency _ωinv to the drive frequency _ωr in the inverter frequency calculation circuit 7 located downstream of the selection circuit 6. The above is the operating principle of the HPF group 5 and the selection circuit 6, and it is possible to match the drive frequency _ωr and the inverter frequency _ωinv without being affected by the offset _iofs even when the drive frequency _ωr is unknown. As a result, it is possible to prevent torque shock when restarting the free run, and to contribute to reducing vibration and noise in the load drive system.

In addition to the HPF group 5 in Figure 1, which has multiple HPFs with different passbands, an HPF with a passband of 0 Hz may be added that passes the detection values i _uf , i _vf , and i _wf as is. This is because, during free-run restart, motor 1 may be stopped, and if motor 1 is an induction motor and there is residual magnetic flux in the rotor, the detection values of DC components i _uf , i _vf , and i _wf will be observed.

5 can be applied as is in this case, and since the detection values i _uf , i _vf , and i _wf are DC components, only the HPF with a passband of 0 Hz is selected in step S1, and that HPF is uniquely selected in step S2. As a result, the detection values i _uf , i _vf , and i _wf of the DC components are input to the inverter frequency calculation circuit 7, and the inverter frequency ω _inv converges to zero. In this way, the selection circuit 6 can detect the stop of the motor 1 by including the current detection value as one of the options.

Figure 6 is a diagram showing the main components of a load driving system according to Example 2. In Example 2, the PLL unit 7b includes a phase overflow (hereinafter sometimes abbreviated as "phase OF" or simply "OF") detection unit 7b3, an OF count calculation unit 7b4, and a phase difference correction unit 7b5, and the internal configuration of each is described below.

The phase OF detection unit 7b3 includes a delay element 7b3a, absolute value calculation units 7b3b and 7b3c, threshold determination units 7b3d and 7b3e, and a logical product unit 7b3f. Figures 7A and 7B show waveform comparison diagrams with and without the phase OF detection unit 7b3. As shown in Figure 7A, when the phase OF detection unit 7b3 is not present, Δθ may exceed +π [rad] and change discontinuously to -π [rad] in the process in which the inverter frequency ω _inv converges to the drive frequency ω _r .

The time when this discontinuous change occurs is designated as ta. After time ta, while Δθ is negative, the inverter frequency ω _inv decreases, and the difference with the drive frequency ω _r increases. When Δθ becomes positive, the inverter frequency ω _inv increases again, but the same phenomenon is repeated thereafter, and Δω remains at a predetermined time _t2 , causing a torque shock. To prevent this, the phase OF detection unit 7b3 sets the phase OF detection flag F _ovr to 1 when Δθ exceeds ±π. Below, it will be shown that F _ovr can be correctly output by the configuration shown in Figure 6.

In FIG. 6, "F _ovr = 1" occurs when the following (x) and (y) are both satisfied according to threshold decision units 7b3d and 7b3e and logical product unit 7b3f.
(x) The current value Δθ _now and the past value Δθ _old of Δθ are different in sign.
(y) The sum S of the absolute values of Δθ _now and Δθ _old is greater than or equal to π [rad].
If (x) is true, the signs of Δθ _now and Δθ _old are negative/positive or positive/negative, which are represented by cases A and B in FIG. 8, respectively.

_{8 are} the start point and end point, the arc that passes through the reference axis (Δθ = 0) is denoted by p (dotted line), and the arc that does not pass through the reference axis is denoted by q (solid line). The change from Δθ _old to Δθ _now follows either path p or q, and if the calculation cycle of phase OF detection unit 7b3 is sufficiently short, it is reasonable to consider that the change took the shorter path.

Since S in (y) is the angle formed by p, if (y) is true, then q is shorter than p. Therefore, the change from Δθ _old to Δθ _now is q, and since the change includes ±π [rad], OF occurs. Conversely, the cases in which OF occurs are either Case A or B in Figure 8, so by following the argument in reverse, it can be shown that if OF occurs, then "F _ovr = 1". From the above, it can be said that F _ovr can be correctly output by the configuration shown in Figure 6.

As shown in Fig. 6, the OF count calculation unit 7b4 is composed of threshold determination units 7b4a, 7b4b, logical product units 7b4c, 7b4d, and a delay element 7b4e. _Fpn represents the increase/decrease direction of Δθ when OF occurs, and is defined as 1 and -1 when Δθ increases and decreases, respectively. _Ncnt represents the cumulative number of OFs. However, the number of OFs in the Δθ increase/decrease direction is offset and counted. Below, it will be shown that _Fpn and _Ncnt can be calculated by the configuration shown in Fig. 6.

"F _pn = 1" occurs when "F _ovr = 1" is true and Δθ _now is negative. This corresponds to case A in Figure 8, and the direction of change from Δθ _old to Δθ _now is represented by arrows j and k. As the arrow directions indicate, Δθ in case A is increasing, and conversely, the only case in which Δθ increases when OF occurs is case A. Therefore, following the argument in reverse, "F _pn = 1" is true.

Therefore, "F _pn = 1" is equivalent to Δθ increasing when OF occurs. The same is true for "F _pn = -1". Since N _cnt calculates the integral value of F _pn by feedback including delay element 7b4e as shown in Figure 6, it is clear that the cumulative number of OFs can be counted. From the above, it can be said that F _pn and N _cnt can be correctly calculated by the configuration shown in Figure 6.

The phase difference correction unit 7b5 calculates the expanded phase difference _Δθc based on _Ncnt . _Δθc is a variable that allows Δθ to be calculated beyond ±π [rad], and as shown in Fig. 7B, when Δθ exceeds π [rad] at time ta, the variable changes as follows: " _Fovr : 0→1", " _Fpn : 0→1", " _Ncnt : 0→1".

Here, as shown in FIG. 6, since "Δθ _c = Δθ + 2π・N _cnt ", Δθ _c changes continuously beyond π [rad]. By inputting this Δθ _c to the PI control unit 7b1 in FIG. 6, the stability of the PLL is maintained, and the inverter frequency ω _inv continues to track the drive frequency ω _r . Eventually, at time tb in FIG. 7B, Δθ _c falls below π [rad], and changes to "F _ovr : 0 → 1", "F _pn : 0 → -1", and "N _cnt1 → 0". After tb, "N _cnt = 0", Δθ _c and Δθ are the same, and both converge to zero. As a result, at _t2 , the inverter frequency ω _inv converges to the drive frequency ω _r .

As described above, by providing the phase OF detection unit 7b3, the OF count calculation unit 7b4, and the phase difference correction unit 7b5, it is possible to make the inverter frequency ω _inv coincide with the drive frequency ω _r even when Δθ exceeds ±π [rad]. This makes it possible to prevent torque shock in the following cases.

(1) When motor 1 is designed to be high speed in order to achieve high efficiency.
(2) The calculation period of the PI control unit 7b1 is set to be long in order to reduce the CPU load, and KP (proportional gain) and KI (integral gain) are reduced in order to ensure the stability of the PLL.
(3) When KP and KI are decreased in order to reduce Δω caused by an error in _θi resulting from detection errors or quantization errors of the detected values _iuf , _ivf , and _iwf .

The above is the effect of the second embodiment, and the processes required to achieve this can be summarized as follows.
Phase OF detector 7b3: Detects when Δθ, which is the difference between _θi and θ _PLL , falls below ±π [rad].
OF count calculation unit 7b4: Counts _Ncnt .
Phase difference correction unit 7b5: Adds the product of N _cnt and 2π [rad] to Δθ.

9 is a configuration diagram of a load driving system according to a third embodiment. The load driving system according to the third embodiment includes a plurality of motors 1, wheels 9 connected to the motors 1, a wheel wear amount detection unit 10, and a vehicle 11, and receives power from an overhead line 12. The wheel wear amount detection unit 10 receives inverter frequencies ω _inv1 to ω _inv4 corresponding to the plurality of motors 1, and if there is a variation in these frequencies, it determines that wear has occurred in a specific wheel 9 and outputs a wear detection flag F _w . The reason why wear can be detected from the variation in the inverter frequencies ω _inv1 to ω _inv4 will be described below.

As long as the wheels 9 do not spin, the amount of rotation of the wheels 9 per unit time is the same for all the wheels. Therefore, when only a specific wheel 9 is worn, the rotation speed of that wheel 9 becomes relatively high, and the inverter frequency ω _invj (j = 1 to 4) of the motor 1 connected to that wheel 9 also becomes relatively high. For this reason, by detecting the variation in the inverter frequency ω _invj (j = 1 to 4), it is possible to determine that wear has occurred in the specific wheel 9. According to the third embodiment, even if there is no detection unit for the drive frequency ω _r , it is possible to detect wear of the specific wheel 9 and extend the maintenance interval. This makes it possible to reduce the maintenance cost of the vehicle 11.

The load driving system according to the embodiment of the present invention (the present system) can be summarized as follows.
[1] This system is a load drive system that drives a motor 1 as a load 1 of an inverter 2, and is equipped with the inverter 2, an inverter control circuit 8 that controls the switching of the inverter 2, an inverter frequency calculation circuit 7, a current detection circuit 4, a frequency filter (bandpass filter) 5, and a selection circuit 6.

Instead of being equipped with a resolver, the motor 1, which has residual magnetic flux in its rotor, can detect the rotation speed from the three-phase AC current that accompanies the rotation. In this system, the drive frequency _ωr associated with coasting and slipping of the motor 1 (railroad is an example) is estimated when restarting the free run. To this end, the inverter control circuit 8 obtains the three-phase AC currents _iu , _iv , and _iw that are generated from the motor 1 due to coasting and slipping by shorting the terminals of the motor 1 while stopping the inverter output. In this short-circuit state, the current detection circuit 4 detects the current detection values _iuf , _ivf , and _iwf for the currents _iu , _iv , and _iw that are generated by the slipping of the motor 1.

The currents _iu , _iv , and _iw generated by the idling of the motor 1 contain an offset _iofs according to the residual magnetic flux phase. The frequency filter 5 distributes the current detection values _iuf , _ivf , and _iwf to different pass bands and outputs them. The selection circuit 6 removes the offset _iofs by selecting the distributed output of the frequency filter 5 in a desired pass band. The desired pass band is a frequency band that passes the drive frequency _ωr of the motor 1 but removes the offset _iofs .

The selection circuit 6 selects one of the outputs of the frequency filter 5 as a selected output i _us , i _vs , i _ws based on the output corresponding to each pass band of the frequency filter 5. In other words, the inverter frequency calculation circuit 7 calculates and generates the inverter frequency ω _inv based on the selected outputs i _us , i _vs , i _ws according to a desired pass band among those output from the frequency filter 5 having a plurality of different pass bands.

In this way, in order to remove the influence of the offset i _ofs , if the output signal of the frequency filter 5 selected to the desired pass band is input to the inverter frequency calculation circuit 7, the inverter frequency ω _inv generated therein will converge to an appropriate drive frequency ω _r . In other words, when restarting the free run, it is possible to obtain an inverter frequency ω _inv that is synchronized so as to match the phase with the drive frequency ω _r associated with the coasting and idling of the motor 1.

When this convergence is complete, PWM control by the inverter control circuit 8 begins, allowing the torque of the motor 1 to rise smoothly. As a result, this system can reduce torque shocks that cause vibrations and noise by suppressing current offset errors during free-running and restarting the motor at an accurately estimated motor rotation speed.

[2] It is preferable that the selection circuit 6 selects the selected outputs i _us , i _vs , i _ws that are equal to or higher than a predetermined value and have the highest frequency band among the outputs of the frequency filter 5 that are distributed to different pass bands. Noise related to the offset i _ofs often contains low frequency components, regardless of the drive frequency ω _r that drives the motor 1.

Furthermore, in the frequency filter 5 in this system, the higher the pass band of the HPF is set, the easier it is to remove the offset i _ofs , and the noise components related to the offset i _ofs are removed from the selected outputs i _us , i _vs , and i _ws selected by the selection circuit 6, making it possible to effectively generate only the drive frequency ω _r that drives the motor 1. As a result, this system can more effectively reduce torque shock.

[3] It is preferable that the frequency filter 5 has an option to output the input current detection values i _uf , i _vf , and i _wf including direct current (DC) components without filtering them. When the motor 1 is stopped, the DC component current detection values i _uf , i _vf , and i _wf are input to the inverter frequency calculation circuit 7, and the inverter frequency ω _inv converges to zero. In this way, the selection circuit 6 includes the DC component as one of the current detection values to be selected, so that the system can detect the stop of the motor 1.

[4] The inverter frequency calculation circuit 7 preferably comprises a current phase calculation unit 7a that calculates the current phase _θi based on the selection outputs i _us , i _vs , and i _ws , and a PLL unit 7b that receives the current phase _θi calculated thereby as an input. Here, the rate of change of the current phase _θi coincides with the frequency of the selection outputs i _us , i _vs , and i _ws .

In the PLL unit 7b, the phase difference Δθ, the inverter frequency ω _inv , and the PLL output phase θ _PLL are calculated by a PLL consisting of a PI control unit 7b1 and an integration unit 7b2. Due to the stability of the PLL, the PLL output phase θ _PLL is synchronized with the current phase θ _i , so the rate of change of θ _PLL , i.e., the inverter frequency ω _inv , matches the frequency of the selected outputs i _us , i _vs , and i _ws .

By equipping this system with such a PLL section 7b and employing PLL control, the system's ability to respond to reality can be improved. For example, in an implementation environment, if there is a lot of noise and the S/N ratio is degraded, the system stabilizes the system by lowering the KP (proportional gain) and KI (integral gain) provided in the PLL section 7b. Conversely, if there is little noise and the S/N ratio is good, the system increases the KP and KI to improve responsiveness. As a result, the system is more practical and can reduce torque shock.

[5] In the above-mentioned embodiment 1, the inverter frequency calculation circuit 7 shown in Fig. 2 does not have the phase OF detection unit 7b3 shown in Fig. 6. In this case, as shown in Fig. 7A, when Δθ exceeds +π [rad] and discontinuously changes to -π [rad], the circuit lacks the ability to distinguish between forward and reverse directions, and the true drive frequency _ωr cannot be detected. As a result, the inverter frequency ω _inv may not converge to the drive frequency _ωr .

Therefore, as shown in FIG. 6 as a second embodiment, in the present system described in [4] above, it is preferable that the PLL unit 7b includes a phase OF detection unit 7b3, an OF count calculation unit 7b4, and a phase difference correction unit 7b5. The phase OF detection unit 7b3 can correctly output F _ovr every time Δθ exceeds ±π. The OF count calculation unit 7b4 counts the cumulative number of OFs N _cnt .

The phase difference correction unit 7b5 calculates the expanded phase difference _Δθc based on the cumulative number _Ncnt of OF. _Δθc is a variable that allows Δθ to be calculated beyond ±π [rad], and as shown in Fig. 7B, when Δθ exceeds π [rad] at time ta, it changes as follows: " _Fovr : 0→1", " _Fpn : 0→1", " _Ncnt : 0→1". Here, as shown in Fig. 6, " _Δθc = Δθ + 2π・_Ncnt ", so the expanded phase difference _Δθc changes continuously beyond π [rad].

The expanded phase difference Δθ _c changes continuously beyond π [rad] by the processing of each part of the PLL unit 7b, and the forward/reverse direction discrimination ability is obtained by the phase difference correction unit 7b5. By inputting this phase difference Δθ _c to the PI control unit 7b1 in Fig. 6, the stability of the PLL is maintained, and the inverter frequency ω _inv continues to track the drive frequency ω _r .

As a result, at time _t2 in Fig. 7B, the inverter frequency ω _inv converges to the drive frequency ω _r . This makes it possible to prevent torque shock not only when the response speed is slowed down by lowering KP (proportional gain) and KI (integral gain), but also when the phase difference Δθ is easily offset by ±π [rad] due to the high speed of motor 1. Note that in an actual train, power supply to motor 1 is started several seconds after the convergence time _t2 , for example, with a margin of 2 seconds.

[6] A railway vehicle 11 according to a third embodiment of the present invention includes a motor 1 driven by the load drive system described in any one of [1] to [5] above, and wheels 9 connected to the motor 1. As a result, the railway vehicle 11 can reduce torque shock that causes vibration and noise by suppressing the current offset error during free running and restarting at an accurately estimated motor rotation speed.

[7] The railway vehicle 11 described in [6] above has a plurality of motors 1, and includes wheels 9 connected to the respective motors 1, and a wheel wear detection unit 10 that detects the wear of the wheels 9 from the variation in the inverter frequency ω _inv corresponding to each motor 1. In a railway vehicle 11 in which multi-axle wheels 9 are driven by a plurality of motors 1, if only a specific wheel 9 is worn, the rotational speed of that wheel 9 becomes relatively high, and the inverter frequency ω _invj (j = 1 to 4) of the motor 1 connected to that wheel 9 also becomes relatively high.

Therefore, by detecting the variation in the inverter frequency ω _invj (j = 1 to 4), wear on a specific wheel 9 can be continuously monitored in real time and the timing for performing maintenance can be appropriately determined. As a result, even if there is no detector for the drive frequency ω _r , it is possible to detect wear on a specific wheel 9 and extend the maintenance interval. As a result, the maintenance cost of the vehicle 11 can be reduced.

1...motor (load), 2...inverter, 3...capacitor, 4...current detection circuit, 5...frequency filter (band pass filter or HPF group), 5a...first HPF, 5b...second HPF, 5c...third HPF, 6...selection circuit, 7...inverter frequency calculation circuit, 7a...current phase calculation unit, 7a1...three-phase/two-phase conversion unit, 7a2...arc tangent function, 7b...PLL unit, 7b1...PI control unit, 7b2...integration unit, 7b3...phase OF detection unit (phase OF detection unit), 7b3a...delay element, 7b3b...absolute value calculation unit, 7b3c...absolute value calculation unit, 7b3d...threshold value calculation unit, 7b3e...threshold value calculation unit, 7b3f...logical product unit, 7b4...OF count calculation unit, 7b4a...threshold value calculation unit, 7b4b...threshold value calculation unit, 7b4c...logical product unit, 7b4d...logical product unit, 7b4e...delay element, 7b5...phase difference correction unit, 8...inverter control circuit, 9...wheel, 10...wheel wear amount detection unit, 11...vehicle, 12...overhead line, F _ovr ...phase OF detection flag, F _w ...wear detection flag, Δθ...phase difference

Claims (14)

An inverter;
an inverter control circuit that controls switching of the inverter;
Equipped with
A load drive system for driving a load of the inverter, comprising:
an inverter frequency calculation circuit that calculates an inverter frequency that is a drive frequency for driving the load;
a current detection circuit for detecting a current flowing through the load;
a plurality of frequency filters receiving the detected current as an input;
A selection circuit for selecting outputs of the plurality of frequency filters;
Equipped with
The inverter control circuit shorts the terminals of the load,
the selection circuit selects an output of one of the plurality of frequency filters based on a band and an output of each of the plurality of frequency filters;
The inverter frequency calculation circuit calculates the inverter frequency based on the selected output.
Load drive system. The selection circuit selects a selected output that is equal to or greater than a predetermined value and has the highest frequency band from among the outputs of the frequency filter that are assigned to different pass bands.
The load driving system according to claim 1 . The frequency filter has an option of outputting the current detection value inputted including the DC component as it is.
The load driving system according to claim 1 . The inverter frequency calculation circuit includes a current phase calculation unit that calculates a current phase based on the selected output, and a PLL unit that receives the current phase as an input.
The load driving system according to claim 1 . the PLL unit includes a phase overflow detection unit that detects that a phase difference between the current phase and a PLL output phase by the PLL unit has overflowed ±π [rad], an overflow frequency calculation unit that counts the number of overflows, and a phase difference correction unit that adds a product of the number of overflows and 2π [rad] to the phase difference,
5. A load driving system according to claim 4. A railway vehicle comprising a motor driven by the load drive system according to any one of claims 1 to 5 and wheels connected to the motor. a wheel wear amount detection unit that detects the amount of wear of the wheels from a variation in the inverter frequency corresponding to each of the motors;
7. The railway vehicle according to claim 6, comprising: In a load driving method in which an inverter controlled by an inverter control circuit drives a load,
The frequency filter divides the current detection value of the current flowing through the load into different pass bands and outputs the same;
The inverter control circuit includes:
The terminals of the load are shorted,
causing a selection circuit to select one of the outputs of the frequency filter as a selected output based on the outputs corresponding to each of the pass bands;
The inverter frequency of the inverter calculated by an inverter frequency calculation circuit based on the selected output is set as the drive frequency of the load.
Load driving method. the selection circuit selects, as a selected output, an output of a frequency filter having a highest band among outputs of the frequency filters that are equal to or greater than a predetermined value;
The load driving method according to claim 8. The frequency filter is substantially shorted, and the input current detection value including the DC component is output as it is.
The load driving method according to claim 8. The inverter frequency calculation circuit causes a phase calculation unit to calculate a current phase based on the selected output, and inputs the current phase to a PLL unit.
The load driving method according to claim 8. The PLL unit executes the following process:
A phase overflow detection unit detects that a phase difference between the current phase and a PLL output phase by the PLL unit has overflowed ±π [rad],
causing an overflow count calculation unit to count the number of overflows;
A product of the number of overflows and 2π [rad] is added to the phase difference by a phase difference correction unit.
The load driving method according to claim 11. A method for operating a railway vehicle by driving a motor connected to a wheel using the load driving method described in any one of claims 8 to 12. Detecting the amount of wear of the wheels from the variations between the wheels connected to each of the plurality of motors and the inverter frequencies corresponding to each of the motors.
The method for operating a railway vehicle according to claim 13.

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