JP7500636B2 - Gaming Machines - Google Patents

Description

The present invention relates to a gaming machine capable of playing games.

A gaming machine has been proposed that executes a warning display or stops control in response to the temperature detected by a temperature detection signal periodically sent from a temperature detection sensor (for example, Patent Document 1).

JP 2011-206469 A

The gaming machine described in Patent Document 1 executes control and temperature-related processes as a single process, which increases the processing load and can lead to control malfunctions.

This invention was made in consideration of the above situation, and aims to provide a gaming machine that can be appropriately controlled.

In order to achieve the above object, the gaming machine according to the present invention is a gaming machine capable of playing a game (e.g., a pachinko gaming machine 1, etc.), and is equipped with a processing means capable of executing processing according to a program (e.g., a CPU 120A of a performance control microcomputer 100A, etc.), a detection means capable of detecting temperature (e.g., a processor temperature sensor 156, a board temperature sensor 160, etc.), and a storage means capable of storing information related to temperature (e.g., an internal RAM 122A provided with a temperature-related data storage area 05AK100, etc.), and the processing means performs a first process related to the control of the performance (e.g., a timer interrupt process for performance control, etc.), The first process can be executed in one cycle (e.g., 1 ms (millisecond)), a second process (e.g., a temperature detection timer interrupt process) capable of storing information regarding the temperature detected by the detection means in the storage means can be executed in a second cycle (e.g., 1 s (second)), the first process has a higher priority than the second process (e.g., the processing priority shown in FIG. 12-2 (B)), the first cycle is shorter than the second cycle, and the first process can monitor the information regarding the temperature stored in the storage means by the second process (e.g., the temperature monitoring process of step 05AKS31 can be executed).
With this configuration, the processing load can be reduced and appropriate control can be performed.

FIG. 2 is a front view of the pachinko game machine. FIG. 2 is a configuration diagram showing various control boards, etc. FIG. 13 is a diagram showing an example of a random number for gaming. 13 is a flowchart showing a main process for game control. 13 is a flowchart showing an example of a timer interrupt process for game control. 13 is a flowchart showing an example of a special symbol process. A diagram showing an example of the configuration of a special pattern process processing jump table. 13 is a flowchart showing a main process for performance control. 13 is a flowchart showing an example of a performance control process. FIG. 2 is a diagram showing an example of the configuration of a microcomputer for game control. FIG. 13 is a diagram illustrating an example of an address map. 11A and 11B are diagrams showing main setting examples of addresses included in a function setting register area; 11A and 11B are diagrams illustrating examples of main setting of addresses included in a function control register area. A diagram for explaining an example of settings for random numbers for gaming. FIG. 11 is a diagram for explaining a random number update period. 13 is a flowchart illustrating an example of a power supply start response process. FIG. 13 is a diagram illustrating an example of a configuration of a function setting register stored value table. FIG. 13 is a diagram illustrating an example of the configuration of an RWM access protection register. 10 is a flowchart illustrating an example of a power-off process. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart illustrating an example of a random number update process. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart illustrating an example of an initial value changing random number updating process. 13 is a flowchart showing an example of an initial value determination random number update process. 13 is a flowchart showing an example of a start port switch passing process. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart showing an example of normal special symbol processing. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart showing an example of a special pattern determination process. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart showing an example of a special symbol information setting process. A flowchart showing an example of a jackpot information data selection process. FIG. 13 is a diagram for explaining an example of use of a data configuration. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart showing an example of a variation pattern setting process. 11 is a flowchart showing an example of a winning time fluctuation pattern type table selection process. 11 is a flowchart showing an example of a process for selecting a fluctuation pattern type table when a loss occurs. A diagram for explaining an example of the configuration of a fluctuation pattern type allocation table. 13 is a diagram for explaining an example of the configuration of a fluctuation pattern allocation table. FIG. 13 is a diagram for explaining an example of the configuration of a fluctuation pattern allocation table. FIG. 13 is a diagram for explaining an example of the configuration of a fluctuation pattern allocation table. FIG. 13 is a flowchart showing an example of normal symbol process processing. FIG. 13 is a diagram for explaining an example of use of a data configuration. 13 is a flowchart showing an example of a gate switch passing process. 13 is a flowchart showing an example of normal processing of normal symbols. FIG. 13 is a diagram for explaining an example of use of a data configuration. FIG. 2 is a diagram showing memory areas of a ROM. FIG. 13 is a diagram illustrating an example of setting unused data. FIG. 13 is a diagram illustrating an example of the configuration of a RST command. FIG. 2 is a diagram illustrating an example of a description of a program module. FIG. 11 illustrates an example of how table data is stored. FIG. 13 is a diagram illustrating an example of setting zero data. FIG. 11 illustrates an example of how table data is stored. FIG. 13 is a diagram illustrating an example of an output of a dump list. A diagram showing an example configuration of a performance control board and a backup memory board. 13 is a flowchart showing a main process for controlling performance. FIG. 4 is a diagram illustrating an example of the configuration of a temperature-related data storage area. 13 is a flowchart showing an example of a temperature detection timer interrupt process. 10 is a flowchart showing an example of a determination process at the time of temperature detection. 10 is a flowchart illustrating an example of a temperature error determination process. 13 is a flowchart showing an example of a timer interrupt process for performance control. 13 is a flowchart illustrating an example of a temperature monitoring process. 13 is a flowchart illustrating an example of a command analysis process. 10 is a flowchart illustrating an example of a temperature display control process. FIG. 11 is a sequence diagram showing a first processing example for managing data and information relating to temperature. FIG. 11 is a sequence diagram showing a second processing example for managing data and information relating to temperature. FIG. 11 illustrates an example of setting data to be backed up. 13A and 13B are diagrams illustrating examples of a temperature error notification screen and a temperature display screen.

(Basic explanation)
First, the basic configuration and control of the pachinko gaming machine 1 will be described.

(Configuration of Pachinko Game Machine 1, etc.)
1 is a front view of a pachinko game machine 1, showing the layout of the main components. The pachinko game machine (game machine) 1 is broadly composed of a game board (gauge board) 2 that constitutes the game board surface, and a game machine frame (base frame) 3 that supports and fixes the game board 2. A game area is formed on the game board 2, and game balls as game media are shot into this game area by a predetermined ball shooting device.

A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions on the game board 2. In the example shown in FIG. 1, they are provided on the right side of the game area. The first special symbol display device 4A and the second special symbol display device 4B can each variably display special symbols as multiple types of special identification information. Special symbols are also called "special symbols." The variable display of special symbols is also called "special symbol game." Both the first special symbol display device 4A and the second special symbol display device 4B are configured using 7-segment LEDs or the like. The special symbols are represented by numbers showing "0" to "9," symbols showing "-," or any other lighting pattern. The special symbols may include a pattern in which all LEDs are turned off.

The "variable display" of special symbols means, for example, a display of multiple types of special symbols that can be changed. For other symbols such as performance symbols, small symbols, and normal symbols, "variable display" also means a display of multiple types of symbols that can be changed. Performance symbols are also called decorative symbols or ornamental symbols. Variable display is also called variable display, or simply "change". Changes include updating multiple symbols, scrolling multiple symbols, and deforming, enlarging, or reducing one or more symbols. Changes may include a mode of displaying a symbol in a flashing manner. In the variable display of special symbols or normal symbols, multiple types of special symbols or normal symbols are displayed in a variable manner. In the variable display of performance symbols, multiple types of performance symbols are scrolled or updated, or one or more performance symbols are deformed, enlarged, or reduced. In the variable display of any symbol, a predetermined symbol is displayed as a stop display as a display result at the end. Stop display is also called derived display, or simply derived. The symbol that is finally stopped and displayed in a variable display is also called the final stop symbol or the final symbol. The final stop symbol in a special symbol game is also called the final special symbol. The display result of the variable display includes the display result of the special symbol, and is also called the variable display result. The display result of the special symbol is also called the special symbol display result. The execution time of the variable display includes the special symbol change time, which is the change time of the special symbol, and is also called the variable display time. The special symbol change time can be set to a different time corresponding to the change pattern of the special symbol, of which multiple patterns are prepared in advance.

The special pattern variably displayed on the first special pattern display device 4A is also called the "first special pattern." The special pattern variably displayed on the second special pattern display device 4B is also called the "second special pattern." A special pattern game using the first special pattern is also called the "first special pattern game." A special pattern game using the second special pattern is also called the "second special pattern game." There may be only one type of special pattern display device that variably displays special patterns.

A normal symbol display 20 is provided at a predetermined position on the game board 2. In the example shown in FIG. 1, it is provided on the left side of the game area. The normal symbol display 20 can perform variable display of normal symbols as multiple types of normal identification information different from special symbols. The normal symbols are also called "normal symbols". The variable display of normal symbols is also called "normal symbol game". The normal symbol display 20 is configured using 7-segment LEDs, etc. The normal symbols are represented by numbers indicating "0" to "9", symbols indicating "-", and other arbitrary lighting patterns. The normal symbols may include a pattern in which some or all of the multiple LEDs are lit, or a pattern in which all of the multiple LEDs are turned off. The final stop symbol in the normal symbol game is also called a confirmed normal symbol. The display result of the normal symbol is also called a normal symbol display result. The execution time during which the normal symbol is variably displayed in the normal symbol game is also called a normal symbol fluctuation time. The normal symbol variation time can be set to a different time depending on the normal symbol variation pattern, of which multiple patterns are prepared in advance.

An image display device 5 is provided near the center of the play area on the game board 2. The image display device 5 may be configured using a mechanism capable of forming any image, such as an LCD (liquid crystal display), an organic EL (electro luminescence), a dot matrix LED, a projector and screen, a stereoscopic image projection device, or any other device. The image display device 5 is capable of displaying various types of performance images. Furthermore, the image display device 5 is not limited to performance images, and can display any control-related image, such as an inspection image or a setting image.

For example, on the screen of the image display device 5, the variable display of the performance pattern can be executed in synchronization with the first special pattern game or the second special pattern game. The performance pattern is a display pattern showing numbers or the like, and is a plurality of types of decorative identification information different from the special pattern and the normal pattern. On the screen of the image display device 5 shown in FIG. 1, the performance pattern display areas 5L, 5C, and 5R of "left", "middle", and "right" are provided, and the performance pattern is displayed in a variable manner, for example, by scrolling or updating the performance pattern in the vertical direction in synchronization with the first special pattern game or the second special pattern game. The synchronization of the variable display may be a common timing for different types of patterns, between the timing when the pattern starts to change and the timing when the change ends and the pattern is finally stopped and displayed. The final stop pattern in the variable display of the performance pattern is also called the determined performance pattern, determined decoration pattern, or determined decoration pattern. Since the variable display of the performance pattern is synchronized with the first special pattern game or the second special pattern game, the variable display time of the performance pattern is the same as the special pattern change time.

The screen of the image display device 5 may be provided with a display area capable of displaying performance images corresponding to the pending display and the active display. The pending display is a display corresponding to a variable display that has not yet been executed and is on hold. The active display is a display corresponding to a variable display that is being executed. The pending display and the active display are also collectively referred to as a variable display-compatible display corresponding to the variable display. A display area that performs a pending display is also referred to as a pending display area. A display area that performs an active display is also referred to as an active display area. The number of variable displays that are on hold is also referred to as the number of pending memories. The number of pending memories that corresponds to the first special game is also referred to as the first number of pending memories. The number of pending memories that corresponds to the second special game is also referred to as the second number of pending memories. The sum of the first number of pending memories and the second number of pending memories is also referred to as the total number of pending memories.

A first reserve indicator 25A and a second reserve indicator 25B, each of which includes a plurality of LEDs, are provided above the first special symbol display device 4A and the second special symbol display device 4B shown in FIG. 1. The first reserve indicator 25A displays the first reserve memory number by the number of lit LEDs. The second reserve indicator 25B displays the second reserve memory number by the number of lit LEDs. A regular pattern reserve indicator 25C, each of which includes a plurality of LEDs, is provided above the regular pattern display device 20 shown in FIG. 1. The regular pattern reserve indicator 25C displays the regular pattern reserve number by the number of lit LEDs. The regular pattern reserve number is the reserve memory number corresponding to the regular pattern game.

Below the image display device 5, there are provided a winning ball device 6A and a variable winning ball device 6B. The winning ball device 6A forms a first start winning opening that is always kept in a constant open state so that game balls can enter, for example, by a predetermined ball receiving member. The variable winning ball device 6B forms a second start winning opening that can be changed between a closed state and an open state by a normal electric role solenoid 81 shown in FIG. 2 as a normal electric role. The variable winning ball device 6B is equipped with, for example, an electric tulip-type role having a pair of movable wings, and when the normal electric role solenoid 81 is in the off state, the movable wings are in a vertical position, so that the second start winning opening is in a closed state in which game balls cannot enter, or in a normal open state in which game balls have difficulty entering the second start winning opening. When the normal electric device solenoid 81 is on, the variable winning ball device 6B has a movable wing piece in a tilted position, so that the second start winning port is in an open state where game balls can enter, or in an expanded open state where game balls can easily enter the second start winning port. The open state where game balls can enter the second start winning port, or the expanded open state where game balls can easily enter, is also called the first variable state. The closed state where game balls cannot enter the second start winning port, or the normal open state where game balls cannot easily enter, is also called the second variable state. Note that the variable winning ball device 6B is not limited to one equipped with an electric tulip-type device, as long as it can be changed between the first and second variable states.

The entry of a game ball into the first start winning hole formed by the winning ball device 6A is also called the first start winning. The entry of a game ball into the second start winning hole formed by the variable winning ball device 6B is also called the second start winning. The game ball that entered the first start winning hole is detected by the first start winning hole switch 22A shown in FIG. 2. The game ball that entered the second start winning hole is detected by the second start winning hole switch 22B shown in FIG. 2. Based on the occurrence of the first start winning, a predetermined number of prize balls, for example, three balls, are paid out, and the first reserved memory number can be updated so that it is incremented by one. However, if the first reserved memory number has reached the upper limit, the first reserved memory number is not updated even if the first start winning occurs. In response to the first reserved memory number being incremented by one, the first start condition is established, and the first special pattern game in which the special pattern is variably displayed by the first special pattern display device 4A becomes executable. When the second start winning occurs, a predetermined number of prize balls, for example, three balls, are paid out, and the second reserved memory count can be updated to increment by 1. However, if the second reserved memory count has reached its upper limit, the second reserved memory count is not updated even if the second start winning occurs. When the second reserved memory count is incremented by 1, the second start condition is met, and the second special symbol game in which the special symbol is variably displayed by the second special symbol display device 4B becomes executable.

At predetermined positions on the game board 2, general winning openings 10 are provided which are always kept in a constant open state by a predetermined ball receiving member. In the example shown in FIG. 1, general winning openings 10 are provided in two locations on the lower left of the game area. When a game ball enters one of the general winning openings 10, a predetermined number of prize balls, for example 10, are paid out.

In the game area formed by the game board 2, a first path and a second path are provided as flow paths for game balls to flow down. The first path is mainly provided in the area to the left of the image display device 5 when viewed from the front. The second path is mainly provided in the area to the right of the image display device 5 when viewed from the front. The left area of the image display device 5 is also called the left game area or the left game area. The right area of the image display device 5 is also called the right game area or the right game area. The left game area and the right game area may be divided, for example, by the end face of the image display device 5 in the game area or the arrangement of the game nails. Firing a game ball toward the left game area to make it flow down the first path is also called a left hit. Firing a game ball toward the right game area to make it flow down the second path is also called a right hit. The first path is also called a left hit path. The second path is also called a right hit path. The first path and the second path may be separate paths, or may be paths that are partially shared.

In response to the operation of a ball operating handle provided on the ball launching device, a game ball is launched from the ball launching device and launched into the game area. When a game ball launched into the game area is guided to the left game area and flows down the first path, it is guided, for example, along the arrangement of game nails, making it impossible or difficult to guide to the second path in the right game area. When a game ball launched into the game area is guided to the right game area and flows down the second path, it is guided, for example, along the arrangement of game nails, making it impossible or difficult to guide to the first path in the left game area.

The winning ball device 6A is provided on a first path in the left-side play area, allowing game balls flowing down the first path to enter. The variable winning ball device 6B is provided on a second path in the right-side play area, allowing game balls flowing down the second path to enter. The variable winning ball device 6B may also allow game balls flowing down the first path in the left-side play area to enter. The variable winning ball device 6B may be positioned so that game balls flowing down the second path in the right-side play area have an easier time entering than game balls flowing down the first path in the left-side play area.

The second path in the right game area is provided with a passing gate 41 and a special variable winning ball device 50. The passing gate 41 forms a passing area through which game balls can pass. Game balls that pass through the passing gate 41 are detected by the gate switch 21 shown in FIG. 2. Based on the game ball passing through the passing gate 41, the normal reserved memory number can be added and updated, and variable display of normal symbols by the normal symbol display device 20 can be executed as a normal symbol game. The passing gate 41 can be configured as a normal symbol operation port through which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol operation port switch that can detect game balls that have entered the normal symbol operation port.

The special variable winning ball device 50 is a special electric device that forms a large winning port that can be changed between a closed state and an open state by a large winning port solenoid 82. The upper part of the special variable winning ball device 50 is formed with a guide passage with a passage width in the front and rear direction that allows the game ball to pass through. This guide path slopes downward from the right side to the left side, and walls are provided on the front and back sides of the extended passage. In the center of the guide passage, a role entrance that serves as the large winning port is formed. In the special variable winning ball device 50, a movable member 52 that can move in the front and rear directions is provided as a large winning port opening and closing member at a position where the large winning port can be opened and closed. In the special variable winning ball device 50, a fixed member 53 that forms a fixed passage is provided in the part of the guide passage where the large winning port is not formed.

The movable member 52 is driven by the large prize opening solenoid 82 and can move forward and backward to open and close the role entrance which becomes the large prize opening. In the special variable prize ball device 50, the game ball that enters the inside from the large prize opening is detected by the count switch 23. Inside the special variable prize ball device 50, a V prize area 51 which is a specific area is provided as a prize area through which the game ball can pass. In addition, inside the special variable prize ball device 50, a normal area different from the V prize area 51 is provided. At the top of the V prize area 51, a plate-shaped distribution member which can switch the V prize area 51 between an open state and a closed state is provided as a V prize opening opening and closing member. The distribution member is driven by the specific area solenoid 83 and can move forward and backward to open and close the V prize area 51. When the V prize area 51 is in an open state, the game ball can pass through it, and when it is in a closed state, the game ball cannot pass through it. Game balls that pass through the V winning area 51 are detected by the specific area switch 24. Game balls that do not pass through the V winning area 51 pass through the normal area. Game balls that pass through the V winning area 51 and game balls that do not pass through the V winning area 51 but pass through the normal area are both detected by the discharge switch 26 and then discharged to the outside of the special variable winning ball device 50.

In addition to the above features, the surface of the game board 2 is provided with a windmill that changes the direction and speed of the game balls, and numerous obstacle nails. At the bottom of the game area, an outlet is provided for game balls that do not enter any of the winning holes. Speakers 8L, 8R for playing and outputting sound effects and the like are provided at the upper left and right positions of the game machine frame 3, and game effect lamps 9 for lighting up the game effects are provided around the periphery of the game area. The game effect lamps 9 are composed of LEDs. A movable body 32 that operates according to the effects is provided at a predetermined position on the game board 2.

At the lower right position of the gaming machine frame 3, there is provided a ball operation handle that is operated by a player or the like to launch gaming balls toward the playing area using the ball launching device. The ball operation handle is also called an operation knob. At a specified position of the gaming machine frame 3 below the playing area, there is provided a ball supply tray that holds gaming balls paid out as prize balls or gaming balls lent out by a specified ball lending machine so that they can be supplied to the ball launching device. The ball supply tray is also called the upper tray. Below the upper tray, there is provided a prize ball storage tray where prize balls paid out when the upper tray is full flow down and are stored. The prize ball storage tray is also called the lower tray.

A stick controller 31A and a push button 31B are provided at predetermined positions on the gaming machine frame 3 below the gaming area. The stick controller 31A can be held by the player and tilted, and is provided with a trigger button that the player can push and pull. Operation of the stick controller 31A is detected by a controller sensor unit 35A shown in FIG. 2. The push button 31B can be pressed by the player. Operation of the push button 31B is detected by a push sensor 35B shown in FIG. 2. In the pachinko gaming machine 1, the stick controller 31A and the push button 31B are used as detection means for detecting the player's operation and other actions, but other detection means may also be used.

(Outline of game progress)
A game ball is launched toward the game area by a player rotating a ball-hitting operation handle provided on the pachinko game machine 1. When the game ball passes through the passing gate 41, a normal game is started by the normal symbol display device 20. In addition, when the game ball passes through the passing gate 41 during the period during which the previous normal game is being executed, the normal game based on the passage cannot be executed immediately, so the normal game based on the passage is reserved up to a predetermined upper limit number, for example, "4". In the normal game, when a specific normal symbol, such as a normal winning symbol, is stopped and displayed as a confirmed normal symbol, the display result of the normal symbol is "normal winning". On the other hand, when a normal symbol other than the normal winning symbol, such as a normal losing symbol, is stopped and displayed as a confirmed normal symbol, the display result of the normal symbol is "normal losing". In the case of "normal winning", an opening control is performed to make the variable winning ball device 6B in an open state or an expanded opening state for a predetermined period. At this time, the second starting winning port is in an open state or an expanded open state.

When a game ball passes through and enters the first start winning hole formed in the winning ball device 6A, the first special game can be started by the first special pattern display device 4A. When a game ball passes through and enters the second start winning hole formed in the variable winning ball device 6B, the second special game can be started by the second special pattern display device 4B. Note that, during the period when the special pattern game is being executed or during the period when the game ball enters the start winning hole and a start winning occurs, the special pattern game based on the start winning cannot be executed immediately, so the special pattern game based on the start winning is reserved up to a predetermined upper limit number, for example, "4". In the special pattern game, when a specific special pattern such as a jackpot pattern is stopped and displayed as a confirmed special pattern, the display result of the special pattern becomes "jackpot". In contrast, when a predetermined special pattern, such as a small win pattern, that is different from a big win pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern is "small win". Also, when a special pattern, such as a miss pattern, that is different from a big win pattern or a small win pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern is "miss". Furthermore, when a special pattern, such as a time-saving pattern, that is different from a big win pattern, a small win pattern, or a miss pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern may be "time-saving". The special pattern may not include a time-saving pattern. In other words, the display result of the special pattern may not include "time-saving".

In the special game, after the display result of the special pattern becomes "jackpot", the game is controlled to a jackpot game state as an advantageous state for the player. In the jackpot game state, the jackpot entry port formed in the special variable winning ball device 50 can be opened in a predetermined manner. The open state at this time continues until the timing of the passage of a predetermined period, such as 29 seconds or 1.8 seconds, or the timing when the number of game balls that have entered the jackpot entry port reaches a predetermined number, whichever comes first. The predetermined period during which the jackpot entry port can be controlled to be in an open state is the upper limit period during which the jackpot entry port can be opened in one round, and is also called the open upper limit period. One cycle in which the jackpot entry port is in an open state in the jackpot game state is called a round or round game. In the jackpot game state, such rounds can be repeatedly executed until a predetermined upper limit number of times is reached, such as 15 times or 2 times. In the jackpot game state, the player can obtain prize balls by entering the game ball into the jackpot entry port. Therefore, the jackpot gaming state is an advantageous state for the player. The more rounds in the jackpot gaming state, and the longer the upper limit open period, the more advantageous it is for the player.

When the display result of the special pattern is a "jackpot", it includes multiple jackpot types. For example, the opening mode of the jackpot entry port, such as the number of rounds and the maximum opening period, and the game state after the end of the jackpot game state, such as the normal state, time-saving state, or probability change state, are set to multiple different types, and a jackpot type is specified corresponding to each setting. The multiple jackpot types may include some or all of the jackpot types that allow many prize balls to be obtained, jackpot types that allow few prize balls to be obtained, or jackpot types that allow almost no prize balls to be obtained, or may include jackpot types with the same number of prize balls that can be obtained. Controlling to a jackpot game state based on the display result of the special pattern being a "jackpot" is also called a pattern jackpot, a jackpot with a special pattern, a variable display jackpot, or a direct hit jackpot.

In the special game, after the display result of the special pattern becomes "small hit", the game is controlled to a small hit game state. In the small hit game state, the large winning opening formed in the special variable winning ball device 50 can be opened in a predetermined opening state. For example, in the small hit game state, the large winning opening may be opened in the same opening state as the large winning game state in some large hit types. The large winning opening may be opened in the same opening state by having the same number of openings and opening period. Alternatively, in the small hit game state, the large winning opening may be opened in an opening state different from the large hit game state. As with the large hit type, multiple small hit types may be included even when the display result of the special pattern becomes "small hit". The large hit type and the small hit type are also collectively referred to as the hit type. The operation of opening and closing the large winning opening in the small hit game state is also called the starting operation. When the special variable winning ball device 50 is in a small winning state, the special variable winning ball device 50's role entrance, which is the large winning opening, is opened, and when the game ball passes through the V winning area 51 and is detected by the specific area switch 24, the conditions for a big win are met, and control to the big win game state is possible. When the game ball passes through the V winning area 51 in a small winning game state, control to the big win game state based on the occurrence of a V winning is also called a small winning via big win.

After the jackpot game state ends, the game state can be controlled to a time-saving state or a probability-changing state in accordance with the jackpot type. In addition, in the special game, after the display result of the special pattern becomes "time-saving", the game state is not controlled to the jackpot game state but is controlled to a time-saving state. The time-saving state is a game state in which the second special pattern game by the second special pattern display device 4B is more likely to be executed than in the normal state. A game state in which the second special pattern game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to pass through and enter the second start winning hole than in the normal state. The control of whether or not the game ball is more likely to pass through the second start winning hole is also called base control. The base control in the normal state is also called normal base control or low base control. The base control in the time-saving state includes high base control. In addition to the high base control, the time-saving state may include medium base control. The medium base control is a base control that makes it easier for the game ball to pass through the second start winning port than the low base control, but makes it harder for the game ball to pass through the second start winning port than the high base control. The game state in which the medium base control is performed is also called the medium base state. The game state in which the high base control is performed is also called the high base state. The high base control is also called the high opening control.

In the normal state, medium base state, and high base state, it is possible for the time-saving pattern to be displayed as a stopped result of the display of the special pattern. However, in the medium base state and high base state, even if the time-saving pattern is displayed as a stopped result of the display of the special pattern, base control based on the time-saving pattern is not performed, and new control to transition to the medium base state or high base state is not initiated. In the time-saving state, it is possible to perform time-saving control that shortens the average variable display time more than in the normal state. For this reason, the time-saving state is also called the time-shortening state.

The time-saving state is a state in which the efficiency of fluctuation of special symbols, especially the second special symbol, is improved, so it is included in the special states that are advantageous to players and different from the jackpot game state. When the game state is the probability variable state, in addition to the time-saving control, probability variable control is possible in which the probability of the display result of the special symbol being a "jackpot" is higher than in the normal state. As a result, the probability variable state is also called a probability variable state. The probability variable state is a state in which the efficiency of fluctuation of the special symbol is improved and it is easy to become a "jackpot", so it is included in the special states that are advantageous to players and different from the jackpot game state. The time-saving state and probability variable state continue until one of the predetermined end conditions is met first, such as the execution of a specified number of special symbol games or the control being made to the next jackpot game state. The end condition is that the specified number of special symbol games have been executed, also called the number-cut. The number-cut time-saving state is also called the number-cut time-cut. The number-cut probability variable state is also called the number-cut probability variable.

The normal game state is a game state that is not included in advantageous states such as a big win game state that is advantageous to the player, predetermined states such as a small win game state, or special states such as a time-saving state or a probability change state. The normal state is a game state in which the probability that the display result in a normal game will be a "normal win" and the probability that the display result in a special game will be a "jackpot" are controlled to be the same as the initial setting state of the pachinko game machine 1. The initial setting state of the pachinko game machine 1 is the control state after the initial setting process is performed without performing the specified recovery process after power is turned on, such as when a system reset is performed.

The state in which the probability variable control is being executed is also called a high probability state, and the state in which the probability variable control is not being executed is also called a low probability state. The state in which the time-saving control is being executed is also called a high base state, and the state in which the time-saving control is not being executed is also called a low base state. Combining these, the time-saving state is also called a low probability high base state, the probability variable state is a high probability high base state, and the normal state is a low probability low base state. The high probability state and low base state are also called a high probability low base state. Note that the pachinko gaming machine 1 may not include a probability variable state as a gaming state.

After the small win game state ends, there are cases where the game state is controlled to a big win game state based on the occurrence of a V win, and cases where a V win does not occur and the game state before the small win game state remains unchanged. However, when the display result of the special game becomes a "small win" and a specified number of special games are played in the number cutoff, the control of the time-saving state and the probability of winning state ends and the game returns to the normal state. Note that the pachinko game machine 1 may not include a small win game state as a game state. In other words, the display result of the special pattern may not include a "small win".

When a time-saving condition based on the number of times the variable display is executed is established, the game state may be controlled to a time-saving state. Such a time-saving state is also called a rescue time-saving state. The time-saving condition may be a condition that can be established when, after the power is turned on to the pachinko game machine 1, after a jackpot occurs, or after the display result of the special game becomes "time-saving," control to a new jackpot game state or time-saving state is not performed even if a specific number of variable displays are executed.

(Progression of the performance, etc.)
In the pachinko game machine 1, various effects can be executed in accordance with the progress of the game. These effects include effects that notify the progress of the game and effects that liven up the game. These effects include displaying various effect images on the image display device 5, outputting sound effects from the speakers 8L and 8R, turning on the game effect lamp 9, operating the movable body 32, vibrating the stick controller 31A or the push button 31B, or a combination of some or all of these, and may be executed using any effect device.

The effects that can be executed in accordance with the progress of the game include variable display of the effect patterns. In response to the start of the first special game or the second special game, the variable display of the effect patterns is started in the effect pattern display areas 5L, 5C, and 5R of "left", "middle", and "right" provided on the screen of the image display device 5. When the determined special pattern that is the display result in the first special game or the second special game is stopped and displayed, the determined effect pattern that is the display result is stopped and displayed in the variable display of the effect patterns. The determined effect pattern is composed of a combination of three effect patterns corresponding to the effect pattern display areas 5L, 5C, and 5R of "left", "middle", and "right". During the period from the start to the end of the variable display of the effect patterns, the display mode in the variable display of the effect patterns may become a reach mode. The reach mode is a mode in which the effect patterns that have stopped on the screen of the image display device 5 constitute part of a jackpot combination and the fluctuation of the effect patterns that have not yet stopped continues. When the display pattern of the variable display of the performance symbols becomes a reach pattern, it is said that a reach has been achieved.

When the variable display of the performance pattern becomes a reach state, a reach performance can be executed. The pachinko gaming machine 1 can execute multiple types of reach performance so that the rate at which the display result of the variable display becomes a "jackpot" varies when the performance state differs. The rate of a "jackpot" corresponding to the performance state is also called the jackpot reliability or jackpot expectation rate. Reach performance includes, for example, a normal reach and a super reach, which has a higher jackpot reliability than a normal reach. In addition, it may include a short reach and a long reach, which has a longer execution time than a short reach, corresponding to the execution time of the reach performance.

When the display result of the special pattern is "jackpot", a fixed performance pattern that is a predetermined jackpot combination is displayed as a display result of the performance pattern on the screen of the image display device 5. As an example, the same performance pattern, such as a performance pattern showing the number "7", is displayed stopped on a predetermined effective line in the performance pattern display areas 5L, 5C, and 5R of "left", "middle", and "right". In the case of a "probability jackpot" that is controlled to a probability jackpot state after the end of the jackpot game state, odd-numbered performance patterns, such as a performance pattern showing the number "7", may be displayed stopped. In the case of a "non-probability jackpot" that is not controlled to a probability jackpot state after the end of the jackpot game state, even-numbered performance patterns, such as a performance pattern showing the number "6", may be displayed stopped. A "non-probability jackpot" is also called a "normal jackpot". In this case, the odd-numbered performance patterns are also called probability jackpot patterns. The even-numbered performance patterns are also called non-probability jackpot patterns or normal patterns. After a non-variable symbol is in a reach state, an advancement effect may be executed that ultimately results in a "variable jackpot."

When the display result of the special pattern is a "small win", a confirmed performance pattern that is a predetermined small win combination is displayed as a stopped result of the performance pattern on the screen of the image display device 5. As an example, the same performance pattern, such as a performance pattern showing a number other than "7", may be displayed stopped on a predetermined valid line in the "left", "middle", and "right" performance pattern display areas 5L, 5C, and 5R. A common confirmed performance pattern may be displayed when the display result of the special pattern is a "big win" and when it is a "small win".

When the display result of the special pattern is a "miss", the display result may be displayed as a stop without the variable display of the performance pattern becoming a reach state. In this case, the fixed performance pattern of the non-reach combination is displayed as a stop as the display result of the performance pattern. A display result in which the fixed performance pattern of the non-reach combination is displayed as a stop without becoming a reach state is also called a non-reach miss. When the display result of the special pattern is a "miss", the variable display of the performance pattern may become a reach state, and the display result may be displayed as a stop after the reach performance is executed. In this case, the display result of the performance pattern may be displayed as a fixed performance pattern of the reach combination that is not a big hit combination or a small hit combination. A display result in which the fixed performance pattern of the reach combination is displayed as a stop after becoming a reach state is also called a reach miss.

The effects that the pachinko gaming machine 1 can execute include variable display compatible displays such as reserved displays and active displays. In addition, for example, a preview effect that predicts the jackpot reliability can be executed while the performance pattern is variable displayed. The preview effect may include a variable preview effect that predicts the jackpot reliability corresponding to the variable display currently being executed, and a look-ahead preview effect that predicts the jackpot reliability corresponding to the variable display before execution whose execution is on hold. The look-ahead preview effect may be capable of executing a change effect that changes the display mode of a variable display compatible display such as reserved displays and active displays to a mode different from normal.

On the screen of the image display device 5, it may be possible to temporarily stop the performance symbols during the variable display of the performance symbols, and then resume the variable display, thereby executing a pseudo consecutive performance in which one variable display appears as multiple variable displays. The pseudo consecutive performance may be set so that the reliability of a jackpot is higher when the number of times the variable display is resumed after the performance symbols are temporarily stopped is large than when the number of times the number is small. In the variable display of the performance symbols, there may be cases where the pseudo consecutive performance is executed before the reach state is reached, and cases where the pseudo consecutive performance is executed after the reach state is reached. In addition, in the variable display of the performance symbols, it may be possible to execute the pseudo consecutive performance at multiple times.

During control of the jackpot gaming state, a jackpot performance can be executed to notify the jackpot gaming state. The jackpot performance may include a performance to notify the number of rounds and an advancement performance that suggests or notifies the player that the advantage of the jackpot gaming state is improving. During control of the small jackpot gaming state, a small jackpot performance can be executed to notify the player of a small jackpot gaming state. By executing a common performance during control of the jackpot gaming state and during control of the small jackpot gaming state, it may be possible to make it impossible or difficult for the player to recognize whether the current gaming state is a jackpot gaming state or a small jackpot gaming state.

In a non-playing state where a special game or the like is not being executed and no game is progressing, a demonstration effect image can be displayed on the screen of the image display device 5. A demonstration effect image is also called a demo image. The display of a demo image is also called a demo display. The effect by the demo display is also called a customer waiting demo effect.

(Board configuration)
2, the pachinko machine 1 is equipped with a main board 11, a performance control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17, etc. In addition, various boards such as a payout control board, an information terminal board, and a launch control board are arranged on the back of the pachinko machine 1.

The main board 11 is the main control board and has the function of controlling the progress of the game in the pachinko game machine 1. The progress of the game includes the execution of various games and transitions of game states, such as the execution of special games with reserved management, the execution of regular games with reserved management, big win game state, small win game state, time-saving state, and probability change state. The main board 11 is equipped with a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

The game control microcomputer 100 provided on the main board 11 is, for example, a one-chip microcomputer, and can be configured with a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, a random number circuit 104, and an I/O (Input/Output port) 105. The ROM 101, the RAM 102, and a part or all of the random number circuit 104 may be configured to be external to the game control microcomputer 100, or may be configured to be built into the game control microcomputer 100. The switch circuit 110 takes in detection signals from various switches for game ball detection and transmits them to the game control microcomputer 100. The various switches for game ball detection include, for example, a gate switch 21, start port switches such as a first start port switch 22A and a second start port switch 22B, a count switch 23, a specific area switch 24, and an outlet switch 26. The detection signal indicates that a game ball has passed or entered and a switch has been turned on. The transmission of the detection signal indicates that the game ball has passed or entered. The solenoid circuit 111 can supply a solenoid drive signal from the game control microcomputer 100 to the normal electric role solenoid 81, the big prize opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

The ROM 101 provided in the game control microcomputer 100 is a non-volatile storage device that stores computer programs and data used for game control. The data stored in the ROM 101 includes table data constituting tables used for variation patterns, performance control commands, and various other settings, judgments, and decisions. The RAM 102 provided in the game control microcomputer 100 is a temporary storage device that provides a stack for saving work areas and data used for game control. The RAM 102 may be a backup RAM that stores the contents of part or all of the memory area so that they can be restored within a specified period even if the power supply to the pachinko game machine 1 is stopped. The RAM 102 is also called RWM (Read/Write Memory). The work area of the RAM 102 includes a memory area capable of storing various data used for game control, such as a counter, a timer, a buffer, and a storage area for various other codes and numerical values. The CPU 103 of the game control microcomputer 100 can control the progress of the game in the pachinko game machine 1 by executing processes corresponding to the programs stored in the ROM 101.

The random number circuit 104 provided in the game control microcomputer 100 counts updatable numerical data indicating various random number values used when controlling the progress of the game. The random numbers used when controlling the progress of the game are also called game random numbers. Some or all of the game random numbers may be updated by hardware using a dedicated circuit, or may be updated by software such as a computer program executed by the CPU 103.

Figure 3 shows an example of a gaming random number. The gaming random numbers include a random number MR1-1 for determining special symbols, a random number MR1-2 for winning symbols, a random number MR1-3 that serves as the initial value for winning symbols, a random number MR2-1 for normal winning symbols, a random number MR2-2 that serves as the initial value for normal winning symbols, a random number MR3-1 for normal symbol variation patterns, a random number MR3-2 for selecting a losing performance, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern.

The random number MR1-1 for determining the special symbol is used to determine the display result of the special symbol, such as whether the display result of the special symbol is a "big hit" or whether the display result of the special symbol is a "small hit". The random number MR1-2 for the winning symbol is used to select a confirmed special symbol from multiple special symbols, such as a big hit symbol when the display result of the special symbol is a "big hit" or a small hit symbol when the display result of the special symbol is a "small hit". The random number MR1-3, which is the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The random number MR2-1 for the winning normal symbol is used to select a confirmed normal symbol from multiple normal symbols to be displayed when the display result is a "normal hit" in the variable display of the normal symbol. The random number MR2-2, which is the initial value for the winning normal symbol, is used to set the initial value of the random number MR2-1. The random number MR3-1 for the normal symbol variation pattern is used to determine the variation pattern of the normal symbol to one of multiple patterns prepared in advance. The random number MR3-2 for selecting a miss effect is used to select whether or not the variable display of the effect pattern will be in a reach state when the display result of the special symbol is a "miss". The random number MR3-3 for selecting the variation pattern type is used to select the variation pattern type of the special symbol. The variation pattern type of the special symbol is a group that classifies the variation patterns of the special symbol in advance based on, for example, the performance state during the variable display of the effect pattern, and may be configured to include one or multiple variation patterns. The random number MR3-4 for the variation pattern is used to select the variation pattern of the special symbol.

When making various judgments and decisions based on random number values, such as numerical data indicating the value of a gaming random number, the CPU 103 reads out and references various tables from the ROM 101. Even if random number values are not used, the necessary tables may be read out and referenced from the ROM 101 to make various judgments, decisions, settings, and the like.

The I/O 105 of the game control microcomputer 100 includes an input port to which various signals are input, and an output port to which various signals are output. The various signals input to the input port of the I/O 105 may include detection signals from various switches transmitted via the switch circuit 110. The various signals output from the output port of the I/O 105 may include signals for controlling the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first reserved display device 25A, the second reserved display device 25B, the normal reserved display device 25C, etc., and solenoid drive signals for driving the normal electric role solenoid 81, the large prize opening solenoid 82, the specific area solenoid 83, etc.

The main board 11 transmits a presentation control command according to the progress of the game to the presentation control board 12 as part of the operation of controlling the progress of the game by the game control microcomputer 100. The presentation control command is a command that specifies or notifies the progress of the game. The presentation control command output from the main board 11 is relayed by the relay board 15 and supplied to the presentation control board 12. The presentation control command may include commands that specify various determination results on the main board 11, such as the display result of the special game, the type of win, and the variation pattern, commands that specify the status of the game, such as the start or end of the variable display, the opening status of the big prize opening, the occurrence of a win, the number of reserved memories, and the game status, and commands that specify the occurrence of an error, etc.

The performance control board 12 is a sub-control board independent of the main board 11, and has the function of receiving performance control commands and controlling the performance based on the received performance control commands. The performances that can be controlled by the performance control board 12 include various performances according to the progress of the game, such as driving the movable body 32, and also various notifications such as error notifications and notifications of power outage recovery. The performance control board 12 comprises a performance control CPU 120, a ROM 121, a RAM 122, a display control unit 123, a random number circuit 124, and an I/O 125.

The performance control CPU 120 executes a program stored in the ROM 121 to perform processing for controlling the execution of performance together with the display control unit 123. This processing is for implementing the various functions of the performance control board 12, and includes determining the performance to be executed. The performance control CPU 120 uses various data stored in the ROM 121, such as data from various tables, and also uses the RAM 122 as its main memory. The performance control CPU 120 may instruct the display control unit 123 to execute a performance based on detection signals from the controller sensor unit 35A and the push sensor 35B. The detection signal here is a signal that is output when an operation by the player is detected, and may be a signal that appropriately indicates the content of the operation.

The display control unit 123 includes a VDP (Video Display Processor), a CGROM (Character Generator ROM), a VRAM (Video RAM), etc., and controls the execution of mainly display-related effects based on instructions to execute effects from the effect control CPU 120. The display control unit 123 displays an effect image on the screen of the image display device 5 by supplying a video signal corresponding to the effect to be executed to the image display device 5. The display control unit 123 also supplies a sound designation signal to the sound control board 13 and a lamp signal to the lamp control board 14. The sound designation signal designates the sound to be output from the speakers 8L and 8R. The lamp signal designates the on/off state of the game effect lamp 9. The supply of the sound designation signal and the lamp signal enables the sound output from the speakers 8L and 8R and the turning on or off of the game effect lamp 9 in synchronization with the display of the effect image. The display control unit 123 may be capable of supplying a signal for operating the movable body 32 to a motor or solenoid of the movable body 32, or to a driver circuit that drives the movable body 32. A driver board for driving the movable body 32 may be provided separately from the performance control board 12.

The random number circuit 124 counts updatable numerical data indicating various random number values used when controlling the execution of various performances. The random numbers used when controlling the execution of performances are also called performance random numbers. The performance random numbers may be updated by software such as a computer program executed by the performance control CPU 120. When making various judgments and decisions based on random number values, such as numerical data indicating the values of performance random numbers, the performance control CPU 120 reads out and refers to various tables from ROM 121. Even when random number values are not used, the performance control CPU 120 may read out and refer to the necessary tables from ROM 121 to make various judgments, decisions, settings, etc.

The I/O 125 is configured to include an input port for taking in performance control commands transmitted from the main board 11, for example, and an output port for transmitting various signals. The input port of the I/O 125 may include an input terminal for a detection signal supplied from the controller sensor unit 35A, and an input terminal for a detection signal supplied from the push sensor 35B. The output port of the I/O 125 may include an output terminal for a video signal supplied to the image display device 5, an output terminal for a sound designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14.

The sound control board 13 is equipped with various circuits for driving the speakers 8L and 8R, and drives the speakers 8L and 8R based on a sound designation signal from the display control unit 123, and outputs the sound designated by the sound designation signal from the speakers 8L and 8R. The lamp control board 14 is equipped with various circuits for driving the game effect lamp 9, and drives the game effect lamp 9 based on a lamp signal from the display control unit 123, and turns the game effect lamp 9 on or off in the manner designated by the lamp signal. In this way, the sound output from the speakers 8L and 8R and the turning on and off of the game effect lamp 9 can be controlled based on a signal from the display control unit 123. Note that the control of the sound output and the turning on and off of the lamp, such as the supply of the sound designation signal and the lamp signal, and the control of the movable body 32, such as the supply of a signal to operate the movable body 32, may be performed in part or in whole by the performance control CPU 120. Boards other than the main board 11, such as the performance control board 12, the audio control board 13, and the lamp control board 14, are also called sub-boards. As in the configuration example shown in FIG. 2, multiple sub-boards may be provided for different functions, or, unlike the configuration example shown in FIG. 2, one sub-board may be configured to have multiple functions.

The power supply board 17 can supply power from an AC power source such as AC 100V in an external power source such as a commercial power source to electrical components including various control boards such as the main board 11 and the performance control board 12. The power supply board 17 is equipped with, for example, a rectifier circuit for converting AC to DC, a power supply circuit for converting a predetermined DC voltage to a specific DC voltage (for example, DC 12V or DC 5V, etc.). The pachinko game machine 1 can switch between starting and ending the power supply by operating the power switch 91. The switch circuit 110 of the main board 11 takes in a reset signal, a power off signal, and a clear signal from the power supply board 17 and transmits them to the game control microcomputer 100. The reset signal is an operation stop signal for putting a control circuit such as the game control microcomputer 100 into an operation stop state, and can be output using any of a power supply monitoring circuit, a watchdog timer built-in IC, and a system reset IC. The power-off signal is turned off when the predetermined power supply voltage used in the pachinko game machine 1 exceeds a predetermined value, and is turned on when the period during which the predetermined power supply voltage remains below the predetermined value continues for the power-off reference time or longer. The clear signal is turned on, for example, in response to pressing the clear switch 92 provided on the power supply board 17.

(motion)
Next, the operation (function) of the pachinko gaming machine 1 will be described.

(Main Operations of Main Board 11)
First, a description will be given of the main operations of the main board 11. When power supply to the pachinko gaming machine 1 is started, the game control microcomputer 100 is started up, and the CPU 103 executes main processing for game control.

Figure 4 is a flow chart showing the main processing P_MAIN for game control executed by the CPU 103 on the main board 11. When the main processing P_MAIN for game control shown in Figure 4 is started, the CPU 103 executes the power supply start response processing P_POWER_ON (step S1), and then executes the RWM check processing P_RWM_CHK (step S2). The power supply start response processing P_POWER_ON in step S1 can execute the initial setting of the game control microcomputer 100 in response to the start of power supply in the pachinko game machine 1. The initial setting of the game control microcomputer 100 may include the initialization of the output port, the setting of the interrupt vector, the setting of the built-in device register, and the setting of the specific register. The RWM check processing P_RWM_CHK in step S2 includes a checksum calculation processing, and compares the checksum data obtained as a result of the processing with the stored data in the checksum buffer. If the two data match, it is determined that the stored contents in the RAM 102 are normal.

Next, it is determined whether or not a predetermined recovery condition is satisfied (step S3). The recovery condition can be satisfied when the clear signal corresponding to the operation of the clear switch 92 is in the OFF state, there is normal stored data in the checksum buffer, and the stored contents in the RAM 102 as the backup RAM are normal. When the power of the pachinko game machine 1 is turned on, for example, if the clear switch 92 provided on the power supply board 17 is pressed, a clear signal in the ON state is input to the game control microcomputer 100. When such a clear signal in the ON state is input, it is sufficient to determine in step S3 that the recovery condition is not satisfied. The checksum buffer stores the checksum data calculated in the checksum calculation process when the backup judgment time was measured by the backup monitoring timer at the time of the previous power outage. When the time value of the backup monitoring timer does not match the specific value corresponding to the backup judgment time, it is sufficient to determine in step S3 that the recovery condition is not satisfied. The backup data may be stored data in the game work area in the RAM 102 as the backup RAM for game control. In step S3, it is determined whether the recovery conditions can be met based on the results of checking or inspecting the presence or absence of backup data and data errors by the RWM check process P_RWM_CHK in step S2.

If the recovery condition is met (step S3; Yes), the backup setting process P_BACKUP_SET is executed (step S4). The backup setting process P_BACKUP_SET uses the backup command transmission table to enable the performance control command corresponding to the backup to be sent from the main board 11 to the performance control board 12. The backup setting process P_BACKUP_SET also clears the process code, timer, counter, and flag specified by the backup setting table to enable initialization.

If the recovery condition is not met (step S3; No), the initialization setting process P_INIT_SET is executed (step S5). The initialization setting process P_INIT_SET enables the transfer of clear data to the game work area, which is the working area in RAM 102. This initializes the game work area in RAM 102. The initialization setting process P_INIT_SET then uses the initialization command transmission table to enable the transmission of the performance control command corresponding to the initialization from the main board 11 to the performance control board 12. The initialization setting process P_INIT_SET also clears the buffers, timers, pointers, and counters specified by the initialization setting table, making them initializeable.

Then, the control start setting process P_STACON is executed (step S6). The control start setting process P_STACON may include a wait process. The wait process executes a loop process and waits until the set waiting time has elapsed, thereby ensuring that the sub-boards such as the performance control board 12 can be started. The control start setting process P_STACON may also include a specific number of command transmission process or a command transmission process for chip individual number information. The specific number of command transmission process enables a performance control command that specifies the count value of the specific number counter when the power is turned on to be transmitted from the main board 11 to the performance control board 12. The specific number counter is provided at a specified address in the RAM 102, and may be capable of counting the remaining number of times until the number of executions of the variable display reaches a specific number corresponding to the time-saving condition. The command transmission process for chip individual number information enables a performance control command that specifies the stored value of the chip individual number register to be transmitted from the main board 11 to the performance control board 12. The chip individual number register is included in the built-in register of the game control microcomputer 100, and it is sufficient if it is capable of storing a different value assigned to each chip as the chip individual number.

The control start setting process P_STACON may include a start-up out-of-area process. The start-up out-of-area process is a process executed by reading out a program stored in the non-game program area of the ROM 101 in response to the start-up of the pachinko gaming machine 1 due to the start of power supply. The start-up out-of-area process may be, for example, a performance display RWM initial value setting process. The performance display RWM initial value setting process makes it possible to set an initial value for performing an initial display by a 7-segment LED constituting the performance display monitor. The performance display monitor may be mounted on, for example, the main board 11, and may display contents related to the setting value and contents related to the base. When the pachinko gaming machine 1 is in a setting change state in which the settings can be changed, the setting value can be changed to one of a number of stages, for example, six stages, and makes it possible to set the probability that the display result of the special pattern will be a "jackpot". The base is calculated by dividing the number of prize balls paid out when a game ball passes through each winning hole, such as the start winning hole, the general winning hole, and the big winning hole, by the number of game balls released into the game area.

After the control start setting process P_STACON in step S6, the timer interrupt counter setting is performed (step S7). In step S7, the PTC counter output value is set so that a regular timer interrupt occurs at a predetermined time interval, for example, 4 [ms (milliseconds)]. After that, the main process P_MAIN for game control enters a loop process. In this loop process, interrupt prohibition is set (step S8), the random number update process P_TFINIT for initial value determination is executed (step S9), and the loop outside area process P_REGOUT is executed (step S10), and then interrupt permission is set (step S11), and the process returns to step S8. Then, when the interrupt permission state is in effect, the CPU 103 is able to execute timer interrupt processing each time an interrupt request signal is input from the PTC to the CPU 103. This allows the CPU 103 to execute timer interrupt processing each time a predetermined time, for example, 4 [ms], has elapsed.

Figure 5 is a flow chart showing an example of timer interrupt processing P_PCT for game control. In the timer interrupt processing P_PCT shown in Figure 5, power-off processing P_POWER_OFF is executed (step S51). Next, it is determined whether the fraudulent activity monitoring flag is "0" (step S52). When magnetism is detected by the magnet sensor or when radio waves are detected by the frame radio wave sensor, the fraudulent activity monitoring flag is set to "1", which corresponds to the on state. In all other cases, the fraudulent activity monitoring flag is set to "0", which corresponds to the off state.

If the fraud monitoring flag is "1" (step S52; No), the game stop process P_GAME_STOP is executed (step S53). The game stop process P_GAME_STOP may be a process that initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and if it is in the off state, the execution of the payout process in the payout control board is stopped.

When the fraudulent activity monitoring flag is "0" (step S52; Yes), switch processing P_SW is executed (step S54), switch error notification processing P_CON_CHK is executed (step S55), random number update processing P_RANDOM is executed (step S56), and random number update processing for initial value determination P_TFINIT is executed (step S57). In addition, special symbol process processing P_TPROC is executed (step S58), normal symbol process processing P_FPROC is executed (step S59), information output processing P_JYOUHOU is executed (step S60), prize ball processing P_PAY is executed (step S61), and display processing P_HYOUZI is executed (step S62). Furthermore, other timer interrupt response processing is executed (step S63). After that, interrupt permission is set (step S64), and then the timer interrupt processing P_PCT ends.

The power-off process P_POWER_OFF in step S51 judges the power confirmation signal transmitted from the power supply board 17, and enables checksum calculation processing and the like to be executed when the power is off. The switch process P_SW in step S54 judges the state of the input port, and enables updating of the switch-on buffer and the like. The switch error notification process P_CON_CHK in step S55 can update the count value of a sensor-on counter specified, for example, by a switch error notification judgment table, and enables error notification display when the count value reaches a sensor abnormality error judgment value. The random number update process P_RANDOM in step S56 enables those of the game random numbers that will become software random numbers to be updated by software. The random number update process P_TFINIT for initial value determination in step S57 enables those of the game random numbers that are used as random number initial values to be updated by software.

The special symbol process P_TPROC in step S58 includes processes related to the variable display of special symbols and the game state, such as the execution and reservation management of the special symbol game, the control of the big win game state and the small win game state, and the control of the game state. The normal symbol process P_FPROC in step S59 includes processes related to the variable display of normal symbols and the state control of the second start winning port, such as the execution and reservation management of the normal symbol game based on the detection signal from the gate switch 21, and the opening and closing control of the variable winning ball device 6B based on the "normal hit". The information output process P_JYOUHOU in step S60 sets the information output signal. The information output signal is a signal corresponding to information such as big win information, start information, and probability fluctuation information supplied to a hall management computer installed outside the pachinko game machine 1. The big win information indicates the number of big wins, etc. The start information indicates the number of start winnings, etc. The probability fluctuation information indicates the number of times the probability variable state has been reached, etc. The prize ball processing P_PAY in step S61 includes a prize ball command output counter addition process and a prize ball control process. The prize ball command output counter addition process uses a prize ball number table to determine whether the switch is on, and when on is detected, updates the prize ball command output counter and the winning information output counter. The prize ball control process selects a process corresponding to the prize ball process code and controls the payout of prize balls based on the detection of game balls. The display process P_HYOUZI in step S62 sets the display by the first reserve indicator 25A, the second reserve indicator 25B, the regular reserve indicator 25C, and various other status indicator lights.

Figure 6 is a flow chart showing an example of processing that can be executed in step S58 shown in Figure 5 as the special symbol process processing P_TPROC. The CPU 103 sets the first start winning corresponding flag in the special symbol process processing P_TPROC (step S101). The first start winning corresponding flag setting reflects the state of the first start port switch 22A included in the switch-on buffer in the flag register of the CPU 103 by executing a logical operation command or the like. At this time, the zero flag in the flag register being in the on state indicates that the first start winning corresponding flag is in the off state. In contrast, the zero flag being in the off state indicates that the first start winning corresponding flag is in the on state. Next, the first start port winning table is set by a transfer command for setting the table pointer (step S102). Then, it is determined whether the first start winning corresponding flag is on (step S103). If the first start winning flag is on (step S103; Yes), the start port switch passing process P_TZU_ON is executed (step S104).

If the first start winning corresponding flag is off in response to step S103 (step S103; No), or after the start port switch passing process P_TZU_ON in step S104, the second start winning corresponding flag is set (step S105). The second start winning corresponding flag is set by executing a logical operation command or the like to reflect the state of the second start port switch 22B contained in the switch-on buffer in the flag register of the CPU 103. At this time, the zero flag in the flag register being on indicates that the second start winning corresponding flag is off. In contrast, the zero flag being off indicates that the second start winning corresponding flag is on. Next, the second start port winning table is set by a transfer command for setting the table pointer (step S106). Then, it is determined whether the second start winning corresponding flag is on (step S107). If the second start winning corresponding flag is on (step S107; Yes), the start port switch passing process P_TZU_ON is executed (step S108).

The start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102 to update the first reserved memory number and the total reserved memory number by adding 1 if the first reserved memory number is less than the upper limit, extracts the random number MR1-1 for determining the special pattern, the random number MR3-2 for selecting a miss performance, the random number MR3-3 for selecting the type of variation pattern, and the random number MR3-4 for the variation pattern, stores them in their respective random number buffers, and then transfers them to the first special pattern reserved buffer. In addition, the first reserved memory information designation command transmission table is used to enable the first reserved memory information designation command, which designates the first reserved memory number, to be sent from the main board 11 to the performance control board 12. Then, a value indicating "1" is stored in the start port winning buffer as the start port winning designation value.

The start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106 to update the second reserved memory number and the total reserved memory number by adding 1 if the second reserved memory number is less than the upper limit, extracts the random number MR1-1 for determining the special pattern, the random number MR3-2 for selecting a miss performance, the random number MR3-3 for selecting the variation pattern type, and the random number MR3-4 for the variation pattern, stores them in their respective random number buffers, and then transfers them to the second special pattern reserved buffer. In addition, the second reserved memory information designation command transmission table is used to enable the second reserved memory information designation command, which designates the second reserved memory number, to be sent from the main board 11 to the performance control board 12. Then, a value indicating "2" is stored in the start port winning buffer as the start port winning designation value.

A common start port switch passing process P_TZU_ON can be executed in steps S104 and S108. Meanwhile, the start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102, whereas the start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106. In this way, the common start port switch passing process P_TZU_ON is executed using different start port winning tables. Therefore, different data settings and controls are possible by the common process when the game ball enters the first start port and when it enters the second start port. The start port switch passing process P_TZU_ON may include a winning performance process using the extracted game random number.

If the second start winning flag is off in response to step S107 (step S107; No), or after the start port switch passing process P_TZU_ON in step S108, a transfer command that sets a pointer sets the special symbol process jump table (step S109). The special symbol process jump table is an address management table that selects and executes the process that corresponds to the read value of the special symbol process code. The special symbol process code can be updated to any of 00[H] to 0B[H] in response to the progress of game control in the pachinko game machine 1, and is also called the special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] can also be used to indicate a binary number.

Following step S109, a transfer command to read out stored data is used to load the special symbol process code (step S110). Next, the 2-byte data selection process P_ABXEXEC is executed (step S111) to obtain the address of the process selected in accordance with the special symbol process code. The address obtained at this time is set in the pointer. After this, the process pointed to by the pointer is executed in accordance with a subroutine call command (step S112), making it possible to execute the process selected in accordance with the special symbol process code. When the process selected in this manner ends and a return command is issued to return to the special symbol process process P_TPROC, this special symbol process process P_TPROC also ends, and a return command is issued to return to the timer interrupt process P_PCT for game control.

Figure 7 shows a configuration example TT01 of a special symbol process jump table used in the special symbol process P_TPROC. The special symbol process jump table is configured to include table data that can set the address of the process selected corresponding to the special symbol process code in an internal register of the CPU 103 used as a pointer. The special symbol process jump table of the configuration example TT01 includes special symbol normal processing P_TNORMAL when the special symbol process code is 00 [H], special symbol fluctuation processing P_TSTART when the special symbol process code is 01 [H], special symbol stop processing P_TSTOP when the special symbol process code is 02 [H], small win opening pre-processing P_TLFAN when the special symbol process code is 03 [H], small win opening mid-processing P_TLOPEN when the special symbol process code is 04 [H], small win opening post-processing P_TLCLSF when the special symbol process code is 05 [H], and ... It includes table data that allows the pointer to be set to an address value corresponding to the following: small win discharge ball waiting process P_TLOUT when the separate pattern process code is 06 [H], small win end process P_TLEND when the special pattern process code is 07 [H], large prize opening pre-opening process P_TINT when the special pattern process code is 08 [H], large prize opening open process P_TOPEN when the special pattern process code is 09 [H], large prize opening post-opening process P_TCLSF when the special pattern process code is 0A [H], and large win end process P_TEND when the special pattern process code is 0B [H].

The special symbol normal processing P_TNORMAL makes it possible to determine whether or not to start a special symbol game based on the presence or absence of stored reserved information, to determine the special symbol display result using the random number MR1-1 for determining the special symbol, to determine the confirmed special symbol to be displayed in a stopped state in the variable display of the special symbol, and to determine the variation pattern of the special symbol. The special symbol display result includes "jackpot", "small hit", "miss", etc., and when it is determined to be a "jackpot", it is decided to control to a jackpot game state that is advantageous to the player. Also, when the display result of the special symbol is a "jackpot", it is decided which of multiple types of jackpot game states with different degrees of advantage for the player the game will be controlled to, corresponding to the jackpot symbol that is the confirmed special symbol. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether or not to control the state to an advantageous state that is advantageous to the player, and can determine which of multiple types of advantageous states with different degrees of advantage to the player to control to. Furthermore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine which of multiple types of variation patterns to control to.

The special pattern change process P_TSTART measures the time that has elapsed since the special pattern began to change on the first special pattern display device 4A or the second special pattern display device 4B, and makes it possible to determine whether the special pattern change time corresponding to the change pattern has elapsed. The special pattern stop process P_TSTOP measures the time that has elapsed since the special pattern stopped changing on the first special pattern display device 4A or the second special pattern display device 4B, and makes it possible to determine whether the pattern stop time has elapsed. The pattern stop time may be set as the time for stopping the special pattern to be displayed when it is determined in the special pattern change process P_TSTART that the special pattern change time has elapsed. When the pattern stop time has elapsed, the special pattern process code is updated and various settings are made according to the special pattern display result. For example, if the special chart display result is a "big win," the special chart process code can be updated to 08 [H], if the special chart display result is a "small win," the special chart process code can be updated to 03 [H], and if the special chart display result is a "miss," the special chart process code can be updated to 00 [H].

Processing before small win opening P_TLFAN, processing during small win opening P_TLOPEN, processing after small win opening P_TLCLSF, waiting for small win ball ejection P_TLOUT, and processing after small win end P_TLEND are processes for controlling the progress of the game in the small win game state. Processing before large win opening P_TINT, processing during large win opening P_TOPEN, processing after large win opening P_TCLSF, and processing after big win end P_TEND are processes for controlling the progress of the game in the big win game state.

(Main operations of the performance control board 12)
Next, a description will be given of the main operations of the performance control board 12. In the performance control board 12, when a power supply voltage is supplied from the power supply board 17 or the like, the performance control CPU 120 starts up and executes the performance control main process.

Figure 8 is a flowchart showing the main processing S_MAIN for performance control executed by the performance control CPU 120 in the performance control board 12. When the main processing S_MAIN for performance control shown in Figure 8 is started, the performance control CPU 120 executes the performance control initialization processing S_INIT (step S71). The performance control initialization processing S_INIT includes clearing the RAM 122, setting various initial values, and register settings for the timer circuit mounted on the performance control board 12. Next, the initial operation control processing S_SYOKI is executed (step S72). The initial operation control processing S_SYOKI makes it possible to control the initial operation of the movable body 32, such as controlling the movable body 32 to return to its initial position and controlling the predetermined operation check. Then, it is determined whether the timer interrupt flag is on (step S73). The timer interrupt flag is set to the on state every time a predetermined time, such as 2 [ms (milliseconds)], elapses based on the register setting for the timer circuit. If the timer interrupt flag is off (step S73; No), step S73 is repeated and the system waits.

When the timer interrupt flag is on (step S73; Yes), the timer interrupt flag is cleared to the off state (step S74), and the command analysis process S_COMMAND is executed (step S75), the performance control process process S_CPROC is executed (step S76), the performance random number update process S_RANDOM is executed (step S77), and the performance output process S_OUT is executed (step S78). Then, other timer interrupt response processes are executed (step S79), and the process returns to step S73.

The command analysis process S_COMMAND in step S75 enables the reading of the performance control command stored in the performance control command receiving buffer and the setting and control corresponding to the read performance control command. By executing the command analysis process S_COMMAND, the performance control CPU 120 can update the storage data indicating the state of the flag, the storage data of the register, and any other storage data in the working area of the RAM 122 in response to the performance control command transmitted from the main board 11. The performance control process process S_CPROC in step S76 enables the execution of performances using various performance devices, including, for example, the display of the performance image on the screen of the image display device 5, the sound output from the speakers 8L and 8R, the lighting or extinguishing of the decorative light-emitting body such as the game effect lamp 9 and the decorative LED, and the drive control of the movable body 32. The control contents of the performances using various performance devices may be judged, determined, set, etc. based on the performance control command transmitted from the main board 11 and the execution result of the processing by the performance control CPU 120. The performance random number update process S_RANDOM in step S77 enables at least a portion of the performance random numbers used on the performance control board 12 to be updated by executing a software program.

Figure 9 (A) is a flow chart showing an example of processing that can be executed in step S76 shown in Figure 8 as the performance control process processing S_CPROC. The performance control CPU 120 executes the look-ahead performance setting processing S_SAKI_SET in the performance control process processing (step S151). The look-ahead performance setting processing S_SAKI_SET enables judgment, decision and setting regarding the execution of a look-ahead preview performance, for example, based on the performance control command at the time of the start winning transmitted from the main board 11. The look-ahead performance setting processing S_SAKI_SET also enables the hold display to be updated based on the number of hold memories specified from the performance control command.

After the pre-read effect setting process S_SAKI_SET in step S151, a transfer command that sets a pointer sets the effect control process jump table (step S152). The effect control process jump table is an address management table that selects and executes the process corresponding to the read value of the effect control process code. The effect control process code can be updated to any of 00 [H] to 0A [H] in accordance with the progress of effect control in the pachinko gaming machine 1, and is also called the effect process code. The effect control process code is loaded by a transfer command for reading out stored data (step S153). The address of the process to be selected corresponding to the effect control process code thus obtained is set in the effect control pointer (step S154). Therefore, by executing the process pointed to by the effect control pointer (step S115), the process selected corresponding to the effect control process code becomes executable.

Figure 9 (B) shows an example configuration TT02 of a performance control process processing jump table used in the performance control process processing S_CPROC. The performance control process processing jump table is configured to include table data that can set the address of the processing selected corresponding to the performance control process code in a register used as a performance control pointer. The presentation control process jump table of the configuration example TT02 includes table data that can set address values corresponding to the following in the presentation control pointer: waiting for a change pattern command when the presentation control process code is 00 [H], starting presentation pattern change when the presentation control process code is 01 [H], processing during presentation pattern change when the presentation control process code is 02 [H], stopping presentation pattern change when the presentation control process code is 03 [H], displaying small wins when the presentation control process code is 04 [H], processing during small win opening when the presentation control process code is 05 [H], ending presentation of small wins when the presentation control process code is 06 [H], displaying big wins when the presentation control process code is 07 [H], processing during a round when the presentation control process code is 08 [H], post-round processing when the presentation control process code is 09 [H], and ending presentation of big wins when the presentation control process code is 0A [H].

The waiting for receiving a variation pattern command process makes it possible to determine whether or not a variation pattern designation command transmitted from the game control microcomputer 100 of the main board 11 has been received. If it is determined that a variation pattern designation command has been received, the performance control process code is updated to 01 [H] corresponding to the performance pattern variation start process, and if it is determined that a variation pattern designation command has not been received, the demo display can be controlled. The performance pattern variation start process makes it possible to start a variation-time performance corresponding to a special game. For example, in response to a variation pattern command transmitted from the main board 11, it makes it possible to select a performance pattern used to control the variation-time performance and to start updating the performance process timer that measures the performance execution time. The performance pattern variation process makes it possible to control the switching timing of each performance element that constitutes the performance pattern, and makes it possible to determine whether or not the performance execution time has elapsed based on the measured value of the performance process timer. If it is determined that the performance execution time has elapsed, the performance control process code is updated to 03 [H] corresponding to the performance pattern variation stop process. The performance pattern change stop process enables the end control of the performance during change and the display control of the performance result corresponding to the determined special pattern based on the establishment of the end condition of the performance during change, such as the elapse of the performance execution time or the reception of a performance pattern determination command. At this time, the performance control process code is updated and various settings are made according to the display result of the variable display. For example, if the display result of the variable display is a "big hit", the performance control process code can be updated to 07 [H], if the display result of the variable display is a "small hit", the performance control process code can be updated to 04 [H], and if the display result of the variable display is a "miss", the performance control process code can be updated to 00 [H].

The small hit display process, small hit opening process, and small hit end presentation process are processes for controlling the progress of presentation corresponding to the small hit game state. The big hit display process, round process, post-round process, and big hit end presentation process are processes for controlling the progress of presentation corresponding to the big hit game state.

(Variations of the basic explanation, etc.)
The pachinko gaming machine 1 is not limited to the configuration, functions, processing, and operation in the basic description and other descriptions, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not need to have all the technical features shown in the embodiment, and may have a part of the configuration described in the embodiment so as to solve at least one problem in the prior art. When a subordinate concept is described in the embodiment, an invention of a superordinate concept using a homologous or similar matter, or an invention of a superordinate concept using a common property, is included as the present invention, and may have a part of the structure or characteristics described in the embodiment so as to solve at least one problem in the prior art.

The pachinko gaming machine 1 may be a payout type gaming machine that pays out a predetermined number of gaming media as prizes when a prize is won, or it may be an enclosed type gaming machine that encloses gaming media and awards points when a prize is won.

The display during the variable display of the special pattern may be only one type of pattern, such as a symbol indicating "-", and the variable display may be such that this pattern is repeatedly displayed and turned off. One type of pattern may be displayed during the variable display, and this pattern may not be displayed when the variable display is stopped. For example, the display result may be a non-display state in which the symbol indicating "-" is not displayed, and no special pattern is displayed.

The pachinko game machine 1 may be configured to change the probability of winning a jackpot or the ball payout rate in response to a plurality of set values. For example, in the special symbol normal processing of the special symbol process processing, the probability of winning a jackpot or the ball payout rate may be changed by using a different jackpot determination value for each set value. As a specific example, the set value is made up of six levels from 1 to 6, with 6 being the highest probability of winning a jackpot, and the smaller the value is in the order of 6, 5, 4, 3, 2, and 1, the lower the probability of winning a jackpot. In this case, if 6 is set as the set value, the player has the highest advantage, and the smaller the value is in the order of 6, 5, 4, 3, 2, and 1, the lower the advantage is in stages. If the probability of winning a jackpot changes according to the set value, the ball payout rate may also change according to the set value. The probability of winning a jackpot is constant regardless of the set value, while the number of rounds in the jackpot game state may change according to the set value. The pachinko game machine 1 may be configured to be able to set any of a plurality of set values with different advantages for the player. The setting value set in the pachinko gaming machine 1 may be notified by sending a setting value designation command from the main board 11 to the performance control board 12. During execution of the variable display, a setting suggestion performance that suggests the setting value in the pachinko gaming machine 1 at a predetermined rate may be executed. The suggestion regarding the setting value of the pachinko gaming machine 1 is not limited to suggesting the setting value in the pachinko gaming machine 1, and may be, for example, a suggestion as to whether or not the setting value in the pachinko gaming machine 1 has been changed. The setting suggestion performance may suggest the probability of a jackpot through any performance, and may also be able to give a suggestion regarding the setting value of the pachinko gaming machine 1.

Instead of some or all of the suggestions regarding the control of the jackpot gaming state, or in addition to some or all of the suggestions regarding the control of the jackpot gaming state, suggestions regarding the control of a state that is advantageous to the player and different from the jackpot gaming state may be given. For example, suggestions regarding a probability variable state that is controlled after the end of the jackpot gaming state may be given. In addition, suggestions regarding a state in which any gaming value that is advantageous to the player is awarded as an advantageous state may be given, depending on whether or not it is controlled.

The invention relating to gaming machines is not limited to the pachinko gaming machine 1, but can also be applied to slot machines as appropriate. A slot machine can execute a game in which medals are inserted and a predetermined bet amount is set, multiple types of symbols are rotated in response to the player's operation of an operating lever, and a predetermined number of medals are paid out to the player when the symbols are stopped in response to the player's operation of a stop button and a specific combination of stopped symbols is formed. In a slot machine, advantageous states that are advantageous to the player may include one or more of the so-called bonuses, such as a big bonus, regular bonus, RT, AT, ART, and CZ.

The programs and data for implementing various controls, including the progress of the game and the execution of the performance, may be distributed and provided to a computer device included in a gaming machine such as the pachinko gaming machine 1 by a removable recording medium, or may be distributed and provided by being installed in advance in a storage device of the computer device. In addition, the machine may be provided with a communication processing unit that can be connected to an external device on a network via a communication line, etc., and may distribute and provide the programs and data by downloading them from the external device. The execution form of the game and performance may also be executable by mounting a removable recording medium, or may be executable by temporarily storing the programs and data downloaded via a communication line, etc. in an internal memory, or may be executable directly using the hardware resources of an external device on a network connected via a communication line, etc., or may be executable by exchanging data with another computer device, etc., via a network.

When comparing various percentages, such as the decision percentage of a process or data, or the execution percentage of a performance, expressions such as "high", "low", and "different" may include the case where one is a percentage of "0%" or "100%". For example, for one decision result or execution content, it may include the case where there is no decision or execution at a percentage of "0%", or the case where there is always a decision or execution at a percentage of "100%".

(Explanation regarding characteristic part 01AK)
FIG. 10-1 shows an example of the configuration of the game control microcomputer 100 with respect to the characteristic part 01AK. The game control microcomputer 100 of the characteristic part 01AK is configured with an external bus interface 131, a clock circuit 132, a unique information storage circuit 133, a reset controller 134, an interrupt controller 135, a timer circuit 136, an address decode circuit 137, a free-running counter 138, and a serial communication circuit 139 in addition to the ROM 101, the RAM 102, and the CPU 103. The random number circuit 104 shown in FIG. 2 is configured to include a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I/O 105 shown in FIG. 2 is configured to include a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

The external bus interface 131 is a bus interface that has an interface function between the external bus and internal bus of the chips that make up the game control microcomputer 100, and a function for controlling the direction of an address bus, a data bus, and each control signal. For example, the external bus interface 131 may be connected to an external memory or an external input/output device that is external to the game control microcomputer 100, and may transmit and receive address signals, data signals, various control signals, and the like between these external devices. The external bus interface 131 may include an internal resource access control circuit that controls access to the internal data of the game control microcomputer 100 from the external device.

The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the external control clock terminal EXC. The external control clock terminal EXC may receive a control clock generated by a control clock generation circuit provided in the game control microcomputer 100. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, the 16-bit random number circuit 104A, and the 8-bit random number circuit 104B. The internal system clock SCLK can also be output from the system clock output terminal CLKO to the outside of the game control microcomputer 100. Alternatively, the internal system clock SCLK may be restricted from being output to the outside of the game control microcomputer 100, making it difficult to identify the operating state of the game control microcomputer 100 from the outside.

The unique information storage circuit 133 can store multiple types of unique information that are internal information of the game control microcomputer 100, for example. For example, the unique information storage circuit 133 may store a ROM code, a chip individual number, and an ID number as unique information that differs for each chip of the game control microcomputer 100. The ROM code is numerical data that can be generated from data stored in a specified area of the ROM 101. The chip individual number and the ID number are numbers that are assigned when the game control microcomputer 100 is manufactured, and indicate different numerical values for each chip. The chip individual number may be readable by a user program such as a game program, while the ID number may be set so that it cannot be read by the user program. The unique information storage circuit 133 may be included in a specified area of the ROM 101, or may be included in a built-in register of the game control microcomputer 100.

The reset controller 134 can control various resets that occur inside and outside the game control microcomputer 100. Resets that can be controlled by the reset controller 134 include a system reset and a user reset. A system reset occurs when the input signal of the external system reset terminal XSRST is at a low level for a certain period of time. A user reset occurs due to a specified factor, such as the occurrence of a timeout signal of the watchdog timer 134A or the occurrence of a driving prohibition outside a designated area (IAT). The reset controller 134 includes a watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to the monitoring time, and can perform a countdown that periodically updates the timer value by subtracting 1. When the timer value becomes "0" and a timeout occurs, the watchdog timer 134A can output a timeout signal to reset the game control microcomputer 100 and restart it. This allows the watchdog timer 134A to measure the monitoring time and reset the game control microcomputer 100 when it is determined that the monitoring time has elapsed. The watchdog timer 134A can be set to enable or disable operation, for example, according to a game program.

The interrupt controller 135 can control various interrupt requests that occur inside or outside the game control microcomputer 100. The interrupts that can be controlled by the interrupt controller 135 include the non-maskable interrupt NMI and the maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that can be accepted unconditionally even when the CPU 103 is in an interrupt-prohibited state, and occurs when the input signal of the external non-maskable interrupt terminal XNMI (also used as the input port PI6) is at a low level for a certain period of time. The maskable interrupt INT is an interrupt that can permit or prohibit the acceptance of interrupt requests by a setting command of the CPU 103, and multiple interrupts can be executed by setting priority levels. The maskable interrupt INT can be caused by any or all of the following multiple types of interrupt causes: the input signal of the external maskable interrupt terminal XINT (also used as input port PI5) being at a low level for a certain period of time, a timeout occurring in the timer circuit 136, or numeric data indicating a random value being stored in the random value register by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B.

The timer circuit 136 is configured to include a PTC (Programmable Timer Counter) as a timer counter corresponding to the three channels PTC0 to PTC2, and enables real-time interrupt generation and time measurement. Each channel PTC0 to PTC2 of the timer circuit 136 uses a count clock generated based on the internal system clock SCLK, and it is sufficient if it can update the timer value in response to signal changes in the count clock, such as the falling edge timing when the clock signal changes from high level to low level.

The address decode circuit 137 can decode various signals obtained from each functional block inside the game control microcomputer 100, and can output a chip select signal, which is a decoded signal for an external device. The chip select signal selectively enables the internal circuitry of the game control microcomputer 100 or an external device that is a peripheral device, allowing access from the CPU 103. The output terminals that the address decode circuit 137 can use may be multi-function terminals that can selectively output a parallel output signal from the POP 105B, a serial transmission signal from the serial communication circuit 139, a clock output signal from the clock circuit 132, and a chip select signal generated by the address decode circuit 137.

The free-running counter 138 is configured to include counter circuits corresponding to the four channels FRC0 to FRC3, and can update the count value separately from the operation of the CPU 103. Each channel FRC0 to FRC3 of the free-running counter 138 can be started by an independent update clock, and can be set to stop or change its operation, for example, according to a game program. The count value by the free-running counter 138 can be stored in a hard latch register in response to a latch signal transmitted from an input terminal that serves as a latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a game program, etc.

The serial communication circuit 139 is configured to include serial communication units corresponding to three channels SCU0, SCU1, and STU2, and enables communication with an external device by a serial communication method. Each channel SCU0, SCU1, and STU2 of the serial communication circuit 139 can process communication data, for example, in full duplex, asynchronous, or standard NRZ (Non Return to Zero) format. The channels SCU0 and SCU1 of the serial communication circuit 139 are included in a first channel transmission/reception circuit that can transmit and receive serial data bidirectionally with an external circuit. The channel STU2 of the serial communication circuit 139 is included in a second channel transmission circuit that can only transmit serial data unidirectionally with an external circuit. For example, the channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. The channel SCU1 of the serial communication circuit 139 is used for data communication with the performance control board 12. Instead of the channel SCU1 of the serial communication circuit 139, the channel STU2 of the serial communication circuit 139 may be used for data communication with the performance control board 12.

The 16-bit random number circuit 104A is configured to include random number generation units corresponding to the four channels RL0 to RL3, and each of them can generate random numbers from "0" to "65535" using numerical data indicating the value of a 16-bit pseudo-random number by independent operation. The maximum value of the random numbers generated by each channel RL0 to RL3 in the 16-bit random number circuit 104A can be set to any value in the range of "256" to "65535". By setting such a maximum value, it is possible to perform initial setting to select the random number startup method so that the update of the numerical data indicating the random number value is started. Alternatively, it is possible to perform initial setting to select the random number startup method for each channel RL0 to RL3 in the 16-bit random number circuit 104A so that it is automatically started when the operation mode of the game control microcomputer 100 shifts from the security mode to the user mode. The 16-bit random number circuit 104A can update the random number MR1-1 for determining special symbols using channel RL0, and can update the random number MR3-2 for selecting a losing performance using channel RL2.

The 8-bit random number circuit 104B is configured to include random number generation units corresponding to the four channels RS0 to RS3, each of which can generate random numbers from "0" to "255" using numerical data indicating the value of an 8-bit pseudo-random number by independent operation. The maximum value of the random numbers generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value in the range of "16" to "255". By setting such a maximum value, it is possible to perform initial setting to select the random number startup method so that the update of the numerical data indicating the random number value is started. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B may be initially set to select the random number startup method so that it is automatically started when the operation mode of the game control microcomputer 100 shifts from the security mode to the user mode. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the type of variation pattern via channel RS1, the random number MR3-4 for the variation pattern via channel RS2, and the random number MR3-1 for the normal symbol variation pattern via channel RS3.

PIP105A has an 8-bit wide dedicated input port built in, for example, and allows various signals to be input from outside the game control microcomputer 100. PIP105A can use input terminals corresponding to input ports PI0 to PI7. Input port PI5 uses a multi-function terminal that can be used with the external maskable interrupt terminal XINT. Input port PI6 uses a multi-function terminal that can be used with the external non-maskable interrupt terminal XNMI. Input port PI7 uses a multi-function terminal that can be used with the receiving terminal of channel SCU0 in the serial communication circuit 139. POP105B has an 11-bit wide dedicated output port built in, for example, and allows various signals to be output to the outside of the game control microcomputer 100. POP105B can supply parallel output signals corresponding to output ports PO0 to PO7 and PO10 to PO12 to the address decode circuit 137.

Figure 10-2 shows an example of an address map in the game control microcomputer 100. In the example shown in Figure 10-2, the area of addresses 0000 [H] to 3FFF [H] is assigned to the ROM 101, and includes a game program area, a game data area, a non-game program area, a non-game data area, a ROM comment area, a program management area, and other unused areas. The area of addresses F000 [H] to F3FF [H] is assigned to the RAM 102, and includes a game work area, a game stack area, a non-game work area, a non-game stack area, and other unused areas. The area of addresses FE00 [H] to FEBF [H] is a function setting register area assigned to the built-in register of the game control microcomputer 100. The area of addresses FF00 [H] to FFFF [H] is a function control register area assigned to the built-in register of the game control microcomputer 100.

In the ROM 101, the game program area can store game programs, which are computer programs related to the progress of a game. The game data area can store game data used by the game programs. The non-game program area can store non-game programs, which are computer programs related to control and processing other than the progress of a game. The non-game data area can store non-game data used by the non-game programs. These programs and data stored in the ROM 101 are designed and created in advance by the manufacturer of the pachinko gaming machine 1, who is the user of the game control microcomputer 100. Therefore, the game programs and non-game programs are included in the user programs. The game data and non-game data are included in the user data.

The memory area of ROM 101 is provided with a game program area capable of storing game programs related to the progress of the game, and a non-game program area for control and processing other than the progress of the game, and the area in front of the non-game program area to which a rear address is assigned is an unused area with a memory area of more than the boundary byte number, for example 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to the progress of the game, and the non-game program area capable of storing non-game programs related to control and processing other than the progress of the game, making it easier to design and manage the programs and data stored in ROM 101.

The memory area of ROM 101 is provided with a game program area capable of storing game programs related to the progress of the game, and a game data area capable of storing game data used by the game programs, and the area in front of the game data area to which the latter address is assigned is an unused area of memory space with a boundary byte number or more, for example 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to the progress of the game, and the game data area capable of storing game data used by the game programs, facilitating the design and management of the programs and data stored in ROM 101.

In the storage area of ROM 101, a non-game program area capable of storing non-game programs related to control and processing different from the progress of the game, and a non-game data area capable of listening to non-game data used by the non-game programs are provided adjacent to each other, and among the non-game program area and the non-game data area, the area behind the non-game program area to which a forward address is assigned becomes the non-game data area, and the area in front of the non-game data area to which a backward address is assigned becomes the non-game program area. In this way, the non-game program area capable of storing non-game programs related to control and processing different from the progress of the game and the non-game data area capable of storing non-game data used by the non-game program can be provided in storage areas assigned consecutive addresses to enhance the unity, and the design and management of the programs and data stored in ROM 101 can be made easier. In addition, an unused area of storage area of more than the boundary byte number may be provided between the non-game program area and the non-game data area to make it easier to identify the non-game program area and the non-game data area.

In the memory area of ROM 101, data indicating a value of "0" may be stored in all areas of the memory area that will become unused areas. This makes it easy to distinguish between game program areas and game data areas, non-game program areas and non-game data areas, and unused areas. Furthermore, if unauthorized data is stored in an unused area, this data can be easily found. Note that data indicating a value of "1" may be stored in all areas of the memory area that will become unused areas. In other words, data indicating the same value may be stored in all areas of the memory area that will become unused areas. This makes it easy to distinguish between multiple types of memory areas, and makes it easy to find unauthorized stored data.

In RAM 102, the game work area can be used as a work area when CPU 103 executes a game program. The game stack area can be used as a stack area when CPU 103 executes a game program. The non-game work area can be used as a work area when CPU 103 executes a non-game program. The non-game stack area can be used as a stack area when CPU 103 executes a non-game program.

The game program area and game data area provided in the memory area of ROM 101, and the game work area and game stack area provided in the memory area of RAM 102 are included in the memory area for game control. The non-game program and non-game data area provided in the memory area of ROM 101, and the non-game work area and non-game stack area provided in the memory area of RAM 102 are included in the memory area for non-game control.

The ROM comment area provided in the storage area of ROM 101 stores data indicating any program-specific information, such as the program title and version. The program management area provided in the storage area of ROM 101 can store setting information required for the internal settings of the game control microcomputer 100 so that the CPU 103 can execute game programs and non-game programs.

Figure 10-3 shows a main setting example AKA01 of the addresses included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function setting register area is the first area for setting functions using various circuits included in the game control microcomputer 100, such as the watchdog timer 134A of the reset controller 134, the interrupt controller 135, the timer circuit 136, and the serial communication circuit 139.

In setting example AKA01, the setting values of the WDT start register at address FE1A[H] and the WDT clear register at addresses FE1B[H] to FE1C[H] are invalid values corresponding to unused states. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. As the setting value of the interrupt mask register at address FE00[H] is 7E[H], the interrupt control function using the interrupt controller 135 is set to an enabled state for maskable interrupt IR0. As the setting values of the registers related to channel PTC0 of the timer circuit 136 at addresses FE01[H] to FE03[H] are valid values, the time measurement function using channel PTC0 of the timer circuit 136 is set to an enabled state. At addresses FE04[H] to FE09[H], the register settings for channels PTC1 and PTC2 of timer circuit 136 are invalid values corresponding to unused states, so the timing function using channels PTC1 and PTC2 of timer circuit 136 is set to an unused state.

The register settings for channels SCU0 and SCU1 of serial communication circuit 139 at addresses FE0A[H] to FE11[H] are valid, so that the serial communication function using channels SCU0 and SCU1 of serial communication circuit 139 is set to an available state. The register settings for channel STU2 of serial communication circuit 139 at addresses FE12[H] to FE14[H] are invalid, so that the serial communication function using channel STU2 of serial communication circuit 139 is set to an unused state.

When the register settings for the input ports of PIP 105A at addresses FE2C[H] to FE2E[H] are valid values, the signal input function using each input port is set to an available state. When the register settings for the random number circuit 104 at addresses FE36[H] to FE4A[H] include valid and invalid values, the random number generation function using the random number circuit 104 is set to an available state for the channels corresponding to the valid values, and to an unused state for the channels corresponding to the invalid values. For example, of the four channels RL0 to RL3 in the 16-bit random number circuit 104A, the random number generation function is set to an available state for channels RL0 and RL2, whose corresponding maximum value setting register settings are valid values, while the random number generation function is set to an unused state for channels RL1 and RL3, whose corresponding maximum value setting register settings are invalid values. In addition, of the four channels RS0 to RS3 in the 8-bit random number circuit 104B, the random number generation function is set to an available state for channels RS1 to RS3 whose corresponding maximum value setting registers are set to valid values, and the random number generation function is set to an unused state for channel RS0 whose corresponding maximum value setting registers are set to invalid values.

In this way, the various circuits included in the game control microcomputer 100 only need to be able to set the various functions using the respective circuits to either an available state or an unused state, corresponding to the setting value in the function setting register area. The function setting register area is not limited to the various circuits included in the game control microcomputer 100, and may be a first area for setting any function.

Figure 10-4 shows a main setting example AKA02 of the addresses included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function control register area is the second area for function control using various circuits included in the game control microcomputer 100, such as the RAM 102, the random number circuit 104, the PIP 105A, and the serial communication circuit 139.

In the setting example AKA02, the RWM access protection register at address FF00[H] corresponds to a setting value of 00[H] or 01[H], enabling function control to prohibit or permit access to the RAM 102, which is the RWM. The internal information register at address FF01[H] has a setting value of an invalid value corresponding to unused, and function control using the corresponding circuit is in an unused state. The internal information register can store data indicating internal information such as an abnormality in the random number update state, an abnormality in the frequency of the random number update clock, a system reset occurrence, a WDT timeout occurrence, and an IAT occurrence, but is not used as an unused state in this embodiment.

Each register with addresses FF25[H] to FF28[H] can store a setting value used when controlling the serial communication function using channel SCU0 of serial communication circuit 139 when that function is available. Each register with addresses FF29[H] to FF2C[H] can store a setting value used when controlling the serial communication function using channel SCU1 of serial communication circuit 139 when that function is available.

Each register with addresses FF60[H] to FF67[H] can store a random number value that can be obtained using the soft latch random number value acquisition function of the 16-bit random number circuit 104A. Of these, the RL0 soft latch random number register with addresses FF60[H] to FF61[H] can store a random number that can be generated by channel RL0 of the 16-bit random number circuit 104A when numerical data indicating the value is acquired by soft latch. The RL1 soft latch random number register with addresses FF62[H] to FF63[H] can store a random number that can be generated by channel RL1 of the 16-bit random number circuit 104A when numerical data indicating the value is acquired by soft latch. The RL2 soft latch random number register with addresses FF64[H] to FF65[H] can store a random number that can be generated by channel RL2 of the 16-bit random number circuit 104A when numerical data indicating the value is acquired by soft latch. The RL3 soft latch random number register at addresses FF66[H] to FF67[H] can store the random numbers that can be generated by channel RL3 of the 16-bit random number circuit 104A when numerical data indicating the value is obtained by the soft latch.

Each of the registers at addresses FF68[H] to FF6B[H] can store random numbers that can be obtained using the soft latch random number acquisition function of the 8-bit random number circuit 104B. Of these, the RS0 soft latch random number register at address FF68[H] can store random numbers that can be generated by channel RS0 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by soft latch. The RS1 soft latch random number register at address FF69[H] can store random numbers that can be generated by channel RS1 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by soft latch. The RS2 soft latch random number register at address FF6A[H] can store random numbers that can be generated by channel RS2 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by soft latch. The RS3 soft latch random number register at address FF6B[H] can store the random numbers that can be generated by channel RS3 of the 8-bit random number circuit 104B when numerical data indicating the value is obtained by the soft latch.

The RL0 hard latch random number register number "0" at addresses FF88[H] to FF89[H] and the RL0 hard latch random number register number "1" at addresses FF98[H] to FF99[H] can store random numbers that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A when numerical data indicating the value is acquired by the hard latch. Here, the RL0 hard latch random number register includes multiple storage areas corresponding to multiple register numbers, and different hard latch conditions can be set corresponding to the storage areas of different register numbers. For example, the RL0 hard latch random number register number "0", which is the RL0 hard latch random number register corresponding to register number "0", can establish a hard latch condition when the game ball detection signal by the first start port switch 22A is in the on state. In contrast, the RL0 hard latch random number register number "1", which is the RL0 hard latch random number register corresponding to register number "1", can satisfy the hard latch condition when the game ball detection signal from second start port switch 22B is in the on state. As a result, RL0 hard latch random number register number "0" can be stored when the numerical data indicating the value of random number MR1-1 for determining special symbols obtained in response to the occurrence of a first start winning is obtained by the hard latch. RL0 hard latch random number register number "1" can be stored when the numerical data indicating the value of random number MR1-1 for determining special symbols obtained in response to the occurrence of a second start winning is obtained by the hard latch.

Each of the registers with addresses FFF0[H] to FFF2[H] and FF35[H] can store the signal value input at each input port, corresponding to the signal input function using the input port of PIP 105A being in a usable state. Of these, the input port number "0" register with address FFF0[H] can store the signal value input for the input port with port number "0" provided in PIP 105A. The input port number "1" register with address FFF1[H] can store the signal value input for the input port with port number "1" provided in PIP 105A. The input port number "2" register with address FFF2[H] can store the signal value input for the input port with port number "2" provided in PIP 105A. The input port number "3" register with address FF35[H] can store the signal value input for the input port with port number "3" provided in PIP 105A.

In this way, the various circuits included in the game control microcomputer 100 only need to be able to control their respective operating states in response to the values stored in the function control register area. Furthermore, the various circuits included in the game control microcomputer 100 may be able to update the values stored in the function control register area in response to their respective operating states. The function control register area is not limited to the various circuits included in the game control microcomputer 100, and may be a second area for controlling any function.

Figure 10-5 is a diagram for explaining an example of settings in this embodiment for the gaming random numbers shown in Figure 3. The gaming random numbers shown in Figure 3 can be classified into random numbers used to determine the display results in the variable display of special symbols, random numbers used to determine the display results in the variable display of normal symbols, and random numbers used to determine the display mode in the variable display of special symbols and normal symbols, depending on their respective uses.

Figure 10-5 (A) shows a setting example AKA11 of a game random number used to determine the display result in the variable display of a special symbol. The game random numbers in setting example AKA11 include a random number MR1-1 for determining a special symbol, a random number MR1-2 for a winning symbol, and a random number MR1-3 that serves as an initial value for the winning symbol. For example, the random number MR1-1 for determining a special symbol can be used to determine whether the special symbol display result is a "big hit" or a "small hit". The random number MR1-2 for the winning symbol can be used to determine the big hit symbol designation value or the small hit symbol designation value that corresponds to the confirmed special symbol when the special symbol display result is a "big hit" or a "small hit". The random number MR1-3 that serves as the initial value for the winning symbol can be used to set the initial value of the random number MR1-2.

The range of random number MR1-1 is the range of values that can update random number MR1-1, which is "0" to "65535". The size of random number MR1-1 is the total number of random numbers included in the update range of random number MR1-1, which is "65536" corresponding to the range of random number MR1-1, "0" to "65535". Since the size of random number MR1-1 is "65536", the total number of random numbers included in the update range is not a prime number. The number of bytes of numerical data used to update the value of random number MR1-1 is "2". The method for setting the maximum value of random number MR1-1 is by initial setting of a register provided in correspondence with 16-bit random number circuit 104A. The method for updating random number MR1-1 is by hardware update using 16-bit random number circuit 104A. The update condition for random number MR1-1 is the system clock input in 16-bit random number circuit 104A. The conditions for obtaining the random number MR1-1 include a hard latch corresponding to the start winning and reading into the random number buffer by software corresponding to the start winning. The period of the random number MR1-1 is 4.369 [ms].

The range of the random number MR1-2 is the range of values that can update the random number MR1-2, which is "0" to "199". The size of the random number MR1-2 is the total number of random numbers included in the update range of the random number MR1-2, which is "200" corresponding to the range of the random number MR1-2, "0" to "199". Since the size of the random number MR1-2 is "200", the total number of random numbers included in the update range is not a prime number. The number of bytes of the numerical data used to update the value of the random number MR1-2 is "1". The method for setting the maximum value of the random number MR1-2 is by setting the immediate value of the program code. The method for updating the random number MR1-2 is the software update SA1. The update condition for the random number MR1-2 is a timer interrupt due to the passage of a specified time. The acquisition condition for the random number MR1-2 is reading by software corresponding to the start winning. The period of the random number MR1-2 is 800 [ms].

The range of random number MR1-3 is the range of values that can update random number MR1-3, and is the same as random number MR1-2, from "0" to "199". The size of random number MR1-3 is the total number of random numbers included in the update range of random number MR1-3, and is "200", the same as random number MR1-2, corresponding to the range of random number MR1-3, which is "0" to "199". Since the size of random number MR1-3 is "200", the total number of random numbers included in the update range is not a prime number. For random number MR1-3, the number of bytes of numerical data used to update its value is "1". The method for setting the maximum value of random number MR1-3 is by setting the immediate value of the program code. The method for updating random number MR1-3 is software update SA2. The update conditions for random number MR1-3 include a timer interrupt due to the passage of a predetermined time and during loop processing, which is standby processing in the main processing P_MAIN for game control. The condition for obtaining random numbers MR1-3 is that random numbers MR1-2 have completed one cycle. The period for random numbers MR1-3 is indefinite due to the update conditions.

Figure 10-5 (B) shows a setting example AKA12 of a gaming random number used to determine the display result in the variable display of a normal pattern. The gaming random numbers in setting example AKA12 include a random number MR2-1 for a pattern per normal pattern, and a random number MR2-2 that serves as an initial value for the pattern per normal pattern. For example, the random number MR2-1 for a pattern per normal pattern can be used to determine a normal pattern designation value corresponding to a confirmed normal pattern as a display result of the normal pattern. The random number MR2-2 that serves as an initial value for the pattern per normal pattern can be used when setting the initial value of the random number MR1-2.

The range of random number MR2-1 is the range of values that can update random number MR2-1, which is "0" to "198". The size of random number MR2-1 is the total number of random numbers included in the update range of random number MR2-1, which is "199" corresponding to the range of random number MR2-1, "0" to "198". Since the size of random number MR2-1 is "199", the total number of random numbers included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR2-1 is "1". The method for setting the maximum value of random number MR2-1 is by setting an immediate value in the program code. The method for updating random number MR2-1 is software update SA1. The update condition for random number MR2-1 is a timer interrupt due to the passage of a predetermined time. The acquisition condition for random number MR2-1 is a readout by software in response to the game ball passing through pass gate 41, which can be configured as a normal symbol activation port. The period of the random number MR2-1 is 796 [ms].

The range of random number MR2-2 is the range of values that can update random number MR2-2, and is the same as random number MR2-1, from "0" to "198". The size of random number MR2-2 is the total number of random numbers included in the update range of random number MR2-2, and is "199", the same as random number MR2-1, corresponding to the range of random number MR2-2, which is "0" to "198". Since the size of random number MR2-2 is "199", the total number of random numbers included in the update range is a prime number. For random number MR2-2, the number of bytes of numerical data used to update its value is "1". The method for setting the maximum value of random number MR2-2 is by setting an immediate value in the program code. The method for updating random number MR2-2 is software update SA2. The update conditions for random number MR2-2 include a timer interrupt due to the passage of a predetermined time and during loop processing, which is standby processing in the main processing P_MAIN for game control. The condition for obtaining random number MR2-2 is that random number MR2-1 has completed one cycle. The period of random number MR2-2 is indefinite due to its update conditions.

Figure 10-5 (C) shows a setting example AKA13 of a gaming random number used to determine the display mode in the variable display of special and normal symbols. The gaming random numbers in setting example AKA13 include a random number MR3-1 for a normal symbol variable pattern, a random number MR3-2 for selecting a miss effect, a random number MR3-3 for selecting a variable pattern type, and a random number MR3-4 for a variable pattern. For example, the random number MR3-1 for a normal symbol variable pattern can be used to determine a normal symbol variable pattern corresponding to the variable display of a normal symbol. The random number MR3-2 for selecting a miss effect can be used to determine a variable display mode corresponding to the variable display of a special symbol whose special symbol display result is "miss". The random number MR3-3 for selecting a variable pattern type can be used to select a variable pattern type corresponding to the variable display of a special symbol. The random number MR3-4 for the variation pattern can be used to determine the variation pattern that corresponds to the variable display of the special symbol.

The range of random number MR3-1 is the range of values that can update random number MR3-1, which is "0" to "232". The size of random number MR3-1 is the total number of random numbers included in the update range of random number MR3-1, which is "233" corresponding to the range of random number MR3-1, "0" to "232". Since the size of random number MR3-1 is "233", the total number of random numbers included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR3-1 is "1". The method for setting the maximum value of random number MR3-1 is by initial setting of a register provided in correspondence with 8-bit random number circuit 104B. The method for updating random number MR3-1 is by hardware update using 8-bit random number circuit 104B. The update condition for random number MR3-1 is the system clock input in 8-bit random number circuit 104B. The condition for obtaining the random number MR3-1 is the start of fluctuations in the variable display of normal symbols. The period of the random number MR3-1 is 0.249 [ms].

The range of random number MR3-2 is the range of values that can update random number MR3-2, which is "0" to "65518". The size of random number MR3-2 is the total number of random numbers included in the update range of random number MR3-2, which is "65519" corresponding to the range of random number MR3-2, "0" to "65518". Since the size of random number MR3-2 is "65519", the total number of random numbers included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR3-2 is "2". The method for setting the maximum value of random number MR3-2 is by initial setting of a register provided in correspondence with 16-bit random number circuit 104A. The method for updating random number MR3-2 is by hardware update using 16-bit random number circuit 104A. The update condition for random number MR3-2 is the system clock input in 16-bit random number circuit 104A. The conditions for obtaining the random number MR3-2 include reading it into the random number buffer using software that corresponds to the start winning. The period of the random number MR3-2 is 139.774 [ms].

The range of random number MR3-3 is the range of values that can update random number MR3-3, which is "0" to "240". The size of random number MR3-3 is the total number of random numbers included in the update range of random number MR3-3, which is "241" corresponding to the range of random number MR3-3, "0" to "240". Since the size of random number MR3-3 is "241", the total number of random numbers included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR3-3 is "1". The method for setting the maximum value of random number MR3-3 is by initial setting of a register provided in correspondence with 8-bit random number circuit 104B. The method for updating random number MR3-3 is by hardware update using 8-bit random number circuit 104B. The update condition for random number MR3-3 is the system clock input in 8-bit random number circuit 104B. The conditions for obtaining the random number MR3-3 include reading it into a random number buffer using software that corresponds to the start winning. The period of the random number MR3-3 is 0.257 [ms].

The range of random number MR3-4 is the range of values that can update random number MR3-4, which is "0" to "250". The size of random number MR3-4 is the total number of random numbers included in the update range of random number MR3-4, which is "251" corresponding to the range of random number MR3-4, "0" to "250". Since the size of random number MR3-4 is "251", the total number of random numbers included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR3-4 is "1". The method for setting the maximum value of random number MR3-4 is by initial setting of a register provided in correspondence with 8-bit random number circuit 104B. The method for updating random number MR3-4 is by hardware update using 8-bit random number circuit 104B. The update condition for random number MR3-4 is the system clock input in 8-bit random number circuit 104B. The conditions for obtaining the random number MR3-4 include reading it into a random number buffer using software that corresponds to the start winning. The period of the random number MR3-4 is 0.268 [ms].

The software update SA1, which is a method of updating the random numbers MR1-2 and MR2-1, can be updated by adding 1 to the previous value each time the software update process is executed. At this time, if the updated value exceeds the maximum random number value, it is changed to "0" as the minimum random number value. Also, if the updated value matches the random number initial value, the corresponding initial random number is used to set the current random number value and stored as the new random number initial value. For example, for random number MR1-2, if the updated value matches the random number initial value, the current random number value is set using random number MR1-3, which is the initial value for the winning symbol, and the random number value is stored as the new random number initial value. For random number MR2-1, if the updated value matches the random number initial value, the current random number value is set using random number MR2-2, which is the initial value for the winning symbol for normal symbols, and the random number value is stored as the new random number initial value.

Software update SA2, which is a method of updating random numbers MR1-3 and MR2-2, can update the previous value by adding 1 each time the software update process is executed. If the updated value exceeds the maximum random number value at this time, it is changed to "0", the minimum random number value. In this case, unlike software update SA1, no random number initial value is used, so the updated value will be either the previous value plus 1, or the minimum random number value of "0".

Figure 10-6 is a diagram for explaining the random number update period when updating random values using the 16-bit random number circuit 104A and 8-bit random number circuit 104B included in the random number circuit 104. Here, the random numbers that can be generated by channels RL0 to RL4 provided in the 16-bit random number circuit 104A are referred to as 16-bit random numbers RLn. Also, the random numbers that can be generated by channels RS0 to RS4 provided in the 8-bit random number circuit 104B are referred to as 8-bit random numbers RSn. The period in which the 16-bit random numbers RLn that can be updated by the 16-bit random number circuit 104A completes one cycle is determined by different relational expressions depending on whether the maximum value of the 16-bit random number RLn is a specific maximum value expressed using a power of two. The period in which the 8-bit random number RSn, which can be updated by the 8-bit random number circuit 104B, goes through one cycle is determined by a different relational formula depending on whether the maximum value of the 8-bit random number RSn is a specific maximum value expressed using a power of 2.

FIG. 10-6(A) shows a 16-bit random number period setting example AKA21 in a 16-bit random number circuit 104A. The 16-bit random number period is the period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A makes one revolution. In the 16-bit random number period setting example AKA21, if the maximum value of the 16-bit random number RLn corresponds to 2 ^m -1 when m=9 to 16, the period in which the 16-bit random number sequence makes one revolution is proportional to the inverse of the count clock frequency, that is, the count clock period. Then, it becomes a linear function in which the value obtained by adding 1 to the maximum value, that is, the magnitude of the 16-bit random number RLn, is a variable. On the other hand, if the maximum value of the 16-bit random number RLn does not correspond to 2 ^m -1 when m=9 to 16, the period in which the 16-bit random number sequence makes one revolution is proportional to the inverse of the count clock frequency, that is, 32 times the count clock period. Then, it becomes a linear function with the maximum value plus 1, i.e., the magnitude of the 16-bit random number RLn as a variable. In this way, when the maximum value of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is a specific maximum value, the random number update period is shorter, i.e., the update speed of the random number value is faster, than when the maximum value is other than the specific maximum value.

FIG. 10-6(B) shows an example AK22 of setting an 8-bit random number period in the 8-bit random number circuit 104B. The 8-bit random number period is the period in which the 8-bit random number RSn, which can be updated by the 8-bit random number circuit 104B, completes one cycle. In the example AK22 of setting an 8-bit random number period, if the maximum value of the 8-bit random number RSn corresponds to 2 ^m -1 when m=5 to 8, the period in which the 8-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., the count clock period. Then, it becomes a linear function in which the value obtained by adding 1 to the maximum value, i.e., the magnitude of the 8-bit random number RSn, is used as a variable. On the other hand, if the maximum value of the 8-bit random number RSn does not correspond to 2 ^m -1 when m=5 to 8, the period in which the 8-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., 16 times the count clock period. Then, it becomes a linear function with the maximum value plus 1, that is, the magnitude of the 8-bit random number RSn as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is a specific maximum value, the random number update period is shorter, that is, the update speed of the random number value is faster, than when the maximum value is other than the specific maximum value.

Figure 10-6 (C) shows a random number comparison example AKA23 that compares the random number values that can be updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B. The 16-bit random number circuit 104A can update the random number values corresponding to the random number MR1-1 for determining a special pattern and the random number MR3-2 for selecting a losing performance. The 8-bit random number circuit 104B can update the random number values corresponding to the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for the variation pattern.

The random number MR1-1 has a maximum value of "65535", which corresponds to 2 ^m -1 when m = 16. This results in a period of 4.369 [ms], and an update speed of 15000 [times/ms]. The random number MR3-2 has a maximum value of "65518", which does not correspond to 2 ^m -1 when m = 9 to 16. This results in a period of 139.774 [ms], and an update speed of 469 [times/ms]. The random number MR3-3 has a maximum value of "240", which does not correspond to 2 ^m -1 when m = 5 to 8. This results in a period of 0.257 [ms], and an update speed of 938 [times/ms]. The random number MR3-4 has a maximum value of "250," which does not correspond to 2 ^m -1 for any of m = 5 to 8. As a result, the period of the random number MR3-4 is 0.268 [ms], and the update speed at this time is 938 [times/ms].

In this way, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include the random number MR1-1 for determining special symbols and the random number MR3-2 for selecting a losing effect. Both of these random numbers MR1-1 and MR3-2 have a number of bytes of numerical data of "2", which is a specific number of bytes. The size of the random number MR1-1 is "65536" and the size of the random number MR3-2 is "65519", so if the total number of random numbers included in the update range of the random number MR1-1 is a specific number, the total number of random numbers included in the update range of the random number MR3-2 is a predetermined number smaller than the specific number. The update speed of the random number MR1-1 is 15000 [times/ms] and the update speed of the random number MR3-2 is 469 [times/ms], so the update speed of the random number MR1-1 is faster than that of the random number MR3-2. This prevents random numbers from being synchronously generated, allowing for appropriate updates to random numbers.

Furthermore, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR3-2 for selecting a losing effect. The gaming random numbers that can be updated by the 8-bit random number circuit 104B include a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern. The total number of random numbers included in the update range of all of these random numbers MR3-2 to MR3-4 is a prime number. The update speed of the random number MR3-2 is 469 times/ms, while the update speed of the random numbers MR3-3 and MR3-4 is 938 times/ms. In other words, the update speed of the random numbers MR3-3 and MR3-4 is twice the update speed of the random number MR3-2, which is an integer multiple. Therefore, if random number MR3-2 is the first random number value, and random numbers MR3-3 and MR3-4 are the second random number values, the first random number value has an update speed of the first speed, and the second random number value has an update speed of the second speed that is an integer multiple of the first speed. The update range of random number MR3-2 is "0" to "65518", the update range of random number MR3-3 is "0" to "240", and the update range of random number MR3-4 is "0" to "250", so the total number of random number values included in each update range is different for the first random number value and the second random number value, and the total number of random number values included in each update range is a prime number. This makes it possible to suppress the occurrence of synchronization of random number values and update the random number values appropriately.

The CPU 103 is provided with multiple registers, such as a program counter, an interrupt register, a stack pointer, an index register, a flag register, an address register, and general-purpose registers including an accumulator. The index register, the flag register, and the general-purpose register may be provided as a main register and a sub-register. The registers included in the main register and the sub-register, and the stack pointer may be provided so as to be able to configure multiple register banks. The multiple register banks may include a first register bank for use within an area that can be used when executing a game program, and a second register bank for use outside the area that can be used when executing a non-game program. This eliminates the need to save and restore stored values in the general-purpose registers, etc., to and from the stack area when switching between game programs and non-game programs, for example, and prevents an increase in the amount of programs and processing load.

The program counter, also known as the PC register, is used to hold the address value of the next instruction to be executed by the CPU 103. The value stored in the program counter is counted up sequentially each time an instruction is executed, and the address value of the branch destination of a branch instruction is set. The interrupt register, also known as the I register, can hold the upper address value of the interrupt vector table. The value stored in the I register is set in response to the start of power supply to the pachinko gaming machine 1.

The stack pointer can hold an address value corresponding to the game stack area or the non-game stack area, and is also called the SP register. The stored value of the stack pointer can specify a destination address for saving and holding a stored value or immediate value in a predefined register including the program counter or a register specified by an instruction in response to an interrupt occurrence, execution of a PUSH instruction, execution of a subroutine call instruction such as a CALL instruction, a CALLF instruction, or a RST instruction, and is updated to a value indicating the top address of the storage area holding the stored value upon saving. The stored value of the stack pointer can also specify a read address for restoring the saved register stored value in response to the end of an interrupt process, execution of a POP instruction, end of a subroutine process, and is updated to a value indicating the address corresponding to the readout of the stored value upon this return. In addition, the stored value of the stack pointer can be set to a stored value or immediate value of a register specified by a load instruction such as an LD instruction.

The index registers include the IX register and the IY register, which have a storage capacity of 2 bytes and can store 16-bit data. The accumulator is also called the A register. Other general-purpose registers include a number of registers, such as the B register, C register, D register, E register, H register, and L register, which have a storage capacity of 1 byte and can store 8-bit data. The B register and the C register can be used as the BC register of a pair of registers that can store 16-bit data. The D register and the E register can be used as the DE register of a pair of registers that can store 16-bit data. The H register and the L register can be used as the HL register of a pair of registers that can store 16-bit data.

The internal registers of the CPU 103 can update the stored values in response to calculation instructions and transfer instructions executed by the CPU 103, and are used to specify program addresses, data addresses, or built-in register addresses provided in the game control microcomputer 100, to hold calculation data and transfer data, etc.

In the game control microcomputer 100, the instruction set for causing the CPU 103 to execute a program is composed of transfer instructions such as load instructions, subroutine call instructions, jump instructions, other calculation instructions including arithmetic operation instructions and logical operation instructions, input/output instructions, etc. Computer programs such as game programs and non-game programs that can be executed by the CPU 103 are prepared in advance as program code that describes these various instructions, and are stored in the ROM 101.

The load instruction is a transfer instruction that can be used when data read from a memory area or built-in device area of ROM 101 or RAM 102 is stored and set in an internal register of CPU 103, when a value stored in an internal register of CPU 103 is written and stored in a memory area or built-in device area of RAM 102, and when a numerical value specified by an operand is set or stored as an immediate value in an internal register of CPU 103 or a memory area or built-in device area of RAM 102. The target to which data is transferred by the load instruction can be specified according to the instruction code or operand, and generally includes the source and destination of the data. However, when an immediate value is specified by the operand, the source of the data is not included.

The load instructions include a normal LD instruction, a special LDQ instruction, a special LDF instruction, and a special ICPLD instruction. The normal LD instruction is also called a normal transfer instruction. The special LDQ instruction is also called a first special transfer instruction. The special LDF instruction is also called a second special transfer instruction. The special ICPLD instruction is also called a third special transfer instruction.

The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can transfer data by specifying both a high-order address and a low-order address when transferring data to a storage area or built-in device area of ROM 101 or RAM 102. In addition, the LD instruction, which is a normal transfer instruction, can transfer data by specifying the destination or source address using a pointer by using a pair register such as the HL register as a pointer when transferring data to a storage area or built-in device area of ROM 101 or RAM 102.

The first special transfer instruction, the LDQ instruction, can transfer data by specifying only the lower address using the Q register, a special register included in the internal registers of the CPU 103. A value indicating the upper address is preset in the Q register, and by combining this with the lower address specified by the LDQ instruction, it is possible to specify the destination or source address and transfer data.

The LDQ instruction, which is the first special transfer instruction, can transfer data with less program code than the LD instruction, which is the normal transfer instruction. However, in a program that frequently changes the value stored in the Q register, the amount of program code may actually be greater than with the normal LD instruction. Therefore, it is sufficient to be able to execute data transfers using the LDQ instruction, which is the first special transfer instruction, in response to processes that require the transfer of various data multiple times to the game work area at addresses F000 [H] to F0D7 [H], the function setting register area at addresses FE00 [H] to FEBF [H], and the function control register area at addresses FF00 [H] to FFFF [H].

The second special transfer command, the LDF command, can transfer data by specifying only the lower addresses of stored data in a specific address range. The specific address range is, for example, the range of addresses 1200 [H] to 1DFF [H]. Therefore, by setting the game data area of ROM 101 in advance to be included in this specific address range and combining it with the lower address specified by the LDF command, it is possible to specify the address from which data is to be transferred. Note that the game data area of ROM 101 is read-only and cannot be written to, so the address of the game data area is never specified as the destination address.

The second special transfer command, the LDF command, can transfer data with a smaller amount of program code than the normal transfer command, the LD command. However, since the specific address range is fixed by specification, it is sufficient to set the storage area of frequently used data, such as the game data area of ROM 101, to be included in the specific address range, and to be able to transfer data using the second special transfer command, the LDF command.

The ICPLD instruction, which is the third special transfer instruction, compares the update target value with the comparison judgment value, and updates the update target value by adding 1 if the update target value is less than the comparison judgment value, but changes the update target value to the minimum value "0" if the update target value is equal to or greater than the comparison judgment value. The update target value may be the value indicated by the stored data at the address pointed to by the pointer, or may be the value stored in a register. The comparison judgment value may be the value stored in a register, or may be the value indicated by the operand of the ICPLD instruction.

In this way, the third special transfer instruction, the ICPLD instruction, is a single compare and add instruction that includes comparing the update target value with the comparison judgment value, incrementing the update target value by 1 if the comparison result is less than the comparison judgment value, and changing the update target value to the minimum value if the comparison result is equal to or greater than the comparison judgment value.

Setting a stored value in an internal register of CPU 103 using an immediate value from an operand of a transfer command is also called "set." Reading stored data in the game data area of ROM 101 or the game work area of RAM 102 and storing it in an internal register of CPU 103 is also called "load." Storing a stored value in an internal register of CPU 103 in a buffer, counter, timer, or any other storage area provided in the game work area of RAM 102 is also called "store."

Figure 10-7 is a flow chart showing an example of the power supply start response processing P_POWER_ON. The power supply start response processing P_POWER_ON is included in the processing that can be called from the main processing P_MAIN for game control shown in Figure 4, and can be executed in step S1 in response to the start of power supply in the pachinko game machine 1. When the CPU 103 executes the power supply start response processing P_POWER_ON, it sets interrupt prohibition (step AKS1) and then sets the in-area stack pointer initial value to the stack pointer (step AKS2). The in-area stack pointer initial value may be address F200 [H], which is the final address of the game stack area plus 1, corresponding to the initial state in which no saved data is stored in the game stack area.

Following step AKS2, a connection confirmation signal ON output value is set by a transfer command for setting the internal register of CPU 103 (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is ON, and may be, for example, 00 [H]. At this time, a function control register upper address is set in the Q register by a transfer command for setting the Q register included in the internal register of CPU 103 (step AKS4). The function control register upper address is a value FF [H] indicating the upper address of the function control register area in the setting example AKA02 shown in FIG. 10-4. When the function control register upper address is set in this way, a transfer command using the upper address indicated by the stored value of the Q register stores the connection confirmation signal ON output value (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer command. The stored value of the Q register is set to the upper address of the function control register area by step AKS4. Therefore, the connection confirmation signal ON output value set in step AKS3 can be stored in the function control register of the specified address in the function control register area by a transfer command for writing to a memory area of a specified address, such as a special 2-byte LDQ command that specifies a lower address. In step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. As a result, the connection confirmation signal transmitted from the main board 11 to the dispensing control board is set to the ON state.

When the connection confirmation signal is set to the ON state in step AKS5, the SCU0 command register clear output value is stored by a transfer command using the upper address indicated by the stored value of the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer command. The stored value of the Q register is set to the upper address of the function control register area in step AKS4. The SCU0 command register clear output value can be specified by the operand of the transfer command. Therefore, the SCU0 command register clear output value can be stored in the function control register of the specified address in the function control register area by a transfer command for writing to a memory area of a specified address, such as a 3-byte special LDQ command that specifies a lower address and the SCU0 command register clear output value. In step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register provided at address FF28 [H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using channel SCU0 of the serial communication circuit 139 is controlled to the initial state.

After step AKS6, the SCU1 command register clear output value is stored by a transfer command using the upper address indicated by the stored value of the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer command. The stored value of the Q register is set to the upper address of the function control register area by step AKS4. The SCU1 command register clear output value can be specified by the operand of the transfer command. Therefore, the SCU1 command register clear output value can be stored in the function control register of the specified address in the function control register area by a transfer command for writing to a memory area of a specified address, such as a 3-byte special LDQ command that specifies a lower address and the SCU0 command register clear output value. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register provided at address FF2C[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using the channel SCU1 of the serial communication circuit 139 is controlled to the initial state.

When these serial communication functions are controlled to the initial state, a transfer command for setting the internal registers of CPU 103 sets the interrupt vector table upper address (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of ROM 101. The interrupt vector table stores the top address at a table position corresponding to the interrupt priority for, for example, timer interrupt processing P_PCT for game control that is executed in response to the occurrence of a timer interrupt. Such an interrupt vector table upper address is set in the I register by a transfer command for setting the internal registers of CPU 103 (step AKS9).

After step AKS9, the stored value of the Q register is updated to subtract 1 (step AKS10). The stored value of the Q register was set to the upper address of the function control register area by step AKS4. When this stored value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in FIG. 10-3 is stored in the Q register. In this way, after the function control register set in the function control register area is set, the function setting register set in the function setting register area is made settable. At this time, the function setting register storage value table address is set by a transfer command for setting the pointer (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of ROM 101. Then, the number of processes is loaded by a transfer command for reading the stored data of the address pointed to by the pointer (step AKS12). Also, setting is performed using the function setting register storage value table by a function setting register store command (step AKS13). The function setting register store instruction may be an instruction to specify a function setting register based on the stored data at the address when the address pointed to by the pointer is added by 1, to store the function setting register setting value indicated by the stored data at the address when the address pointed to by the pointer is added by 2 in the specified function setting register, to add 2 to the stored value of the pointer, and to subtract 1 from the processing count, repeating this process until the processing count becomes 0. In this way, the initial setting of the function setting register is possible.

When the initial setting of the function setting register is completed in step AKS13, an access permission output value is stored in the RWM access protection register (step AKS14). The access permission output value of the RWM access protection register is set to, for example, 01 [H] by a transfer command for setting the internal register of the CPU 103. Such an access permission output value is stored in the RWM access protection register by a transfer command for writing to the memory area of the top address in the function setting register area. The RWM access protection register enables function control to allow access to the RAM 102, which is the RWM, in response to the setting of the access permission output value 01 [H]. Therefore, by storing the access permission output value in the RWM access protection register in step AKS14, access to the RAM 102 is permitted in response to the start of power supply in the pachinko gaming machine 1.

After step AKS14, the upper address of the game work area, which is the working area of RAM 102, is set in the Q register (step AKS15), and the power supply start response process P_POWER_ON ends. In this way, after access to RAM 102 is permitted by step AKS14, a value F0 [H] indicating the upper address of the game work area in RAM 102 is set in the Q register. After step AKS15, when the LDQ command, which is the first special transfer command, is executed, F0 [H], which is the value stored in the Q register, can be used as the upper address of the transfer destination or source without being specified by an operand. This reduces the program capacity of the process using the game work area in RAM 102, improving the marketability of the gaming machine.

Figure 10-8 shows a configuration example AKT01 of the function setting register storage value table used in the power supply start response process P_POWER_ON. In the power supply start response process P_POWER_ON, for example, the function setting register storage table whose address is set in step AKS11 is used to load the number of processes in step AKS12, and the stored values of each function setting register are stored by the function setting register store command in step AKS13. The function setting register storage value table of configuration example AKT01 stores a value of 18 [H] indicating the number of processes at the top address 1200 [H]. In step AKS12, this table data is read and loaded into the internal register of the CPU 103. After that, the function setting register store command in step AKS13 sequentially reads table data that combines the lower addresses and stored values of the function setting registers, and makes it possible to store the stored values in the function setting registers corresponding to each lower address.

In the function setting register storage value table of configuration example AKT01, the table data is configured so that the stored value of the function setting register with a smaller value indicating the lower address can be set first, and the stored value of the function setting register with a larger value indicating the lower address can be set later. As a result, in the function setting register area, the stored values of each function setting register are set in the order of the stored value of the function setting register closest to the top address being set first, and the stored value of the function setting register closest to the final address being set last. This makes it easier to design and manage the data indicating the stored values of the function setting registers, improving the marketability of the gaming machine.

The 16-bit random number circuit 104A can start updating from the channel whose maximum value is set in the maximum value setting register corresponding to the four channels RL0 to RL3. The 8-bit random number circuit 104B can start updating from the channel whose maximum value is set in the maximum value setting register corresponding to the four channels RS0 to RS3. The function setting register area of the setting example AKA01 shown in Figure 10-3 is provided with an RL0 maximum value setting register at addresses FE3F[H] to FE40[H], an RL1 maximum value setting register at addresses FE41[H] to FE42[H], an RL2 maximum value setting register at addresses FE43[H] to FE44[H], and an RL3 maximum value setting register at addresses FE45[H] to FE46[H] corresponding to the four channels RL0 to RL3 in the 16-bit random number circuit 104A. In addition, this function setting register area includes an RS0 maximum value setting register at address FE47 [H], an RS1 maximum value setting register at address FE48 [H], an RS2 maximum value setting register at address FE49 [H], and an RS3 maximum value setting register at address FE4A [H], which correspond to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. In the function setting register storage value table of the configuration example AKT01, the table data is configured so that, among these maximum value setting registers, the stored value of the RL0 maximum value setting register is set first, the stored value of the RL2 maximum value setting register is set next, the stored value of the RS1 maximum value setting register is set next, the stored value of the RS2 maximum value setting register is set next, and the RS3 maximum value setting register is set last. Therefore, the update of channel RL0 in the 16-bit random number circuit 104A is started first, the update of channel RL2 in the 16-bit random number circuit 104A is started next, the update of channel RS1 in the 8-bit random number circuit 104B is started next, the update of channel RS2 in the 8-bit random number circuit 104B is started next, and the update of channel RS3 in the 8-bit random number circuit 104B is started last. In this way, since the updates start in order from the random number value for which the maximum random number value is set, the uncertainty of the random number value is increased depending on the timing at which the update of the random number value is started, the processing load is reduced, and appropriate random number value updating is possible.

The power supply start response process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control, which is a startup process executed based on the start of power supply in the pachinko game machine 1, and makes it possible to set a stored value in the function setting register area as a storage area for functions using the function setting register storage value table of the configuration example AKT01. At this time, since the maximum random number value of the random number value updated by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B can be set, the power supply start response process P_POWER_ON can be executed as a maximum value setting process. The 16-bit random number circuit 104A can update a first random number value consisting of 16 bits corresponding to 2 bytes as a specific byte number. The 8-bit random number circuit 104B can update a second random number value consisting of 8 bits corresponding to 1 byte as a predetermined byte number smaller than the specific byte number. Then, when executing the power supply start response process P_POWER_ON, the function setting register storage value table of the configuration example AKT01 is used to set the maximum random number value of the first random number value that can be updated by the 16-bit random number circuit 104A, and then set the maximum random number value of the second random number value that can be updated by the 8-bit random number circuit 104B. In this way, by setting the first random number value of a specific number of bytes and then setting the second random number value of a predetermined number of bytes, the first random number value and the second random number value can be stably updated, making it possible to update the random number values appropriately.

Figure 10-9 shows an example of the configuration of the RWM access protection register. The RWM access protection register is provided at address FF00[H] in the example configuration AKA02 of the function control register area shown in Figure 10-4. The value stored in the RWM access protection register will be different depending on whether access to the RAM 102 that is the RWM is prohibited or permitted.

Figure 10-9 (A) shows an example of the bit configuration of the RWM access protection register. The RWM access protection register can store 8-bit data RAP with bit numbers "0" to "7", and bit data RAP0 with bit number "0" can be set to 0 [B] or 1 [B]. In contrast, bit data from bit number "1" to bit number "7" are always set to 0 [B], indicating a fixed value that is never set to "1".

Figure 10-9 (B) is a diagram for explaining an example of the use of bit data RAP of the RWM access protection register. In the bit data RAP, bit data RAP0 with bit number "0" is an RWM access control bit, and a setting of 0 [B] prohibits access to the RWM, and a setting of 1 [B] permits access to the RWM. In response to the start of power supply to the pachinko gaming machine 1, bit data RAP0 with bit number "0" is set to its initial value of 0 [B]. This makes it possible to prohibit access to the RAM 102, which becomes the RWM, in response to the start of power supply to the pachinko gaming machine 1.

Figure 10-10 is a flowchart showing an example of power-off processing P_POWER_OFF. Power-off processing P_POWER_OFF is included in the processing that can be called from the timer interrupt processing P_PCT for game control shown in Figure 5, and can be executed in step S51 each time a timer interrupt occurs. When the CPU 103 executes power-off processing P_POWER_OFF, it sets the backup monitoring timer address by a transfer command for setting a pointer (step AKS31). The backup monitoring timer address is the address of the backup monitoring timer provided in the game work area of RAM 102.

Input port number "3" is input (step AKS32). Input port number "3" is an input port to which "3" is assigned as the port number, and includes a power check signal input bit. Therefore, a logical AND operation is performed using the input data of input port number "3" and the check data corresponding to the bit position of the power check signal input bit. At this time, it is determined whether the power check signal input bit is "0" or not depending on whether the zero flag is on or not (step AKS33). When the power check signal input bit's bit value is 0 [B] corresponding to "0", it indicates that the power check signal is in the OFF state, and when the bit value is 1 [B] corresponding to "1", it indicates that the power check signal is in the ON state.

If the power supply confirmation signal input bit is "1" rather than "0" (step AKS33; No), backup monitoring timer clear data is stored by a transfer command capable of updating the stored data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing the clear data in the backup monitoring timer, the backup monitoring timer can be cleared when the power supply confirmation signal is in the ON state, in response to a state other than the power cut determination being made.

When the power supply confirmation signal input bit is "0" in response to step AKS33 (step AKS33; Yes), the backup monitoring timer is updated to add 1 to the time value (step AKS35). Also, the backup monitoring timer is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AKS36). Then, by a calculation return command capable of comparing the time value of the backup monitoring timer with the judgment value corresponding to the backup judgment time (step AKS37), it is confirmed that the backup monitoring timer does not indicate the backup judgment time (step AKS38). This calculation return command corresponds to a zero flag that is turned off when the time value of the backup monitoring timer and the judgment value corresponding to the backup judgment time are different, and enables the power off process to be terminated and a return to the special symbol process process to be made. Thus, when the backup monitoring timer does not indicate the backup judgment time (step AKS38; Yes), the power off process is terminated.

When the backup monitoring timer indicates the backup judgment time in response to step AKS38 (step AKS38; No), the checksum calculation process P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC in step AKS39 may be a process common to the checksum calculation process included in the RWM check process P_RWM_CHK in step S2 in the main process P_MAIN for game control shown in FIG. 4. In this way, by executing a common checksum calculation process in response to the start and stop of power supply in the pachinko game machine 1, it becomes possible to determine whether or not recovery using backup data is possible depending on whether the memory contents in the game work area of RAM 102 are retained without change. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer command for writing to the memory area of the address pointed to by the pointer (step AKS40).

After step AKS40, the clear data is set to the output value data by an exclusive OR operation command (step AKS41). This exclusive OR operation command operates the exclusive OR of the stored values of a single register, so that all bit values become the exclusive OR of the same value, and the stored value can be initialized to the clear data of 00 [H]. Such clear data is stored in the RWM access protection register by a transfer command for writing to the memory area of the top address in the function setting register area (step AKS42). The RWM access protection register enables function control to prohibit access to the RAM 102, which is the RWM, in response to the setting of the clear data, 00 [H]. Therefore, by storing the clear data in the RWM access protection register by step AKS42, access to the RAM 102 is prohibited in response to the stop of the power supply to the pachinko game machine 1.

After step AKS42, the output port numbers "0" to "10" are cleared (step AKS43). The output port numbers "0" to "10" are the output ports with port numbers "0" to "10", and are all the output ports in the game control microcomputer 100. Therefore, in response to the stop of the power supply in the pachinko game machine 1, all the output ports in the game control microcomputer 100 are set to a clear state by step AKS43. At this time, a connection confirmation signal off output value is set by a transfer command for setting the internal register of the CPU 103 (step AKS44). The connection confirmation signal off output value is a value indicating that the connection confirmation signal is in an off state, and may be, for example, 01 [H]. Such a connection confirmation signal off output value is stored in the output port number "1" register by a transfer command for writing to a memory area of a specified address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to an off state.

Following step AKS45, a PTC0 interrupt inhibit output value is set by a transfer command for setting an internal register of the CPU 103 (step AKS46). The PTC0 interrupt inhibit output value is an output value for inhibiting the occurrence of a timer interrupt using channel PTC0 of the timer circuit 136. This PTC0 interrupt inhibit output value is stored in the PTC0 control register by a transfer command for writing to a function setting register at a specified address in the function setting register area (step AKS47). The PTC0 control register can set the usage state of the timekeeping function using channel PTC0 of the timer circuit 136. In step AKS47, the PTC0 interrupt inhibit output value set in step AKS46 is stored in the PTC0 control register, and accordingly, in response to the stop of the power supply to the pachinko gaming machine 1, the timer interrupt for game control is set to the inhibited state.

When the setting corresponding to the lapse of the backup determination time is made, the system transitions to a standby state by executing a loop process. In this standby state, the input port number "3" is input (step AKS48), and it is determined whether the power supply confirmation signal input bit is "0" (step AKS49). If the power supply confirmation signal is in the OFF state and the power supply confirmation signal input bit is "0" (step AKS49; Yes), the system continues the loop process returning to step AKS48. In this way, by maintaining a standby state until operation stops due to a power outage in response to a power supply interruption in the pachinko gaming machine 1, it is possible to prevent inconvenient changes to stored data and runaway processing by the CPU 103.

If the power check signal input bit is "1" and not "0" in response to step AKS49 (step AKS49; No), the power interruption recovery vector table address is set to the stack pointer (step AKS50), and the power interruption process P_POWER_OFF is terminated by an interrupt return command. The power interruption recovery vector table address is the address of the power interruption recovery vector table provided in the game program area of ROM 101. The interrupt return command can use the stack pointer as a pointer to set the stored data of the memory area indicated by the address specified by the stored value of the stack pointer to the program counter. For example, the stored data of the memory area indicated by the address specified by the stored value of the stack pointer is set to the lower byte of the program counter, and the stored data of the memory area indicated by the address specified by the value obtained by adding 1 to the stored value of the stack pointer is set to the upper byte of the program counter.

Figures 10-11 are diagrams for explaining examples of data configurations related to power-off processing P_POWER_OFF. In power-off processing P_POWER_OFF, for example, step AKS38 executes branch processing using the time value of the backup monitoring timer, and step AKS40 saves checksum data using a checksum buffer. In addition, step AKS50 sets a vector table address for power-off recovery, so that if the operation does not stop after a power supply interruption is detected in the pachinko gaming machine 1 and normal power supply is resumed, the game control program can be executed from the beginning. In this way, power-off processing P_POWER_OFF uses the backup monitoring timer, checksum buffer, and power-off recovery vector table to enable control when the power supply to the pachinko gaming machine 1 is interrupted.

Figure 10-11 (A) shows a configuration example AKB01 of a memory area that serves as a backup data area. The backup data area of configuration example AKB01 can store backup setting data that is used when backing up stored data in the game work area of RAM 102. This backup data area includes a backup monitoring timer at address F000 [H] and a checksum buffer at address F0DE [H]. Address F000 [H] is the first address of the game work area, and address F0DE [H] is the last address of the game work area. In this way, by providing a backup data area at the first address and the last address of the game work area, it is possible to properly back up stored data in the game work area of RAM 102.

Figure 10-11 (B) shows a configuration example AKT11 of a vector table at the time of power interruption recovery. The power interruption recovery vector table of the configuration example AKT11 can specify a return address from the power interruption process in response to an interrupt return command when normal power supply is resumed. The power interruption recovery vector table is configured to include, as table data, lower address designation data 00 [H] stored at address 0016 [H] in the game program area of ROM 101 and upper address designation data 00 [H] stored at address 0017 [H] in the game program area of ROM 101. In step AKS50 of the power interruption process P_POWER_OFF, data indicating address 0016 [H] is set in the stack pointer as the vector table address at the time of power interruption recovery. After that, the stored value of the program counter is set to 0000 [H] by an interrupt return command to return the process, making it possible to execute the main process P_MAIN for game control from the beginning.

Figure 10-12 is a flowchart showing an example of the random number update process P_RANDOM. The random number update process P_RANDOM is included in the process that can be called from the timer interrupt process P_PCT for game control shown in Figure 5, and can be executed in step S56 in response to the occurrence of a periodic timer interrupt due to the passage of a predetermined time, for example, 4 ms. On the other hand, the random number update process P_RANDOM is not included in the process that can be called from the main process P_MAIN for game control shown in Figure 4, and is not executed in the loop process that is repeated until a timer interrupt occurs after step S7. Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt due to the passage of a predetermined time, it is not included in the second process that can be repeatedly executed until the first process is executed. In addition, the random number update process P_RANDOM can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, but in the main process P_MAIN for game control that is executed based on the start of power supply in the pachinko game machine 1, it is not called and cannot be executed in the standby process as a repeated loop process after startup processes such as the power supply start response process P_POWER_ON in step S1.

The random number update process P_RANDOM uses internal registers of the CPU 103, such as the B register, DE register, and HL register, to update the numerical data indicating the values of the random number MR1-2 for the winning symbol and the random number MR2-1 for the normal and winning symbols. The random number MR1-2 for the winning symbol is used to determine the confirmed special symbol that is the display result of the special symbol, corresponding to the special symbol game, which is a variable display of the special symbol on the first special symbol display device 4A or the second special symbol display device 4B. The random number MR2-1 for the normal and winning symbol is used to determine the confirmed normal symbol that is the display result of the normal symbol, corresponding to the normal symbol game, which is a variable display of the normal symbol on the normal symbol display device 20. The random number update process P_RANDOM can update the random number value for each of the following two cases: when updating the random number MR1-2 for the winning symbol, and when updating the random number MR2-1 for the normal winning symbol, by using the B register, DE register, and HL register as common internal registers.

When the CPU 103 executes the random number update process P_RANDOM, it sets the random number counter address for the winning symbol by a transfer command for setting the HL register used as a random number pointer (step AKS61). The random number counter address for the winning symbol is the address of the random number counter for the winning symbol provided in the game work area of the RAM 102. The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, the random number MR1-2 for the winning symbol can be set as the random number value to be updated by storing the address of the random number counter for the winning symbol in the random number pointer by the LDQ command.

Following step AKS61, a transfer command is issued to set the B register to be used as the random number maximum register, and a random number maximum value corresponding to the random number maximum judgment value for the winning symbol is set (step AKS62). The random number maximum register can store the maximum value that the random number to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for the random number MR1-2 for the winning symbol, the maximum value included in the update range of the random number MR1-2, such as C7 [H] corresponding to "199", is stored in the random number maximum register by the LD command. This makes it possible to set the maximum random number of the random number MR1-2 that was set as the random number to be updated in step AKS61.

After step AKS62, the random number initial value data buffer address for the winning symbol is set by a transfer command to set the DE register used as the initial value pointer (step AKS63). The random number initial value data buffer address for the winning symbol is the address of the random number initial value data buffer for the winning symbol provided in the game work area of RAM 102. The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and the random number initial value can be obtained or changed by setting the stored value. In step AKS63, the address of the random number initial value data buffer for the winning symbol is stored in the initial value pointer by the LDQ command, thereby setting the random number initial value to be obtainable and changeable corresponding to the random number MR1-2 set as the random number to be updated by step AKS61. Next, the initial value change random number update process P_RANCP is executed by a subroutine call command (step AKS64). The initial value change random number update process P_RANCP in step AKS64 makes it possible to update the random numbers MR1-2 for the winning symbols, which are the random number values to be updated, and to change the random number initial value, based on the settings in steps AKS61 to AKS63.

After the initial value change random number update process P_RANCP in step AKS64, the random number counter address for the normal symbol is set by a transfer command to set the HL register used as a random number pointer (step AKS65). The random number counter address for the normal symbol is the address of the random number counter for the normal symbol provided in the game work area of RAM 102. In step AKS65, the random number MR2-1 for the normal symbol can be set as the random number value to be updated by storing the address of the random number counter for the normal symbol in the random number pointer by the LDQ command.

Following step AKS65, a transfer command is issued to set the B register used as the random number maximum register, and a random number maximum value corresponding to the random number maximum judgment value for the normal symbol pattern is set (step AKS66). In step AKS66, for the random number MR2-1 for the normal symbol pattern, the maximum value included in the update range of the random number MR2-1, for example C6[H] corresponding to the maximum value "198", is stored in the random number maximum register by the LD command. This makes it possible to set the random number maximum value of the random number MR2-1 that was set as the random number value to be updated in step AKS65.

After step AKS66, the random number initial value data buffer address for the normal symbol is set by a transfer command to set the DE register used as the initial value pointer (step AKS67). The random number initial value data buffer address for the normal symbol is the address of the random number initial value data buffer for the normal symbol provided in the game work area of RAM 102. In step AKS67, the address of the random number initial value data buffer for the normal symbol is stored in the initial value pointer by the LDQ command, and the random number initial value for the random number MR2-1 set as the random number value to be updated in step AKS65 is set to be obtainable and changeable. Next, the initial value change random number update process P_RANCP is executed by a subroutine call command common to step AKS64 (step AKS68). The initial value change random number update process P_RANCP in step AKS68 makes it possible to update the random number MR2-1 for the normal winning symbol, which is the random number value to be updated, and to change the random number initial value, based on the settings in steps AKS65 to AKS67.

Figure 10-13 is a diagram for explaining an example of the use of data configuration related to the random number update process P_RANDOM. In the random number update process P_RANDOM, the initial value change random number update process P_RANCP is executed in step AKS64 using the random number counter for winning symbols whose address is set in the random number pointer in step AKS61 and the random number initial value data buffer for winning symbols whose address is set in the initial value pointer in step AKS63. In addition, in the random number update process P_RANDOM, the initial value change random number update process P_RANCP is executed in step AKS68 using the random number counter for winning normal symbols whose address is set in the random number pointer in step AKS65 and the random number initial value data buffer for winning normal symbols whose address is set in the initial value pointer in step AKS67. The random number counter for winning symbols is provided in the random number buffer area for special symbols, and can store numerical data corresponding to the random numbers MR1-2 for winning symbols. The random number initial value data buffer for the winning symbol is provided in the random number data area for the winning symbol, and can store numerical data corresponding to the random number initial value of the random number MR1-2. The random number counter for the winning symbol for the normal symbol is provided in the random number data area for the winning symbol, and can store numerical data corresponding to the random number MR2-1 for the winning symbol for the normal symbol. The random number initial value data buffer for the winning symbol for the normal symbol is provided in the random number data area for the winning symbol, and can store numerical data corresponding to the random number initial value of the random number MR2-1. In this way, the random number update process P_RANDOM enables the random numbers MR1-2 and MR2-1 to be updated by software using the random number initial value data buffer for the winning symbol provided in the random number data area for the winning symbol, the random number counter for the winning symbol for the normal symbol, the random number initial value data buffer for the winning symbol for the normal symbol, and the random number counter for the winning symbol provided in the random number buffer area for the special symbol.

Figure 10-13 (A) shows a configuration example AKB11 of a random number data area for winning symbols. The winning symbol random number data area of the configuration example AKB11 includes a random number initial value data buffer for winning symbols at address F050 [H], an initial value random number counter for winning symbols at address F051 [H], a random number counter for normal winning symbols at address F052 [H], a random number initial value data buffer for normal winning symbols at address F053 [H], and an initial value random number counter for normal winning symbols at address F054 [H]. Of these, the address F050[H] of the random number initial value data buffer for the winning symbol is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, the address F052[H] of the random number counter for the normal winning symbol is set to the random number pointer by step AKS65 of the random number update process P_RANDOM, and the address F053[H] of the random number initial value data buffer for the normal winning symbol is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The initial value random number counter for the winning symbol can store numerical data corresponding to the random numbers MR1-3 that are the initial values for the winning symbol. The initial value random number counter for the normal winning symbol can store numerical data corresponding to the random numbers MR2-2 that are the initial values for the normal winning symbol.

Figure 10-13 (B) shows a configuration example AKB12 of the random number buffer area for special symbols. The random number buffer area for special symbols of the configuration example AKB12 includes a random number buffer for special symbol determination at address F07F [H], a random number counter for winning symbols at address F081 [H], a random number buffer for selecting a variation pattern type at address F082 [H], a random number buffer for variation patterns at address F083 [H], and a random number buffer for selecting a losing performance at address F084 [H]. Of these, the address F081 [H] of the random number counter for winning symbols is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The random number buffer for special symbol determination can store numerical data corresponding to the random number MR1-1 for special symbol determination obtained from the 16-bit random number circuit 104A. The random number buffer for selecting a variation pattern type can store numerical data corresponding to the random number MR3-3 for selecting a variation pattern type obtained from the 8-bit random number circuit 104B. The random number buffer for variation patterns can store numerical data corresponding to the random number MR3-4 for variation patterns obtained from the 8-bit random number circuit 104B. The random number buffer for selecting a losing performance can store numerical data corresponding to the random number MR3-2 for selecting a losing performance obtained from the 16-bit random number circuit 104A.

Figure 10-14 is a flow chart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the process that can be called from the random number update process P_RANDOM shown in Figure 10-12, and can be executed in step AKS64 after the settings for the random number MR1-2 for the winning symbol are made in steps AKS61 to AKS63, and can be executed in step AKS68 after the settings for the random number MR2-1 for the normal winning symbol are made in steps AKS65 to AKS67. Such initial value change random number update process P_RANCP makes it possible to update the value of the random number MR1-2 using the numerical data corresponding to the random number MR1-2 for the winning symbol in step AKS64. Also, the initial value change random number update process P_RANCP makes it possible to update the value of the random number MR2-1 using the numerical data corresponding to the random number MR2-1 for the normal winning symbol in step AKS68.

When the CPU 103 executes the initial value change random number update process P_RANCP, it first executes a compare and add command (step AKS101). This compare and add command can be executed by a single ICPLD command, which is a third special transfer command, with the stored data at the address indicated by the stored value of the HL register, which is a random number pointer, as the update target value, and the stored value of the B register, which is a random number maximum register, as the comparison judgment value. The stored value of the HL register, which is a random number pointer, indicates the address of the random number counter in which the numerical data corresponding to the update target random number value is stored. The stored value of the B register, which is a random number maximum register, indicates the random number maximum value set corresponding to the update target random number value. Then, when the count value of the random number counter indicating the update target random number value is less than the stored value of the random number maximum register, the count value of the random number counter is updated to be incremented by 1, thereby incrementing the update target random number value by 1. On the other hand, when the count value of the random number counter indicating the update target random number value is equal to or greater than the stored value of the random number maximum register, the random number counter is cleared and the count value is initialized to "0", so that the update target random number value is changed to the random number minimum value. Therefore, the compare and add instruction of step AKS101 is a single instruction that includes comparing the random number value to be updated with the maximum random number, incrementing the random number value to be updated by 1 if the comparison result is less than the maximum random number, and changing the random number value to the minimum random number if the comparison result is equal to or greater than the maximum random number. In this way, when updating the random number value to be updated using the initial value change random number update process P_RANCP, a single compare and add instruction is executed first. By executing such a single compare and add instruction first, it is possible to suppress the occurrence of malfunctions and update the random number value appropriately.

When the compare and add instruction is executed in step AKS101, a transfer instruction for reading stored data is used to load the random number value pointed to by the random number pointer (step AKS102). The random number pointer and the initial value pointer are also exchanged (step AKS103). The random number value loaded in step AKS102 is then compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). It is determined whether the compared random number value is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random number value to be updated. Therefore, in step AKS104, after the compare and add instruction of step AKS101 is executed, the random number value to be updated after the compare and add instruction is compared with the random number initial value.

When the random number value corresponding to step AKS105 differs from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the compare and add command of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated indicates the updated random number value. Then, when the initial value change random number update process P_RANCP ends due to the judgment result of step AKS105, the stored value of the random number counter indicating the updated random number value to be updated is stored as the current random number value. Therefore, in step AKS105, if the updated random number value to be updated does not match the random number initial value, the initial value change random number update process P_RANCP ends, and the updated random number value to be updated can be stored as the current random number value.

If the random number value is the same as the value stored in the random number initial value data buffer pointed to by the initial value pointer in response to step AKS105 (step AKS105; No), the initial value random number counter pointed to when the value stored in the initial value pointer is incremented by 1 is loaded (step AKS106). In the configuration example AKB11 of the random number data area for winning symbols shown in FIG. 10-13(A), the next address F051[H] when the address F050[H] where the random number initial value data buffer for winning symbols is provided is incremented by 1 has a winning symbol initial value random number counter provided. Also, the next address F054[H] when the address F053[H] where the random number initial value data buffer for normal winning symbols is incremented by 1 has a normal winning symbol initial value random number counter provided. Therefore, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for the winning symbol, the count value of the initial value random number counter for the winning symbol is read out. Also, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for the normal winning symbol, the count value of the initial value random number counter for the normal winning symbol is read out. In this way, in step AKS106, the count value of the initial value random number counter can be read out as the random number value for the initial value.

When the initial value random number counter is loaded in step AKS106, the count value of the initial value random number counter thus read is stored in the random number counter pointed to by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 can store the count value of the initial value random number counter as the current random number value to be updated. Therefore, if the result of the determination in step AKS105 is that the updated random number value to be updated matches the random number initial value, step AKS107 can store the initial value random number value read in step AKS106 as the current random number value.

Following step AKS107, the count value of the initial value random number counter read out in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), and then the initial value change random number update process P_RANCP ends. Since the stored value of the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, the count value of the initial value random number counter can be stored as a new random number initial value in step AKS108. Therefore, if the update target random number value after update matches the random number initial value as determined in step AKS105, the initial value random number value is stored as the current random number value in step AKS107, and the initial value random number value read out in step AKS106 can be stored as a new random number initial value in step AKS108. In this way, the uncertainty of the random number value is increased by setting a new random number initial value, and by storing it as the current random number value as well, an increase in data volume is prevented, enabling appropriate random number value updating.

The random number update process P_RANDOM shown in Figure 10-12 executes the initial value change random number update process P_RANCP in step AKS64 after setting the random number value to be updated, the maximum random number value, and the initial random number value for the random number MR1-2 for the winning symbol in steps AKS61 to AKS63. The initial value change random number update process P_RANCP makes it possible to update the random number value to be updated and change the initial random number value based on the settings for the random number value to be updated, the maximum random number value, and the initial random number value. The initial value change random number update process P_RANCP in step AKS64 makes it possible to update the random number MR1-2 for the winning symbol, which has been set as the random number value to be updated in step AKS61, using the maximum random number set in step AKS62 and the initial random number value set in step AKS63. Additionally, the initial value change random number update process P_RANCP in step AKS64 enables the random number initial value to be changed when the value of the random number MR1-2 for the winning symbol that is set as the random number to be updated in step AKS61 matches the random number initial value set in step AKS63. In this way, appropriate random number values can be updated by updating the set random number to be updated, etc.

In the random number update process P_RANDOM, after setting the random number value to be updated, the maximum random number value, and the initial random number value for the random number MR2-1 for the normal symbol per symbol in steps AKS65 to AKS67, the initial value change random number update process P_RANCP in step AKS68 is executed. The initial value change random number update process P_RANCP in step AKS68 enables the update of the random number MR2-1 for the normal symbol per symbol set as the random number value to be updated in step AKS65 using the maximum random number value set in step AKS66 and the initial random number value set in step AKS67. In addition, the initial value change random number update process P_RANCP in step AKS68 enables the change of the initial random number value for the random number MR2-1 for the normal symbol per symbol set as the random number value to be updated in step AKS65 when the value matches the initial random number value set in step AKS67. In this way, the update of the set random number value to be updated enables the update of the appropriate random number value. Additionally, by updating the random number value to be updated and changing the initial random number value, it is possible to update the random number value appropriately.

The random number update process P_RANDOM can update the random number MR1-2 for the winning symbol used when determining the display result of the special symbol by a first update process consisting of steps AKS61 to AKS64, and can update the random number MR2-1 for the normal winning symbol used when determining the display result of the normal symbol by a second update process consisting of steps AKS65 to AKS68. Then, the random number MR1-2 for the winning symbol is updated as the first random number value by steps AKS61 to AKS64, and then the random number MR2-1 for the normal winning symbol is updated as the second random number value by steps AKS65 to AKS68. The confirmed special symbol that results in the display of the special symbol corresponds to the maximum number of times the big prize opening is opened in the big prize game state. In addition, the determined special pattern, which is the display result of the special pattern, may correspond to whether or not the game is controlled to a high probability state after the end of the jackpot game state, or the maximum number of variable display times that can be executed in the time-saving state after the end of the jackpot game state. In contrast, the determined normal pattern, which is the display result of the normal pattern, corresponds to the opening time and number of openings of the second large prize opening. Therefore, the display result of the special pattern attracts more attention from the player than the display result of the normal pattern. By updating the random number MR1-2 as the first random number value and then updating the random number MR2-1 as the second random number value by the random number update process P_RANDOM, which is a specific update process, the first random number value used to determine the display result that attracts the player's attention is updated before the second random number value, thereby suppressing the occurrence of malfunctions and enabling appropriate random number updates.

In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2 that becomes the first random number value, and steps AKS65 to AKS68 can update the random number MR2-1 that becomes the second random number value. Then, the initial value change random number update process P_RANCP of step AKS64 can be called and executed in response to the random number MR1-2 that becomes the first random number value, and the initial value change random number update process P_RANCP of step AKS68 can be called and executed in response to the random number MR2-1 that becomes the second random number value. In this way, the random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value, making their initial values changeable, by calling the initial value change random number update process P_RANCP, which is a common update process, in response to the first random number value and the second random number value. The initial value change random number update process P_RANCP, which serves as a common update process, prevents an increase in program capacity and enables stable updates of the first random number value and the second random number value, thereby enabling appropriate updates of the random number values.

In the random number update process P_RANDOM, steps AKS61 to AKS64, which enable updating of the random number MR1-2, which becomes the first random number value, constitute the first update process, and steps AKS65 to AKS68, which enable updating of the random number MR2-1, which becomes the second random number value, constitute the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM updates the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value, and enables their initial values to be changed, by calling the initial value change random number update process P_RANCP as a common update process in the first update process and the second update process. The initial value change random number update process P_RANCP, which serves as a common update process, prevents an increase in program capacity and enables stable updates of the first random number value and the second random number value, thereby enabling appropriate updates of the random number values.

In the random number update process P_RANDOM, steps AKS61 to AKS64, which enable updating of random number MR1-2, which will become the first random number value, constitute the first update process, and steps AKS65 to AKS68, which enable updating of random number MR2-1, which will become the second random number value, constitute the second update process. Then, in the first and second update processes, the HL register, B register, and DE register of CPU 103, which are common internal storage means, are used to enable updating of random number MR1-2 as the first random number value and random number MR2-1 as the second random number value. In this way, the first random number value and the second random number value can be stably updated using the common internal storage means, making it possible to update the random number values appropriately.

In the random number update process P_RANDOM, before the initial value change random number update process P_RANCP is executed by step AKS64, reference information such as the winning symbol random number counter address, the winning symbol random number maximum judgment value, and the winning symbol random number initial value data buffer address are stored in the HL register, B register, and DE register of CPU 103, which is the internal storage means, by steps AKS61 to AKS63. Also, in the random number update process P_RANDOM, before the initial value change random number update process P_RANDCP is executed by step AKS68, reference information such as the normal symbol winning symbol random number counter address, the normal symbol winning symbol random number maximum judgment value, and the normal symbol winning symbol random number initial value data buffer address are stored in the HL register, B register, and DE register of CPU 103, which is the internal storage means, by steps AKS65 to AKS67. The instruction used to update the random number MR1-2 to become the first random number value by step AKS61 and the instruction used to update the random number MR2-1 to become the second random number value by step AKS65 are common instructions in that they set the HL register of the CPU 103, and since the random number counter address for the winning symbol is set by step AKS61 but the random number counter address for the normal winning symbol is set by step AKS65, different reference information can be set. The instruction used to update the random number MR1-2 to become the first random number value by step AKS62 and the instruction used to update the random number MR2-1 to become the second random number value by step AKS66 are common instructions in that they set the B register of the CPU 103, and since the random number maximum value corresponding to the winning symbol random number maximum judgment value is set by step AKS62 but the random number maximum value corresponding to the normal winning symbol random number maximum judgment value is set by step AKS66, different reference information can be set. The instruction used to update the random number MR1-2 to become the first random number value by step AKS63 and the instruction used to update the random number MR2-1 to become the second random number value by step AKS67 are common instructions in that they set the DE register of the CPU 103, and since the random number initial value data buffer address for the winning symbol is set by step AKS63, but the random number initial value data buffer address for the normal winning symbol is set by step AKS67, different reference destination information can be set. In these steps AKS61 to AKS63 and steps AKS65 to AKS67, different reference destination information can be set using a common instruction such as the LD instruction or the LDQ instruction, which are transfer instructions for setting the internal register of the CPU 103. Then, in steps AKS64 and AKS68, the initial value change random number update process P_RANCP is called and executed by a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is a specific update process, the instruction used to update the random number MR1-2, which becomes the first random number value, and the instruction used to update the random number MR2-1, which becomes the second random number value, are common. By making it possible to update the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value using a common instruction, it becomes possible to stably update the first random number value and the second random number value, and to update the random number values appropriately.

The random number update process P_RANDOM enables the random number MR1-2, which becomes the first random number value, to be updated by steps AKS61 to AKS64, which is the first update process, and enables the random number MR2-1, which becomes the second random number value, to be updated by steps AKS65 to AKS68, which is the second update process. Then, the initial value change random number update process P_RANCP can be called and executed by steps AKS64 and AKS68. The initial value change random number update process P_RANCP shown in FIG. 10-14 executes a single compare and add instruction first, so that the compare and add instruction can be executed first in both cases of updating the random number MR1-2 as the first random number value and updating the random number MR2-1 as the second random number value. By executing such a compare and add instruction first, it is possible to suppress the occurrence of malfunctions in the first random number value and the second random number value, and to update the random number value appropriately.

When the initial value change random number update process P_RANCP is executed in step AKS64 of the random number update process P_RANDOM, it can update the random number MR1-2 for the winning symbol, and can change the random number initial value corresponding to the random number MR1-2 for the winning symbol by using the random number MR1-3 that becomes the initial value for the winning symbol. Also, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM, it can update the random number MR2-1 for the winning symbol for the normal symbol, and can change the random number initial value corresponding to the random number MR2-1 for the winning symbol for the normal symbol by using the random number MR2-2 that becomes the initial value for the winning symbol for the normal symbol. Therefore, the random number MR1-3, which is the initial value for the winning symbol, is a first initial value random number used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR1-2 for the winning symbol, which is the first random number value, as a result of the execution of the initial value change random number update process P_RANCP in step AKS64 of the random number update process P_RANDOM. The random number MR2-2, which is the initial value for the winning symbol for the normal symbol, is a second initial value random number used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR2-1 for the winning symbol for the normal symbol, which is the second random number value, as a result of the execution of the initial value change random number update process P_RANCP in step AKS68 of the random number update process P_RANDOM.

Figure 10-15 is a flowchart showing an example of the random number update process P_TFINIT for determining initial values. The random number update process P_TFINIT for determining initial values is included in the process that can be called from the main process P_MAIN for game control shown in Figure 4, and can be executed in step S9 of the loop process that is repeated until a timer interrupt occurs after step S7. The random number update process P_TFINIT for determining initial values is also included in the process that can be called from the timer interrupt process P_PCT for game control shown in Figure 5, and can be executed in step AKS57 in response to the occurrence of a periodic timer interrupt due to the passage of a predetermined time, for example, 4 ms. Therefore, the random number update process P_TFINIT for determining initial values is included in a first process that can be executed in response to a timer interrupt due to the passage of a predetermined time, and a second process that can be repeatedly executed until the first process is executed. Furthermore, the initial value determination random number update process P_TFINIT can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, and can also be called and executed by step S9 included in the standby process as a repeated loop process after startup processes such as the power supply start response process P_POWER_ON in step S1 in the main process P_MAIN for game control that is executed based on the start of power supply in the pachinko game machine 1. In this way, the initial value determination random number update process P_IFINIT is included in processes that can be executed in response to periodic timer interrupts as an initial value random number update process, and is also included in processes that can be repeatedly executed irregularly. This makes the update period and update speed of the initial value random number variable indefinite, thereby increasing the uncertainty of the initial value random number variable and enabling appropriate random number value update.

When the CPU 103 executes the initial value determination random number update process P_TINIT, it sets the initial value random number counter address for the winning symbol by a transfer command for setting a pointer (step AKS81). The initial value random number counter address for the winning symbol is the address F051 [H] assigned to the initial value random number counter for the winning symbol in the configuration example AKB11 of the random number data area for the winning symbol shown in FIG. 10-13 (A). When the pointer is set in this way, the count value of the initial value random number counter for the winning symbol can be updated within the update range of "0" to "199" by a comparison and addition command (step AKS82). This comparison and addition command can be executed by a single ICPLD command, which is the third special transfer command, with the stored data at the address pointed to by the pointer as the update target value and the immediate value specified by the operand as the comparison and judgment value. The stored value of the pointer indicates the address of the random number counter in which the numerical data corresponding to the update target initial value random number value is stored. The immediate value specified by the operand indicates the maximum random number for initial values that is set corresponding to the random number for initial values to be updated. If the count value of the random number counter indicating the random number for initial values to be updated is less than the maximum random number for initial values, the count value of the random number counter is updated to increment by 1, thereby incrementing the random number for initial values to be updated by 1. On the other hand, if the count value of the random number counter indicating the random number for initial values to be updated is equal to or greater than the value stored in the maximum random number for initial values register, the random number counter is cleared to initialize the count value to "0", thereby changing the random number for initial values to be updated to the minimum random number value. Therefore, the comparison and addition instruction of step AKS82 is a single instruction that includes: setting the random number MR1-3, which is the initial value for the winning symbol, to the random number value for the initial value to be updated; comparing the random number value for the initial value to be updated to the maximum random number value for the initial value; incrementing the random number value for the initial value to be updated by 1 if the result of the comparison is less than the maximum random number value for the initial value; and changing the random number value for the initial value to be updated to the minimum random number value if the result of the comparison is equal to or greater than the maximum random number value for the initial value. Note that the comparison and addition instruction is not limited to the ICPLD instruction in which the address of the stored data indicating the update target value is specified by a pointer; for example, it may be an ICPLDQ instruction in which the upper address is set using the Q register and the lower address is set using the immediate value specified by the first operand of the comparison and addition instruction. In this case, the immediate value specified by the second operand of the comparison and addition instruction may be set to the comparison judgment value. By updating the random number value for the initial value to be updated using such a comparison and addition instruction, the occurrence of malfunctions is suppressed, and appropriate random number updating is possible.

After step AKS82, the address of the initial value random number counter for the normal symbol is set by a transfer command for setting the pointer (step AKS83). The address of the initial value random number counter for the normal symbol is the address F054 [H] assigned to the initial value random number counter for the normal symbol in the configuration example AKB11 of the random number data area for the winning symbol shown in FIG. 10-13 (A). When the pointer is set in this way, the count value of the initial value random number counter for the normal symbol is made updatable within the update range of "1" to "198" by a comparison and addition command (step AKS84), and the initial value determination random number update process P_TFINIT is completed. The comparison and addition command of step AKS84 may be the same as the comparison and addition command of step AKS82. However, in the comparison and addition command of step AKS84, the random number MR2-2, which is the initial value for the normal symbol, is set as the random number value for the initial value to be updated, and the immediate value specified by the operand indicating the maximum random number value for the initial value is set to a value different from that of the comparison and addition command of step AKS82. Therefore, the comparison and addition command of step AKS84 is a single command that includes setting the random number MR2-2, which is the initial value for the normal symbol, to the random number value for the initial value to be updated, comparing the random number value for the initial value to the maximum random number value for the initial value, adding 1 to the random number value for the initial value to be updated if the result of the comparison is less than the maximum random number value for the initial value, and changing the random number value for the initial value to the minimum random number value if the result of the comparison is equal to or greater than the maximum random number value for the initial value. By updating the random number value for the initial value to be updated using such a comparison and addition command, the occurrence of malfunctions can be suppressed, and appropriate random number value updates can be made.

The random number update process for determining initial values P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol in steps AKS81 and AKS82 as an update of the random number value for the first initial value. At the same time, the random number update process for determining initial values P_TFINIT updates the random number MR2-2 that is the initial value for the winning symbol in steps AKS83 and AKS84 as an update of the random number value for the second initial value. The random number MR1-3 that is the initial value for the winning symbol is the first random number value used when changing the random number initial value when the random number value to be updated is the random number MR1-2 for the winning symbol, which is the first random number value. The random number MR2-2 that is the initial value for the winning symbol in the normal symbol is the second random number value used when changing the random number initial value when the random number value to be updated is the random number MR2-1 for the winning symbol, which is the second random number value. Steps AKS81 and AKS82 of the random number update process P_TFINIT for determining initial values constitute a first initial value update process capable of updating the random number value for the first initial value. Steps AKS83 and AKS84 of the random number update process P_TFINIT for determining initial values constitute a second initial value update process capable of updating the random number value for the second initial value. By updating the random number values for the first and second initial values in this way, it becomes possible to appropriately update the random number values so as to reliably increase the uncertainty of the first and second random number values.

In addition, the random number update process P_TFINIT for initial value determination updates the random number MR1-3, which is the initial value for the winning symbol, as the first random number value for the initial value in steps AKS81 and AKS82, and then updates the random number MR2-2, which is the initial value for the winning symbol for the normal symbol, as the second random number value for the initial value in steps AKS83 and AKS84. Therefore, the random number update process P_TFINIT for initial value determination updates the random number MR1-3, which is the initial value for the winning symbol, which is the first random number value for the initial value, in steps AKS81 and AKS82, which are the first initial value update process, and then updates the random number MR2-1, which is the initial value for the winning symbol for the normal symbol, which is the second random number value for the initial value, in steps AKS83 and AKS84, which are the second initial value update process.

Figure 10-16 is a flow chart showing an example of the start port switch passing process P_TZU_ON. The start port switch passing process P_TZU_ON is included in the processes that can be called from the special pattern process process P_TPROC shown in Figure 6, and can be executed in step S104 if the first start winning corresponding flag is on in step S103, and can be executed in step S108 if the second start winning corresponding flag is on in step S107. When the CPU 103 executes the start port switch passing process P_TZU_ON, it sets the start port winning memory counter address by a transfer command for setting a pointer (step AKS201). The start port winning memory counter address is the address of the first start port winning memory counter or the second start port winning memory counter provided in the game work area of the RAM 102. In step AKS201, a different address in the game work area can be specified in accordance with the first start port winning table or the second start port winning table set by the special symbol process P_TPROC. For example, the upper address F0[H] of the game work area, which is the work area, is set to the upper byte of the pointer by a transfer command, and the lower address of the start port winning memory counter stored in the first start port winning table or the second start port winning table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command. As a result, the value indicating the address of the first start port winning memory counter or the second start port winning memory counter is stored in the internal register of CPU 103, which becomes the pointer. Next, the start port winning memory counter is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AKS202).

After step AKS202, it is determined whether the count value of the start port winning memory counter is equal to or greater than the counter maximum value (step AKS203). For example, if the value loaded in step AKS202 is compared with a counter maximum value such as "4" by a comparison return command, if the value is equal to or greater than the counter maximum value (step AKS203; Yes), the start port switch passing process P_TZU_ON ends and returns to the special pattern process process P_TPROC. On the other hand, if the value is less than the counter maximum value (step AKS203; No), the count value of the start port winning memory counter is updated to add 1 (step AKS204). In this case, an arithmetic and logic operation command that increments the stored data at the address pointed to by the pointer makes it possible to update the count value of the first start port winning memory counter or the second start port winning memory counter by adding 1.

After step AKS204, the special symbol determination buffer address is set as the transfer destination (step AKS205). The special symbol determination buffer address is the address of the first special symbol determination buffer contained in the first special symbol reserve buffer provided in the game work area of RAM 102, or the address of the second special symbol determination buffer contained in the second special symbol reserve buffer. In step AKS205, different addresses in the game work area can be specified in accordance with the first start port winning table or the second start port winning table set by the special symbol process processing P_TPROC, and the count value of the first start port winning counter or the second start port winning counter loaded in step AKS202.

The first special symbol reserved buffer is secured as a plurality of storage areas, such as five storage areas corresponding to the buffer numbers "0" to "4", corresponding to the case where the variable display of the first special symbol is being executed and the number of first reserved memories that have not yet been executed, by the first reserved memory buffer, which is composed of a first special symbol determination buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first miss performance selection buffer. The second special symbol reserved buffer is secured as a plurality of storage areas, such as five storage areas corresponding to the buffer numbers "0" to "4", corresponding to the case where the variable display of the second special symbol is being executed and the number of second reserved memories that have not yet been executed, by the second reserved memory buffer, which is composed of a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second miss performance selection buffer.

In step AKS205, a value corresponding to the buffer size of the first reserved memory buffer or the second reserved memory buffer is multiplied by the count value of the start port winning counter, and the multiplied value is added to the lower address of the first reserved memory buffer or the second reserved memory buffer with buffer number "1". By setting this added value to the transfer destination pointer, the special pattern determination buffer address can be set as the transfer destination.

Following step AKS205, the RL0 hard latch random number register address is set (step AKS206). The RL0 hard latch random number register address is the address of the RL0 hard latch random number register provided in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer by a transfer command, and the lower address of the RL0 hard latch random number register stored in the first start port winning table or the second start port winning table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command. The lower address of the RL0 hard latch random number register with buffer number "0" is stored in the first start port winning table. The lower address of the RL0 hard latch random number register with buffer number "1" is stored in the second start port winning table. As a result, the address of the RL0 hard latch random number register, which differs between the first start winning and the second start winning, is stored in the internal register of CPU 103, which serves as the pointer.

Following step AKS206, the RL0 hard latch random number register is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AK207). The value thus obtained from the RL0 hard latch random number register is stored in the special symbol determination random number buffer by a transfer command to write it to a memory area at a specified address in the game work area of RAM 102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random number register in the special symbol determination random number buffer, numerical data indicating the value of the special symbol determination random number MR1-1 is extracted, and the value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

After step AKS208, the RL2 soft latch random number register is loaded by a transfer command to read the stored data from the memory area of the specified address in the function control register area (step AKS209). The value stored in the RL2 soft latch random number register obtained at this time is stored in the random number buffer for selecting a losing performance by a transfer command to write it to the memory area of the specified address in the game work area of RAM 102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random number register in the random number buffer for selecting a losing performance, numerical data indicating the value of the random number MR3-2 for selecting a losing performance is extracted, and the value of the random number MR3-2 can be stored in the random number buffer for selecting a losing performance.

After step AKS210, the RS1 soft latch random number register is loaded by a transfer command to read the stored data from the memory area of the specified address in the function control register area (step AKS211). The value stored in the RS1 soft latch random number register obtained at this time is stored in the random number buffer for selecting the fluctuation pattern type by a transfer command to write it to the memory area of the specified address in the game work area of RAM 102 (step AKS212). In this way, by storing the numerical data obtained from the RS1 soft latch random number register in the random number buffer for selecting the fluctuation pattern type, numerical data indicating the value of the random number MR3-3 for selecting the fluctuation pattern type is extracted, and the value of the random number MR3-3 can be stored in the random number buffer for selecting the fluctuation pattern type.

After step AKS212, the RS2 soft latch random number register is loaded by a transfer command to read stored data from a memory area at a specified address in the function control register area (step AKS213). The value stored in the RS2 soft latch random number register obtained at this time is stored in the random number buffer for fluctuation patterns by a transfer command to write it to a memory area at a specified address in the game work area of RAM 102 (step AKS214). In this way, by storing the numerical data obtained from the RS2 soft latch random number register in the random number buffer for fluctuation patterns, numerical data indicating the value of random numbers MR3-4 for fluctuation patterns is extracted, and the value of random numbers MR3-4 can be stored in the random number buffer for fluctuation patterns.

Following step AKS214, block transfer is performed from the random number buffer to the special symbol determination buffer (step AKS215). The random number buffer includes a special symbol determination random number buffer in which the value of random number MR1-1 is stored by step AKS208, a loss performance selection random number buffer in which the value of random number MR3-2 is stored by step AKS210, a variation pattern type selection random number buffer in which the value of random number MR3-3 is stored by step AKS212, and a variation pattern random number buffer in which the value of random number MR3-4 is stored by step AKS214. In step AKS215, the address of the special symbol determination random number buffer is set as the transfer source, and a value corresponding to the buffer size of the random number buffer is set as the transfer count. The special symbol determination buffer address to which the transfer is to be made is set by step AKS205. Based on these settings, by executing a block transfer command, the value of each random number temporarily stored in the random number buffer can be stored as new reserved information in the first reserved storage buffer or the second reserved storage buffer.

When the new memory information is stored by step AKS215, it is determined whether the winning performance condition is satisfied (step AKS216). The winning performance condition may be set in advance as a condition for enabling the pre-reading performance. For example, if the starting port winning designation value is "2", it is determined that the winning performance condition is satisfied. Also, if the starting port winning designation value is "1", the time-saving function flag is "0" corresponding to the time-saving state not being in, and the special pattern process code is less than 03 [H] corresponding to the time-saving state not being in the small win game state or the big win game state, it is determined that the winning performance condition is satisfied. If it is determined that the winning performance condition is satisfied (step AKS216; Yes), the winning performance process P_GAME_CHK is executed (step AKS217). The winning performance process P_GAME_CHK includes a hit determination of the special pattern, and selects a performance designation value corresponding to the determination result, making it possible to send a winning performance command.

When it is determined that the winning performance condition is not satisfied in response to step AKS216 (step AKS216; No), or after the winning performance processing is executed by step AKS217, the performance memory information designation command transmission table address is set by a transfer command for setting a pointer (step AKS218). The performance memory information designation command transmission table address is the address of the performance memory information designation command transmission table stored in the game data area of ROM101. Then, by executing the command set processing P_COM_SET (step AKS219), the first performance memory information designation command or the second performance memory information designation command can be transmitted as the start winning command. The first performance memory information designation command is a performance control command that designates the first reserved memory number indicated by the count value of the first start port winning memory counter. The second performance memory information designation command is a performance control command that designates the second reserved memory number indicated by the count value of the second start port winning memory counter. In this way, the command set process P_COM_SET in step AKS219 allows the performance control command, which becomes the command at the time of the initial winning, to be sent from the main board 11 to the performance control board 12.

After step AKS219, the start port winning buffer memory counter address is set by a transfer command for setting a pointer (step AKS220). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of RAM 102. In this way, the count value of the start port winning buffer memory counter whose address has been set is updated to add 1 (step AKS221). In addition, the pointer is updated corresponding to the start port winning buffer memory counter by a composite transfer command for setting a register or pointer (step AKS222). For example, the count value of the start port winning buffer memory counter after the update by step AKS221 is loaded into the internal register of CPU 103, and the stored value of the pointer is updated to add 1, so that a value indicating the top address of the start port winning buffer is stored in the pointer. Furthermore, the count value of the loaded start port winning buffer memory counter is added to the stored value of the pointer, making it possible to identify the storage area of the buffer number to be updated in the start port winning buffer.

After updating the pointer in step AKS222, the start port winning designation value is loaded (step AKS223). The start port winning designation value can be set to "1" indicating a first start winning or "2" indicating a second start winning, corresponding to the first start port winning table or the second start port winning table set by the special pattern process processing P_TPROC. In step AKS223, the start port winning designation value can be obtained by a transfer command to read table data from the first start port winning table or the second start port winning table. The start port winning designation value thus obtained is stored in the start port winning buffer by a transfer command to write it to the memory area of the address pointed to by the pointer (step AKS224), and the start port switch passing processing P_TZU_ON ends.

Figure 10-17 is a diagram for explaining an example of the use of data configuration related to the start port switch passing process P_TZU_ON. In the start port switch passing process P_TZU_ON, various settings and controls are performed using the first start port winning table set in step S102 or the second start port winning table set in step S106 of the special pattern process process P_TPROC shown in Figure 6. For example, the first start port winning memory counter and the second start port winning memory counter, whose count value can be updated in step AKS204, are provided in the special pattern control data area and can store data corresponding to the first reserved memory number and the second reserved memory number. The start port winning buffer memory counter, whose count value can be updated by AKS221, and the start port winning buffer, in which the start port winning designation value is stored by AKS224, are provided in the start port winning buffer area and can store the total number of first start winnings and the second start winnings and the order of occurrence. In addition, the command set process P_COM_SET in step AKS219 uses the first effect memory information designation command transmission table or the second effect memory information designation command transmission table whose address was set in step AKS218.

In this way, the start port switch passing process P_TZU_ON enables control of the special pattern game, which is a variable display of special patterns, using the first start port winning table or the second start port winning table, the first start port winning memory counter or the second start port winning memory counter provided in the special pattern control data area, the start port winning buffer memory counter and the start port winning buffer provided in the start port winning buffer area, and the first performance memory information designation command sending table or the second performance memory information designation command sending table.

Figure 10-17 (A1) shows a configuration example AKT21 of the first start port winning table. The first start port winning table of the configuration example AKT21 is configured to include table data indicating the lower address of the first start port winning memory counter, the lower address of the RL0 hard latch random number register number "0", the lower address of the first special pattern determination buffer number "1", the address of the first performance memory information designation command transmission table, and the start port winning designation value "1".

The first start port winning memory counter is provided in the game work area of the RAM 102, and can store data corresponding to the first reserved memory number. The RL0 hard latch random number register number "0" is an RL0 hard latch random number register with register number "0" provided in the function control register area, and can acquire and store numerical data indicating the value of the random number MR1-1 for special symbol determination that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A by hard latching. The first special symbol determination buffer number "1" is a first special symbol determination buffer included in the first reserved memory buffer with buffer number "1" in the first special symbol reservation buffer. The first performance memory information designation command transmission table is stored in the game data area of the ROM 101, and is used when transmitting the first performance memory information designation command that designates the first reserved memory number. The start port winning designation value "1" is a designation value that identifiably indicates that a first start winning has occurred.

Figure 10-17 (A2) shows a configuration example AKT22 of the second start port winning table. The second start port winning table of the configuration example AKT22 is configured to include table data indicating the lower address of the second start port winning memory counter, the lower address of the RL0 hard latch random number register number "1", the lower address of the second special pattern determination buffer number "1", the address of the second performance memory information designation command transmission table, and the start port winning designation value "2".

The second start port winning memory counter is provided in the game work area of the RAM 102, and can store data corresponding to the second reserved memory number. The RL0 hard latch random number register number "1" is an RL0 hard latch random number register with register number "1" provided in the function control register area, and can acquire and store numerical data indicating the value of the random number MR1-1 for special symbol determination that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A by hard latching. The second special symbol determination buffer number "1" is a second special symbol determination buffer included in the second reserved memory buffer with buffer number "1" in the second special symbol reservation buffer. The second performance memory information designation command transmission table is stored in the game data area of the ROM 101, and is used when transmitting the second performance memory information designation command that designates the second reserved memory number. The start port winning designation value "2" is a designation value that identifiably indicates that a second start winning has occurred.

Figure 10-17 (B1) shows a configuration example AKB21 of a special symbol control data area. The special symbol control data area of configuration example AKB21 can store various data related to control by the special symbol process processing P_TPROC, such as a special symbol game which is a variable display of special symbols, and a small win game state and a big win game state which can be controlled based on the display result. This special symbol control data area includes a special symbol process timer at address F030[H], a win flag at address F032[H], a special symbol process code at address F033[H], a first start hole winning memory counter at address F034[H], a big win symbol determination buffer at address F035[H], a small win symbol determination buffer at address F036[H], a big win hole winning number counter at address F037[H], a big win hole opening number counter at address F038[H], a big win hole opening pattern timer at address F039[H], a big win hole opening pattern table pointer at address F03B[H], a demo display flag at address F03D[H], and a second start hole winning memory counter at address F099[H].

The special symbol process timer can store a time value corresponding to the control time by the special symbol process processing P_TPROC. The special symbol process code can specify the processing selected in the special symbol process processing P_TPROC. The first start port winning memory counter can store a count value corresponding to the first reserved memory number. The big win symbol determination buffer can store data corresponding to the big win symbol designation value. The big win symbol designation value is a designation value corresponding to the confirmed special symbol displayed when the display result in the variable display of the special symbol is "big win", and makes it possible to set the type of big win game state. The small win symbol determination buffer can store data corresponding to the small win symbol designation value. The small win symbol designation value is a designation value corresponding to the confirmed special symbol displayed when the display result in the variable display of the special symbol is "small win", and makes it possible to set the alcoholic beverage in the small win game state. The big win port winning number counter can store a count value corresponding to the number of game balls that have passed through the big win port formed by the special variable winning ball device 50. The large prize opening number counter can store a count value corresponding to the number of times the large prize opening is opened in a small win game state or a big win game state. The large prize opening pattern timer can store a time value corresponding to the remaining time for controlling the large prize opening to an open state in a small win game state or a big win game state. The large prize opening pattern table pointer can specify a storage address of the large prize opening opening pattern table in which the opening time of the large prize opening is set. The demo display flag can store a flag value corresponding to an on state or an off state depending on whether a demonstration display is being executed or not. The second start opening winning memory counter can store a count value corresponding to the second reserved memory number.

Figure 10-17 (B2) shows a configuration example AKB22 of the start port winning buffer area. The start port winning buffer area of the configuration example AKB22 can store various data related to the first start winning and the second start winning that occur when the game ball enters the first start winning port and the second start winning port. This start port winning buffer area includes a start port winning buffer memory counter at address F0BA [H] and start port winning buffer numbers "0" to "8" at addresses F0BB [H] to F0C3 [H].

The start port winning buffer memory counter can store a count value corresponding to the number of valid start port winning designation values stored in the start port winning buffer area. Therefore, the count value of the start port winning buffer memory counter indicates the total number of first start winnings and second start winnings. Start port winning buffer numbers "0" to "8" are start port winning buffers to which buffer numbers "0" to "8" are assigned, and can store start port winning designation values in the order in which the first start winnings and second start winnings occurred. As a result, the stored information in the start port winning buffer indicates the order in which the first start winnings and second start winnings occurred.

Figure 10-17 (C1) shows an example configuration AKT23 of the first performance memory information designation command transmission table. The first performance memory information designation command transmission table of the example configuration AKT23 is configured to include table data indicating the first performance memory information designation command upper byte and the first start port winning memory counter reference designation value. The command set process P_COM_SET of step AKS219 enables the first performance memory information designation command to be transmitted when the first performance memory information designation command transmission table is used. The first performance memory information designation command can set the lower byte corresponding to the count value of the first start port winning memory counter. By transmitting such a first performance memory information designation command, the first reserved memory number can be notified to the performance control board 12.

Figure 10-17 (C2) shows an example configuration AKT24 of the second performance memory information designation command transmission table. The second performance memory information designation command transmission table of the example configuration AKT24 is configured to include table data indicating the second performance memory information designation command upper byte and the second start port winning memory counter reference designation value. The command set process P_COM_SET of step AKS219 enables the second performance memory information designation command to be transmitted when the second performance memory information designation command transmission table is used. The second performance memory information designation command can set the lower byte corresponding to the count value of the second start port winning memory counter. By transmitting such a second performance memory information designation command, the second reserved memory number can be notified to the performance control board 12.

The start port switch passing process P_TZU_ON shown in FIG. 10-16 stores the stored value of the RL2 soft latch random number register loaded in step AKS209 in the random number buffer for selecting a losing performance in step AKS210, thereby making it possible to extract numerical data indicating the value of the random number MR3-2 for selecting a losing performance. The start port switch passing process P_TZU_ON also stores the stored value of the RS1 soft latch random number register loaded in step AKS211 in the random number buffer for selecting a fluctuation pattern type in step AKS212, thereby making it possible to extract numerical data indicating the value of the random number MR3-3 for selecting a fluctuation pattern type. The start port switch passing process P_TZU_ON also stores the stored value of the RS2 soft latch random number register loaded in step AKS213 in the random number buffer for selecting a fluctuation pattern in step AKS214, thereby making it possible to extract numerical data indicating the value of the random number MR3-4 for a fluctuation pattern. Here, if the random number MR3-2 for selecting a losing effect is the first random number, the random number MR3-3 for selecting a variation pattern type is the second random number, and the random number MR3-4 for the variation pattern is the third random number, the start port switch passing process P_TZU_ON is executed in response to the occurrence of a start winning, so the first random number, the second random number, and the third random number can be extracted by the establishment of a common extraction condition, that is, the occurrence of a start winning, for the first random number, the second random number, and the third random number. The random number MR3-2 for selecting a losing effect is included in the game random numbers that can be updated by the 16-bit random number circuit 104A, and the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for the variation pattern are included in the game random numbers that can be updated by the 8-bit random number circuit 104B, and the total number of random numbers included in the update range for each is a prime number. The update speed of the random number MR3-2 is 469 times/ms, while the update speed of the random numbers MR3-3 and MR3-4 is 938 times/ms. That is, the update speed of the random numbers MR3-3 and MR3-4 is twice the update speed of the random number MR3-2, which is an integer multiple. The update range of the random number MR3-2 is "0" to "65518", the update range of the random number MR3-3 is "0" to "240", and the update range of the random number MR3-4 is "0" to "250", so the total number of random numbers included in each update range is different, and all the total numbers of random numbers included in the update range are prime numbers. In this way, when the update speed of the second random number value and the third random number value is an integer multiple of the update speed of the first random number value, the total number of random numbers included in each update range is different, and all the total numbers of random numbers included in the update range are prime numbers. This makes it possible to prevent synchronization between the first, second, and third random number values, and to update the random number values appropriately.

Figure 10-18 is a flow chart showing an example of the special symbol normal processing P_TNORMAL. The special symbol normal processing P_TNORMAL is included in the processing that can be called from the special symbol process processing P_TPROC shown in Figure 6, and can be executed in step S112 when the special symbol process code loaded in step S110 is 00 [H]. When the special symbol normal processing P_TNORMAL is executed, the CPU 103 sets the start port winning buffer memory counter address by a transfer command for setting a pointer (step AKS241). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of RAM 102. In this way, it is determined whether the count value of the start port winning buffer memory counter whose address has been set is "0" or not (step AKS242). For example, an arithmetic jump instruction that branches processing depending on whether the stored data at the address pointed to by the pointer is 00 [H], which corresponds to "0", makes it possible to execute different processing contents depending on whether the count value of the start port winning buffer storage counter is "0" or not.

If the count value of the start port winning buffer memory counter is not "0" in response to step AKS242 (step AKS242; No), the count value of the start port winning buffer memory counter is updated to subtract 1 (step AKS243). Also, a block transfer for shifting the start port winning buffer is performed (step AKS244). In step AKS244, the transfer destination address is set to the lower address BB [H] of start port winning buffer number "0", the transfer source address is set to the lower address BC [H] of start port winning buffer number "1", and the number of transfers is set to "8", which is the buffer size of the start port winning buffer. After that, by executing a block transfer command, the memory contents in the start port winning buffer can be transferred and shifted one unit at a time to the previous buffer. Then, the memory area of the start port winning buffer number "8" can be initialized by clearing it.

After step AKS244, a transfer command for setting a table pointer is used to set a second special symbol determination control table address (step AKS245). The second special symbol determination control table address is the address of the second special symbol determination control table stored in the game data area of ROM 101. At this time, a start port winning check process is executed to determine whether the start port winning designation value is "1" (step AKS246). For example, in the start port winning check process, if the start port winning designation value is "1", the zero flag is turned on, and if the start port winning designation value is "2", the zero flag is turned off. After such a start port winning check process is executed, a jump command is used to branch the process depending on whether the zero flag is off, making it possible to execute different processing contents depending on whether the start port winning designation value is "1" or "2".

When the starting gate winning designation value is "1" in response to step AKS246 (step AKS246; Yes), the first special symbol determination control table address is set by a transfer command for setting the table pointer (step AKS247). The first special symbol determination control table address is the address of the first special symbol determination control table stored in the game data area of ROM 101. In step AKS247, the value of the table pointer is overwritten by a transfer command for setting the table pointer. In this way, in the special symbol normal processing P_TNORMAL, after the second special symbol determination control table address is set by step AKS245, the starting gate winning designation value corresponds to "1" in step AKS246, and the first special symbol determination control table address is re-set by overwriting in step AKS247. As a result, when the second special symbol determination control table is used more frequently than the first special symbol determination control table, the program capacity required for table setting can be reduced, improving the marketability of the pachinko gaming machine 1. Also, when the second special symbol determination control table is used more frequently than the first special symbol determination control table, the processing using the jump command as a branch command can be simplified, making it easier to check at the design stage, and improving the marketability of the pachinko gaming machine 1.

If the starting port winning designation value is "2" and not "1" in response to step AKS246 (step AKS246; No), after step AKS247, the special pattern determination process P_TDECISION is executed (step AKS248), and the variable pattern setting process P_TPATSET is executed (step AKS249), after which the normal special pattern processing ends.

When the count value of the start port winning buffer storage counter is "0" in response to step AKS242 (step AKS242; Yes), it is determined whether the demo display flag is on (step AKS250). The demo display flag is a flag indicating that a demonstration display is being executed. When the demo display flag is on (step AKS250; Yes), the normal processing of the special symbol ends. On the other hand, when the demo display flag is off (step AKS250; No), a transfer command for setting the demo display flag is used to store 01 [H], which is a designated value during demo display, in the demo display flag (step AKS251). This sets the demo display flag to the on state. In addition, a transfer command for setting a pointer is used to set the standby command transmission table address (step AKS252). The standby command transmission table address is the address of the standby command transmission table stored in the game data area of ROM 101. Then, the command set process P_COM_SET is executed (step AKS253), and the normal special pattern processing ends.

Figure 10-19 is a diagram for explaining an example of the use of the data configuration related to the special symbol normal processing P_TNORMAL. In the special symbol normal processing P_TNORMAL, the special symbol determination processing in step AKS248 is executed using the second special symbol determination control table whose address is set in step AKS245 or the first special symbol determination control table whose address is set in step AKS247. In addition, the command set processing P_COM_SET in step AKS253 uses the standby command transmission table whose address is set in step AKS252. In this way, the special symbol normal processing P_TNORMAL enables control of the special symbol game, which is a variable display of special symbols, using the first special symbol determination control table or the second special symbol determination control table or the standby command transmission table.

Figure 10-19 (A1) shows a configuration example AKT31 of the first special symbol determination control table. The first special symbol determination control table of the configuration example AKT31 is configured to include table data indicating the address of the first special symbol buffer shift control table, the lower address of the first special symbol determination buffer number "0", the lower address of the first winning symbol buffer number "0", the lower address of the first special symbol buffer, and the address of the work setting table after the first special symbol hit determination. The first special symbol buffer shift control table is stored in the game data area of ROM 101, and is used when shifting the memory contents of the first special symbol reserved buffer. The first special symbol determination buffer number "0" is the first special symbol determination buffer included in the first reserved memory buffer of buffer number "0" in the first special symbol reserved buffer. The first winning symbol buffer number "0" is a first winning symbol buffer included in the first reserved memory buffer of buffer number "0" in the first special symbol reserved buffer. The first special symbol buffer is provided in the game work area of RAM 102, and can store a special symbol pattern designation value corresponding to the confirmed special symbol stopped and displayed in the first special symbol game by the first special symbol display device 4A. The first special symbol hit determination work setting table is stored in the game data area of ROM 101, and is used when initializing data in response to the end of the special symbol determination process P_TDECISION.

Figure 10-19 (A2) shows a configuration example AKT32 of the second special symbol determination control table. The second special symbol determination control table of the configuration example AKT32 is configured to include table data indicating the address of the second special symbol buffer shift control table, the lower address of the second special symbol determination buffer number "0", the lower address of the second winning symbol buffer number "0", the lower address of the second special symbol buffer, and the address of the work setting table after the second special symbol hit determination. The second special symbol buffer shift control table is stored in the game data area of ROM 101, and is used when shifting the memory contents of the second special symbol reserved buffer. The second special symbol determination buffer number "0" is the second special symbol determination buffer included in the second reserved memory buffer of buffer number "0" in the second special symbol reserved buffer. The second winning symbol buffer number "0" is a second winning symbol buffer included in the second reserved memory buffer of buffer number "0" in the second special symbol reserved buffer. The second special symbol buffer is provided in the game work area of RAM 102, and can store a special symbol pattern designation value corresponding to the confirmed special symbol stopped and displayed in the second special symbol game by the second special symbol display device 4B. The second special symbol winning determination work setting table is stored in the game data area of ROM 101, and is used when initializing data in response to the end of the special symbol determination process P_TDECISION.

Figure 10-19 (B) shows a configuration example AKT33 of the standby command transmission table AKT33. The standby command transmission table of the configuration example AKT33 is configured to include table data indicating the number of processes, the second specific number of times designation command upper byte, the specific number of times command buffer reference designation value, the background color designation command upper byte, the special symbol state designation code reference designation value, the customer waiting demo command upper byte, and the customer waiting demo command lower byte. The command set process P_COM_SET of step AKS253 uses the standby command transmission table of the configuration example AKT33 to enable the second specific number of times designation command, the background color designation command, and the customer waiting demo command to be transmitted. The second specific number of times designation command can set a lower byte corresponding to the storage value of the specific number of times command buffer. The background color designation command can set a lower byte corresponding to the special symbol state designation code. The customer waiting demo command can set a lower byte using a fixed value 03 [H].

Figure 10-20 is a flowchart showing an example of the special symbol determination process P_TDECISION. The special symbol determination process P_TDECISION is included in the process that can be called from the special symbol normal process P_TNORMAL shown in Figure 10-18, and can be executed in step AKS248 when variable display of special symbols is started. When the CPU 103 executes the special symbol determination process P_TDECISION, it sets the special symbol buffer shift control table address by a transfer command for setting a pointer (step AKS301). The special symbol buffer shift control table address is the address of the first special symbol buffer shift control table or the second special symbol buffer shift control table stored in the game data area of the ROM 101. In step AKS301, a different address in the game data area can be specified in response to the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal process P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the address 13C2[H] of the first special symbol buffer shift control table is set in the pointer. Also, when the second special symbol determination control table is set, a value indicating the address 13C8[H] of the second special symbol buffer shift control table is set in the pointer.

Following step AKS301, the special symbol buffer shift process P_TBUFSHIFT is executed (step AKS302). The special symbol buffer shift process P_TBUFSHIFT in step AKS302 can shift the memory contents of the first special symbol reserve buffer or the second special symbol reserve buffer using the first special symbol buffer shift control table or the second special symbol buffer shift control table whose address is set in step AKS301. For example, by executing a block transfer command after setting the transfer destination address, transfer source address, and transfer count, the memory contents of the first reserved memory buffer of the first special symbol buffer or the second reserved memory buffer of the second special symbol buffer can be transferred and shifted by one unit at a time to the previous buffer.

After step AKS302, the special symbol determination buffer with buffer number "0" is loaded (step AKS303). The special symbol determination buffer with buffer number "0" is the first special symbol determination buffer or the second special symbol determination buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reservation buffer. In step AKS303, the stored value of the special symbol determination buffer can be read from the first special symbol reservation buffer or the second special symbol reservation buffer in accordance with the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal processing P_TNORMAL. For example, the upper address F0[H] of the game work area, which is the working area, is set to the upper byte of the pointer by a transfer command, and the lower address of the first special pattern determination buffer number "0" or the second special pattern determination buffer number "0" stored in the first special pattern determination control table or the second special pattern determination control table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command, and then the stored data of the address in the game work area pointed to by the pointer can be read to read the random number MR1-1 for special pattern determination stored in the special pattern determination buffer with buffer number "0".

After step AKS303, the special symbol jackpot determination process P_TFVR_CHK is executed (step AKS304). The special symbol jackpot determination process P_TFVR_CHK in step AKS304 can determine whether the special symbol display result is a "jackpot" or not by comparing the value of the random number MR1-1 for special symbol determination read out in step AKS303 with the jackpot determination value. The determination of whether the special symbol display result is a "jackpot" or not is also called the special symbol jackpot determination, and is a determination of whether to control the game state to a jackpot game state as an advantageous state. Then, when the special symbol display result is determined to be a "jackpot" in the special symbol jackpot determination, 01 [H], which is the jackpot designated value, is stored in the hit flag. The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F032 [H]. The special symbol jackpot determination process in step AKS304 can store a jackpot designated value in the hit flag by a transfer command for writing to a memory area of a designated address in the game work area of RAM 102. Note that the hit flag can be set to an initial value of 00 [H] by a clear command executed in response to the start of the special symbol jackpot determination process P_TFVR_CHK in step AKS304.

Along with the special symbol big win determination process P_TFVR_CHK in step AKS304, the special symbol small win determination process P_TLITTLE_CHK is executed (step AKS305). The special symbol small win determination process P_TLITTLE_CHK in step AKS305 can determine whether the special symbol display result is a "small win" by comparing the value of the special symbol determination random number MR1-1 read by loading the special symbol determination buffer in step AKS303 with the small win determination value. The determination of whether the special symbol display result is a "small win" is also called the special symbol small win determination, and is a determination of whether to control to a small win game state as a predetermined state. Then, when the special symbol small win determination determines that the special symbol display result is a "small win", 02 [H], which is the small win designated value, is stored in the win flag. The special symbol small win determination process P_TLITTLE_CHK in step AKS305 can store the small win designated value in the win flag by a transfer command to write to the memory area of the designated address in the game work area of RAM 102.

In the special pattern small hit judgment process P_TLITTLE_CHK in step AKS305, the small hit judgment value is included in a range different from the big hit judgment value, so after the special pattern big hit judgment judges that the special pattern display result is a "big hit", the special pattern small hit judgment will not judge the special pattern display result to be a "small hit". However, for example, if an error occurs and the special pattern small hit judgment judges that the special pattern display result is a "small hit" after the special pattern big hit judgment judges that the special pattern display result is a "big hit", the small hit designated value will be stored in the hit flag. Therefore, when the judgment of the special pattern big hit judgment judges that the special pattern display result is a "big hit" and the judgment of the special pattern small hit judgment judges that the special pattern display result is a "small hit" conflict, it is possible to prevent fraudulent acts due to a malfunction of the judgment process and control the game appropriately so that the game is not controlled to a big hit game state that is more advantageous than a small hit game state.

When the special symbol small hit determination process P_TLITTLE_CHK in step S305 is executed, the winning symbol buffer with buffer number "0" is loaded (step AKS306). The winning symbol buffer with buffer number "0" is the first winning symbol buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol buffer, or the second winning symbol buffer included in the second reserved memory buffer with buffer number "0" in the second special symbol buffer. In step AKS306, the stored value of the winning symbol buffer can be read from the first special symbol buffer or the second special symbol buffer in response to the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal process P_TNORMAL. For example, it is sufficient if the upper address F0[H] of the game work area, which is the working area, is set to the upper byte of the buffer pointer by a transfer command, and the lower address of the special pattern determination buffer stored in the first special pattern determination control table or the second special pattern determination control table pointed to by the table pointer is set to the lower byte of the buffer pointer by a transfer command, and then the stored data of the address in the game work area pointed to by the buffer pointer can be read to read the random number MR1-2 for the winning pattern stored in the winning pattern buffer with buffer number "0".

After step AKS306, the special symbol buffer lower address is loaded (step AKS307). The special symbol buffer lower address is the address of the first special symbol buffer or the second special symbol buffer provided in the game work area of RAM 102. In step AKS307, a different lower address can be specified corresponding to the first special symbol determination control table or the second special symbol determination control table whose address is set by the special symbol normal processing P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the lower address B8 [H] of the first special symbol buffer is set in the lower byte of the buffer pointer. Also, when the second special symbol determination control table is set, a value indicating the lower address B9 [H] of the second special symbol buffer is set in the lower byte of the buffer pointer. In the upper byte of the buffer pointer, the upper address F0 [H] of the game work area has already been stored by step AKS306.

Following step AKS307, the special symbol information setting process P_TZU_SET is executed (step AKS308). The special symbol information setting process P_TZU_SET makes it possible to determine the confirmed special symbol to be stopped and displayed in the special symbol game, and to store the special symbol pattern designation value corresponding to the determination result in the special symbol buffer. Following the special symbol information setting process P_TZU_SET, the work setting table address after the special symbol hit determination is set (step AKS309). The work setting table address after the special symbol hit determination is the address of the first special symbol hit determination work setting table or the second special symbol hit determination work setting table stored in the game data area of ROM 101. In step AKS309, a different address in the game data area can be specified in response to the first special symbol hit determination control table or the second special symbol hit determination control table whose address is set by the special symbol normal process P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the address 12BB [H] of the work setting table after the first special symbol hit determination is set in the pointer. Also, when the second special symbol determination control table is set, a value indicating the address 12C0 [H] of the work setting table after the second special symbol hit determination is set in the pointer.

After step AKS309, the data set process P_DATASET is executed (step AKS310), and the special symbol determination process P_TDECISION is completed. The data set process P_DATASET in step AKS310 uses the work setting table after the special symbol hit determination whose address was set in step AKS309 to clear the special symbol determination buffer and the winning symbol buffer in the first reserved memory buffer or the second reserved memory buffer with buffer number "0", thereby making them initializeable. For example, when the first special symbol hit determination work setting table is set, the first special symbol determination buffer and the first winning symbol buffer are initialized in the first reserved memory buffer with buffer number "0" included in the first special symbol reserve buffer. Also, when the second special symbol hit determination work setting table is set, the second special symbol determination buffer and the second winning symbol buffer are initialized in the second reserved memory buffer with buffer number "0" included in the second special symbol reserve buffer.

Figure 10-21 is a diagram for explaining an example of the use of data configuration related to the special symbol determination process P_TDECISION. In the special symbol determination process P_TDECISION, the special symbol big win determination process P_TFVR_CHK in step AKS304 and the special symbol small win determination process P_TLITTLE_CHK in step AKS305 use the random number MR1-1 for special symbol determination to determine whether the display result in the variable display of the special symbol is to be a "big win" or a "small win" in response to the start of the variable display. Also, the special symbol information setting process P_TZU_SET in step AKS308 uses the special symbol buffer with the lower address loaded in step AKS307. In this way, the special symbol determination process P_TDECISION enables control of the special symbol game, which is the variable display of special symbols, using the random number MR1-1 for special symbol determination and the special symbol buffer.

Figure 10-21 (A) shows a special symbol determination example AKC01 by the special symbol jackpot determination process P_TFVR_CHK in step AKS304 and the special symbol small jackpot determination process P_TLITTLE_CHK in step AKS305. The special symbol jackpot determination process P_TFVR_CHK in step AKS304 makes it possible to execute a comparison operation with the jackpot determination value to determine whether the value of the random number MR1-1 for special symbol determination is within the jackpot determination range. The jackpot determination value includes a jackpot lower limit determination value and a jackpot upper limit determination value. When the value of the random number MR1-1 is subtracted from the jackpot lower limit determination value, if the carry flag is in the off state, the value of the random number MR1-1 is equal to or less than the jackpot lower limit determination value, and if the carry flag is in the on state, the value of the random number MR1-1 is a value exceeding the jackpot lower limit determination value. If the value of the random number MR1-1 is equal to or less than the jackpot lower limit judgment value, it is not within the jackpot judgment range, and the special symbol jackpot judgment process P_TFVR_CHK is terminated to return to the special symbol judgment process P_TDECISION. On the other hand, if the value of the random number MR1-1 is greater than the jackpot lower limit judgment value, the value of the random number MR1-1 is subtracted from the jackpot upper limit judgment value. At this time, if the carry flag is in the off state, the value of the random number MR1-1 is equal to or less than the jackpot upper limit judgment value, and if the carry flag is in the on state, the value of the random number MR1-1 is greater than the jackpot upper limit judgment value. Therefore, if the value of the random number MR1-1 is equal to or less than the jackpot upper limit judgment value, it is within the jackpot judgment range, and 01 [H], which is the jackpot designated value, is stored in the hit flag. If the value of the random number MR1-1 exceeds the jackpot upper limit judgment value, it is not within the jackpot judgment range, and the special pattern jackpot judgment process P_TFVR_CHK is terminated, returning to the special pattern judgment process P_TDECISION.

As an example, the lower limit judgment value for a jackpot may be preset to "60000" and the upper limit judgment value to "60285". As a result, as in the special pattern judgment example AKC01, when the start port winning designation value corresponds to "1" and "2" and the value of the random number MR1-1 is within the jackpot judgment range from "60001" to "60285", the judgment result for the special pattern display result will be "jackpot".

The special symbol small hit determination process P_TLITTLE_CHK in step AKS305 makes it possible to perform a comparison operation with the small hit determination value to determine whether the value of the random number MR1-1 for special symbol determination is within the small hit determination range. The small hit determination value includes a small hit lower limit determination value and a small hit upper limit determination value. When the value of the random number MR1-1 is subtracted from the small hit lower limit determination value, if the carry flag is in the off state, the value of the random number MR1-1 is a value below the small hit lower limit determination value, and if the carry flag is in the on state, the value of the random number MR1-1 is a value above the small hit lower limit determination value. If the value of the random number MR1-1 is a value below the small hit lower limit determination value, it corresponds to not being within the small hit determination range, and by terminating the special symbol small hit determination process P_TLITTLE_CHK, it returns to the special symbol determination process P_TDECISION. On the other hand, if the value of the random number MR1-1 is a value that exceeds the small hit lower limit judgment value, the value of the random number MR1-1 is subtracted from the small hit upper limit judgment value. At this time, if the carry flag is in the off state, the value of the random number MR1-1 is a value equal to or less than the small hit upper limit judgment value, and if the carry flag is in the on state, the value of the random number MR1-1 is a value equal to or less than the small hit upper limit judgment value, and 02 [H], which is the small hit designated value, is stored in the hit flag in response to being within the small hit judgment range. If the value of the random number MR1-1 is a value that exceeds the small hit upper limit judgment value, the special pattern small hit judgment process P_TLITTLE_CHK is terminated in response to not being within the small hit judgment range, and the process returns to the special pattern judgment process P_TDECISION. The small hit upper limit judgment value may be set to a different value depending on whether the start port winning designated value is "1" or "2".

As an example, the small win lower limit judgment value may be preset to be the same "21000" whether the starting port winning designation value is "1" or "2". The small win upper limit judgment value may be preset to be "21285" when the starting port winning designation value is "1" and "29282" when the starting port winning designation value is "2". As a result, as in the special pattern judgment example AKC01, when the starting port winning designation value corresponds to "1" and the value of the random number MR1-1 is within the small win judgment range from "21001" to "21285", or when the starting port winning designation value corresponds to "2" and the value of the random number MR1-1 is within the small win judgment range from "21001" to "29282", the judgment result for the special pattern display result is "small win".

Figure 10-21 (B) shows a configuration example AKB31 of the special symbol buffer area. The special symbol buffer area of the configuration example AKB31 can store a special symbol pattern designation value corresponding to a determined special symbol that is stopped and displayed as a display result of the special symbol. This special symbol buffer area includes a first special symbol buffer at address F0B8 [H] and a second special symbol buffer at address F0B9 [H]. The first special symbol buffer can store a special symbol pattern designation value when the first special symbol game is executed by the first special symbol display device 4A. The second special symbol buffer can store a special symbol pattern designation value when the second special symbol game is executed by the second special symbol display device 4B. The special symbol pattern designation value is a designation value of a display pattern corresponding to a determined special symbol that is a display result in the variable display of the special symbol by the first special symbol display device 4A or the second special symbol display device 4B, and includes a big win special symbol pattern designation value and a small win special symbol pattern designation value. The big win special symbol pattern designation value is a designation value of a display pattern corresponding to a confirmed special symbol displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result in the variable display of the special symbol is "big win". The small win special symbol pattern designation value is a designation value of a display pattern corresponding to a confirmed special symbol displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result in the variable display of the special symbol is "small win".

Figure 10-22 is a flowchart showing an example of the special symbol information setting process P_TZU_SET. The special symbol information setting process P_TZU_SET is included in the processes that can be called from the special symbol determination process P_TDECISION shown in Figure 10-20, and can be executed in step AKS308 after the special symbol big win determination process P_TFVR_CHK in step AKS304 and the special symbol small win determination process P_LITTLE_CHK in step AKS305 are executed. When the CPU 103 executes the special symbol information setting process P_TZU_SET, it loads a win flag (step AKS321). The win flag is provided in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1), and is assigned address F032 [H]. In step AKS321, the hit flag is loaded by a transfer command to read out the stored data at the specified address in the game work area of RAM 102. Then, a calculation jump command that can compare the hit flag with a judgment value corresponding to the jackpot specified value is used to confirm that the hit flag is not the jackpot specified value (step AKS322).

When the winning flag is the jackpot designated value corresponding to step AKS322 (step AKS322; No), the winning symbol buffer with buffer number "0" is set (step AKS323). The winning symbol buffer with buffer number "0" has its stored value loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20. This loaded content can be set as the processing target by transferring it to a processing register included in the internal register of CPU 103. For the winning symbol buffer with buffer number "0" set in this way, its stored value is stored in the special symbol buffer (step AKS324). The special symbol buffer is the first special symbol buffer or the second special symbol buffer whose lower address has been loaded by step AKS307 of the special symbol determination process P_TDECISION shown in FIG. 10-20. As a result, for the random number MR1-2 for the winning symbol stored in the winning symbol buffer with buffer number "0", the numerical data indicating the random number value is stored in the first special symbol buffer or the second special symbol buffer. Therefore, the numerical data indicating the value of the random number MR1-2 corresponds to the special symbol whose confirmed special symbol is the winning symbol when the special symbol display result is "jackpot", and can be used as a jackpot special symbol pattern designation value.

Following step AKS324, the start port winning buffer with buffer number "0" is loaded to the start port winning designated value (step AKS325). The start port winning buffer with buffer number "0" is provided in the start port winning buffer area of the configuration example AKB22 shown in FIG. 10-17 (B2), and is assigned address F0BB [H]. In step AKS325, the start port winning buffer with buffer number "0" is loaded by a transfer command to read stored data from the memory area of the specified address in the game work area of RAM 102.

After step AKS325, the jackpot information data selection process P_TFVR_ZU is executed (step AKS326). The jackpot information data selection process P_TFVR_ZU can determine the jackpot pattern designation value using the start-up winning designation value loaded by step AKS325 and the storage value of the winning pattern buffer loaded by step AKS306 of the special pattern determination process P_TDECISION shown in FIG. 10-20, and can set the jackpot information setting data corresponding to the determined result. The jackpot information setting data is data indicating the jackpot performance designation value, the fanfare display designation value, and the jackpot end display designation value. The jackpot pattern designation value determined by this jackpot information data selection process P_TFVR_ZU is stored in the jackpot pattern determination buffer (step AKS327). The jackpot symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F035 [H]. In step AKS327, the jackpot symbol designation value is stored by a transfer command for writing to the memory area of the designated address in the game work area of RAM 102.

After step AKS327, the data for setting the jackpot information is transferred (step AKS328). In this case, in the jackpot information setting table stored in the game data area of ROM 101, the storage address of the data for setting the jackpot information corresponding to the result of determining the jackpot pattern designation value is set in the pointer that designates the transfer source. Also, the address of the performance pattern information buffer provided in the game work area of RAM 102 is set in the buffer pointer that designates the transfer destination. Furthermore, the data size of the data for setting the jackpot information is set in the number of transfers. After that, the data for setting the jackpot information read from the jackpot information setting table is transferred and stored in the performance pattern information buffer, fanfare display buffer, and jackpot end display buffer by a block transfer command. At this time, the variable command designation buffer is set (step AKS329). The variable command designation buffer is provided in the game work area of RAM 102 at the next address of the jackpot end display buffer, and the stored value can be set using the destination address updated by the block transfer command of step AKS327. For example, the variable command designation value 01 [H], which corresponds to the special chart display result being determined to be a "jackpot", can be set as the stored value of the variable command designation buffer. Note that the stored value may be initialized to 00 [H] by clearing the variable command designation buffer in response to the presentation state after the end of the jackpot game state or the stored value of the presentation pattern information buffer.

When the variable command designation buffer is set in step AKS329, the maximum number of times the large prize opening is performed is set (step AKS330). The maximum number of times the large prize opening is performed is set in the game work area of RAM 102 at the next address of the variable command designation buffer, and can store the maximum number of times the large prize opening is controlled to be open in a large prize game state. In step AKS330, the maximum number of times the large prize opening is performed can be determined using the jackpot pattern designation value determined in the jackpot information data selection process P_TFVR_ZU in step AKS326 and the maximum number of times the large prize opening is performed table stored in the game data area of ROM 101. The stored value corresponding to the maximum number of times the large prize opening is determined at this time can be stored in the maximum number of times the large prize opening is performed buffer by a transfer command for writing it to the memory area of the designated address in the game work area of RAM 102.

If the hit flag is not the big hit designated value in response to step AKS322 (step AKS322; Yes), the hit flag and the judgment value corresponding to the small hit designated value are compared by an arithmetic jump instruction to confirm that the hit flag is not the small hit designated value (step AKS331). If the hit flag is the small hit designated value (step AKS331; No), the small hit special symbol pattern designated value is stored in the special symbol buffer (step AKS332). The small hit special symbol pattern designated value may be created by adding a preset small hit symbol addition value to the stored value read from the hit symbol buffer with buffer number "0". In addition, the small hit special symbol pattern designated value may be a value different from the big hit special symbol pattern designated value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer whose lower address is loaded by step AKS307 of the special symbol determination process P_TDECISION shown in FIG. 10-20. In step AKS332, the small win special symbol pattern designation value created using the small win symbol addition value or the like is stored in the first special symbol buffer or the second special symbol buffer by a transfer command for writing the value to a memory area at a specified address in the game work area of RAM 102.

After storing the small win special symbol pattern designation value in step AKS332, the small win symbol designation value is determined (step AKS333). The small win symbol designation value can be determined using the stored value of the winning symbol buffer loaded in step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20 and the first small win state setting table or the second small win state setting table set corresponding to the starting hole winning designation value. The small win symbol designation value determined at this time is stored in the small win symbol determination buffer (step AKS334). The small win symbol determination buffer is provided in the special symbol control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F036 [H]. In step AKS334, the small win symbol designation value may be stored by a transfer command for writing to the memory area of the designated address in the game work area of RAM 102.

After step AKS334, a small win effect designation value is determined (step AKS335). The small win effect designation value can be determined using the small win information setting table stored in the game data area of ROM 101 and the small win pattern designation value determined in step AKS333. The small win effect designation value determined at this time is stored in the effect pattern information buffer (step AKS336). In step AKS336, the small win effect designation value determined in step AKS335 is stored in the effect pattern information buffer by a transfer command for writing the small win effect designation value determined in step AKS335 to a memory area of a specified address in the game work area of RAM 102.

When the small hit performance designation value is stored by step AKS336, the small hit information setting data is transferred (step AKS337). The small hit information setting data is data indicating the small hit fanfare display designation value and the small hit ending display designation value. In step AKS337, in the small hit information setting table stored in the game data area of ROM 101, the storage address of the small hit information setting data corresponding to the determination result of the small hit performance designation value is set to the pointer that designates the transfer source. In addition, the address of the small hit fanfare display buffer provided in the game work area of RAM 102 is set to the transfer destination. Furthermore, the data size of the small hit information setting data is set to the transfer count. After that, the small hit information setting data read from the small hit information setting table is transferred and stored to the small hit fanfare display buffer and the small hit ending display buffer by a block transfer command.

When the hit flag is not the small hit designated value in response to step AKS331 (step AKS331; Yes), the miss special symbol pattern designated value is stored in the special symbol buffer (step AKS338). The miss special symbol pattern designated value may be a value different from the big hit special symbol pattern designated value and the small hit special symbol pattern designated value. For example, F1 [H] may be set as the miss special symbol pattern designated value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer whose lower address is loaded by step AKS307 of the special symbol determination process P_TDECISION shown in FIG. 10-20. In step AKS338, the miss special symbol pattern designated value prepared in advance may be stored in the first special symbol buffer or the second special symbol buffer by a transfer command for writing the miss special symbol pattern designated value in the memory area of the designated address in the game work area of RAM 102.

Following step AKS338, the effect pattern information buffer is cleared (step AKS339). The effect pattern information buffer can store effect designation values corresponding to the special chart display result being a "big win" or a "small win". On the other hand, in the case where the special chart display result is a "miss", the effect pattern information buffer is cleared, thereby initializing the stored value to 00 [H]. In addition, the variable command designation buffer is cleared (step AKS340).

After steps AKS330, AKS337, and AKS340, a transfer command for setting a pointer is issued to set the pre-change start command transmission table address (step AKS341). The pre-change start command transmission table address is the address of the pre-change start command transmission table stored in the game data area of ROM 101. Then, the command set process P_COM_SET is executed (step AKS342), and the special symbol information setting process P_TZU_SET ends.

Figure 10-23 is a flow chart showing an example of the jackpot information data selection process P_TFVR_ZU. The jackpot information data selection process P_TFVR_ZU is called in the special symbol information setting process P_TZU_SET shown in Figure 10-22, and can be executed in step AKS326 if the hit flag is the jackpot designated value in step AKS322. When the CPU 103 executes the jackpot information data selection process P_TFVR_ZU, it sets the second jackpot state setting table address by a transfer command for setting a pointer (step AKS401). The second jackpot state setting table address is the address of the second jackpot state setting table stored in the game data area of the ROM 101.

Following step AKS401, it is confirmed that the starting hole winning designation value is not "1" (step AKS402). The starting hole winning designation value is stored in the internal register of the CPU 103 by step AKS325 of the special symbol information setting process P_TZU_SET shown in FIG. 10-22. If this starting hole winning designation value is "1" (step AKS402; No), a transfer command for setting a pointer is issued to set the table address for setting the first jackpot state (step AKS403). The table address for setting the first jackpot state is the address of the table for setting the first jackpot state stored in the game data area of the ROM 101. In step AKS403, the value of the pointer is overwritten by a transfer command for setting a pointer. In this way, in the special symbol information setting process P_TZU_SET, after setting the second jackpot state setting table address in step AKS401, the starting hole winning designation value corresponds to "1" in step AKS402, and the first jackpot state setting table address is reset by overwriting in step AKS403. This makes it possible to reduce the program capacity required for table setting when the second jackpot state setting table is used more frequently than the first jackpot state setting table, thereby improving the marketability of the pachinko gaming machine 1. Also, when the second jackpot state setting table is used more frequently than the first jackpot state setting table, the process using the jump command as a branch command is simplified, making it easier to check at the design stage, and improving the marketability of the pachinko gaming machine 1.

If the starting hole winning designation value is "2" and not "1" in response to step AKS402 (step AKS401; Yes), or after step AKS403, a winning symbol buffer is set (step AKS404). The winning symbol buffer is the winning symbol buffer with buffer number "0" whose stored value was loaded by step AKS306 of the special symbol determination process P_TDECISION shown in FIG. 10-20. This loaded content can be set as the processing target by transferring it to a processing register included in the internal register of CPU 103. The stored value of the winning symbol buffer set in this way is used together with the second jackpot state setting table set by step AKS401 or the first jackpot state setting table set by step AKS403 to execute the second allocation determination value comparison process P_HANTEI2 (step AKS405).

The second allocation judgment value comparison process P_HANTEI2 sets the stored data of the top address of the table as the start number data, the stored data of the next address as the processing count data, and initially sets the start number data to the allocation result data. After that, the process of comparing the numerical data set as the comparison value with the allocation judgment value indicated by the stored data at the next address and subsequent addresses of the processing count data is made executable in increasing order from the top to the bottom of the table addresses until the allocation judgment value exceeds the comparison value. At this time, if the allocation judgment value is equal to or less than the comparison value, the allocation result data is updated to add 1 and the next comparison is performed, and if the allocation judgment value exceeds the comparison value, the second allocation judgment value comparison process P_HANTEI2 ends. If the number of comparisons corresponds to the processing count data but the allocation judgment value does not exceed the comparison value, the process can be repeated from the setting of the start number data and the processing count data using the stored data at the next address and subsequent addresses. In the second allocation judgment value comparison process P_HANTEI2 in step AKS405, the random number MR1-2 for the winning symbol, which is the stored value in the winning symbol buffer, is set as a comparison value, and the jackpot symbol designation value indicated by the allocation result data can be determined as the type of jackpot game state corresponding to the display result by the first special symbol display device 4A or the second special symbol display device 4B, based on the stored data in the first jackpot state setting table or the second jackpot state setting table. The second allocation judgment value comparison process P_HANTEI2 may be executed even when the small jackpot symbol designation value is determined by step AKS333 in the special symbol information setting process P_TZU_SET. In this case, the random number MR1-2 for the winning pattern, which is the stored value in the winning pattern buffer, is set as a comparison value, and the small win designation value indicated by the allocation result data can be determined as the type of small win game state corresponding to the display result by the first special pattern display device 4A or the second special pattern display device 4B, based on the stored data in the first small win state setting table or the second small win state setting table.

When the second allocation judgment value comparison process P_HANTEI2 of step AKS405 is completed, data for setting the jackpot information is determined (step AKS406). The data for setting the jackpot information can be selected from among multiple types of data sets prepared in advance using the jackpot information data designation table selected corresponding to the stored value of the presentation state selection buffer and the jackpot pattern designation value determined by the second allocation judgment value comparison process P_HANTEI2 of step AKS405. The presentation state selection buffer can be set to a stored value corresponding to the presentation state after the end of the jackpot game state.

Figure 10-24 is a diagram for explaining an example of the use of data configuration corresponding to the control of the jackpot game state with respect to the special symbol information setting process P_TZU_SET and the jackpot information data selection process P_TFVR_ZU. When the hit flag is a jackpot designated value in step AKS322 of the special symbol information setting process P_TZU_SET, the jackpot information data selection process P_TFVR_ZU can be executed in step AKS326. In this jackpot information data selection process P_TFVR_ZU, the second allocation judgment value comparison process P_HANTEI2 in step AKS405 is executed using the second jackpot state setting table whose address is set in step AKS401 or the first jackpot state setting table whose address is set in step AKS403, thereby making it possible to determine the jackpot symbol designated value. Then, in step AKS328 of the special symbol information setting process P_TZU_SET, the jackpot information setting data read from the jackpot information setting table corresponding to the jackpot symbol designated value can be transferred to and stored in the performance symbol information buffer, fanfare display buffer, and jackpot end display buffer. The performance symbol information buffer, fanfare display buffer, and jackpot end display buffer are provided in the performance symbol information area, and can store setting data when controlled to a jackpot game state. In addition, in step AKS330 of the special symbol information setting process P_TZU_SET, the maximum number of times the jackpot opening port is opened can be determined corresponding to the jackpot symbol designated value using the maximum number of times the jackpot opening port is opened table.

In this way, the jackpot information data selection process P_TFVR_ZU makes it possible to determine the jackpot pattern designated value using the first jackpot state setting table or the second jackpot state setting table. The special pattern information setting process P_TZU_SET makes it possible to set the storage values of the performance pattern information buffer, fanfare display buffer, and jackpot display buffer provided in the performance pattern information area, and also makes it possible to determine the maximum number of times the large prize opening will be opened corresponding to the jackpot pattern designated value.

Figure 10-24 (A1) shows a configuration example AKT41 of the first jackpot state setting table. In the first jackpot state setting table of the configuration example AKT41, the value 00 [H] corresponding to the jackpot pattern designated value "1" is stored in the first address 1AFD [H], and the value 0A [H] indicating the number of processes is stored in the next address 1AFE [H]. The stored data from address 1AFF [H] onwards indicates allocation judgment values corresponding to the jackpot pattern designated values "1" to "10". When the first jackpot state setting table of the configuration example AKT41 is used, the second allocation judgment value comparison process P_HANTEI2 of step AKS405 can determine one of the jackpot pattern designated values "1" to "10" in response to the random number MR1-2 for the winning pattern indicated by the stored value of the winning pattern buffer. For example, if the random number MR1-2 for the winning symbol is 00 [H], which corresponds to the minimum random number value of "0", the jackpot symbol designation value "1" is determined.

Figure 10-24 (A2) shows a configuration example AKT42 of the second jackpot state setting table. In the second jackpot state setting table of the configuration example AKT42, the value 0A [H] corresponding to the jackpot pattern designated value "11" is stored at the first address 1B09 [H], and the value 04 [H] indicating the number of processes is stored at the next address 1B0A [H]. The stored data from address 1B0B [H] onwards indicates the allocation judgment value corresponding to the jackpot pattern designated values "11" to "14". When the second allocation judgment value comparison process P_HANTEI2 of step AKS405 is used for the second jackpot state setting table of the configuration example AKT42, it can determine one of the jackpot pattern designated values "11" to "14" in response to the random number MR1-2 for the winning pattern indicated by the stored value of the winning pattern buffer. For example, if the random number MR1-2 for the winning symbol is 00 [H], which corresponds to the minimum random number value of "0", the jackpot symbol designation value "11" is determined.

Figure 10-24 (B) shows a configuration example AKB41 of the effect symbol information area. The effect symbol information area of the configuration example AKB41 can store various data related to game control and effect control, including variable display of effect symbols, in response to control in the big win game state or small win game state. This effect symbol information area includes an effect symbol information buffer at address F056 [H], a fanfare display buffer at address F057 [H], a big win end display buffer at address F058 [H], a variable command designation buffer at address F059 [H], a large prize opening number maximum value buffer at address F05A [H], a small win fanfare display buffer at address F05F [H], and a small win ending display buffer at address F060 [H].

Figure 10-24 (C) shows an example of determining the maximum number of times the large prize opening is performed AKD01. In step AKS330 of the special symbol information setting process P_TZU_SET, the maximum number of times the large prize opening is performed corresponding to the jackpot symbol designated value determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS405 of the jackpot information data selection process P_TFVR_ZU can be determined. In the example of determining the maximum number of times the large prize opening is performed AKD01, the maximum number of times the large prize opening is performed can be determined to be any of the following, including 02 [H] corresponding to "2", 04 [H] corresponding to "4", 07 [H] corresponding to "7", and 0A [H] corresponding to "10". In addition, the first jackpot state setting table of the configuration example AKT41 is used when the starting hole winning designated value is "1", and makes it possible to determine any of the jackpot symbol designated values "1" to "10". In contrast, the second jackpot state setting table of the configuration example AKT42 is used when the starting hole winning designation value is "2", and allows the determination of any one of the jackpot pattern designation values "11" to "14". On the other hand, in the example AKD01 of determining the maximum number of times of opening the jackpot, when the jackpot pattern designation value is 00[H] to 09[H] corresponding to "1" to "10", the maximum number of times of opening the jackpot can be determined to either 04[H] corresponding to "4" or 0A[H] corresponding to "10". On the other hand, in the example AKD01 of determining the maximum number of times of opening the jackpot, when the jackpot pattern designation value is 0A[H] to 0D[H] corresponding to "11" to "14", the maximum number of times of opening the jackpot can be determined to either 02[H] corresponding to "2", 04[H] corresponding to "4", 07[H] corresponding to "7", or 0A[H] corresponding to "10".

In this way, in the example AKD01 for determining the maximum number of times the large prize opening is performed, when the jackpot pattern designated value is 00 [H] corresponding to "1", the maximum number of times the large prize opening is performed is 04 [H] corresponding to "4". This corresponds to the smaller "4" of the maximum number of times the large prize opening can be determined when the starting prize opening designated value is "1", which is either "4" or "10". The jackpot pattern designated value "1" can be determined when the random number MR1-2 for the winning pattern indicated by the stored value in the winning pattern buffer is the minimum random number value "0". Also, in the example AKD01 for determining the maximum number of times the large prize opening is performed, when the jackpot pattern designated value is 0A [H] corresponding to "11", the maximum number of times the large prize opening is performed is 02 [H] corresponding to "2". This corresponds to the smallest "2" of the maximum number of times the large prize opening can be determined when the starting prize opening designated value is "2", which is either "2", "4", "7", or "10". The jackpot symbol designation value "11" can be determined when the random number MR1-2 for the winning symbol, which is indicated by the stored value in the winning symbol buffer, is the minimum random number value "0". Therefore, among the special symbol games in which the special symbol is variably displayed on the first special symbol display device 4A or the second special symbol display device 4B, when the random number MR1-2 for the winning symbol is the minimum random number value "0" corresponding to the special symbol game in which the special symbol display result is a "jackpot", the display result is not determined to be more advantageous than when it is other than the minimum random number value. This makes it possible to update the random number value appropriately to prevent fraudulent acts due to a malfunction of the first random number value when the random number MR1-2 for the winning symbol is set to the first random number value.

Figure 10-25 is a diagram for explaining an example of the use of a data configuration corresponding to the control of the small win game state with respect to the special pattern information setting process P_TZU_SET, etc. If the hit flag is a small win designated value in step AKS331 of the special pattern information setting process P_TZU_SET, step AKS333 makes it possible to determine the small win pattern designated value. In this case, if the starting hole winning designated value is "1", the small win pattern designated value is determined using the first small win state setting table. On the other hand, if the starting hole winning designated value is "2", the small win pattern designated value is determined using the second small win state setting table. After that, in step AKS339 of the special pattern information setting process P_TZU_SET, the small win performance designated value determined in step AKS338 is stored in the performance pattern information buffer. Then, in step AKS340 of the special symbol information setting process P_TZU_SET, the small win information setting data read from the small win information setting table corresponding to the small win symbol designation value can be transferred to and stored in the small win fanfare display buffer and the small win ending display buffer. The performance symbol information buffer, small win fanfare display buffer, and small win ending display buffer are provided in the performance symbol information area shown in FIG. 10-24 (B), and can store setting data when controlled to a small win game state. Also, in step S112 of the special symbol process process P_TPROC shown in FIG. 6, when the special symbol process code corresponds to 03 [H] and the small win opening pre-processing P_TLFAN is executed, the opening time and number of openings of the large prize opening can be determined using the small win opening work setting table, etc.

In this way, the special pattern information setting process P_TZU_SET makes it possible to determine the small win pattern designation value using the first small win state setting table or the second small win state setting table. The special pattern information setting process P_TZU_SET can also set the storage values of the performance pattern information buffer, small win fanfare display buffer, and small win ending display buffer provided in the performance pattern information area. Furthermore, the small win pre-opening process P_TLFAN, which is executed in response to control to the small win game state, can determine the opening time and number of times the large prize opening is opened.

Figure 10-25 (A1) shows a configuration example AKT43 of the first small win state setting table. In the first small win state setting table of the configuration example AKT43, the value 00 [H] corresponding to the small win pattern designated value "1" is stored in the first address 1B0B [H], and the value 01 [H] indicating the number of processes is stored in the next address 1B0C [H]. The stored data in address 1B0D [H] indicates the allocation judgment value corresponding to the small win pattern designated value "1". When the first small win state setting table of the configuration example AKT43 is used, step AKS333 of the special pattern information setting process P_TZU_SET can determine only the small win pattern designated value "1" in response to the random number MR1-2 for the winning pattern indicated by the stored value in the winning pattern buffer. Therefore, when the random number MR1-2 for the winning symbol is 00[H], which corresponds to the minimum random number value of "0", the small winning symbol designation value "1" is determined.

Figure 10-25 (A2) shows a configuration example AKT44 of the second small win state setting table. In the second small win state setting table of the configuration example AKT44, the value 01 [H] corresponding to the small win pattern designated value "2" is stored in the first address 1B0E [H], and the value 06 [H] indicating the number of processes is stored in the next address 1B0F [H]. The stored data from address 1B10 [H] onwards indicates the allocation judgment value corresponding to the small win pattern designated values "2" to "7". When the second small win state setting table of the configuration example AKT44 is used, step AKS333 of the special pattern information setting process P_TZU_SET can determine one of the small win pattern designated values "2" to "7" in response to the random number MR1-2 for the winning pattern indicated by the stored value of the winning pattern buffer. For example, if the random number MR1-2 for the winning symbol is 00[H], which corresponds to the minimum random number value of "0", the small winning symbol designation value "2" is determined.

Figure 10-25 (B) shows an example of determining the large prize opening mode AKD02. In the small prize opening pre-processing P_TLFAN, it is possible to determine the large prize opening mode corresponding to the start prize opening designated value. The large prize opening mode can be determined to be one of multiple modes with different opening times and opening counts of the large prize opening. In the example of determining the large prize opening mode AKD02, the opening time of the large prize opening is determined to be 36 [ms] and the number of openings is 15 [times] in response to the start prize opening designated value "1". In the example of determining the large prize opening mode AKD02, the opening time of the large prize opening is determined to be 1600 [ms] and the number of openings is 1 [time] in response to the start prize opening designated value "2".

In this way, the large prize opening mode in the small prize game state can be determined to have different opening times and opening counts of the large prize opening in response to the starting prize opening designated value, regardless of the value of the small prize pattern designated value. The small prize pattern designated value can be determined in response to the random number MR1-2 for the winning pattern indicated by the stored value of the winning pattern buffer. If the starting prize opening designated value is the same value, the large prize opening mode is determined to be common when the random number MR1-2 for the winning pattern is the minimum random number value "0" and when it is other than the minimum random number value. Therefore, among the special pattern games in which the special pattern is variably displayed on the first special pattern display device 4A or the second special pattern display device 4B, when the random number MR1-2 for the winning pattern is the minimum random number value "0" in response to the special pattern game in which the special pattern display result is "small prize", the display result with a higher advantage is not determined compared to when it is other than the minimum random number value. This makes it possible to update the random number value appropriately to prevent fraudulent activity due to a malfunction of the first random number value when the random number MR1-2 for the winning symbol is set as the first random number value.

Figure 10-26 is a flow chart showing an example of the variable pattern setting process P_TPATSET. The variable pattern setting process P_TPATSET is included in the process that can be called from the normal special symbol process P_TNORMAL shown in Figure 10-18, and can be executed in step AKS249 when variable display of special symbols is started. When the variable pattern setting process P_TPATSET is executed, the CPU 103 loads the hit flag (step AKS361). The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1), and is assigned the address F032 [H]. In step AKS361, the hit flag may be loaded by a transfer command for reading out the stored data of the specified address in the game work area of the RAM 102. Then, it is confirmed that the hit flag is not the jackpot specified value by an arithmetic jump command that can compare the hit flag with a judgment value corresponding to the jackpot specified value (step AKS362).

When the hit flag is the jackpot designated value corresponding to step AKS362 (step AKS362; No), the jackpot pattern determination buffer is loaded (step AKS363). The jackpot pattern determination buffer is provided in the special pattern control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F035 [H]. In step AKS363, the jackpot pattern determination buffer may be loaded by a transfer command for reading out the stored data of the specified address in the game work area of RAM 102. At this time, the state-specific jackpot selection table address is set by a transfer command for setting the pointer (step AKS364). The state-specific jackpot selection table address is the address of the state-specific jackpot selection table stored in ROM 101. After that, the winning time fluctuation pattern type table selection process P_TPATA is executed (step AKS365). The winning fluctuation pattern type table selection process P_TPATA in step AKS365 makes it possible to select a fluctuation pattern type allocation table when the special chart display result corresponds to a "jackpot."

If the hit flag is not the big hit designated value in response to step AKS362 (step AKS362; Yes), the hit flag is compared with the judgment value corresponding to the small hit designated value by an arithmetic jump command to confirm that the hit flag is not the small hit designated value (step AKS366). If the hit flag is the small hit designated value (step AKS366; No), the variable command designation buffer is set (step AKS367). The variable command designation buffer is provided in the performance pattern information area of the configuration example AKB41 shown in FIG. 10-24 (B), and is assigned the address F059 [H]. In step AKS367, 01 [H] may be stored in the variable command designation buffer by a transfer command for writing to the memory area of the designated address in the game work area of RAM 102. In addition, the small hit pattern judgment buffer is loaded (step AKS368). The small win pattern determination buffer is provided in the special pattern control data area of the configuration example AKB21 shown in FIG. 10-17 (B1), and is assigned the address F036 [H]. In step AKS368, the small win pattern determination buffer is loaded by a transfer command for reading the stored data of the specified address in the game work area of RAM 102. At this time, the state-specific small win selection table address is set by a transfer command for setting a pointer (step AKS369). The state-specific small win selection table address is the address of the state-specific small win selection table stored in ROM 101. After that, the win-time fluctuation pattern type table selection process P_TPATA is executed (step AKS370). The win-time fluctuation pattern type table selection process P_TPATA in step AKS370 makes it possible to select a fluctuation pattern type allocation table in response to the special pattern display result being "small win".

If the hit flag is not the small hit designated value in response to step AKS366 (step AKS366; Yes), the miss time fluctuation pattern type table selection process P_TPATH is executed (step AKS371). The miss time fluctuation pattern type table selection process P_TPATH of step AKS371 corresponds to the special chart display result being "miss", and makes it possible to select a fluctuation pattern type allocation table.

After steps AKS365, AKS370, and AKS371, the buffer for selecting the type of variation pattern with buffer number "0" is loaded (step AKS372). The buffer for selecting the type of variation pattern with buffer number "0" is the first buffer for selecting the type of variation pattern included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer, or the second buffer for selecting the type of variation pattern included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. In step AKS372, after setting the address of the buffer for selecting the type of variation pattern with buffer number "0", a start port winning check process is executed, and if the designated value for the start port winning is "1", the address of the buffer for selecting the type of variation pattern with buffer number "0" is set, and then a transfer command for reading the stored data of the set address is issued to read the random number MR3-3 for selecting the type of variation pattern stored in the buffer for selecting the type of variation pattern with buffer number "0".

When the random number MR3-3 for selecting a variation pattern type is read out by step AKS372, the variation pattern allocation table selection process P_TPATTBL is executed (step AKS373). The variation pattern allocation table selection process P_TPATTBL of step AKS373 makes it possible to select a variation pattern allocation table using the variation pattern type allocation table selected by step AKS365, AKS370, or AKS371 and the random number MR3-3 for selecting a variation pattern type read out by step AKS372.

After step AKS373, the buffer for the variation pattern with buffer number "0" is loaded (step AKS374). The buffer for the variation pattern with buffer number "0" is the first variation pattern buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer, or the second variation pattern buffer included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. In step AKS374, after setting the address of the buffer for the second variation pattern with buffer number "0", a start port winning check process is executed, and if the start port winning designation value is "1", the address of the buffer for the first variation pattern with buffer number "0" is set, and then a transfer command for reading the stored data of the set address is issued, so that the random number MR3-4 for the variation pattern stored in the buffer for the variation pattern with buffer number "0" can be read.

When the random number MR3-4 for the fluctuation pattern is read out by step AKS374, the second allocation judgment value comparison process P_HANTEI2 is executed (step AKS375). The second allocation judgment value comparison process of step AKS375 makes it possible to determine a fluctuation pattern using the fluctuation pattern allocation table selected by step AKS373 and the random number MR3-4 for the fluctuation pattern read out by step AKS374. At this time, the fluctuation pattern designation data corresponding to the determined fluctuation pattern is stored in the performance symbol fluctuation pattern buffer (step AKS376). The performance symbol fluctuation pattern buffer is provided in the game work area of RAM 102, and is capable of storing different fluctuation pattern designation data corresponding to the determined result of the fluctuation pattern.

Following step AKS376, a variable command transmission table is selected (step AKS377). In step AKS377, the variable command transmission table is made selectable using the variable command transmission table selection table and the stored value of the variable command designation buffer. This allows a different variable command transmission table to be selected when the special chart display result is, for example, a "big win" or "small win" and when it is a "miss". The variable command transmission table is configured to include table data indicating the number of processes, the upper byte of the pattern information designation command, the pattern information designation code reference designation value, the upper byte of the performance pattern designation command, the performance pattern designation code reference designation value, the performance pattern change command, and the change pattern designation data reference designation value. Then, the command set process P_COM_SET is executed (step AKS378). The command set process P_COM_SET in step AKS378 makes it possible to transmit the pattern information designation command, the performance pattern designation command, and the performance pattern change command using the variable command transmission table selected in step AKS377. This command set process P_COM_SET in step AKS378 allows the performance control command, which becomes the command at the start of fluctuation, to be sent from the main board 11 to the performance control board 12.

When the fluctuation start command can be sent by step AKS378, the special symbol fluctuation time is set (step AKS379). In step AKS379, a time data expansion process is executed using the special symbol fluctuation time table and the fluctuation pattern designation data, thereby making it possible to set different special symbol fluctuation times corresponding to the result of the fluctuation pattern determination. Next, a transfer command for setting a pointer is used to set the post-fluctuation pattern setting work table address (step AKS380). The post-fluctuation pattern setting work table address is the address of the post-fluctuation pattern setting work table stored in the game data area of ROM 101. Next, data set process P_DATASET is executed (step AKS381), and the fluctuation pattern setting process P_TPATSET is terminated. The data set process P_DATASET in step AKS381 uses the post-variation pattern setting work table whose address was set in step AKS380 to set the special pattern process code to 01 [H], which is the special pattern variation processing designated value, and sets the storage value of the special pattern variation display buffer to 01 [H], which is the special pattern variation display data. In addition, the special pattern display update timer, the buffer for selecting a miss performance with buffer number "0", the buffer for selecting a variation pattern with buffer number "0", and the buffer for the variation pattern with buffer number "0" are cleared to enable initialization. At this time, by referencing different tables depending on whether the start port winning designated value is "1" or "2", it is possible to set or clear different buffers and timers.

Figure 10-27 (A) is a flowchart showing an example of the winning time fluctuation pattern type table selection process P_TPATA. The winning time fluctuation pattern type table selection process P_TPATA is included in the process that can be called from the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, and can be executed in step AKS365 if the winning flag is a jackpot designated value in step AKS362, and can be executed in step AKS370 if the winning flag is a small jackpot designated value in step AKS366. When the winning time fluctuation pattern type table selection process P_TPATA is executed, the CPU 103 loads the presentation state selection buffer (step AKS421). The presentation state selection buffer is provided in the game work area of the RAM 102, and a storage value corresponding to the presentation state after the end of the jackpot game state can be set. In step AKS421, it is sufficient that the stored value in the performance state selection buffer can be read by a transfer command to read the stored data at a specified address in the game work area of RAM 102.

Following step AKS421, a fluctuation pattern type selection table is determined (step AKS422). In step AKS422, the fluctuation pattern type selection table is determined using the state-specific big win selection table or state-specific small win selection table and the stored value of the performance state selection buffer read by step AKS421. The state-specific big win selection table has an address set by step AKS364 when the hit-time fluctuation pattern type table selection process P_TPATA is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26. The state-specific small win selection table has an address set by step AKS369 when the hit-time fluctuation pattern type table selection process P_TPATA is executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26. The state-specific big win selection table and state-specific small win selection table are configured to include table data that allows different variation pattern type selection tables to be determined in response to the stored value of the performance state selection buffer. Therefore, step AKS422 allows different variation pattern type selection tables to be determined in response to the stored value of the performance state selection buffer when the special chart display result is a "big win" or a "small win".

When the variation pattern type selection table is determined by step AKS422, the winning pattern designation value is set (step AKS423). In step AKS423, the loaded contents from the big win pattern determination buffer or the small win pattern determination buffer may be set as the processing target by transferring them to a processing register included in the internal register of the CPU 103. The big win pattern determination buffer is loaded by step AKS363 when the winning time variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. The small win pattern determination buffer is loaded by step AKS368 when the winning time variation pattern type table selection process P_TPATA is executed in step AKS370 of the variation pattern setting process P_TPATSET shown in FIG. 10-26. The stored value of the big win pattern determination buffer indicates the big win pattern designation value. The stored value of the small win pattern determination buffer indicates the small win pattern designation value. The winning symbol designation value set in this manner is used together with the variation pattern type selection table determined in step AKS422 to execute the allocation judgment value comparison process P_HANTEI (step AKS424).

The allocation judgment value comparison process P_HANTE compares the numerical data set as the comparison value with the allocation judgment value indicated by the table storage data in increasing order from the top to the bottom of the table address until the allocation judgment value exceeds the comparison value. At this time, if the allocation judgment value is equal to or less than the comparison value, it proceeds to the next comparison, and makes the table storage data readable as designated data corresponding to the allocation judgment value that exceeds the comparison value. In the allocation judgment value comparison process P_HANTEI of step AKS424, the big win pattern designated value or small win pattern designated value is set as the comparison value, and the designated data corresponding to the allocation judgment value that exceeds the comparison value is read out from the stored data of the variation pattern type selection table.

When the allocation judgment value comparison process P_HANTEI of step AKS424 is completed, the fluctuation pattern type allocation table is determined (step AKS425), and the hit-time fluctuation pattern type table selection process P_TPATA is completed. In step AKS425, the specified data read out by the allocation judgment value comparison process P_HANTEI of step AKS424 is added to the top address of the fluctuation pattern type allocation table, and the address of the fluctuation pattern type allocation table to be used is set in the pointer, making it possible to determine the fluctuation pattern type allocation table.

Figure 10-27 (B1) shows an example AKD11 of a variation pattern type allocation table determination in which the special chart display result corresponds to "jackpot". When the special chart display result is "jackpot", the second allocation judgment value comparison process P_HANTEI2 can determine one of the values 00 [H] to 0D [H] corresponding to the jackpot symbol designated value "1" to "14". When the winning time variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in Figure 10-26, it can determine a variation pattern type allocation table in response to the determination result of the jackpot symbol designated value. In the example of determining the fluctuation pattern type allocation table AKD11, it is possible to determine one of the fluctuation pattern type allocation tables AKU01 to AKU03 in response to the value 00 [H] to 0D [H] indicating the jackpot symbol designation value.

Figure 10-27 (B2) shows an example of a variation pattern type allocation table determination AKD12 in which the special chart display result corresponds to a "small win". When the special chart display result is a "small win", in step AKS333 of the special pattern information setting process P_TZU_SET shown in Figure 10-22, it can be determined to be one of the values 00 [H] to 06 [H] corresponding to the small win pattern designation value "1" to "7". When the winning time variation pattern type table selection process P_TPATA is executed in step AKS370 of the variation pattern setting process P_TPATSET shown in Figure 10-26, it can determine a variation pattern type allocation table in response to the determination result of the small win pattern designation value. In the variation pattern type allocation table determination example AKD12, it can be determined to be one of the variation pattern type allocation tables AKU11 and AKU12 in response to the small win pattern designation value 00 [H] to 06 [H].

Figure 10-28 (A) is a flowchart showing an example of the loss time fluctuation pattern type table selection process P_TPATH. The loss time fluctuation pattern type table selection process P_TPATH is included in the process that can be called from the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, and can be executed in step AKS371 when the hit flag is not the small hit designated value in step AKS366. When the loss time fluctuation pattern type table selection process P_TPATH is executed, the CPU 103 sets the state-specific loss selection table address by a transfer command for setting a pointer (step AKS441). The state-specific loss selection table address is the address of the first state-specific loss selection table or the second state-specific loss selection table stored in the game data area of the ROM 101. In step AKS441, different addresses in the game data area can be specified in response to the start port winning designated value being "1" and "2". This allows the address of the first state-specific miss selection table to be set when the start port winning designation value is "1", and the address of the second state-specific miss selection table to be set when the start port winning designation value is "2". Then, the presentation state selection buffer is loaded (step AKS442). The presentation state selection buffer is provided in the game work area of RAM 102, and a storage value corresponding to the presentation state after the end of the big win game state can be set.

Following step AKS442, a reservation-based miss performance allocation selection table is determined (step AKS443). In step AKS443, the reservation-based miss performance allocation selection table is determined using the first state-based miss selection table or the second state-based miss selection table whose address is set in step AKS441 and the storage value of the performance state selection buffer loaded in step AKS442. The first state-based miss selection table and the second state-based miss selection table are configured to include table data that allows different reservation-based miss performance allocation selection tables to be determined in response to the storage value of the performance state selection buffer. In addition, the reservation-based miss performance allocation selection table is configured to include table data that allows different miss performance allocation tables to be determined in response to the count value of the start port winning memory counter. Therefore, step AKS443 can determine a different pending miss performance allocation selection table according to the stored value in the performance status selection buffer when the start port winning designation value is "1" or "2."

After step AKS443, the start port winning memory counter is loaded (step AKS444). The start port winning memory counter is the first start port winning memory counter when the start port winning designation value is "1" or the second start port winning memory counter when the start port winning designation value is "2". In step AKS444, the second start port winning memory counter address is set to the memory pointer, and then the start port winning check process is executed. If the start port winning designation value is "1", the first start port winning memory counter address is set to the memory pointer, and then a transfer command for reading the stored data at the address set in the memory pointer makes it possible to obtain the count value of the first start port winning memory counter or the second start port winning memory counter.

After step AKS444, allocation judgment value comparison process P_HANTEI is executed (step AKS445). In allocation judgment value comparison process P_HANTEI in step AKS445, the count value of the first start port winning memory counter or the second start port winning memory counter acquired in step AKS444 is set as a comparison value, and designated data corresponding to the allocation judgment value that exceeds the comparison value is read out based on the stored data of the pending miss performance allocation selection table determined in step AKS443.

When the allocation judgment value comparison process P_HANTEI of step AKS445 is completed, a miss effect allocation table is determined (step AKS446). In step AKS446, the designated data read by the allocation judgment value comparison process P_HANTEI of step AKS445 is added to the top address of the miss effect allocation table, and the address of the miss effect allocation table to be used is set in the pointer, making it possible to determine the miss effect allocation table.

After step AKS446, the buffer for selecting a losing performance with buffer number "0" is loaded (step AKS447). The buffer for selecting a losing performance with buffer number "0" is the first buffer for selecting a losing performance included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer, or the second buffer for selecting a losing performance included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. In step AKS447, after setting the address of the second buffer for selecting a losing performance with buffer number "0", if the starting port winning designation value is "1" by the starting port winning check process, the address of the first buffer for selecting a losing performance with buffer number "0" is set, and then the random number MR3-2 for selecting a losing performance stored in the buffer for selecting a losing performance with buffer number "0" can be read by a transfer command for reading the stored data of the set address.

When the random number MR3-2 for selecting a losing performance is read out by step AKS447, the allocation judgment value comparison process P_HANTEI is executed (step AKS448). The allocation judgment value comparison process P_HANTEI of step AKS448 makes it possible to determine the offset value of the variation pattern type allocation table using the losing performance allocation table determined by step AKS446 and the random number MR3-2 for selecting a losing performance read out by step AKS447. In this case, the random number MR3-2 for selecting a losing performance read out by step AKS447 is set as a comparison value, and the offset value of the variation pattern type allocation table indicated by the designated data corresponding to the allocation judgment value that exceeds the comparison value can be read out by the stored data of the losing performance allocation table determined by step AKS446.

When the allocation judgment value comparison process P_HANTEI of step AKS448 is completed, the fluctuation pattern type allocation table is determined (step AKS449), and the miss-time fluctuation pattern type table selection process P_TPATH is completed. In step AKS449, the offset value indicated by the specified data read by the allocation judgment value comparison process P_HANTEI of step AKS448 is added to the top address of the fluctuation pattern type allocation table, and the address of the fluctuation pattern type allocation table to be used is set in the pointer, making it possible to determine the fluctuation pattern type allocation table.

Figure 10-28 (B1) shows an example AKD21 of a miss effect allocation table determination corresponding to a first special symbol miss. A first special symbol miss is when the start port winning designation value corresponds to "1" and the special symbol display result is "miss" in a special symbol game using the first special symbol by the first special symbol display device 4A. When the start port winning designation value is "1", the count value of the first start port winning memory counter can be obtained in step AKS444 of the miss time variation pattern type table selection process P_TPATH. The count value of the first start port winning memory counter indicates the first reserved memory number. Then, the allocation judgment value comparison process P_HANTEI in step AKS445 reads out the designated data corresponding to the count value of the first start port winning memory counter, and in step AKS446, a miss effect allocation table corresponding to the first reserved memory number can be determined. In the example of determining the miss effect allocation table AKD21, it is possible to determine one of the miss effect allocation tables AKV01 to AKV04 in accordance with the first reserved memory number "0" to "3".

Figure 10-28 (B2) shows an example AKD22 of a miss effect allocation table determination corresponding to a miss on the second special symbol. A miss on the second special symbol is when the start port winning designation value corresponds to "2" and the special symbol display result is "miss" in the special symbol game using the second special symbol by the second special symbol display device 4B. When the start port winning designation value is "2", the count value of the second start port winning counter can be obtained in step AKS444 of the miss time variation pattern type table selection process P_TPATH. The count value of the second start port winning memory counter indicates the second reserved memory number. Then, the allocation judgment value comparison process P_HANTEI in step AKS445 reads out the designated data corresponding to the count value of the second start port winning memory counter, and the miss effect allocation table corresponding to the second reserved memory number can be determined in step AKS446. In the example of determining the miss effect allocation table AKD22, only the common miss effect allocation table AKV11 can be determined in correspondence with the second reserved memory counts "0" to "3".

Figure 10-28 (C) shows an example AKD23 of a variation pattern type allocation table for a failure performance allocation table AKV01. The failure performance allocation table AKV01 can be determined in the example AKD21 of a failure performance allocation table when the first reserved memory number is "0" when the start port winning designation value is "1". When the start port winning designation value is "1", in step AKS447 of the failure time variation pattern type table selection process P_TPATH, the random number MR3-2 for failure performance selection can be read from the first failure performance selection buffer with buffer number "0". Then, the designation data corresponding to the random number MR3-2 for failure performance selection is read by the allocation judgment value comparison process P_HANTEI in step AKS448, and the variation pattern type allocation table can be determined in step AKS449. In the example of determining the variation pattern type allocation table AKD23, it is possible to determine one of the variation pattern type allocation tables AKU21 to AKU25 in response to the random number MR3-2 for selecting the miss performance.

Figure 10-29 is a diagram for explaining an example of the configuration of a fluctuation pattern type allocation table. When the winning fluctuation pattern type table selection process P_TPATA shown in Figure 10-27 (A) is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, it can determine one of a plurality of fluctuation pattern type allocation tables, such as one of the fluctuation pattern type allocation tables AKU01 to AKU03 in the fluctuation pattern type allocation table determination example AKD11 shown in Figure 10-27 (B1), in response to the determination result of the jackpot symbol designation value. When the winning time fluctuation pattern type table selection process P_TPATA shown in FIG. 10-27(A) is executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26, it can be determined to be one of a plurality of fluctuation pattern type allocation tables, such as one of the fluctuation pattern type allocation tables AKU11 and AKU12 in the fluctuation pattern type allocation table determination example AKD12 shown in FIG. 10-27(B2), in response to the determination result of the small winning pattern designation value. Step AKS449 of the losing time fluctuation pattern type table selection process P_TPATH shown in FIG. 10-28(A) can be determined to be one of a plurality of fluctuation pattern type allocation tables, such as one of the fluctuation pattern type allocation tables AKU21 to AKU25 in the fluctuation pattern type allocation table determination example AKD23 shown in FIG. 10-28(C). The fluctuation pattern allocation table selection process P_TPATTBL executed in step AKS373 of the fluctuation pattern setting process P_TPATSET shown in FIG. 10-26 can select a fluctuation pattern type by referencing the fluctuation pattern type allocation table using the random number MR3-3 for selecting the fluctuation pattern type read out in step AKS372, and can select a fluctuation pattern allocation table corresponding to the selection result.

Figure 10-29 (A) shows an example of the configuration of the fluctuation pattern type allocation table AKU01. The fluctuation pattern type allocation table AKU01 is included in a plurality of fluctuation pattern type allocation tables that can be determined in response to the jackpot symbol designation value. The fluctuation pattern type allocation table AKU01 in Figure 10-29 (A) has table data configured so that it can be determined to be one of the fluctuation pattern types CPA01 to CPA05 in response to the random number MR3-3 for selecting the fluctuation pattern type.

Figure 10-29 (B1) shows an example of the configuration of the fluctuation pattern type allocation table AKU11. The fluctuation pattern type allocation table AKU11 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the small win symbol designated value. The fluctuation pattern type allocation table AKU11 in Figure 10-29 (B1) is configured so that the table data can be determined to only the common fluctuation pattern type CPB01 in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figure 10-29 (B2) shows an example of the configuration of the fluctuation pattern type allocation table AKU12. The fluctuation pattern type allocation table AKU12 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the small win symbol designated value. The fluctuation pattern type allocation table AKU12 in Figure 10-29 (B2) is configured so that the table data can be determined to only the common fluctuation pattern type CPB02 in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figure 10-29 (C1) shows an example of the configuration of the fluctuation pattern type allocation table AKU21. The fluctuation pattern type allocation table AKU21 is included in a plurality of fluctuation pattern type allocation tables that can be determined in correspondence with the random number MR3-2 for selecting a miss performance. The fluctuation pattern type allocation table AKU21 in Figure 10-29 (C1) has table data configured so that it can be determined to be either the fluctuation pattern type CPC01 or CPC02 in correspondence with the random number MR3-3 for selecting the fluctuation pattern type.

Figure 10-29 (C2) shows an example of the configuration of the fluctuation pattern type allocation table AKU22. The fluctuation pattern type allocation table AKU22 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a miss performance. The fluctuation pattern type allocation table AKU22 in Figure 10-29 (C2) is configured so that the table data can be determined to only the common fluctuation pattern type CPC03 in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figure 10-29 (C3) shows an example of the configuration of the fluctuation pattern type allocation table AKU23. The fluctuation pattern type allocation table AKU23 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a miss performance. The fluctuation pattern type allocation table AKU23 in Figure 10-29 (C3) is configured so that the table data can be determined to only the common fluctuation pattern type CPC04 in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figure 10-29 (C4) shows an example of the configuration of the fluctuation pattern type allocation table AKU24. The fluctuation pattern type allocation table AKU24 is included in a plurality of fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a miss performance. The fluctuation pattern type allocation table AKU24 in Figure 10-29 (C4) has table data configured so that it can be determined to be one of the fluctuation pattern types CPC05 to CPC07 in response to the random number MR3-3 for selecting the fluctuation pattern type.

Figure 10-29 (C5) shows an example of the configuration of the fluctuation pattern type allocation table AKU25. The fluctuation pattern type allocation table AKU25 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a miss performance. The fluctuation pattern type allocation table AKU25 in Figure 10-29 (C5) is configured so that the table data can be determined to only the common fluctuation pattern type CPC08 in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figures 10-30 to 10-32 are diagrams for explaining examples of the configuration of fluctuation pattern allocation tables that can be used in accordance with the fluctuation pattern type. In the fluctuation pattern allocation table selection process P_TPATTBL executed in step AKS373 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, a fluctuation pattern allocation table is selected in accordance with the selection result of the fluctuation pattern type using the random number MR3-3 for selecting the fluctuation pattern type. Thereafter, the second allocation judgment value comparison process P_HANTEI2 in step AKS375 makes it possible to determine the fluctuation pattern by referring to the fluctuation pattern allocation table using the random number MR3-4 for the fluctuation pattern read out in step AKS374.

Figure 10-30 (A1) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA01. When using the fluctuation pattern type allocation table AKU01 that can be determined in response to the jackpot symbol designation value, the fluctuation pattern type CPA01 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A1), the fluctuation pattern allocation table is configured with table data so that it can be determined to any one of the fluctuation patterns PA01 to PA03, PA51, and PA52 in response to the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA01 can be determined to any one of the fluctuation patterns PA01 to PA03, PA51, and PA52.

Figure 10-30 (A2) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA02. When using the fluctuation pattern type allocation table AKU01 that can be determined in accordance with the jackpot symbol designation value, the fluctuation pattern type CPA02 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A2), the fluctuation pattern allocation table is configured with table data so that it can be determined to any one of the fluctuation patterns PA04 to PA11, PA21 to PA23, and PA54 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA02 can be determined to any one of the fluctuation patterns PA04 to PA11, PA21 to PA23, and PA54.

Figure 10-30 (A3) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA03. When using the fluctuation pattern type allocation table AKU01 that can be determined in response to the jackpot symbol designation value, the fluctuation pattern type CPA03 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A3), the fluctuation pattern allocation table is configured so that the table data can be determined to be one of the fluctuation patterns PA31 to PA38, PA24 to PA26, and PA55 in response to the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA03 can be determined to be one of the fluctuation patterns PA31 to PA38, PA24 to PA26, and PA55.

Figure 10-30 (A4) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA04. When using the fluctuation pattern type allocation table AKU01 that can be determined in response to the jackpot symbol designated value, the fluctuation pattern type CPA04 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A4), the fluctuation pattern allocation table is configured with table data so that only the common fluctuation pattern PA41 can be determined in response to the random number MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA04 can only be determined to the fluctuation pattern PA41.

Figure 10-30 (A5) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA05. When using the fluctuation pattern type allocation table AKU01 that can be determined in response to the jackpot symbol designated value, the fluctuation pattern type CPA05 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A5), the fluctuation pattern allocation table is configured with table data so that only the common fluctuation pattern PA42 can be determined in response to the random number MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA05 can only be determined to the fluctuation pattern PA42.

Figure 10-30 (B1) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPB01. When using the fluctuation pattern type allocation table AKU11 that can be determined in response to the small win symbol designation value, the fluctuation pattern type CPB01 can be determined in response to the random number MR3-3 for selecting all fluctuation pattern types. In the configuration example of Figure 10-30 (B1), the fluctuation pattern allocation table is configured with table data so that only the common fluctuation pattern PB01 can be determined in response to the random number MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPB01 can be determined only to the fluctuation pattern PB01.

Figure 10-30 (B2) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPB02. When using the fluctuation pattern type allocation table AKU12 that can be determined in response to the small win symbol designated value, the fluctuation pattern type CPB02 can be determined in response to all of the random numbers MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (B2), the fluctuation pattern allocation table is configured with table data so that it can be determined to any of the fluctuation patterns PB11 to PB14 in response to the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPB02 can be determined to any of the fluctuation patterns PB11 to PB14.

Figure 10-31 (A) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC01. When using the fluctuation pattern type allocation table AKU21 that can be determined in correspondence with the random number MR3-2 for selecting a miss performance, the fluctuation pattern type CPC01 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-31 (A), the fluctuation pattern allocation table is configured with table data so that only the common fluctuation pattern PC01 can be determined in correspondence with the random number MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC01 can be determined only to the fluctuation pattern PC01.

Figure 10-31 (B) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC02. When using the fluctuation pattern type allocation table AKU21 that can be determined in correspondence with the random number MR3-2 for selecting a miss performance, the fluctuation pattern type CPC02 can be determined at a predetermined ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-31 (B), the fluctuation pattern allocation table is configured so that the fluctuation pattern type CPC02 can be determined to any one of the fluctuation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, and PC49 in correspondence with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC02 can be determined to any one of the fluctuation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, and PC49.

Figure 10-31 (C) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC03. When using the fluctuation pattern type allocation table AKU22 that can be determined in correspondence with the random number MR3-2 for selecting a miss performance, the fluctuation pattern type CPC03 can be determined in correspondence with all the random numbers MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-31 (C), the fluctuation pattern allocation table is configured with table data so that it can be determined to be one of the fluctuation patterns PC11 to PC18, PC101 in correspondence with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC03 can be determined to be one of the fluctuation patterns PC11 to PC18, PC101.

Figure 10-31 (D) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC04. When using the fluctuation pattern type allocation table AKU23 that can be determined in correspondence with the random number MR3-2 for selecting a miss performance, the fluctuation pattern type CPC04 can be determined in correspondence with all of the random numbers MR3-3 for selecting a fluctuation pattern type. In the configuration example of Figure 10-31 (D), the fluctuation pattern allocation table is configured with table data so that it can be determined to be one of the fluctuation patterns PC19 to PC27, PC102 in correspondence with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC04 can be determined to be one of the fluctuation patterns PC19 to PC27, PC102.

Figure 10-32 (A) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC05. When using the fluctuation pattern type allocation table AKU24 that can be determined in correspondence with the random number MR3-2 for selecting a losing performance, the fluctuation pattern type CPC05 can be determined at a first ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-32 (A), the fluctuation pattern allocation table is configured with table data so that it can be determined to any one of the fluctuation patterns PC28 to PC43 in correspondence with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC05 can be determined to any one of the fluctuation patterns PC28 to PC43.

Figure 10-32 (B) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC06. When using the fluctuation pattern type allocation table AKU24 that can be determined in correspondence with the random number MR3-2 for selecting a losing performance, the fluctuation pattern type CPC06 can be determined at a second rate different from the first rate corresponding to the random number MR3-3 for selecting a fluctuation pattern type. The second rate is a rate lower than the first rate. In the configuration example of Figure 10-32 (B), the fluctuation pattern allocation table is configured with table data so that it can be determined to be one of the fluctuation patterns PC44 to PC59 in correspondence with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC06 can be determined to be one of the fluctuation patterns PC44 to PC59.

Figure 10-32 (C) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC07. When using the fluctuation pattern type allocation table AKU24 that can be determined in correspondence with the random number MR3-2 for selecting a losing performance, the fluctuation pattern type CPC07 can be determined at a third ratio different from the first ratio and the second ratio corresponding to the random number MR3-3 for selecting a fluctuation pattern type. The third ratio is a ratio lower than the first ratio and the second ratio. In the configuration example of Figure 10-32 (C), the fluctuation pattern allocation table is configured with table data so that it can be determined to any one of the fluctuation patterns PC60 to PC75 in correspondence with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC07 can be determined to any one of the fluctuation patterns PC60 to PC75.

Figure 10-32 (D) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC08. When using the fluctuation pattern type allocation table AKU25 that can be determined in correspondence with the random number MR3-2 for selecting a miss performance, the fluctuation pattern type CPC08 can be determined in correspondence with the random number MR3-3 for selecting all fluctuation pattern types. In the configuration example of Figure 10-32 (D), the fluctuation pattern allocation table is configured with table data so that only the common fluctuation pattern PC02 can be determined in correspondence with the random number MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC08 can be determined in correspondence with only the fluctuation pattern PC02.

Figure 10-33 (A) is a flowchart showing an example of normal symbol process processing P_FPROC. The normal symbol process processing P_FPROC is included in the processing that can be called from the timer interrupt processing P_PCT for game control shown in Figure 5, and can be executed in step AKS59 every time a timer interrupt occurs. When the CPU 103 executes the normal symbol process processing P_FPROC, it sets the gate switch passing corresponding flag (step AKS501). The gate switch passing corresponding flag setting is reflected in the flag register of the CPU 103 by executing a logical operation instruction or the like. At this time, the zero flag in the flag register being in the on state indicates that the gate switch passing corresponding flag is in the off state. In contrast, the zero flag being in the off state indicates that the gate switch passing corresponding flag is in the on state. Thereafter, it is determined whether the gate switch passing corresponding flag is on (step AKS502). If the gate switch passing flag is on (step AKS502; Yes), the gate switch passing process P_FZU_ON is executed (step AKS503).

When the gate switch passing flag is off in response to step AKS502 (step AKS502; No), or after the gate switch passing process P_FZU_ON in step AKS503, a transfer command that sets a pointer sets the normal symbol process processing jump table (step AKS504). The normal symbol process processing jump table is an address management table that selects and enables execution of a process that corresponds to the read value of the normal symbol process code. The normal symbol process code can be updated to any of 00 [H] to 04 [H] in response to the progress of game control in the pachinko gaming machine 1, and is also called the normal symbol process code.

Following step AKS504, a transfer command to read out stored data is used to load the normal symbol process code (step AKS505). Next, 2-byte data selection processing P_ABXEXEC is executed (step AKS506) to obtain the address of the processing selected in accordance with the normal symbol process code. The address obtained at this time is set in the pointer. After this, a subroutine call command is used to execute the processing pointed to by the pointer (step AKS507), making it possible to execute the processing selected in accordance with the normal symbol process code. When the processing selected in this manner ends and a return command is issued to return to the normal symbol process processing P_FPROC, this normal symbol process processing P_FPROC also ends, and a return command is issued to return to the timer interrupt processing P_PCT for game control.

Figure 10-33 (B) shows an example of the configuration of the normal symbol process jump table AKT51 used in the normal symbol process P_FPROC. The normal symbol process jump table is configured to include table data that can set the address of the process selected corresponding to the normal symbol process code in an internal register of the CPU 103 used as a pointer. The normal symbol process jump table of the configuration example AKT51 includes table data that can set the address value corresponding to the normal symbol normal process P_FNORM when the normal symbol process code is 00 [H], the normal symbol change process P_FSCRL when the normal symbol process code is 01 [H], the normal symbol stop process P_FSTOP when the normal symbol process code is 02 [H], the normal electric role pre-operation process P_FINT when the normal symbol process code is 03 [H], and the normal electric role operation process P_FOPEN when the normal symbol process code is 04 [H] in the pointer.

The normal pattern normal processing P_FNORM makes it possible to determine whether or not to start a normal pattern game based on the presence or absence of stored normal pattern reserved information, to determine the confirmed normal pattern to be stopped and displayed in the variable display of the normal pattern, and to determine the normal pattern change pattern, which is the change pattern of the normal pattern. The normal pattern change processing P_FSCRL measures the elapsed time since the normal pattern started to change in the normal pattern display device 20, and makes it possible to determine whether the normal pattern change time corresponding to the normal pattern change pattern has elapsed. The normal pattern stop processing P_FSTOP measures the elapsed time since the normal pattern stopped changing in the normal pattern display device 20, and makes it possible to determine whether the normal pattern stop time has elapsed. When the normal pattern stop time has elapsed, it makes it possible to update the normal pattern process code and various settings in accordance with the normal pattern display result. In this embodiment, it is sufficient that the normal pattern process code can be updated to 03 [H] in accordance with all normal pattern display results. The normal electric role pre-operation processing P_FINT and the normal electric role operation processing P_FOPEN are processes that enable the second starting winning port formed in the variable winning ball device 6B to be changed from a closed state to an open state by controlling the normal electric role solenoid 81.

Figure 10-34 is a diagram for explaining an example of the use of data configuration related to the control of the normal symbol game, which is a variable display of normal symbols. For example, the normal symbol process processing P_FPROC shown in Figure 10-33 (A) uses the normal symbol process code loaded in step AKS505 to execute the 2-byte data selection processing P_ABXEXEC in step AKS506, thereby making it possible to execute the processing selected in response to the normal symbol process code in step AKS507. The normal symbol process code is provided in the normal symbol control data area, and the stored value can be updated in response to the control state of the normal symbol game and the second start winning port. The gate switch passing processing P_FZU_ON in step AKS503 can read the random number MR2-1 for the normal symbol, and stores and saves the numerical data indicating the value of the read random number MR2-1 in the normal symbol buffer. The normal symbol buffer is provided in the normal symbol buffer area, and can store numerical data indicating the value of the random number MR2-1 read out until the normal symbol reserved memory number reaches the upper limit. In this way, the normal symbol process processing P_FPROC and the processing executable in the normal symbol process processing P_FPROC use the stored data in the normal symbol control data area and the buffer area for normal symbols to enable control of the normal symbol game, which is a variable display of normal symbols.

Figure 10-34 (A) shows a configuration example AKB51 of the normal symbol control data area. The normal symbol control data area of the configuration example AKB51 can store various data related to control by the normal symbol process processing P_FPROC, such as the normal symbol game, which is a variable display of normal symbols, and the closed or open state of the second start winning port, which can be controlled based on the display result. This normal symbol control data area includes a normal symbol process code at address F03E [H], a gate passing memory counter at address F03F [H], a normal symbol buffer at address F040 [H], a normal electric role release pattern timer at address F041 [H], a normal electric role release pointer at address F043 [H], a normal electric role win count counter at address F045 [H], and a normal symbol process timer at address F04A [H].

The normal symbol process code can specify the processing selected in the normal symbol process processing P_FPROC. The gate passing memory counter can store a count value corresponding to the number of game balls detected by the gate switch 21. The normal symbol buffer can store data corresponding to the normal symbol designated value. The normal symbol designated value is a designated value corresponding to the confirmed normal symbol that is the display result in the variable display of the normal symbol by the normal symbol display device 20, and includes a normal symbol winning symbol designated value. The normal symbol winning symbol designated value is a designated value corresponding to the confirmed normal symbol displayed by the normal symbol display device 20 when the display result in the variable display of the normal symbol is "normal symbol winning". The normal electric role opening pattern timer can store a time measurement value corresponding to the remaining time for controlling the second start winning port to the open state. The normal electric role opening pointer can specify a storage address of the normal electric role opening pattern table in which the time for controlling the second start winning port to the open state is set. The normal electric device winning number counter can store a count value corresponding to the number of game balls detected by the second start switch 22B. The normal symbol process timer can store a time value corresponding to the control time by the normal symbol process processing P_FPROC.

Figure 10-34 (B) shows a configuration example AKB52 of a buffer area for normal symbols. The buffer area for normal symbols of configuration example AKB52 can store numerical data indicating the value of the random number MR2-1 for normal symbols that is read out when the gaming ball passes through the passing gate 41. This buffer area for normal symbols includes normal symbol buffer numbers "1" to "4" at addresses F046 [H] to F049 [H]. The buffer numbers "1" to "4" for normal symbols are buffers for normal symbols that are assigned buffer numbers "1" to "4", and can store the values of the random number MR2-1 in the order in which the gaming ball passed through the passing gate 41. As a result, the information stored in the normal symbol buffer indicates the number of game balls that have passed through the pass gate 41, and also indicates the value of the random number MR2-1 that is read out in response to each pass.

Figure 10-35 is a flow chart showing an example of the gate switch passing process P_FZU_ON. The gate switch passing process P_FZU_ON is included in the processes that can be called from the normal symbol process process P_FPROC shown in Figure 10-33 (A), and can be executed in step AKS503 if the gate switch passing corresponding flag is on in step AKS502. When the CPU 103 executes the gate switch passing process P_FZU_ON, it sets the gate passing memory counter address by a transfer command for setting a pointer (step AKS601). The gate passing memory counter address is the address of the gate passing memory counter provided in the game work area of the RAM 102. Next, it loads the gate passing memory counter by a transfer command for reading the stored data at the address pointed to by the pointer (step AKS602).

After step AKS602, it is determined whether the count value of the gate passing memory counter is equal to or greater than the counter maximum value (step AKS603). For example, if the value loaded in step AKS602 is compared with a counter maximum value such as "4" by a comparison and return command that can compare the value, the gate switch passing process P_FZU_ON ends and returns to the normal symbol process process P_FPROC if the value is equal to or greater than the counter maximum value (step AKS603; Yes). On the other hand, if the value is less than the counter maximum value (step AKS603; No), the count value of the gate passing memory counter is updated to add 1 (step AKS604). In this case, an arithmetic and logic operation command that increments the stored data at the address pointed to by the pointer makes it possible to update the count value of the gate passing memory counter by adding 1.

After step AKS604, the buffer address for the normal symbol is set by a transfer command for setting the pointer (step AKS605). In this case, the address of the buffer for the normal symbol with buffer number "0" provided in the game work area of RAM 102 is set to the pointer. Then, the value loaded by step AKS602 is added to the stored value of the pointer. This allows the address of the buffer for the normal symbol that stores the random number MR2-1 for the normal symbol in the buffer area for the normal symbol to be set to the pointer. Following this, the random number counter for the normal symbol is stored (step AKS606), and the gate switch passing process P_FZU_ON is completed. In step AKS606, the value of the random number MR2-1 obtained from the random number counter for normal symbols in the game work area of RAM102 can be stored in the buffer for normal symbols by a transfer command to write the value read by specifying the lower address of the random number counter for normal symbols in the game work area of RAM102 to the memory area of the address pointed to by the pointer.

Figure 10-36 is a flowchart showing an example of normal symbol normal processing P_FNORM. The normal symbol normal processing P_FNORM is included in the processing that can be called from the normal symbol process processing P_FPROC shown in Figure 10-33 (A), and can be executed in step AKS507 when the normal symbol process code loaded in step AKS505 is 00 [H]. When the normal symbol normal processing P_FNORM is executed, the CPU 103 loads the gate passing memory counter (step AKS621). In this case, the count value of the gate passing memory counter can be obtained by a transfer command for setting the value read by specifying the lower address of the gate passing memory counter in the game work area of the RAM 102 in the internal register of the CPU 103. Then, by a calculation return command that returns the processing when the second zero flag in the flag register of the CPU 103 is in the on state, it is determined whether the count value of the gate passing memory counter is "0" or not (step AKS622). At this time, if the second zero flag is on, the gate passage memory counter count value is "0" (step AKS622; Yes), and the normal pattern normal processing P_FNORM ends and returns to the normal pattern process processing P_FPROC.

If the count value of the gate passing memory counter is not "0" in response to step AKS622 (step AKS622; No), a transfer command for setting a pointer is used to set the table address for setting the symbol for normal symbols (step AKS623). The table address for setting the symbol for normal symbols is the address of the table for setting the symbol for normal symbols stored in the game data area of ROM 101. Then, the buffer for normal symbols with buffer number "1" is loaded (step AKS624). In step AKS624, the random number MR2-1 for normal symbols stored in the buffer for normal symbols with buffer number "1" can be read out by a transfer command for setting the value read by specifying the lower address of the buffer for normal symbols with buffer number "1" in the game work area of RAM 102 in the internal register of CPU 103.

When the random number MR2-1 for the normal symbol winning pattern is read out by step AKS624, the second allocation judgment value comparison process P_HANTEI2 is executed (step AKS625). The value of the random number MR2-1 read out by step AKS624 is set as a comparison value in the second allocation judgment value comparison process P_HANTEI2 of step AKS625, and the normal symbol winning pattern designated value indicated by the allocation result data can be determined as the display result by the normal symbol display device 20 based on the stored data of the normal symbol winning pattern setting table whose address was set by step AKS623. When the normal symbol winning pattern designated value is determined by the second allocation judgment value comparison process P_HANTEI2 of step AKS625, the normal symbol winning pattern designated value is stored in the normal symbol buffer (step AKS626). The normal symbol buffer is provided in the normal symbol control data area shown in FIG. 10-34(A) and is assigned address F040[H]. In step AKS626, the normal symbol per symbol designated value is stored by a transfer command to write to the memory area of the designated address in the game work area of RAM 102.

After step AKS626, the count value of the gate passing memory counter is decremented by 1 (step AKS627). Then, the buffer for normal symbols is shifted (step AKS628). In this case, in the buffer area for normal symbols provided in the game work area of RAM 102, the address of the buffer for normal symbols with buffer number "2" is set to the pointer that specifies the transfer source. Also, the address of the buffer for normal symbols with buffer number "1" is set to the buffer pointer that specifies the transfer destination. Furthermore, the number of transfers corresponding to the data size of the buffer area for normal symbols is set. After that, the contents of the buffer for normal symbols are sequentially transferred and shifted by a block transfer command. At this time, the buffer for normal symbols with buffer number "4" is cleared to initialize the contents.

After step AKS628, the first normal symbol variation pattern allocation table address is set by a transfer command for setting a pointer (step AKS629). The first normal symbol variation pattern allocation table address is the address of the first normal symbol variation pattern allocation table stored in the game data area of ROM 101. In addition, the time-saving check process confirms that the time-saving function flag is not the time-saving activation designated value (step AKS630). At this time, if the time-saving function flag is the time-saving activation designated value (step AKS630; No), the second normal symbol variation pattern allocation table address is set by a transfer command for setting a pointer (step AKS631). The second normal symbol variation pattern allocation table address is the address of the second normal symbol variation pattern allocation table stored in the game data area of ROM 101.

If the time-saving function flag is not the time-saving operation designated value in response to step AKS630 (step AKS630; Yes), or after step AKS631, the RS3 soft latch random number register is loaded (step AKS632). In this case, the address of the RS3 soft latch random number register in the function control register area is specified and the stored value is read out, and then set to be usable as the random number MR3-1 for the normal symbol variation pattern by a transfer command for setting the value in the internal register of CPU 103. Then, the second allocation judgment value comparison process P_HANTEI2 is executed (step AKS633). In the second allocation judgment value comparison process P_HANTEI2 in step AKS633, the value of the random number MR3-1 read in step AKS632 is set as a comparison value, and the normal pattern variation pattern indicated by the allocation result data can be determined based on the stored data of the first normal pattern variation pattern allocation table whose address was set in step AKS629 or the second normal pattern variation pattern allocation table whose address was set in step AKS631.

When the normal symbol variation pattern is determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS633, the normal symbol variation time corresponding to the normal symbol variation pattern is set (step AKS634). In step AKS634, the normal symbol variation time table and the normal symbol variation pattern designation data are used to execute a time data expansion process, thereby making it possible to set the normal symbol variation time corresponding to the determination result of the normal symbol variation pattern. Next, a transfer command for setting a pointer is used to set the normal symbol variation work table address (step AKS635). The normal symbol variation work table address is the address of the normal symbol variation work table stored in the game data area of ROM101. Next, the data set process P_DATASET is executed (step AKS636), and the normal symbol normal process P_FNORM is terminated. The data set process P_DATASET in step AKS636 uses the normal pattern change time work table whose address was set in step AKS635 to set the normal pattern process code to 01 [H], which is the normal pattern change processing designated value, and sets the storage value of the normal pattern change display buffer to 01 [H], which is the normal pattern change display data. Also, the normal pattern display update timer is cleared to enable initialization.

Figure 10-37 is a diagram for explaining an example of the use of data configuration related to normal pattern normal processing P_FNORM. In normal pattern normal processing P_FNORM, the second allocation judgment value comparison process P_HANTEI2 of step AKS625 is executed using the normal pattern per pattern setting table whose address is set in step AKS623, thereby making it possible to determine the pattern designation value per normal pattern. In addition, the second allocation judgment value comparison process P_HANTEI2 of step AKS633 is executed using the first normal pattern variation pattern allocation table whose address is set in step AKS629 or the second normal pattern variation pattern allocation table whose address is set in step AKS631, thereby making it possible to determine the normal pattern variation pattern. In step AKS634, the normal pattern variation time table is used to make it possible to set the normal pattern variation time corresponding to the result of determining the normal pattern variation pattern. In addition, in step AKS507 of the normal symbol process processing P_FPROC shown in FIG. 10-33(A), when the normal symbol process code corresponds to 03[H] and the normal electric role pre-operation processing P_FINT is executed, the opening time of the normal electric role provided in correspondence with the second start winning port can be determined using a work setting table for normal electric role operation, etc.

In this way, normal pattern normal processing P_FNORM makes it possible to determine the pattern designation value for a normal pattern using a table for setting patterns for normal patterns. Also, normal pattern normal processing P_FNORM makes it possible to determine the normal pattern change pattern using the first normal pattern change pattern allocation table or the second normal pattern change pattern allocation table. Furthermore, normal pattern normal processing P_FNORM makes it possible to determine the normal pattern change time using the normal pattern change time table. Normal electric role pre-operation processing P_FINT, which is executed in response to the execution result of the normal game, can determine the opening time of the normal electric role.

Figure 10-37 (A) shows an example of a normal symbol per symbol setting table AKT61. In the normal symbol per symbol setting table of the example AKT61, the value 00 [H] corresponding to the first normal symbol per symbol designated value is stored in the first address 1B54 [H], and the value 03 [H] indicating the number of processes is stored in the next address 1B55 [H]. The stored data from address 1B56 [H] onwards indicates the allocation judgment value corresponding to the first to third normal symbol per symbol designated values. When the normal symbol per symbol setting table of the example AKT61 is used, the second allocation judgment value comparison process P_HANTEI2 of step AKS625 can determine one of the first to third normal symbol per symbol designated values in response to the random number MR2-1 for the normal symbol per symbol. In the configuration example AKT61, the design value for the first normal symbol is 00 [H], the design value for the second normal symbol is 01 [H], and the design value for the third normal symbol is 02 [H]. For example, when the random number MR2-1 for the normal symbol is 00 [H], which corresponds to the minimum random number value "0", the design value for the first normal symbol is determined.

Figure 10-37 (B1) shows a configuration example AKT62 of the first normal pattern variation pattern allocation table. In the first normal pattern variation pattern allocation table of the configuration example AKT62, the value 00 [H] corresponding to the normal pattern variation pattern FPZ1 designated value is stored at the first address 1B59 [H], and the value 04 [H] indicating the number of processes is stored at the next address 1B5A [H]. The stored data from address 1B5B [H] onwards indicates the allocation judgment value corresponding to the normal pattern variation patterns FPZ1 to FPZ4. When the first normal pattern variation pattern allocation table of the configuration example AKT62 is used, the second allocation judgment value comparison process P_HANTEI2 of step AKS633 can determine one of the normal pattern variation patterns FPZ1 to FPZ4 in response to the random number MR3-1 for the normal pattern variation pattern.

Figure 10-37 (B2) shows a configuration example AKT63 of the second normal symbol fluctuation pattern allocation table. In the second normal symbol fluctuation pattern allocation table of the configuration example AKT63, the value 04 [H] corresponding to the normal symbol fluctuation pattern FPZ5 designated value is stored at the first address 1B5F [H], and the value 04 [H] indicating the number of processes is stored at the next address 1B60 [H]. The stored data from address 1B61 [H] onwards indicates the allocation judgment value corresponding to the normal symbol fluctuation patterns FPZ5 to FPZ8. When the second normal symbol fluctuation pattern allocation table of the configuration example AKT63 is used, the second allocation judgment value comparison process P_HANTEI2 of step AKS633 can determine one of the normal symbol fluctuation patterns FPZ5 to FPZ8 in response to the random number MR3-1 for the normal symbol fluctuation pattern.

Figure 10-37 (C) shows an example of normal pattern fluctuation time determination AKD61. In the determination example AKD61, the normal pattern fluctuation time is determined to be 1000 [ms] corresponding to the normal pattern fluctuation patterns FZP1 to FZP4, and the normal pattern fluctuation time is determined to be 100 [ms] corresponding to the normal pattern fluctuation patterns FZP5 to FZP8. In step AKS634, the normal pattern fluctuation time corresponding to the normal pattern fluctuation pattern determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS633 is set. The normal pattern fluctuation patterns FZP1 to FZP4 can be determined using the first normal pattern fluctuation pattern allocation table of the configuration example AKT61 when the time-saving function flag is off. The normal pattern fluctuation patterns FZP5 to FZP8 can be determined using the second normal pattern fluctuation pattern allocation table of the configuration example AKT62 when the time-saving function flag is on. This makes it possible to set the normal pattern change time, which is the variable display time of the normal pattern, to be shorter when time-saving control is being performed than when time-saving control is not being performed.

Figure 10-37 (D) shows an example of normal electric role release time determination AKD62. In the normal electric role operation pre-processing P_FINT, the normal electric role release time can be determined in response to the time-saving operation designated value and the normal symbol per symbol designated value. The normal electric role release time is determined to be 16 ms in response to all normal symbol per symbol designated values 00 [H] to 02 [H] when the time-saving operation designated value is the value 00 [H] corresponding to "x" indicating that the time-saving state is not set. In contrast, the normal electric role operation time is determined to be 5000 ms in response to all normal symbol per symbol designated values 00 [H] to 02 [H] when the time-saving operation designated value is the value 01 [H] corresponding to "○" indicating that the time-saving state is set.

In this way, the normal electric device opening time can be determined to a different time in response to the time-saving operation designated value, regardless of the value of the normal symbol per symbol designated value. The normal symbol per symbol designated value can be determined in response to the random number MR2-1 for the normal symbol per symbol read from the normal symbol per symbol buffer. If the time-saving operation designated value is the same value, the normal electric device operation time is determined to be common when the random number MR2-1 for the normal symbol per symbol is the minimum random number value "0" and when it is other than the minimum random number value. Therefore, in response to the special symbol game, which is a variable display of normal symbols on the normal symbol display device 20, when the random number MR2-1 for the normal symbol per symbol is the minimum random number value "0", the display result with a higher advantage is not determined compared to when it is other than the minimum random number value. This makes it possible to update the random number value appropriately so as to prevent fraudulent acts due to a malfunction of the second random number value when the random number MR2-1 for the normal symbol per symbol is set to the second random number value.

In the game control microcomputer 100 shown in FIG. 10-1, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can update the numerical data indicating the values of the random numbers included in the game random numbers, including the random number MR1-1 for determining the special symbol, the random number MR3-2 for selecting a losing performance, the random number MR3-3 for selecting a variation pattern type, the random number MR3-4 for the variation pattern, and the random number MR3-1 for the normal symbol variation pattern. In addition, the CPU 103 can update the numerical data indicating the values of the random numbers included in the game random numbers, including the random number MR1-2 for the winning symbol, the random number MR1-3 serving as the initial value for the winning symbol, the random number MR2-1 for the winning symbol for the normal symbol, and the random number MR2-2 serving as the initial value for the winning symbol for the normal symbol, by executing the random number update process P_RANDOM shown in FIG. 10-12.

In step AKS248 of the normal special symbol processing shown in Fig. 10-18, when the special symbol determination processing P_TDECISION shown in Fig. 10-20 is executed, it becomes possible to determine whether the special symbol display result is a "big hit" or a "small hit" using the special symbol determination random number MR1-1 by the special symbol big hit determination processing in step AKS304 or the special symbol small hit determination processing in step AKS305. Then, in step AKS308 of the special symbol determination processing P_TDECISION, when the special symbol information setting processing P_TZU_SET shown in Fig. 10-22 is executed, it becomes possible to determine the big hit symbol designation value or the small hit symbol designation value corresponding to the confirmed special symbol that is the display result of the special symbol using the winning symbol random number MR1-2 by the big hit information data selection processing P_TFVR_ZU in step AKS326 or step AKS333. In addition, when the second allocation judgment value comparison process P_HANTEIS is executed in step AKS625 of the normal pattern normal process shown in Figure 10-36, it becomes possible to determine the normal pattern winning symbol designated value corresponding to the confirmed normal pattern that is the display result of the normal pattern using the random number MR2-1 for the winning symbol for the normal pattern. The jackpot symbol designated value determined using the random number MR1-2 for the winning symbol makes it possible to set the maximum number of times the large prize opening is opened in step AKS330 of the special symbol information setting process P_TZU_SET, as in the example AKD01 of determining the maximum number of times the large prize opening is opened shown in Figure 10-24 (C). The normal winning symbol designation value determined using the normal winning symbol random number MR2-1 enables the normal electric device opening time to be set as in the normal electric device opening time determination example AKD62 shown in FIG. 10-37(D) when the normal symbol process code corresponds to 03[H] and the normal electric device pre-operation process P_FINT is executed in step AKS507 of the normal symbol process processing P_FPROC shown in FIG. 10-33(A). Therefore, the winning symbol random number MR1-2 is used to determine the display result by the first special symbol display device 4A and the second special symbol display device 4B, making it possible to set the type of jackpot game state that is advantageous to the player. The normal winning symbol random number MR2-1 is used to determine the display result by the normal symbol display device 20, making it possible to set a change mode that changes the second start winning hole, which is the start area, to an induction state in which the game ball can easily pass through.

In this way, processing related to game control can be executed using random numbers that become various game random numbers, and the random number MR1-2 for the winning symbol, which becomes the first random number value, and the random number MR2-1 for the winning normal symbol, which becomes the second random number value, can be updated in their respective update ranges by a common update process such as the initial value change random number update process P_RANCP that can be called and executed by the random number update process P_RANDOM shown in FIG. 10-12. Here, the update range of the random number MR2-1 for the winning normal symbol is "0" to "198", and the total number of random numbers included in the update range is "199", so the total number of random numbers included in the update range is a prime number. Therefore, the total number of random numbers included in the update range of at least one of the first random number value and the second random number value that can be updated by the common update process is a prime number. In this way, the common update process prevents an increase in program capacity, and the total number of random numbers included in the update range is a prime number, suppressing the occurrence of random number synchronization and enabling appropriate random number updating.

The random number MR1-2 for the winning symbol, which is the first random number value, has an update range of "0" to "199", and the total number of random numbers included in the update range is "200", so the total number of random numbers included in the update range is not a prime number. The random number MR1-2 for the winning symbol is used to determine the jackpot symbol designation value for the fixed special symbol, and may determine whether or not the probability of a special state will be reached after the end of the jackpot game state, depending on the jackpot symbol designation value. In this case, the determination ratio of the jackpot symbol designation value corresponds to the probability of special state entry rate, which is the rate at which the probability of special state is controlled. The probability of special state entry rate is included in the important specifications of the pachinko game machine 1, and it is desirable to make it a value that is clearly recognizable. However, if the total number of random numbers included in the update range of the random number MR1-2 for the winning symbol is a prime number, the denominator of the probability of special state entry rate will be a prime number, making it difficult to express it as a percentage, and there is a risk that the probability of special state entry rate will be difficult to recognize. Therefore, of the random numbers MR1-2 for winning symbols and MR2-1 for normal and winning symbols that can be updated by a common update process, the total number of random numbers included in the update range of the random number MR2-1 for normal and winning symbols may be a prime number, while the total number of random numbers included in the update range of the random number MR1-2 for winning symbols may not be a prime number. This makes it possible to appropriately update the random numbers so that the specifications of the pachinko game machine 1 can be clearly recognized while suppressing the occurrence of synchronization of the random numbers.

The total number of random numbers included in the update range for the winning symbol random number MR1-2, which is the first random number value, may also be a prime number. This makes it possible to more reliably suppress the synchronous occurrence of random numbers that can be updated by a common update process, and to update the random numbers appropriately.

In the random number update process P_RANDOM shown in FIG. 10-12, steps AKS61 to AKS64 can update the random number MR1-2 that becomes the first random number value, and steps AKS65 to AKS68 can update the random number MR2-1 that becomes the second random number value. The random number update process P_RANDOM can update the random number MR1-2 that becomes the first random number value and the random number MR2-1 that becomes the second random number value using the HL register, B register, and DE register of CPU 103, which are common internal storage means. In this way, the first random number value and the second random number value can be stably updated using the common internal storage means, making it possible to update the random number values appropriately.

When the random number MR1-2 for the winning symbol is set as the first random number value and the random number MR2-1 for the normal winning symbol is set as the second random number value, the CPU 103 that executes the random number update process P_RANDOM shown in Fig. 10-12 becomes the first update means that can update the first and second random number values in their respective update ranges by the random number update process. Also, when the 16-bit random number circuit 104A and the 8-bit random number circuit 104B set the third and fourth random number values from among the random number MR1-1 for determining the special symbol, the random number MR3-2 for selecting a losing performance, the random number MR3-3 for selecting a variation pattern type, and the random number MR3-4 for the variation pattern, they become the second update means that can update the third and fourth random number values in their respective update ranges by the system clock input that serves as the random number clock signal. For example, the random number MR2-1 for the winning symbol has an update range of "0" to "198", and the total number of random numbers included in the update range is "199", so the total number of random numbers included in the update range of the second random number is a prime number. On the other hand, for example, the random number MR3-2 for selecting a losing performance has an update range of "0" to "65518", and the total number of random numbers included in the update range is "65519", the random number MR3-3 for selecting a variation pattern type has an update range of "0" to "240", and the total number of random numbers included in the update range is "241", and the random number MR3-4 for the variation pattern has an update range of "0" to "250", and the total number of random numbers included in the update range is "251", so the total number of random numbers included in the update range of at least one of the third random number and the fourth random number is a prime number. In this way, the update methods of the first update means and the second update means are different, and even if the update methods are the same, at least one random number has a total number of random numbers included in the update range that is a prime number, thereby suppressing the occurrence of synchronization and enabling appropriate updating of the random numbers.

The 16-bit random number circuit 104A and the 8-bit random number circuit 104B become the first update means capable of updating the first and second random number values by the system clock input serving as the random number clock signal when the first and second random number values are set from among the random number MR1-1 for determining the special symbol, the random number MR3-2 for selecting the losing performance, the random number MR3-3 for selecting the variation pattern type, and the random number MR3-4 for the variation pattern. The CPU 103 which executes the random number update process P_RANDOM shown in FIG. 10-12 becomes the second update means capable of updating the third random number value by the random number update process when the third random number value is set from among the random number MR1-2 for the winning symbol and the random number MR2-1 for the normal and winning symbols. When the CPU 103 executes the main process P_MAIN for game control shown in FIG. 4 based on the start of power supply in the pachinko game machine 1, it sets the stored value of the function setting register area by the function setting register store command in step AKS13 when it executes the power supply start corresponding process P_POWER_ON shown in FIG. 10-7 in step S1. At this time, by setting the stored value of the maximum value setting register provided corresponding to the 16-bit random number circuit 104A or the 8-bit random number circuit 104B, it is possible to execute a maximum value setting process for setting the maximum random number value of the random number value updated by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B. Then, the 16-bit random number circuit 104A or the 8-bit random number circuit 104B, which is the first updating means, starts updating the first random number in the maximum value setting process by setting the maximum random number value of the first random number value, and then starts updating the second random number by setting the maximum random number value of the second random number value. After executing the power supply start response process P_POWER_ON in step S1, the CPU 103 executing the game control main process P_MAIN shown in FIG. 4 becomes able to execute the game control timer interrupt process P_PCT shown in FIG. 5 in response to the occurrence of a timer interrupt while executing the loop process of steps S8 to S11, and starts updating the third random number value by executing the random number update process P_RANDOM in step S56. In this way, the CPU 103 executing the random number update process P_RANDOM, which serves as the second update means, enables the update of the third random number value after executing the maximum value setting process in the power supply start response process P_POWER_ON, so that by starting the update of a random number value that is highly related to the game value, such as the random number MR1-1 for determining a special symbol, first, the uncertainty is increased, and appropriate random number value updating becomes possible.

In the bit data RAP of the RWM access protection register shown in FIG. 10-9(B), the bit data RAM0 of bit number "0" is set to the initial value 0 [B] in response to the start of power supply in the pachinko gaming machine 1. As a result, the RAM 102 serving as the RWM is prohibited from being accessed in response to the storage value of the RWM access protection register, which is a specific storage area, being set to the first storage value. The CPU 103 that has executed the power supply start response process P_POWER_ON shown in FIG. 10-7 sets the storage value of the function setting register area by the function setting register store command in step AKS13, and then stores the access permission output value in the RWM access protection register in step AKS14. In this way, after setting the storage value in the function setting register area, which is a storage area related to functions, the second storage value that permits access to the RAM 102 as a storage means can be set in the RWM access protection register, which is a specific storage area. Then, as the next process after setting the second stored value, the RWM check process P_RWM_CHK in step S2 in the main process P_MAIN for game control shown in FIG. 4 can be executed to execute a confirmation process to check whether or not the control state can be restored based on the contents stored in the storage means RAM 102. In this way, the contents stored in the storage means are not changed unnecessarily, and the confirmation process can be executed reliably, while the random number value can be updated appropriately.

The CPU 103 executing the power-off process P_POWER_OFF shown in FIG. 10-10 can execute a stop-time storage process in which the checksum data, which is recovery information for restoring the control state in response to a power supply stop, is stored in a storage area such as the checksum buffer of the RAM 102, which is a storage means, by storing the checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 in the checksum buffer in step AKS40. After such a stop-time storage process is executed, the clear data set in the output value data in step AKS41 can be stored in the RWM access protection register in step AKS42, thereby executing a stop-time storage process in which the first storage value is set in a specific storage area. After the stop-time storage process is executed, the loop process of steps AKS48 and AKS49 transitions to a standby state in which game control is not executed. In response to the power supply being restored during this standby state, if the power confirmation signal input bit is not "0" in step AKS49, the power recovery vector table address is set in the stack pointer in step AKS50, and then the power-off processing P_POWER_OFF is terminated by an interrupt return command, making it possible to execute the main processing P_MAIN for game control shown in FIG. 4 from the beginning as startup processing based on the startup of the pachinko gaming machine 1. This prevents unstable operation when the power supply is restored and enables appropriate updating of random numbers.

In the address map of the game control microcomputer 100 shown in Figure 10-2, the function setting register area of the built-in register assigned addresses FE00[H] to FEBF[H] is the first area for function setting using various circuits included in the game control microcomputer 100, and the function control register area of the built-in register assigned addresses FF00[H] to FFFF[H] is the second area for function control using various circuits included in the game control microcomputer 100. Of these, the RWM access protection register at address FF00[H] is a specific storage area in which a storage value indicating whether or not access to the RWM, RAM 102, can be permitted can be set. When the CPU 103 executes the main process P_MAIN for game control shown in FIG. 4 based on the start of power supply in the pachinko game machine 1, it can execute a control storage process to set a stored value in the function control register area, which is the second area, in steps AKS5 to AKS7 when it executes the power supply start corresponding process P_POWER_ON shown in FIG. 10-7 in step S1. After such a control storage process is executed, it can execute a setting storage process to set a stored value in the function setting register area, which is the first area, in steps AKS11 to AKS13. After such a setting storage process is executed, it is possible to set a stored value that allows access to the RAM 102, which is the storage means, in the RWM access protection register, which is the specific storage area, in step AKS14. In this way, it is possible to prevent the contents of the storage means from being changed in an unwanted way and to update the random number value appropriately.

(Means for solving the problems and effects of characteristic part 01AK)
(1-1) A gaming machine that can be controlled to an advantageous state that is advantageous to a player,
An update means capable of updating the random value;
A first display means capable of variably displaying special identification information;
and a second display means capable of variably displaying the normal identification information,
A type of advantageous state is determined in response to the display result by the first display means;
A change mode for changing the starting area into an guiding state in which the game medium can easily pass through is determined in response to the display result by the second display means;
The update method is
The first random number value used to determine the display result by the first display means and the second random number value used to determine the display result by the second display means can be updated within their respective update ranges by a common update process;
The first random number value and the second random number value can be updated using a common internal storage means;
The first random number is a number that is determined by whether the total number of random numbers included in the update range is not a prime number.
The second random value is a prime number, the total number of which is included in the update range.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The update means may be, for example, a CPU 103 that executes a random number update process P_RANDOM. The special identification information may be, for example, a special pattern. The first display means may be, for example, a first special pattern display device 4A and a second special pattern display device 4B. The normal identification information may be, for example, a normal pattern. The second display means may be, for example, a normal pattern display device 20. The display result by the first display means may be, for example, a determined special pattern that is a display result of a special pattern. The display result by the second display means may be, for example, a determined normal pattern that is a display result of a normal pattern. The type of advantageous state may be, for example, a maximum value of the number of times the large prize opening is opened. The change mode may be, for example, a normal electric role opening time. The first random number value may be, for example, a random number MR1-2. The second random number value may be, for example, a random number MR2-1. The update process may be, for example, an initial value change random number update process P_RANCP. The internal storage means may be, for example, the HL register, B register, or DE register of the CPU 103. The total number of the first random numbers may be, for example, the random number MR1-2 having a magnitude of "65536". The total number of the second random numbers may be, for example, the random number MR2-1 having a magnitude of "199".
With this configuration, the common update process prevents an increase in program capacity, and since the total number of random number values included in the update range is a prime number, synchronization between the first random number value and the second random number value is suppressed, making it possible to update the random number values appropriately.

(1-2) When executing an update process, the update means may be capable of updating the random number value to be updated and changing the initial random value after setting the random number value to be updated, the maximum random number value, and the initial random value.
Here, the setting for executing the update process may be, for example, steps AKS61 to AKS63 and AKS65 to AKS67. The update of the random number value to be updated and the change of the random number initial value may be, for example, steps AKS64 and AKS68 that execute the initial value change random number update process P_RANCP.
In such a configuration, it becomes possible to appropriately update the random number values by updating the set random number values to be updated.

(1-3) The update means may update the second random value after updating the first random value through a specific update process.
Here, the specific update process may be, for example, a random number update process P_RANDOM.
In such a configuration, by updating the first random number value, which is used to determine the display result that attracts the player's attention, before the second random number value, the occurrence of malfunctions is suppressed and the random number value can be updated appropriately.

(1-4) The update means may be capable of updating the first random number value and the second random number value and changing initial values of the first random number value and the second random number value by calling a common update process corresponding to the first random number value and the second random number value through the specific update process.
Here, the common update process may be, for example, the initial value change random number update process P_RANCP of steps AKS64 and AKS68 in the random number update process P_RANDOM.
In such a configuration, the common update process prevents an increase in program capacity, and the first random number value and the second random number value are stably updated, making it possible to appropriately update the random number value.

(1-5) The update means may be capable of updating the first random number value and the second random number value by a specific update process using a common internal storage means.
For example, in the random number update process P_RANDOM, the HL register is set in steps AKS61 and AKS65, the B register is set in steps AKS62 and AKS66, and the DE register is set in steps AKS63 and AKS67, and then the initial value change random number update process P_RANCP is executed in steps AKS64 and AKS68.
In such a configuration, the first random number value and the second random number value are stably updated using a common internal storage means, making it possible to appropriately update the random number values.

(1-6) When the specific update process stores the reference information in the internal storage means before the common update process, the update means may be capable of setting different reference information in the internal storage means by using an instruction that is common to the first random value and the second random value.
Here, the internal storage means may be, for example, an HL register, a B register, a DE register, etc. The common instruction may be a transfer instruction such as an LD instruction or an LDQ instruction. The different reference information may be, for example, the address F081 [H] of the random number counter for the winning symbol and the address F052 [H] of the random number counter for the normal winning symbol, or the address F050 [H] of the random number initial value data buffer for the winning symbol and the address F053 [H] of the random number initial value data buffer for the normal winning symbol.
In such a configuration, by making it possible to update the first random number value and the second random number value using a common instruction, it becomes possible to stably update the first random number value and the second random number value, thereby enabling appropriate updating of the random number value.

(1-7) When executing the update process, the update means is capable of changing the random number initial value in response to the update target random number value matching the update target random number value after updating the update target random number value.
For example, in the initial value change random number update process P_RANCP, after updating the random number value to be updated in step AKS101, a new random number initial value is stored in step AKS108 in response to a match with the value stored in the random number initial value data buffer in step AKS105.
In such a configuration, it is possible to appropriately update the random number values by updating the random number values to be updated and changing the initial random number values.

(1-8) When the update means executes the update process to update the random number value to be updated,
Comparing the update target random number with the maximum random number;
If the comparison result is less than the maximum random number value, add 1 to the random number value to be updated.
A single compare and add instruction may be executed first, which includes changing the random value to be updated to the minimum random value if the comparison result is greater than or equal to the maximum random value.
Here, the compare and add instruction may be, for example, the part of step AKS101.
In such a configuration, by executing the compare and add instruction first, it is possible to suppress the occurrence of errors and to update the random number value appropriately.

(1-9) The updating means may execute a compare and add instruction first in both cases of updating the first random value and updating the second random value.
For example, it may be step AKS101 in the initial value change random number update process P_RANCP of steps AKS64 and AKS68.
In such a configuration, by executing the compare and add instruction first, it is possible to suppress the occurrence of errors in the first random number value and the second random number value, and to update the random number value appropriately.

(1-10) When determining a display result by the first display means, when the first random number value is a minimum random number value, the display result is not determined to be more advantageous than when the first random number value is other than the minimum random number value;
When determining the display result by the second display means, when the second random number value is the minimum random number value, it is not necessary to determine a display result that is more advantageous than when the second random number value is other than the minimum random number value.
Here, the display result that is not determined to have a high degree of advantage may be, for example, example AKD01 of determining the number of times the large prize opening is to be performed or example AKD02 of determining the mode of the large prize opening.
In such a configuration, it becomes possible to appropriately update the random number values so as to prevent fraudulent acts due to defects in the first random number values or the second random number values.

(1-11) The update means is
An initial value update process is capable of updating the initial random value used when changing the random initial value;
After executing the compare and add instruction, the update target random number value after the update by the compare and add instruction is compared with the initial random number value;
If the updated random number does not match the initial random number, store the updated random number as the current random number.
If the updated random number value to be updated matches the random initial value, the initial value random number value obtained by the initial value update process may be stored as the current random number value and also as a new random initial value.
Here, the random number value for the initial value may be, for example, random number MR1-3 or random number MR2-2. The initial value update process may be, for example, random number update process P_TFINIT for determining initial value. The comparison with the random number initial value may be, for example, the part of step AKS105. If it does not match the random number initial value, it may be, for example, the case of Yes in step AKS105. If it matches the random number initial value, it may be, for example, the part of steps AKS106 to AKS108 in the case of No in step AKS105.
In such a configuration, the uncertainty of the random number value is increased by setting a new initial random number value, and by storing it as the current random number value, an increase in data volume is prevented, and the random number value can be appropriately updated.

(1-12) The update means is
A first initial value update process for updating a first initial value random value used when changing a random number initial value in response to a case where the random number value to be updated is a first random number value;
In response to the case where the random number value to be updated is a second random number value, it may be possible to execute an initial value update process that includes a second initial value update process that updates a random number value for a second initial value used when changing the random number initial value.
Here, the first initial value random number value may be, for example, random number MR1-3. The first initial value update process may be, for example, steps AKS81 and AKS82 in the initial value determination random number update process P_TFINIT. The second initial value random number value value may be, for example, random number MR2-2. The second initial value update process may be, for example, steps AKS83 and AKS84 in the initial value determination random number update process P_TFINIT.
In such a configuration, the random number values can be appropriately updated by updating the first initial value random number values and the second initial value random number values.

(1-13) The update means may update the first random value for the initial value and then update the second random value for the initial value through the initial value update process.
For example, in the initial value determination random number update process P_TFINIT, steps AKS83 and AKS84 may be executed after steps AKS81 and AKS82.
In such a configuration, by updating the random number value for the first initial value, which has a higher priority, before the random number value for the second initial value, which has a lower priority, the occurrence of malfunctions is suppressed, and the random number values can be updated appropriately.

(1-14) When executing the initial value update process, the update means performs the following based on the settings regarding the random number value for the initial value to be updated and the maximum value of the random number for the initial value:
comparing the random number value for the initial value to be updated with the maximum random number value for the initial value;
If the comparison result is less than the maximum initial value random number, the initial value random number to be updated is incremented by 1;
A single compare and add instruction may be executed, which includes changing the initial value random number value to be updated to the minimum random number value if the comparison result is equal to or greater than the initial value random number maximum value.
Here, the compare and add instruction may be, for example, steps AKS82 and AKS84.
In such a configuration, by updating the random number value for the initial value to be updated using a compare and add instruction, it is possible to suppress the occurrence of malfunctions and to update the random number value appropriately.

(1-15) The update means is
A random number update process capable of updating the random number value to be updated;
An initial value random number update process capable of updating an initial value random number used when changing a random number initial value corresponding to a random number value to be updated;
The first process executable in response to a timer interrupt due to the lapse of a predetermined time includes a random number update process and an initial value random number update process,
The second process that can be repeatedly executed until the first process is executed may not include a random number update process, but may include an initial value random number update process.
Here, the random number value to be updated may be, for example, random number MR1-2 or random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number value for initial value may be, for example, random number MR1-3 or random number MR2-2. The random number update process for initial value may be, for example, random number update process P_TFINIT for initial value determination. The first process may be, for example, timer interrupt process P_PCT for game control. The second process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the uncertainty of the initial value random number value is increased by the initial value random number update process, making it possible to update the random number value appropriately.

(1-16) The update process is
A random number update process capable of updating the random number value to be updated;
An initial value random number update process capable of updating an initial value random number used when changing a random number initial value corresponding to a random number value to be updated;
The random number update process and the initial value random number update process can be called and executed in a timer interrupt process that controls the progress of a game.
The initial value random number update process may be called and executed during standby processing that is repeated after startup processing that is executed based on the start of power supply.
Here, the random number value to be updated may be, for example, random number MR1-2 or random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number value for initial value may be, for example, random number MR1-3 or random number MR2-2. The random number update process for initial value may be, for example, random number update process for initial value determination P_TFINIT. The timer interrupt process may be, for example, timer interrupt process P_PCT for game control. The startup process may be, for example, steps S1 to S7 in the main process P_MAIN for game control. The standby process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the uncertainty of the initial value random number value is increased by the initial value random number update process, making it possible to update the random number value appropriately.

(2-1) A gaming machine that can be controlled to an advantageous state that is advantageous to a player,
An update means capable of updating the random value;
A processing means for executing a process related to game control by using the random number value updated by the updating means,
The update means is capable of updating a first random number value for determining whether or not to control to an advantageous state and a second random number value different from the first random number value;
The first random value is composed of a specific number of bytes, and the total number of random values included in the update range is a specific number,
The second random number value is a specific number of bytes, and the total number of random numbers included in the update range is a predetermined number smaller than the specific number,
The first random value may be updated faster than the second random value.
Here, the advantageous state may be, for example, a jackpot gaming state. The gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, etc. The processing means may be, for example, a CPU 103 that executes a special symbol process P_TPROC. The first random number value may be, for example, a random number MR1-1. The second random number value may be, for example, a random number MR3-2. The specific number of bytes may be, for example, 2 bytes. The specific number may be, for example, "65536", which is the size of the random number MR1-1. The predetermined number may be, for example, "65519", which is the size of the random number MR3-2. A fast update speed means, for example, that the update speed of random number MR1-1 in the comparative random number value AKA23 is 15,000 [times/ms] and the update speed of random number MR3-2 is 469 [times/ms].
In such a configuration, it becomes possible to update the random number value appropriately so that intentional control of an advantageous state becomes difficult due to a fast update speed of the first random number value related to the advantageous state.

(2-2) A gaming machine capable of playing a game,
An update means capable of updating the random value;
A processing means for executing a process related to game control by using the random number value updated by the updating means,
The updating means is capable of updating a first random value and a second random value different from the first random value;
The first random value has an update rate of a first rate,
The second random value is a second speed at which the update speed is an integer multiple of the first speed,
The total number of random values included in the update range of each of the first random value and the second random value may be different, and the total number of random values included in both update ranges may be a prime number.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, a CPU 103 that executes a special symbol process P_TPROC, or the like. The first random number value may be, for example, a random number MR3-2. The second random number value may be, for example, a random number MR3-3, MR3-4, or the like. The first speed may be, for example, 469 [times/ms], or the like. The second speed may be, for example, 938 [times/ms], or the like. The total number of random numbers may be, for example, the size of the random number MR3-2, i.e., "65519", the size of the random number MR3-3, "241", the size of the random number MR3-4, "251", or the like.
In such a configuration, even if the update speed becomes an integer multiple, the total number of random number values included in the update range is a different prime number, thereby suppressing synchronization between the first random number value and the second random number value, thereby enabling appropriate updating of the random number values.

(2-3) A gaming machine capable of playing a game,
An update means capable of updating the random value;
A processing means for executing a process related to game control by using the random number value updated by the updating means,
the updating means is capable of updating a first random value, a second random value different from the first random value, and a third random value different from the first random value and the second random value;
The processing means is capable of extracting the first random number value, the second random number value, and the third random number value when a common extraction condition is satisfied;
The first random value has an update rate of a first rate,
the second random value and the second random value are a second speed at which the update speed is an integer multiple of the first speed;
The total number of random values included in each update range may be different for the first random value, the second random value, and the third random value, and the total number of random values included in each update range may be a prime number.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, a CPU 103 that executes a special symbol process P_TPROC. The first random number may be, for example, a random number MR3-2. The second random number may be, for example, a random number MR3-3. The third random number may be, for example, a random number MR3-4. The first speed may be, for example, 469 [times/ms], or the like. The second speed may be, for example, 938 [times/ms], or the like. The total number of random numbers may be, for example, the size of the random number MR3-2, "65519", the size of the random number MR3-3, "241", the size of the random number MR3-4, "251", or the like.
In such a configuration, even if the update speed becomes an integer multiple, the total number of random numbers included in the update range is a different prime number, thereby suppressing synchronization between the first random number value, the second random number value, and the third random number value, thereby making it possible to update the random number values appropriately.

(2-4) A gaming machine capable of playing a game,
An update means capable of updating the random value;
A processing means for executing a process related to game control using the random number value updated by the updating means,
The update method is
a first update means for updating the first random number value and the second random number value within their respective update ranges by a random number update process;
a second update means capable of updating the third random number value and the fourth random number value within their respective update ranges by a random number clock signal;
At least one of the first random value and the second random value is a random value in which a total number of random values included in an update range is a prime number;
At least one of the third random value and the fourth random value may be such that the total number of random value values included in the update range is a prime number.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or a CPU 103 that executes a random number updating process P_RANDOM. The processing means may be, for example, a CPU 103 that executes a special symbol process P_TPROC or a normal symbol process P_FPROC. The first random number value may be, for example, a random number MR2-1. The second random number value may be, for example, a random number MR1-2. The random number updating process may be, for example, a random number updating process P_RANDOM. The third random number value may be, for example, a random number MR3-3. The fourth random number value may be, for example, a random number MR3-4. The random number clock signal may be, for example, a system clock. The total number of random numbers included in the update range may be, for example, "199", which is the magnitude of random number MR2-1, "200", which is the magnitude of random number MR1-2, "241", which is the magnitude of random number MR3-3, and "251", which is the magnitude of random number MR3-4.
In such a configuration, the update methods of the first update means and the second update means are different, and even if the update methods are the same, at least one of the random number values has a total number of random number values included in the update range that is a prime number, thereby suppressing the occurrence of synchronization and enabling appropriate updating of the random number values.

(3-1) A gaming machine capable of playing a game,
An update means capable of updating the random value;
A processing means for executing a process related to game control using the random number value updated by the updating means;
a storage means including a storage area relating to the functions of the update means and the processing means;
The processing means is capable of executing a maximum value setting process for setting a maximum value of the random number values updated by the update means when a storage value is set in the storage area related to the function by a start-up process executed based on the start of power supply,
The update method is
A first update means capable of updating a first random number value consisting of a specific number of bytes;
and a second update means capable of updating a second random value that is configured with a predetermined number of bytes smaller than the specific number of bytes,
When executing the maximum value setting process, the processing means may set a maximum random value for the first random value and then set a maximum random value for the second random value.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a random number circuit 104. The processing means may be, for example, a CPU 103 that executes a special symbol process processing P_TPROC. The storage area related to the function may be, for example, a function setting register area of setting example AKA01 or a function control register area of setting example AKA02. The storage means may be, for example, a built-in register of the gaming control microcomputer 100. The startup processing may be, for example, a main processing P_MAIN for gaming control. The maximum value setting processing may be, for example, a portion of steps AKS11 to AKS13 in the power supply start corresponding processing P_POWER_ON. The specific number of bytes may be, for example, 2 bytes. The first random number value may be, for example, a random number MR3-2. The first updating means may be, for example, a 16-bit random number circuit 104A. The predetermined number of bytes may be, for example, 1 byte. The second random number value may be, for example, random numbers MR3-3, MR3-4, etc. The second update means may be, for example, an 8-bit random number circuit 104B, etc. Setting the maximum random number value of the first random number value and setting the maximum random number value of the second random number value may be performed by executing step AKS13 using the function setting register storage value table AKT01, etc.
In such a configuration, by setting a first random number value of a specific number of bytes and then setting a second random number value of a predetermined number of bytes, the first random number value and the second random number value can be stably updated, making it possible to update the random number values appropriately.

(3-2) The updating means may start updating the random numbers in order from the random number value for which the maximum random number value is set.
For example, it would be sufficient to use the function setting register storage value table AKT01 to set maximum values for the 16-bit random number circuit channel RL0 with channel number "0", the 16-bit random number circuit channel RL2 with channel number "2", and the 8-bit random number circuit channels RS1 to RS3 with channel numbers "1" to "3".
In such a configuration, the uncertainty of the random value is increased by the timing at which the update of the random value is started, reducing the processing load and enabling appropriate updating of the random value.

(3-3) A gaming machine capable of playing a game,
An update means capable of updating the random value;
A processing means for executing a process related to game control using the random number value updated by the updating means;
a storage means including a storage area relating to the functions of the update means and the processing means;
The processing means is capable of executing a maximum value setting process for setting a maximum value of the random number values updated by the update means when a storage value is set in the storage area related to the function by a start-up process executed based on the start of power supply,
The update method is
a first update means capable of updating the first random number value and the second random number value by a random number clock signal;
A second update means capable of updating the third random number value by a random number update process,
the first updating means, in the maximum value setting process executed by the processing means, starts updating the first random number value as a result of the setting of the maximum random number value of the first random number value, and then starts updating the second random number value as a result of the setting of the maximum random number value of the second random number value;
The second updating means may start updating the third random value after the processing means executes the maximum value setting process.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a random number circuit 104 or a CPU 103 that executes a random number updating process P_RANDOM. The processing means may be, for example, a CPU 103 that executes a special symbol process process P_TPROC or a normal symbol process process P_FPROC. The storage area related to the function may be, for example, a function setting register area of the setting example AKA01 or a function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the gaming control microcomputer 100. The startup process may be, for example, a main process P_MAIN for gaming control. The maximum value setting process may be, for example, a part of steps AKS11 to AKS13 in the power supply start corresponding process P_POWER_ON. The first random number value may be, for example, random numbers MR1-1, MR3-2, etc. The second random number value may be, for example, random numbers MR3-3, MR3-4, etc. The first update means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, etc. The third random number value may be, for example, random numbers MR1-2, MR2-1, etc. The random number update process may be, for example, a random number update process P_RANDOM, etc. The second update means may be, for example, a CPU 103 that executes the random number update process P_RANDOM in step S56. The first random number value update may be started by, for example, a part that sets a maximum value to the 16-bit random number circuit channel RL0 with channel number "0" and the 16-bit random number circuit channel RL2 with channel number "2" using the function setting register storage value table AKT01. The second random number value update may be started by, for example, a part that sets a maximum value to the 8-bit random number circuit channels RS1 to RS3 with channel numbers "1" to "3" using the function setting register storage value table AKT01. The updating of the third random number value may be started, for example, in the part where the random number update process P_RANDOM of step S56 is executed in the timer interrupt process P_PCT for game control after the power supply start response process P_POWER_ON of step S1 is executed.
In such a configuration, the uncertainty is increased by starting the update of random numbers such as MR1-1, which have a high correlation with the game value, first, thereby making it possible to update the random numbers appropriately.

(4-1) a storage means capable of storing information related to game control;
a storage means including a storage area relating to the functions of the update means and the processing means;
a specific storage area among the storage areas relating to the function can be set to a first storage value that prohibits access to the storage means in response to the start of power supply;
The processing means includes:
After setting a storage value in the storage area related to the function, a second storage value that allows access to the storage means can be set in the specific storage area;
As a next process after the second storage value is set in the specific storage area, a confirmation process may be executed to confirm whether or not the control state can be restored based on the stored contents of the storage means.
Here, the storage means may be, for example, a RAM 102. The storage area relating to the function may be, for example, a function setting register area of setting example AKA01 or a function control register area of setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The specific storage area may be, for example, an RWM access protection register. The first storage value may be, for example, 00 [H]. The second storage value may be, for example, 01 [H]. The second storage value may be set in the specific storage area by, for example, executing step AKS14 in the power supply start response process P_POWER_ON. The confirmation process may be, for example, the RWM check process P_RWM_CHK of step S2.
In such a configuration, the contents stored in the storage means are prevented from being changed unnecessarily, so that the confirmation process can be executed reliably and the random number value can be updated appropriately.

(4-2) The processing means is
A stoppage storage process is executed to store recovery information for recovering a control state in a storage means in response to a power supply interruption,
After the stop time storage process is executed, a stop time storage process can be executed to set the first storage value in the specific storage area,
After the stop-time storage process is executed, the machine may transition to a standby state in which no game control is executed, and in response to the power supply being restored while in this standby state, the start-time process based on the start-up of the gaming machine may be executable from the beginning.
The recovery information may be, for example, checksum data. The stop-time storage process may be, for example, the checksum calculation process of step AKS39 or the part of step AKS40 in the power-off process P_POWER_OFF. The stop-time storage process may be, for example, the parts of steps AKS41 and AKS42 in the power-off process P_POWER_OFF. The transition to the standby state may be, for example, the execution of steps AKS48 and AKS49 in the power-off process P_POWER_OFF. The executable from the beginning of the start-up process may be, for example, the execution of step AKS50 in the power-off process P_POWER_OFF and then the execution of the RET command.
In such a configuration, when the power supply is restored, unstable operation can be prevented and the random number values can be updated appropriately.

(4-3) a storage means capable of storing information related to game control;
a storage means including a storage area relating to the functions of the update means and the processing means;
The storage means includes, as a storage area relating to functions,
A first area for setting functions;
a second area for function control;
the second area includes a specific storage area in which a storage value indicating whether or not access to the storage means is permitted can be set;
The processing means, in a startup process executed based on the start of power supply,
A control storage process is executed to set a storage value in the second area,
After the control storage process is executed, a setting storage process can be executed to set a storage value in the first area,
After the setting storage process is executed, a storage value that permits access to the storage means may be set in the specific storage area.
Here, the storage means may be, for example, the RAM 102. The storage area relating to the function may be, for example, the function setting register area of the setting example AKA01 or the function control register area of the setting example AKA02. The storage means may be, for example, a built-in register of the game control microcomputer 100. The first area may be, for example, the function setting register area of the setting example AKA01. The second area may be, for example, the function control register area of the setting example AKA02. The specific storage area may be, for example, an RWM access protection register. The startup process may be, for example, the main process P_MAIN for game control. The control storage process may be, for example, the steps AKS5 to AKS7 in the power supply start response process P_POWER_ON. The setting storage process may be, for example, the steps AKS11 to AKS13 in the power supply start response process P_POWER_ON. The storage value can be set in the specific storage area by, for example, executing step AKS14 in the power supply start response process P_POWER_ON.
In such a configuration, it is possible to prevent the contents stored in the storage means from being changed unintentionally, and to update the random number values appropriately.

(Explanation regarding characteristic part 003AK)
FIG. 11-1 shows the memory area of addresses 0000[H] to 3FFF[H] allocated to the ROM 101 with respect to the characteristic part 003AK. The game program area included in the memory area of the ROM 101 is allocated addresses 0000[H] to 0BD2[H], and has a total storage capacity of 3027 bytes. The game data area included in the memory area of the ROM 101 is allocated addresses 1200[H] to 1D33[H], and has a total storage capacity of 2868 bytes. The non-game program area included in the memory area of the ROM 101 is allocated addresses 2000[H] to 24DD[H]. The non-game data area included in the memory area of the ROM 101 is allocated addresses 24DE[H] to 2576[H]. The ROM comment area included in the memory area of the ROM 101 is assigned addresses 2E00[H] to 2E3F[H]. The program management area included in the memory area of the ROM 101 is assigned addresses 3FC0[H] to 3FFF[H].

The memory area of ROM 101 includes an unused area assigned with addresses 0BD3[H] to 11FF[H] between the game program area and the game data area. The unused area of addresses 0BD3[H] to 11FF[H] has a total storage capacity of 1069 bytes. The memory area of ROM 101 includes an unused area assigned with addresses 1D34[H] to 1FFF[H] between the game data area and the non-game program area. The unused area of addresses 1D34[H] to 1FFF[H] has a total storage capacity of 1228 bytes. The memory area of ROM 101 includes an unused area assigned with addresses 2577[H] to 2DFF[H] between the non-game data area and the ROM comment area. The memory area of ROM 101 includes an unused area assigned with addresses 2E40[H] to 3FBF[H] between the ROM comment area and the program management area.

In all of these unused areas, zero data with a storage value of 00 [H] is stored as unused data. In this way, the unused areas all store zero data with a storage value of 00 [H] as unused data indicating 0. The unused areas may be areas to which access by the CPU 103 is prohibited. For example, it may be possible to set access prohibition for all or part of the unused areas using designated data for the program code end address and program code start address stored in the program management area.

In the game control microcomputer 100, the ROM 101 can store a program, and the CPU 103 can control the progress of the game using the program stored in the ROM 101. Therefore, the ROM 101 can correspond to a storage means capable of storing a program. The CPU 103 can correspond to a control means capable of controlling the progress of the game using the program stored in the storage means. Note that the storage means capable of storing a program may be constituted by an external storage device different from the ROM 101, and the entire game control microcomputer 100 may be constituted as a control means capable of controlling the progress of the game using the program stored in this storage device.

The game program area stores programs related to game control. The game data area stores data used to execute the programs stored in the game program area. A non-game program area and a non-game data area are provided as storage areas different from the game program area and game data area. Thus, the game program area may correspond to a first storage area in which a program related to game control is stored. The game data area may correspond to a second storage area in which data used to execute the programs stored in the first storage area is stored. The non-game program area and non-game data area may correspond to a third storage area different from the first storage area and the second storage area.

In the memory area of ROM 101, if the game program area is the first memory area and the game data area is the second memory area, the unused area from addresses 0BD3 [H] to 11FF [H] becomes an unused memory area capable of storing unused data between the first memory area and the second memory area. Here, unused data indicating all 0 is stored in the unused area that becomes the unused memory area. In this case, the total memory capacity of the game program area that becomes the first memory area is 3027 bytes, which is larger than the total memory capacity of the unused area that becomes the unused memory area, which is 1069 bytes.

In the memory area of ROM 101, if the game program area is the first memory area, the game data area is the second memory area, and the non-game program area and non-game data area are the third memory area, the unused area of addresses 0BD3 [H] to 11FF [H] becomes an unused memory area capable of storing unused data between the first memory area and the second memory area, and the unused area of addresses 1D34 [H] to 1FFF [H] becomes an unused memory area capable of storing unused data between the second memory area and the third memory area. Here, unused data indicating all 0 is stored in the unused area that becomes the unused memory area. In this case, the total memory capacity of the game data area that becomes the second memory area is 2868 bytes, which is larger than the total memory capacity of the unused area that becomes the unused memory area, which is 2297 bytes.

In the memory area of ROM 101, the unused area corresponding to the unused memory area capable of storing unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area may be a single area to which consecutive addresses are assigned and in which unused data indicating 0 is stored. In the memory area of ROM 101, the unused area corresponding to the unused memory area capable of storing unused data between the game data area corresponding to the second memory area and the non-game program area and non-game data area corresponding to the third memory area may be a single area to which consecutive addresses are assigned and in which unused data indicating 0 is stored.

For example, in the address map of the game control microcomputer 100, the memory areas to which addresses are assigned in the ROM 101 are identified in correspondence with the magnitude relationship of the address values, such that the smaller assigned address is in the front and the larger assigned address is in the back. Therefore, a second area to which an address value larger than that of the first area is assigned becomes the second area located behind the first area, and a third area to which an address value smaller than that of the first area is assigned becomes the third area located ahead of the first area. The first, second, and third areas may be arbitrarily set according to the magnitude relationship of the addresses assigned in accordance with the specifications of the pachinko game machine 1. The arrangement of each area in the memory area of the ROM 101, including the game program area, game data area, non-game program area, non-game data area, and other unused areas, may be arbitrarily set according to the addresses assigned in accordance with the specifications of the pachinko game machine 1.

Figure 11-2 shows a setting example 003AKA01 of unused data in a game program area included in the memory area of ROM 101. In setting example 003AKA01, the processing start address includes the start address of the program module and the start address of the table data. The processing end address includes the end address of the program module and the end address of the table data. The unused data amount is the number of bytes that is the storage capacity of an area in which zero data with a storage value of 00 [H] is stored as unused data indicating 0. Therefore, the processing start address is the start address of a program or the start address of data usable for executing a program, and the processing end address is the end address of a program or the end address of data usable for executing a program. However, data usable for executing a program may include data that is not used for executing a program, depending on various instructions and settings in the implemented program.

In the game program area included in the memory area of ROM 101, addresses 0008[H], 0010[H], 0018[H], 0020[H], 0028[H], 0030[H], 0038[H], and 0040[H] are predetermined as restart addresses where program modules can be located. The restart addresses are 8-byte addresses in the area allocated with addresses 0008[H] to 0040[H] included in the game program area, with the lowest digit of the address being 0[H] or 8[H]. Therefore, the restart addresses can correspond to multiple specific addresses allocated at predetermined intervals. The CPU 103 is provided with a RST command, which is a 1-byte restart command that can be executed by calling a program module whose starting address is a predetermined restart address.

Figure 11-3 shows an example of the configuration of an RST instruction. As shown in Figure 11-3 (A), the RST instruction is configured using an operation code from bit 0 to bit 7, and all bits other than bits 3 to 5 are configured with an operation code indicating 1 [B]. As shown in Figure 11-3 (B), the operation code from bit 3 to bit 5 in the RST instruction is a parameter defined corresponding to a specified address, which is the call address of a program module. For example, parameter 001[B] corresponds to address 0008[H], parameter 010[B] corresponds to address 0010[H], parameter 011[B] corresponds to address 0018[H], parameter 100[B] corresponds to address 0020[H], parameter 101[B] corresponds to address 0028[H], parameter 110[B] corresponds to address 0030[H], parameter 111[B] corresponds to address 0038[H], and parameter 000[B] corresponds to address 0040[H]. Thus, each three-digit binary parameter corresponds to a four-digit hexadecimal address.

When a program module is called by the RST instruction, which serves as a restart instruction, an operation code including parameters is used. The RST instruction specifies a parameter with a smaller amount of data than the address in the memory area of ROM 101, making it possible to call a program module stored at an address corresponding to the specified parameter. The operation code of the RST instruction includes a three-digit binary variable t, and multiple restart addresses can be specified using the operation code in which the parameter is substituted for that variable. In this way, the RST instruction is a call instruction that specifies a value corresponding to a predetermined restart address, thereby calling and making executable a program stored at the restart address corresponding to the specified value.

The CPU 103 is provided with a CALL instruction, which is different from the RST instruction, as a call instruction for calling and executing a program stored in the game program area. The CALL instruction is a call instruction that calls and makes executable a program stored at an address specified by an operand. When a program is called and executed by the CALL instruction, a total of two bytes consisting of an upper byte and a lower byte that constitute the start address of the program are specified by the operand of the CALL instruction. The CPU 103 specifies the start address of the program by such an operand of the CALL instruction. Therefore, the CALL instruction can correspond to a first call instruction that calls a program stored at a specified address by specifying an address. In contrast, the RST instruction can correspond to a second call instruction that calls a program stored at a specific address corresponding to the specified parameter among multiple specific addresses assigned at a predetermined interval by specifying a parameter with a smaller data amount than the address.

Of the game programs that control the progress of the game, at least some of the frequently used program modules are stored in the restart area, which starts at the restart address. In the setting example 003AKA01 shown in Figure 11-2, the special symbol process end check process P_TPRO_END, time-saving check process P_JTN_CHK, 2-byte 1-byte addition process P_ABX, output process P_OUT, 2-byte data selection process P_ABXEXC, second allocation judgment value comparison process P_HANTEI2, start port winning check process P_STR_CHK, allocation judgment value comparison process P_HANTEI, and command set process P_COM_SET, each program module is stored in the restart area. In addition, the vector table at the time of power recovery is also included in the data stored in the restart area.

The program module for special pattern process end check processing P_TPRO_END has a start address of address 0008 [H]. The program module for time-saving check processing P_JTN_CHK has a start address of address 0010 [H]. The program module for 2-byte 1-byte addition processing P_ABX has a start address of address 0018 [H]. The program module for 2-byte data selection processing P_ABXEXC has a start address of address 0020 [H]. The program module for second allocation judgment value comparison processing P_HANTEI2 has a start address of address 0028 [H]. The program module for start port winning check processing P_STR_CHK has a start address of address 0030 [H]. The program module for allocation judgment value comparison processing P_HANTEI has a start address of address 0038 [H]. The program module for command set processing P_COM_SET has a start address of address 0040 [H].

In the restart area, the area from one restart address to just before the next restart address is 8 bytes, except when the one restart address is the last restart address at address 0040 [H]. When a program module of less than 8 bytes is stored with a restart address as its starting address, the area after the end address of the program module that starts at the one restart address to just before the next restart address may be able to store other program modules or table data.

For example, the program module for the time-saving check process P_JTN_CHK has address 0010 [H], which is included in multiple restart addresses, as its start address, and address 0014 [H] as its end address. In this case, table data for the vector table at the time of power interruption recovery can be stored in the area from address 0010 [H], which is one restart address, to just before address 0018 [H], which is the next restart address. A vector table at the time of power interruption recovery such as configuration example AKT11 is configured to include, as table data, lower address designation data 00 [H] stored at address 0016 [H] and upper address designation data 00 [H] stored at address 0017 [H].

For example, the program module for the 2-byte 1-byte addition process P_ABX has address 0018[H], which is included in the multiple restart addresses, as its start address, and address 001A[H] as its end address. In this case, the program module for the output process P_OUT can be stored in the area from address 0018[H], which is one restart address, to just before address 0020[H], which is the next restart address. The program module for the output process P_OUT only needs to have address 001B[H], which is different from the multiple restart addresses, as its start address, and address 001F[H] as its end address. Therefore, the restart area starting from address 0018[H], which is the restart address, can store program modules corresponding to multiple processes, such as the 2-byte 1-byte addition process P_ABX and the output process P_OUT, with the process start address being address 0018[H] and the process end address being address 001F[H].

In this way, other program modules or table data may be stored in the area from the end address of a program module whose start address is the restart address to just before the next restart address. This makes it possible to store multiple program modules, or a combination of program modules and table data, in the area from one restart address to just before the next restart address.

In the restart area, the area from one restart address to just before the next restart address is 8 bytes, except when the first restart address is the final restart address, address 0040 [H]. When a program module of less than 8 bytes is stored with a restart address as its starting address, the area after the end address of the program module whose starting address is the first restart address to just before the next restart address may store zero data, with a storage value of 00 [H], as unused data indicating 0.

Figure 11-4 shows an example of the program modules stored in the restart area, which correspond to the start port winning check process P_STR_CHK and the allocation judgment value comparison process P_HANTEI. As shown in Figure 11-4 (A), the start port winning check process P_STR_CHK stores a program module in the restart area from address 0030 [H], which is one restart address, to before address 0038 [H], which is the next restart address, with address 0030 [H] being the start address and including the LDQ command, etc. The start port winning check process P_STR_CHK ends at address 0034 [H], and resumes processing by executing the RET command. As shown in FIG. 11-4 (B), the allocation judgment value comparison process P_HANTEI stores a program module in a restart area from address 0038[H], which is one restart address, to address 0040[H], which is the next restart address, with address 0038[H] being the start address and including the LDIN command, etc. The allocation judgment value comparison process P_HANTEI ends at address 003E[H], and resumes processing by executing the RET command.

The area from addresses 0035[H] to 0037[H] shown in Figure 11-4 (A) stores three bytes of zero data with a storage value of 00[H]. This area is after the end address 0034[H] of the program module where the start port winning check process P_STR_CHK ends with the RET command and returns to the process from which it was called, and before address 0038[H], which is the next restart address. Therefore, the area from addresses 0035[H] to 0037[H] is an area where unused data is stored, unlike an area where programs executed by the CPU 103 and data used to execute programs can be stored. Therefore, the area from addresses 0035[H] to 0037[H] is included in a special storage area where unused data indicating 0 is stored at a special address. In this way, the area assigned addresses 0035[H] to 0037[H] from address 0030[H], which is the first restart address, to just before address 0038[H], which is the next restart address, is included in the special memory area to which special addresses are assigned.

The area of address 003F[H] shown in FIG. 11-4(B) stores one byte of zero data with a storage value of 00[H]. This area is after the end address 003E[H] of the program module where the allocation judgment value comparison process P_HANTEI ends with the RET command and returns to the caller's process, and before address 0040[H] which is the next restart address. Therefore, the area of address 003F[H] is an area where unused data is stored, unlike an area where programs executed by the CPU 103 and data used to execute programs can be stored. Therefore, the area of address 003F[H] is included in a special memory area where unused data indicating 0 is stored at a special address. In this way, the area to which address 003F[H] is assigned, from address 0038[H] which is one restart address to just before address 0040[H] which is the next restart address, is included in a special memory area to which a special address is assigned.

In addition, as shown in Figure 11-2, from address 0014[H], which is the end address of the time-saving check process P_JTN_CHK, to address 0016[H], which is the start address of the vector table at the time of power loss recovery, the area of address 0015[H] stores one byte of zero data with a storage value of 00[H], and is included in a special memory area where unused data indicating 0 is stored at a special address. As a result, the area assigned to address 0015[H] from address 0010[H], which is the first restart address, to just before address 0018[H], which is the next restart address, is included in a special memory area to which special addresses are assigned. The 2-byte data selection process P_ABXEXC has address 0020[H] as its start address and 0025[H] as its end address. In this case, the area of addresses 0026[H] and 0027[H] from address 0020[H], which is the first restart address and the start address of the 2-byte data selection process P_ABXEXC, to just before address 0028[H], which is the next restart address, stores 2 bytes of zero data with a storage value of 00[H], and is included in the special memory area where unused data indicating 0 is stored at the special address. As a result, the area assigned to addresses 0026[H] and 0027[H] from address 0020[H], which is the first restart address, to just before address 0028[H], which is the next restart address, is included in the special memory area to which special addresses are assigned.

In this way, the restart area from one restart address to the next restart address included in the multiple restart addresses stores zero data with a storage value of 00 [H], and may include an area in which unused data indicating 0 is stored in a special address. Therefore, the special memory area includes an area in which unused data is stored in the area from one specific address to the next specific address included in the multiple specific addresses.

In this case, the area from address 0010 [H], which is the first restart address where the program module of the time-saving check process P_JTN_CHK is stored, to address 0018 [H], which is the next restart address, includes a special memory area in which 1 byte of unused data is stored. The area from address 0020 [H], which is the first restart address where the program module of the 2-byte data selection process P_ABXEXC is stored, to address 0028 [H], which is the next restart address, includes a special memory area in which 2 bytes of unused data are stored. The area from address 0030 [H], which is the first restart address where the program module of the start-up winning check process P_STR_CHK is stored, to address 0038 [H], which is the next restart address, includes a special memory area in which 3 bytes of unused data are stored. The area from address 0038 [H], which is the first restart address where the program module of the allocation judgment value comparison process P_HANTEI is stored, to address 0040 [H], which is the next restart address, includes a special memory area in which 1 byte of unused data is stored. Therefore, the total storage capacity of the special storage area in the restart area, where special addresses are assigned and unused data indicating 0 is stored, is 7 bytes.

In addition, multiple restart addresses are assigned every 8 bytes, and each restart address becomes the start address of a program module, so that zero data with a storage value of 00 [H] is stored in the restart area, and the special memory area in which unused data indicating 0 is stored at the special address includes multiple areas assigned with discontinuous addresses. And, in the special memory area in which zero data with a storage value of 00 [H] is stored in the restart area, and unused data indicating 0 is stored at the special address, the special addresses are assigned so that there are no consecutive areas of more than a specific number of bytes, for example 16 bytes.

Figure 11-5 shows an example of storage of table data contained in the interrupt vector table XTBL_INTR. In the game program area contained in the memory area of ROM 101, address 0060 [H] is defined as an address where the interrupt vector table XTBL_INTR can be located. For example, it is sufficient if the lower byte 60 [H] of address 0060 [H] can be set as a vector address corresponding to the interrupt cause by the setting data of the initial interrupt settings stored in the program management area. Also, it is sufficient if the upper byte 00 [H] of address 0060 [H] is set as the upper address of the interrupt vector table by step AKS8 of the power supply start response processing, and it is possible to set it in the I register by step AKS9.

The interrupt initial setting data can set vector addresses corresponding to multiple interrupt factors. In addition, the interrupt mask register at address FE00 [H] included in the function setting register area can store setting values including bit values corresponding to whether or not to use multiple maskable interrupts. In the power supply start response setting process, the function setting register storage value table address is set in step AKS11, the number of processes is loaded in step AKS12, and then the function setting register store command is executed in step AKS13, so that the storage value of the interrupt mask register is set to 7E [H]. The interrupt controller 135 enables maskable interrupts corresponding to multiple interrupt factors, such as seven types of maskable interrupts IR0 to IR6. When the storage value of the interrupt mask register is 7E [H], the maskable interrupt IR0 is set to an enabled state, and the other maskable interrupts IR1 to IR6 are set to an disabled state.

The interrupt vector table XTBL_INTR contains table data that can set the start address of interrupt processing corresponding to multiple maskable interrupts IR0 to IR6. The table data at addresses 0060 [H] and 0061 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR0. The table data at addresses 0062 [H] and 0063 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR1. The table data at addresses 0064 [H] and 0065 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR2. The table data at addresses 0066 [H] and 0067 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR3. The table data at addresses 0068 [H] and 0069 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR4. The table data at addresses 006A[H] and 006B[H] specifies the start address of the interrupt processing corresponding to maskable interrupt IR5. The table data at addresses 006C[H] and 006D[H] specifies the start address of the interrupt processing corresponding to maskable interrupt IR6. Therefore, the area from addresses 0060[H] to 006D[H] that stores the table data included in the interrupt vector table XTBL_INTR can correspond to an address storage area that can store the addresses of the interrupt processing program.

When the value stored in the interrupt mask register is 7E [H], only maskable interrupt IR0 is set to an enabled state, and the other maskable interrupts IR1 to IR6 are set to an disabled state. Therefore, in the interrupt vector table XTBL_INTR, the table data at addresses 0060 [H] and 0061 [H] becomes data used to specify the start address of the interrupt process, while the table data at addresses 0062 [H] to 006D [H] becomes unused data. For example, the table data at address 0060 [H] indicates the lower address, which is the lower byte of the start address, for the timer interrupt process P_PCT for game control. The table data at address 0061 [H] indicates the upper address, which is the upper byte of the start address, for the timer interrupt process P_PCT for game control. As a result, the program that becomes the timer interrupt process P_PCT for game control becomes the interrupt process program whose address is stored in the interrupt vector table XTBL_INTR. In contrast, the table data at addresses 0062[H] to 006D[H] contains 12 bytes of zero data with a storage value of 00[H], which is unused interrupt vector data. Thus, the area from addresses 0062[H] to 006D[H] is an area where unused data is stored, unlike an area where programs executed by the CPU 103 and data used to execute programs can be stored. Therefore, the area from addresses 0062[H] to 006D[H] is included in a special storage area where unused data indicating 0 is stored at a special address.

When the area of addresses 0060[H] to 006D[H], which stores table data included in the interrupt vector table XTBL_INTR, becomes an address storage area, the area assigned to addresses 0062[H] to 006D[H] is included in a special storage area to which a special address is assigned. In this case, the special storage area includes an area in the address storage area in which unused data is stored. The area assigned to addresses 0062[H] to 006D[H] has a total storage capacity of 12 bytes. Therefore, when the area of addresses 0060[H] to 006D[H] becomes an address storage area, the total storage capacity of the special storage area in this address storage area to which a special address is assigned and in which unused data indicating 0 is stored is 12 bytes.

Thus, the game program area includes an area in which unused data indicating 0 is stored. In the game program area, the area in which unused data indicating 0 is stored may correspond to a special memory area to which a special address is assigned. Also, the total memory capacity of the special memory area in which a special address is assigned and unused data indicating 0 is stored in the restart area is 7 bytes. When the area of addresses 0060 [H] to 006D [H] that stores table data included in the interrupt vector table XTBL_INTR becomes an address memory area, the total memory capacity of the special memory area in which a special address is assigned and unused data indicating 0 is stored in this address memory area is 12 bytes. Thus, the total memory capacity of the area that becomes the special memory area in the game program area is 19 bytes. The total memory capacity of the unused area corresponding to the unused memory area that can store unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area is 1069 bytes. Therefore, the total memory capacity of the special memory area is 19 bytes, which is smaller than the total memory capacity of the unused area that becomes the unused memory area, which is 1069 bytes.

The total storage capacity of the game program areas corresponding to the first memory area is greater than the total storage capacity of the unused areas that are unused memory areas capable of storing unused data between the first memory area and the second memory area. When such a first memory area includes a special memory area, the total storage capacity of the special memory area is smaller than the total storage capacity of the unused areas. This increases the possibility of distinguishing between the unused areas and the special memory areas, and enables appropriate management of the memory areas to prevent misidentification of them.

The special memory area to which a special address is assigned in the restart area includes multiple areas to which discontinuous addresses are assigned. For example, the area of addresses 0035[H] to 0037[H] shown in FIG. 11-4(A) and the area of address 003F[H] shown in FIG. 11-4(B) are both included in the special memory area and can correspond to multiple areas to which discontinuous addresses are assigned. In addition, in the area from address 0010[H], which is one restart address in which the program module of the time-saving check process P_JTN_CHK is stored, to address 0018[H], which is the next restart address, the area in which 1 byte of unused data is stored is included in the special memory area and can be included in multiple areas to which discontinuous addresses are assigned from the special memory areas provided in other restart areas. In the area from address 0020 [H], which is one restart address where the program module of the 2-byte data selection process P_ABXEXC is stored, to address 0028 [H], which is the next restart address, the area where the 2-byte unused data is stored is included in the special memory area, and can be included in multiple areas to which discontinuous addresses are assigned from the special memory areas provided in other restart areas. Therefore, the special memory area in the restart area to which a special address is assigned and to which unused data indicating 0 is stored includes multiple areas to which discontinuous addresses are assigned as special addresses.

The special memory area to which a special address is assigned in the restart area and the special memory area to which a special address is assigned in the area storing the table data included in the interrupt vector table XTBL_INTR are assigned discontinuous addresses. The area to store the table data included in the interrupt vector table XTBL_INTR is an area from address 0060[H] to 006D[H], with the address of the program for the timer interrupt process P_PCT for game control stored in the area from address 0060[H] and 0061[H], and unused data indicating 0 stored in the area from address 0062[H] to 006D[H]. Therefore, the special memory area to which a special address is assigned in the area storing the table data included in the interrupt vector table XTBL_INTR is included in the special memory area to which a special address is assigned in the restart area and in multiple areas to which discontinuous addresses are assigned.

In this way, the storage addresses of the unused data in setting example 003AKA01 are assigned discontinuous addresses as special addresses in the special memory area, so that, unlike unused areas that are assigned consecutive addresses and have unused data indicating 0 stored therein, it is difficult for unused data indicating 0 to be stored in an area of consecutive special addresses in the special memory area. This increases the likelihood of distinguishing between unused areas and special memory areas, and enables appropriate management of memory areas to prevent misidentification of the two.

The total storage capacity of the special memory areas to which special addresses are assigned in the restart area is smaller than the total storage capacity of the special memory areas to which special addresses are assigned in the area storing the table data included in the interrupt vector table XTBL_INTR. This allows the program modules to be stored efficiently using the memory area to be the restart area, thereby preventing an increase in the storage capacity of the game program area. In addition, the special memory areas to which special addresses are assigned in the restart area include multiple areas to which discontinuous addresses are assigned, while the special memory areas to which special addresses are assigned in the area storing the table data included in the interrupt vector table XTBL_INTR include a single area to which consecutive addresses are assigned. In this case, the possibility of distinguishing between the unused area and the special memory areas in the restart area is higher than the possibility of distinguishing between the unused area and the special memory areas in the address memory area, and appropriate management of the memory areas is possible to reliably prevent misidentification of the special memory areas in the restart area.

Depending on the configuration of the program modules and table data stored in the restart area, the restart area may not have a special memory area in which a special address is assigned and unused data indicating 0 is stored. Also, depending on the configuration of the interrupt program corresponding to multiple interrupt causes, the area storing table data included in the interrupt vector table XTBL_INTR may not have a special memory area in which a special address is assigned and unused data indicating 0 is stored. In this way, depending on the specifications of the pachinko gaming machine 1, the special memory area may not include an area in which unused data is stored in the area from one specific address to the next specific address included in the multiple specific addresses. Also, depending on the specifications of the pachinko gaming machine 1, the special memory area may not include an area in which unused data is stored in the address memory area.

The zero data with a storage value of 00 [H] in the game program area is not limited to unused data not used in the execution of the program, but may also include data used in the execution of the program. For example, when the interrupt vector table upper address is set by step AKS8 of the power supply start response processing P_POWER_ON, the upper byte of the interrupt vector table address is directly specified by the operand in the transfer command for setting the internal register of the CPU 103. Since the upper byte of the interrupt vector table address is 00 [H], zero data with a storage value of 00 [H] is stored in the game program area as data used to set the interrupt vector table upper address. Also, for example, when the access permission output value is stored in the RWM access protection register by step AKS14 of the power supply start response processing P_POWER_ON, the address of the RWM access protection register is directly specified by the operand in the transfer command for setting the internal register of the CPU 103. The RWM access protection register is located at the beginning of the function control register area, such as setting example AKA02, and is assigned the address FF00 [H]. Therefore, zero data with a storage value of 00 [H] is stored in the game program area as the data used to specify the lower byte of the address of the RWM access protection register.

For example, when backup monitoring timer clear data is stored by step AKS34 of power-off processing P_POWER_OFF, zero data indicating 00 [H] is directly specified by the operand as the clear data in a transfer command that can update the stored data at the address pointed to by the pointer. Therefore, zero data with a storage value of 00 [H] is stored in the game program area as the data used to store the clear data in the backup monitoring timer. For example, when clear data is stored in the RWM access protection register by step AKS42 of power-off processing P_POWER_OFF, the address of the RWM access protection register is directly specified by the operand in the transfer command. Therefore, zero data with a storage value of 00 [H] is stored in the game program area as the data used to specify the lower byte of the address of the RWM access protection register. Furthermore, in the power failure recovery vector table such as the setting example AKT11, the table data of addresses 0016 [H] and 0017 [H] is used to specify address 0000 [H], which is the start address for the main processing P_MAIN for game control. The power failure recovery vector table is used to set the stored value of the program counter when an interrupt return command is executed after the address is set in the stack pointer by step AKS50 of the power failure processing P_POWER_OFF. In this way, the table data included in the power failure recovery vector table is used as address designation data that makes the main processing P_MAIN for game control, which is the startup processing based on the startup of the pachinko gaming machine 1, executable from the beginning. Therefore, zero data with a storage value of 00 [H] is stored in the game program area as address designation data that makes the startup processing executable from the beginning.

In this way, the game program area includes an area in which usage data indicating 0 is stored. In the game program area, the area in which usage data indicating 0 is stored may correspond to a predetermined memory area to which a predetermined address is assigned. In this case, the total storage capacity of the predetermined memory area only needs to be smaller than the total storage capacity of the unused area corresponding to the unused memory area capable of storing unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area. The total storage capacity of the special memory area and the predetermined memory area only needs to be smaller than the total storage capacity of the unused area corresponding to the unused memory area capable of storing unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area.

The predetermined memory area to which a predetermined address is assigned in the gaming program area may include a plurality of areas to which discontinuous addresses are assigned. For example, the addresses 0016[H] and 0017[H] of the table data included in the power interruption recovery vector table such as setting example AKT11, the address storing the usage data used in step AKS34 of the power interruption processing P_POWER_OFF, and the address storing the usage data used in address AKS42 of the power interruption processing P_POWER_OFF may each be set to be discontinuous addresses. In this case, the usage data stored in the predetermined memory area includes address designation data that enables start-up processing based on the start-up of the gaming machine to be executed from the beginning, such as the table data included in the power interruption recovery vector table such as setting example AKT11.

The usage data stored in the specified memory area may include address designation data capable of designating any address, such as the upper byte, lower byte, or both the upper byte and lower byte of an address assigned to any memory area in the ROM 101, RAM 102, or the built-in register of the game control microcomputer 100. The usage data stored in the specified memory area may include stored value setting data that can be used when setting a stored value in any register, counter, timer, or other memory area. Usage data indicating 0 that can be used when setting a stored value in a register is also called register initial setting data. Usage data indicating 0 that can be used when setting a stored value in a counter is also called counter initial setting data. Usage data indicating 0 that can be used when setting a stored value in a timer is also called timer initial setting data.

Depending on the configuration of the programs and table data stored in the game program area, the game program area may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. Also, depending on the configuration of the programs and table data stored in the game program area, for example, the area in which the table data of the vector table at the time of power outage recovery is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. In addition, the area in which any address designation data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. The area in which the register initial setting data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. The area in which the counter initial setting data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. The area in which the timer initial setting data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. In this way, depending on the specifications of the pachinko game machine 1, the game program area corresponding to the first memory area may not include a normal memory area in which a predetermined address is assigned and usage data indicating 0 is stored. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the specified memory area may not include address designation data that enables startup processing based on startup of the gaming machine to be executed from the beginning. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the specified memory area may not include address designation data that can designate an arbitrary address. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the specified memory area may not include setting data that can set a storage value in an arbitrary memory area.

Figure 11-6 shows a setting example 003AKA11 of zero data that becomes unused data or used data in the game data area included in the memory area of ROM 101. Zero data with a storage value of 00 [H] in the game data area may become used data used to execute a program, or unused data not used to execute a program. The stored data in the game data area can constitute table data included in various tables. In setting example 003AKA11, the table data start address is the start address of the table data included in the various tables. The table data end address is the end address of the table data included in the various tables. The zero data amount is the number of bytes that is the storage capacity of the area in which the zero data that becomes unused data or used data is stored. Therefore, the table data start address is the start address of data that can be used to execute a program, and the table data end address is the end address of data that can be used to execute a program. However, the data that can be used to execute a program may include data that is not used to execute a program, depending on various instructions and settings in the implemented program.

In the game data area included in the memory area of ROM 101, the area from address 1200[H] to 121D[H] stores the table data included in each table, which corresponds to the display device control table XD_DG, the first special symbol display control table XD_TOKUZU1, the second special symbol display control table XD_TOKUZU2, the first special symbol buffer shift control table XD_TBUFSHIFT1, the second special symbol buffer shift control table XD_TBUFSHIFT2, and the normal symbol stop display table XD_FZU_STOP. The area from address 121E[H] to 1227[H] stores the table data included in the normal reserved memory count display table XD_FMEM. The area from address 1228[H] to 1231[H] stores the table data included in the first reserved memory count display table XD_TMEM1. The area from addresses 1232[H] to 123B[H] stores table data contained in the second reserved memory count display table XD_TMEM2. The area from addresses 123C[H] to 1247[H] stores table data contained in the variable pattern command distribution selection table XP_TPAT_TBL. The area from addresses 1248[H] to 1250[H] stores table data contained in the right-hit round count display table XD_TOKU1. The area from addresses 1251[H] to 1258[H] stores table data contained in the solenoid pattern distribution selection table XP_YSOL_SEL.

In the game data area, the area where table data included in various tables is stored may store zero data with a storage value of 00 [H] as used data indicating 0. In addition, in the game data area, the area where table data included in various tables is stored may store zero data with a storage value of 00 [H] as unused data indicating 0.

Figure 11-7 shows an example of table data storage included in various tables. The regular map reserved memory number display table XD_FMEM shown in Figure 11-7 (A) has a table data start address of 121E [H] and a table data end address of 1227 [H]. The regular map reserved memory number display table XD_FMEM is used to execute a program that controls the display of the regular map reserved memory number on the regular map reserved display 25C, and contains table data that becomes display data corresponding to regular map reserved memory numbers of "0" to "4". The first reserved memory number display table XD_TMEM1 shown in Figure 11-7 (B) has a table data start address of 1228 [H] and a table data end address of 1231 [H]. The first reserved memory number display table XD_TMEM1 is used to execute a program that controls the display of the first reserved memory number on the first reserved display 25A, and contains table data that becomes display data corresponding to the first reserved memory number of "0" to "4". The right-hit round count display table XD_TOKU1 shown in FIG. 11-7 (C) has a table data start address of 1248 [H] and a table data end address of 1250 [H]. The right-hit round count display table XD_TOKU1 is used to execute a program that controls the display by the light-emitting member that serves as the right-hit indicator and the light-emitting member that serves as the round count indicator, and contains table data that serves as display data corresponding to the jackpot game state and the number of rounds.

The stored data at addresses 121E[H] and 121F[H] shown in FIG. 11-7(A) are the first and second bytes of display data used in response to a normal map reserved memory count of "0". All of these stored data are a total of two bytes of zero data with a stored value of 00[H]. The stored data at addresses 1220[H] and 1221[H] are the first and second bytes of display data used in response to a normal map reserved memory count of "1". Of these, the stored data at address 1221[H] is one byte of zero data with a stored value of 00[H]. The stored data at addresses 1222[H] and 1223[H] are the first and second bytes of display data used in response to a normal map reserved memory count of "2". Of these, the stored data at address 1223[H] is one byte of zero data with a stored value of 00[H]. The stored data at addresses 1224 [H] and 1225 [H] are the first and second bytes of the display data used in response to the general map reserved memory number "3". All of these stored data are non-zero data with a stored value other than 00 [H]. The stored data at addresses 1226 [H] and 1227 [H] are the first and second bytes of the display data used in response to the general map reserved memory number "4". All of these stored data are non-zero data with a stored value other than 00 [H].

The regular map reserved display 25C may be configured using light-emitting bodies such as two LEDs, and may include a first light-emitting unit capable of changing its light-emitting state in response to the first byte of the display data read from the regular map reserved memory count display table XD_FMEM, and a second light-emitting unit capable of changing its light-emitting state in response to the second byte of the display data read from the regular map reserved memory count display table XD_FMEM. The regular map reserved display 25C may display the regular map reserved memory count in a recognizable manner based on the light-emitting states of the first light-emitting unit and the second light-emitting unit. The first light-emitting unit and the second light-emitting unit of such a regular map reserved display 25C may correspond to a light-emitting means. For example, the first light-emitting unit of the regular map reserved display 25C may be turned off when the first byte corresponds to 00 [H], turned on when the first byte corresponds to 20 [H], and flashed when the first byte corresponds to 24 [H] in the display data read from the regular map reserved memory count display table XD_FMEM. In addition, the second light-emitting part of the regular map reservation display 25C may be turned off when the second byte corresponds to 00 [H], turned on when the second byte corresponds to 20 [H], and blinked when the second byte corresponds to 24 [H] in the display data read from the regular map reservation memory number display table XD_FMEM. In the regular map reservation memory number display table XD_FMEM, the table data at addresses 121E [H], 121F [H], 1221 [H], and 1223 [H] is usage data used to execute the program, but is zero data with a storage value of 00 [H]. Therefore, the areas of addresses 121E [H], 121F [H], 1221 [H], and 1223 [H] are included in the regular memory area in which usage data indicating 0 is stored in the regular address. In this case, the usage data stored in the regular memory area includes turn-off control data that can be used to turn off the light-emitting means.

The stored data at addresses 1228[H] and 1229[H] shown in FIG. 11-7(B) are the first and second bytes of display data used in response to the first pending memory number "0". All of these stored data are a total of two bytes of zero data with a stored value of 00[H]. The stored data at addresses 122A[H] and 122B[H] are the first and second bytes of display data used in response to the first pending memory number "1". Of these, the stored data at address 122B[H] is one byte of zero data with a stored value of 00[H]. The stored data at addresses 122C[H] and 122D[H] are the first and second bytes of display data used in response to the first pending memory number "2". Of these, the stored data at address 122D[H] is one byte of zero data with a stored value of 00[H]. The stored data at addresses 122E[H] and 122F[H] are the first and second bytes of display data used in response to the first reserved memory number "3". All of these stored data are non-zero data with a stored value other than 00[H]. The stored data at addresses 1230[H] and 1231[H] are the first and second bytes of display data used in response to the first reserved memory number "4". All of these stored data are non-zero data with a stored value other than 00[H].

The first hold display 25A may be configured using light-emitting bodies such as two LEDs, and may include a first light-emitting unit capable of changing its light-emitting state in response to the first byte of the display data read from the first hold memory number display table XD_TMEM1, and a second light-emitting unit capable of changing its light-emitting state in response to the second byte of the display data read from the first hold memory number display table XD_TMEM1. The first hold display 25A may display the first hold memory number in a recognizable manner by the light-emitting states of the first light-emitting unit and the second light-emitting unit. Such a first light-emitting unit and second light-emitting unit of the first hold display 25A may correspond to a light-emitting means. For example, the first light-emitting unit of the first hold display 25A may be turned off when the first byte corresponds to 00 [H], turned on when the first byte corresponds to 80 [H], and flashed when the first byte corresponds to 90 [H] in the display data read from the first hold memory number display table XD_TMEM1. In addition, the second light-emitting unit of the first reserved display 25A may be turned off when the second byte corresponds to 00 [H], turned on when the second byte corresponds to 80 [H], and blinked when the second byte corresponds to 90 [H] in the display data read from the first reserved memory number display table XD_TMEM1. In the first reserved memory number display table XD_TMEM1, the table data at addresses 1228 [H], 1229 [H], 122B [H], and 122D [H] is usage data used to execute the program, but is zero data with a storage value of 00 [H]. Therefore, the areas of addresses 1228 [H], 1229 [H], 122B [H], and 122D [H] are included in the normal storage area in which usage data indicating 0 is stored in the normal address. In this case, the usage data stored in the normal storage area includes turn-off control data that can be used to turn off the light-emitting means.

The stored data at address 1248[H] shown in FIG. 11-7(C) is display data used for two rounds of round number "2" in a jackpot gaming state. The stored data at address 1249[H] is display data used for three rounds of round number "3" in a jackpot gaming state. The stored data at address 124A[H] is display data used for four rounds of round number "4" in a jackpot gaming state. These stored data are non-zero data with stored values other than 00[H]. The stored data at address 124B[H] is display data corresponding to five rounds of round number "5" in a jackpot gaming state. The stored data at address 124C[H] is display data corresponding to six rounds of round number "6" in a jackpot gaming state. When the number of rounds in the jackpot gaming state is not set to "5" or "6" due to the specifications of the pachinko gaming machine 1, the table data at addresses 124B[H] and 124C[H] becomes unused data. Thus, the areas of addresses 124B[H] and 124C[H] are areas in which unused data is stored, unlike areas in which data used by the CPU 103 to execute a program can be stored. The stored data at address 124D[H] is display data used for 7 rounds of the round number "7" in the jackpot gaming state. The stored data at address 124E[H] is display data corresponding to 8 rounds of the round number "8" in the jackpot gaming state. The stored data at address 124F[H] is display data corresponding to 9 rounds of the round number "9" in the jackpot gaming state. When the number of rounds in the jackpot gaming state is not set to "8" or "9" due to the specifications of the pachinko gaming machine 1, the table data at addresses 124E[H] and 124F[H] becomes unused data. Thus, the areas at addresses 124E[H] and 124F[H] are areas in which unused data is stored, unlike areas in which the CPU 103 can store data used to execute a program. The data stored at address 1250[H] is display data used for 10 rounds when the round count is "10" in a jackpot game state.

The light-emitting member serving as the right-hit indicator or the light-emitting member serving as the round number indicator may include one or more light-emitting parts whose light-emitting state can be changed in response to the display data read from the right-hit round number display table XD_TOKU1. The light-emitting member serving as the right-hit indicator or the round number indicator may display the right-hit notification or the round number corresponding to the jackpot game state in a recognizable manner depending on the light-emitting state of the light-emitting part. Such a light-emitting member serving as the right-hit indicator or the light-emitting member serving as the round number indicator may correspond to a light-emitting means. In the right-hit round number display table XD_TOKU1, the table data at addresses 124B[H], 124C[H], 124E[H], and 124F[H] is unused data that is not used in the execution of the program, and is zero data with a storage value of 00[H]. Therefore, the areas of addresses 124B[H], 124C[H], 124E[H], and 124F[H] are included in a special storage area in which unused data indicating 0 is stored in a special address. In this case, the unused data stored in the special memory area includes state-related data corresponding to a number of rounds that is different from the number of rounds that can be executed in an advantageous state that is favorable to the player, such as a jackpot game state.

As shown in FIG. 11-6, the second reserved memory count display table XD_TMEM2 has address 1232[H] as the table data start address and address 123B[H] as the table data end address. The area from address 1232[H] to 123B[H] contains a normal memory area where 4 bytes of zero data with a storage value of 00[H] are stored and where usage data indicating 0 is stored at a normal address. The variable pattern command allocation selection table XP_TPAT_TBL has address 123C[H] as the table data start address and address 1247[H] as the table data end address. The area from address 123C[H] to 1247[H] contains a normal memory area where 1 byte of zero data with a storage value of 00[H] is stored and where usage data indicating 0 is stored at a normal address. In the solenoid pattern allocation selection table XP_YSOL_SEL, address 1251 [H] is the table data start address, and address 1258 [H] is the table data end address. The area from address 1251 [H] to 1258 [H] stores 2 bytes of zero data with a storage value of 00 [H], and includes a normal storage area in which use data indicating 0 is stored at a normal address.

In this way, the game data area includes a normal memory area in which zero data with a storage value of 00 [H] is stored and in which usage data indicating 0 is stored at a normal address, and a special memory area in which unused data indicating 0 is stored at a special address. Furthermore, the usage data stored in the normal memory area includes turn-off control data that can be used to turn off the light-emitting means. The unused data stored in the special memory area includes state-related data corresponding to a number of rounds that is different from the number of rounds that can be executed in an advantageous state that is advantageous to the player.

In this case, the game data area includes a normal memory area in which 216 bytes of zero data are stored as use data, and a special memory area in which 19 bytes of zero data are stored as unused data. The normal memory area in which zero data with a storage value of 00 [H] is stored in the game data area and use data indicating 0 is stored in the normal address includes a plurality of areas to which discontinuous addresses are assigned. The special memory area in which zero data with a storage value of 00 [H] is stored in the game data area and unused data indicating 0 is stored in the special address includes a plurality of areas to which discontinuous addresses are assigned. The normal memory area in which zero data with a storage value of 00 [H] is stored in the game data area and use data indicating 0 is stored in the normal address is assigned a normal address so that there are no consecutive areas of a specific number of bytes or more, such as 16 bytes. The special memory area in which zero data with a storage value of 00 [H] is stored in the game data area and unused data indicating 0 is stored in the special address is assigned a special address so that there are no consecutive areas of a specific number of bytes or more, such as 16 bytes.

The usage data indicating 0 stored in the normal memory area may include table selection data that can be used as an offset value for setting a reference table address when selecting a table using various specified values or random number values. The usage data indicating 0 stored in the normal memory area may include fluctuation pattern determination data that can be used as an offset value for setting a reference fluctuation pattern when determining a fluctuation pattern using various specified values or random number values. In addition, the usage data indicating 0 stored in the normal memory area may include determination value setting data that can be used to set a reference determination value when determining a control mode using various specified values or random number values.

Thus, the game data area includes an area in which use data indicating 0 is stored and an area in which unused data indicating 0 is stored. In the game data area, the area in which use data indicating 0 is stored may correspond to a normal storage area to which a normal address is assigned. In the game data area, the area in which unused data indicating 0 is stored may correspond to a special storage area to which a special address is assigned. The total storage capacity of the normal storage area in which a normal address is assigned in the game data area and use data indicating 0 is stored is 216 bytes. The total storage capacity of the special storage area in which a special address is assigned in the game data area and unused data indicating 0 is stored is 19 bytes. The total storage capacity of the unused area that becomes the unused storage area between the game program area corresponding to the first storage area and the game data area corresponding to the second storage area is 1069 bytes. The total storage capacity of the unused area that becomes the unused storage area between the game data area corresponding to the second storage area and the non-game program area and non-game data area corresponding to the third storage area is 1228 bytes. Therefore, the total storage capacity of the normal storage area, 216 bytes, is smaller than the total storage capacity of the unused storage area, 2297 bytes. Also, the total storage capacity of the normal storage area and the special storage area, 235 bytes, is smaller than the total storage capacity of the unused storage area, 2297 bytes. This increases the possibility of distinguishing between the unused area and the normal storage area, and enables appropriate management of the storage area to prevent misidentification. Also, it increases the possibility of distinguishing between the unused area and the normal storage area and the special storage area, and enables appropriate management of the storage area to prevent misidentification.

The normal memory area to which normal addresses are assigned in the game data area includes multiple areas to which discontinuous addresses are assigned. For example, the areas of addresses 121E[H], 121F[H], 1221[H], and 1223[H] shown in FIG. 11-7(A) and the areas of addresses 1228[H], 1229[H], 122B[H], and 122D[H] shown in FIG. 11-7(B) are all included in the normal memory area and can correspond to multiple areas to which discontinuous addresses are assigned. In addition, in the area from address 1232[H], which is the table data start address in which the table data of the second reserved memory number display table XD_TMEM2 is stored, to address 123B[H], which is the table data end address, the area in which 4 bytes of zero data are stored as usage data is included in the normal memory area and can be included in multiple areas to which addresses that are discontinuous from other normal memory areas provided in the game data area are assigned. In the area from address 123C [H], which is the table data start address, to address 1247 [H], which is the table data end address, in which the table data of the variable pattern command allocation selection table XP_TPAT_TBL is stored, the area in which 1 byte of zero data is stored as use data is included in the normal storage area, and can be included in a plurality of areas to which addresses that are discontinuous with other normal storage areas provided in the game data area are assigned. In the area from address 1251 [H], which is the table data start address, to address 1258 [H], which is the table data end address, in which the table data of the solenoid pattern allocation selection table XP_YSOL_SEL is stored, the area in which 2 bytes of zero data is stored as use data is included in the normal storage area, and can be included in a plurality of areas to which addresses that are discontinuous with other normal storage areas provided in the game data area are assigned. Therefore, the normal storage area in which normal addresses are assigned in the game data area and use data indicating 0 is stored includes a plurality of areas to which discontinuous addresses are assigned as normal addresses. This increases the likelihood of distinguishing between unused and normal storage areas, and enables proper management of storage areas to prevent misidentification of the two.

The special memory area to which a special address is assigned in the game data area includes multiple areas to which discontinuous addresses are assigned. For example, the areas of addresses 124B[H], 124C[H], 124E[H], and 124F[H] shown in FIG. 11-7(C) are all included in the special memory area and may correspond to multiple areas to which discontinuous addresses are assigned. In addition, in an area in which table data included in an arbitrary table is stored, an area in which zero data is stored as unused data may be included in the special memory area and may be included in multiple areas to which addresses that are discontinuous with other special memory areas provided in the game data area are assigned. Therefore, the special memory area in which a special address is assigned in the game data area and unused data indicating 0 is stored includes multiple areas to which discontinuous addresses are assigned as special addresses. This increases the possibility of distinguishing between the unused area, the normal memory area, and the special memory area, and enables appropriate management of the memory area to prevent misidentification of them.

Depending on the configuration of the table data stored in the game data area, the game data area may not have a normal memory area in which a normal address is assigned and usage data indicating 0 is stored. Also, depending on the configuration of the table data stored in the game data area, the game data area may not have a special memory area in which a special address is assigned and unused data indicating 0 is stored. In this way, depending on the specifications of the pachinko game machine 1, the game data area corresponding to the second memory area may not include a normal memory area in which a normal address is assigned and usage data indicating 0 is stored. Also, depending on the specifications of the pachinko game machine 1, the game data area corresponding to the second memory area may not include a special memory area in which a special address is assigned and unused data indicating 0 is stored.

Depending on the configuration of the table data stored in the game data area, for example, the area in which the table data of the normal reserved memory number display table XD_FMEM or the first reserved memory number display table XD_TMEM1 is stored may not have a normal memory area in which a normal address is assigned and used data indicating 0 is stored. Also, for example, the area in which the table data of the right-hit round number display table XD_TOKU1 is stored may not have a special memory area in which a special address is assigned and unused data indicating 0 is stored. In this way, depending on the specifications of the pachinko game machine 1, the used data stored in the normal memory area may not include turn-off control data that can be used to turn off the light-emitting means. Also, depending on the specifications of the pachinko game machine 1, the unused data stored in the special memory area may not include state-related data corresponding to a round number different from the number of rounds that can be executed in an advantageous state that is advantageous to the player.

Figure 11-8 shows an example of dump list output 003AKB01. The dump list is an output of the storage contents of each area to which an address is assigned in the address map, and can be displayed using any display device or printed using any printing device. The storage contents of the memory area of the ROM 101, etc. are output in units of a specified data size, for example 16 bytes, by the dump list. In the dump list of output example 003AKB01, the multiple display rows representing the horizontal arrangement each correspond to different upper bytes of the addresses in the address map. In the dump list of output example 003AKB01, the multiple display columns representing the vertical arrangement each correspond to different lower bytes of the addresses in the address map. In this way, when the dump list is output in correspondence with the upper and lower bytes of the addresses, the unit size of the programs and data that can be displayed in one display row is 16 bytes.

In this case, the unused areas capable of storing unused data between the game program area and the game data area, between the game data area and the non-game program area and the non-game data area, etc., have a total storage capacity greater than a specific number of bytes, and all zero data with a storage value of 00 [H] is stored as unused data indicating 0. In a dump list such as output example 003AKB01, the total storage capacity of the unused areas is greater than a specific number of bytes, so that zero data with a storage value of 00 [H] is displayed continuously across multiple display lines, making it easy to identify the unused areas. On the other hand, if consecutive addresses are assigned to areas in the game program area or game data area where zero data with a storage value of 00 [H] is stored, it may be difficult to distinguish the unused areas from the areas in the dump list because they are displayed consecutively. Therefore, addresses are assigned to areas in the game program area or game data area where zero data with a storage value of 00 [H] is stored so that there are no consecutive areas with a specific number of bytes or more.

The game program area includes a special memory area in which unused data indicating 0 is stored at a special address. In this special memory area, the portion to which consecutive addresses are assigned is a maximum of 12 bytes from addresses 0062 [H] to 006D [H] in the area that stores the table data included in the interrupt vector table XTBL_INTR. In this way, the special memory area is assigned special addresses so that there are no consecutive areas of 16 bytes or more, which is the specific number of bytes. This makes it easy to distinguish between unused areas and special memory areas, and enables appropriate management of memory areas to prevent misidentification of the two.

The game program area includes a specified memory area in which usage data indicating 0 is stored at a specified address. In this specified memory area, the portion to which consecutive addresses are assigned may be, for example, a 2-byte area at addresses 0016[H] and 0017[H] that stores table data included in the vector table at the time of power recovery from a power outage. In this way, the specified memory area is assigned specified addresses such that there are no consecutive areas of a specific number of bytes, 16 bytes or more. This makes it possible to easily distinguish between unused areas and specified memory areas, and enables appropriate management of memory areas to prevent misidentification of the two.

The game data area includes a normal memory area in which use data indicating 0 is stored at a normal address. In this normal memory area, the portion to which consecutive addresses are assigned may be, for example, a 2-byte area of addresses 121E[H] and 121F[H] in the area that stores table data included in the normal reserved memory count display table XD_FMEM, or a 2-byte area of addresses 1228[H] and 1229[H] in the area that stores table data included in the first reserved memory count display table XD_TMEM1. In this way, normal addresses are assigned to the normal memory area so that there are no consecutive areas of 16 bytes or more, which is a specific number of bytes. This makes it easy to distinguish between unused areas and normal memory areas, and enables appropriate management of memory areas to prevent misidentification.

The game data area includes a special memory area in which unused data indicating 0 is stored at a special address. In this special memory area, the portion to which consecutive addresses are assigned may be, for example, a 2-byte area of addresses 124B[H] and 124C[H] or a 2-byte area of addresses 124E[H] and 124F[H] in the area that stores table data included in the right-hit round count display table XD_TOKU1. In this way, the special memory area is assigned specific addresses so that there are no consecutive areas of 16 bytes or more, which is the specific number of bytes. This makes it easy to distinguish between unused areas and special memory areas, and enables appropriate management of memory areas to prevent misidentification of them.

The game data area is composed of a normal memory area in which used data indicating 0 is stored at a normal address, and a special memory area in which unused data indicating 0 is stored at a special address. Therefore, depending on the arrangement of the normal memory area and the special memory area, it may be difficult to distinguish between the game data area and the adjacent unused area. Therefore, the game data area stores data indicating values other than 0 at the start address and end address. For example, since the game data area is an area from address 1200[H] to 1D33[H], non-zero data with a storage value other than 00[H] is stored at the start address 1200[H], and non-zero data with a storage value other than 00[H] is stored at the end address 1D33[H]. In a dump list such as output example 003AKB01, the storage value at address 1200[H], which is the start address of the game data area, is set to 08[H] other than 00[H], and the storage value at address 1D33[H], which is the end address of the game data area, is set to 02[H] other than 00[H], so that data other than 0 is stored. This makes it easy to distinguish between the unused areas located before and after the game data area and the game data area, and enables appropriate management of the storage area to prevent misidentification of them.

Furthermore, in the game data area, data other than 0 is stored in the address next to the start address and the address before the end address. For example, the start address of the game data area is address 1200 [H], so non-zero data with a storage value other than 00 [H] is stored in the next address 1201 [H]. Also, the end address of the game data area is 1D33 [H], so non-zero data with a storage value other than 00 [H] is stored in the previous address 1D32 [H]. In a dump list such as output example 003AKB01, the start address of the game data area is 1200 [H], the next address 1201 [H] has a storage value of 10 [H] other than 00 [H], the end address of the game data area is 1D33 [H], and the previous address 1D32 [H] has a storage value of 2B [H] other than 00 [H], so that data other than 0 is stored. In this way, the game data area stores data other than 0 in a continuous 2-byte area after the starting address (including the starting address) and in a continuous 2-byte area before the end address (including the end address). This makes it easier to distinguish between the unused areas located before and after the game data area and the game data area, and enables appropriate management of the memory area to reliably prevent misidentification of them.

It is not limited to a continuous 2-byte area, and data other than 0 may be stored in correspondence with an area to which multiple consecutive addresses are assigned after a start address including the start address of the game data area, and an area to which multiple consecutive addresses are assigned before an end address including the end address of the game data area. For example, a non-zero range including multiple addresses may be set in advance, and data other than 0 may be stored in correspondence with an area of the non-zero range after a start address including the start address of the game data area, and an area of the non-zero range before an end address including the end address of the game data area. In this case, the non-zero range set in correspondence with the start address of the game data area and the non-zero range set in correspondence with the end address of the game data area may have address ranges of different sizes. For example, as a non-zero range including multiple addresses, a post-start non-zero range and a pre-end non-zero range having an address range of a size different from the post-start non-zero range are set in advance. Then, data other than 0 may be stored in correspondence with an area of the post-start non-zero range after a start address including the start address of the game data area, and an area of the pre-end non-zero range before an end address including the end address of the game data area. As with the game data area, any memory area other than the unused area in the memory area of ROM 101, such as the game program area, non-game program area, and non-game data area, may store program code or data indicating a value other than 0 in a non-zero range area provided corresponding to the start address and end address. However, for example, like the program management area, there may be a memory area in which zero data with a storage value of 00 [H] is stored in a zero setting range area before the end address including the end address, corresponding to the settings based on the specifications of the pachinko gaming machine 1.

The total storage capacity of the first storage area, the total storage capacity of the second storage area, the total storage capacity of the unused storage area, the total storage capacity of the special storage area, the total storage capacity of the normal storage area, and the total storage capacity of the normal storage area and the special storage area can be changed arbitrarily in accordance with the specifications of the pachinko game machine 1. However, the total storage capacity of the first storage area only needs to be larger than the total storage capacity of the unused storage area capable of storing unused data between the first storage area and the second storage area. The total storage capacity of the special storage area only needs to be smaller than the total storage capacity of the unused storage area capable of storing unused data between the first storage area and the second storage area, and between the second storage area and the third storage area. The total storage capacity of the normal storage area only needs to be smaller than the total storage capacity of the unused storage area capable of storing unused data between the first storage area and the second storage area, and between the second storage area and the third storage area. The total storage capacity of the normal storage area and the special storage area needs only to be smaller than the total storage capacity of the unused storage areas capable of storing unused data between the first storage area and the second storage area, and between the second storage area and the third storage area.

The special memory area, the specified memory area, the normal memory area, and the special memory area may be assigned addresses so that there are no consecutive areas of any particular number of bytes or more, not limited to 16 bytes. For example, the particular number of bytes may be a number of bytes other than 16 bytes, such as 8 bytes, 32 bytes, or 64 bytes. The special memory area, the specified memory area, the normal memory area, and the special memory area may be assigned addresses so that there are no consecutive areas of any particular number of bytes or more, which can be easily recognized as a memory area different from an unused memory area, for example, when a dump list is displayed.

(Means for solving the problem and effects of characteristic part 003AK)
[1-1] A gaming machine capable of playing a game,
A storage means capable of storing a program;
A control means for controlling the progress of a game by a program stored in the storage means,
The storage means is
A first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
an unused storage area capable of storing unused data between the first storage area and the second storage area;
The unused memory area stores unused data that indicates all 0.
The total storage capacity of the first storage area is greater than the total storage capacity of the unused storage area,
the first storage area includes a special storage area in which unused data indicating 0 is stored at a special address;
The total storage capacity of the special storage areas is smaller than the total storage capacity of the unused storage areas,
The special storage area includes a plurality of areas to which discontinuous addresses are assigned as special addresses.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The unused storage area may be, for example, an unused area at addresses 0BD3 [H] to 11FF [H]. The total storage capacity of the first storage area may be, for example, 3027 bytes. The total storage capacity of the unused storage area may be, for example, 1069 bytes. The special storage area may be, for example, a storage area of unused data in setting example 003AKA01. The total storage capacity of the special storage area may be, for example, 19 bytes. The discontinuous addresses may be, for example, storage addresses of unused data in setting example 003AKA01.
According to such a configuration, discontinuous addresses are assigned as special addresses in which unused data is stored in the special storage area, and since the special storage area has a smaller total storage capacity than the unused storage area, appropriate management of the storage area is possible to prevent the special storage area from being mistaken for an unused storage area.

[1-2] The special memory area may be assigned special addresses so that no area of a specific number of bytes or more is consecutive.
Here, the specific number of bytes may be, for example, 16 bytes.
In such a configuration, when the dump list is displayed, it is possible to appropriately manage the storage area so that the special storage area can be prevented from being mistaken for an unused storage area.

[1-3] The control means is
a first call instruction for calling a program stored at a specified address by specifying the address;
a second call instruction for calling a program stored in a specific address corresponding to the specified parameter among a plurality of specific addresses allocated at predetermined intervals by specifying a parameter having a data amount smaller than that of the address;
The special storage area may include an area in which unused data is stored, from one specific address to the next specific address included in the plurality of specific addresses.
Here, the first call command may be, for example, a CALL command, the second call command may be, for example, a RST command, and the specific address may be, for example, a restart address.
In such a configuration, unused data is stored so as to prevent the special storage area from being mistaken for an unused storage area, thereby enabling appropriate management of storage areas.

[1-4] The storage means includes an address storage area capable of storing an address of an interrupt processing program,
The special storage area may include an area in the address storage area where unused data is stored.
Here, the interrupt processing program may be, for example, a program that is a timer interrupt processing P_PCT for game control. The address storage area may be, for example, an area of addresses 0060[H] to 006D[H] that stores table data included in the interrupt vector table XTBL_INTR. The area in the address storage area where unused data is stored may be, for example, an area of addresses 0062[H] to 006D[H].
In such a configuration, unused data is stored so as to prevent the special storage area from being mistaken for an unused storage area, thereby enabling appropriate management of storage areas.

[1-5] The first storage area includes a predetermined storage area in which usage data indicating 0 is stored at a predetermined address,
The predetermined storage area may include a plurality of areas to which discontinuous addresses are assigned as the predetermined addresses.
Here, the specified address may be, for example, addresses 0016[H], 0017[H] of table data included in the vector table at the time of power failure recovery, an address where usage data used in step AKS34 of the power failure processing P_POWER_OFF is stored, or an address where usage data used in step AKS42 of the power failure processing P_POWER_OFF is stored.
In such a configuration, usage data indicating 0 is stored so as to prevent a specific storage area from being mistaken for an unused storage area, thereby enabling appropriate management of the storage area.

[1-6] The usage data stored in the specified memory area may include address designation data that enables start-up processing based on the start-up of the gaming machine to be executed from the beginning.
Here, the startup process may be, for example, a main process P_MAIN for game control, etc. The address designation data may be, for example, zero data with a stored value of 00 [H] in a vector table at the time of power failure recovery, etc.
In such a configuration, usage data indicating 0 is stored so as to prevent a specific storage area from being mistaken for an unused storage area, thereby enabling appropriate management of the storage area.

[2-1] A gaming machine capable of playing a game,
A storage means capable of storing a program;
A control means for controlling the progress of a game by a program stored in the storage means,
The storage means is
A first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, the unused storage area being capable of storing unused data;
The unused memory area stores unused data that indicates all 0.
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
the second storage area includes a normal storage area in which use data indicating 0 is stored at a normal address;
The total storage capacity of the normal storage area is smaller than the total storage capacity of the unused storage area.
The normal storage area may include a plurality of areas to which discontinuous addresses are assigned as normal addresses.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a gaming program area. The second storage area may be, for example, a gaming data area. The third storage area may be, for example, a non-gaming program area and a non-gaming data area. The unused storage area may be, for example, an unused area of addresses 0BD3 [H] to 11FF [H] and an unused area of addresses 1D34 [H] to 1FFF [H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of the unused storage area may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area of zero data that is used data in the setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes. The discontinuous addresses may be, for example, storage addresses of zero data that is used data in the setting example 003AKA01.
According to such a configuration, discontinuous addresses are assigned as normal addresses where usage data is stored in the normal storage area, and since the normal storage area has a smaller total storage capacity than the unused storage area, appropriate management of the storage area is possible to prevent the normal storage area from being mistaken for an unused storage area.

[2-2] A gaming machine capable of playing a game,
A storage means capable of storing a program;
A control means for controlling the progress of a game by a program stored in the storage means,
The storage means is
A first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, the unused storage area being capable of storing unused data;
The unused memory area stores unused data that indicates all 0.
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
The second storage area is
a normal storage area in which use data indicating 0 is stored at a normal address;
a special storage area in which unused data indicating 0 is stored at a special address;
The total storage capacity of the normal storage area and the special storage area is smaller than the total storage capacity of the unused storage area,
The normal storage area includes a plurality of areas to which discontinuous addresses are assigned as normal addresses,
The special storage area may include a plurality of areas to which discontinuous addresses are assigned as special addresses.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a gaming program area. The second storage area may be, for example, a gaming data area. The third storage area may be, for example, a non-gaming program area and a non-gaming data area. The unused storage area may be, for example, an unused area of addresses 0BD3 [H] to 11FF [H] and an unused area of addresses 1D34 [H] to 1FFF [H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of the unused storage area may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area of zero data that becomes the used data in the setting example 003AKA11. The special storage area may be, for example, a storage area of zero data that becomes the unused data in the setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes. The total storage capacity of the special storage area may be, for example, 19 bytes. The discontinuous addresses as normal addresses may be, for example, storage addresses of zero data that are used data in setting example 003AKA11. The discontinuous addresses as special addresses may be, for example, storage addresses of zero data that are unused data in setting example 003AKA11.
According to this configuration, discontinuous addresses are assigned as normal addresses where used data is stored in the normal storage area, and discontinuous addresses are assigned as special addresses where unused data is stored in the special storage area. Furthermore, since the normal storage area and the special storage area have a smaller total storage capacity than the unused storage area, appropriate management of the storage area becomes possible to prevent the normal storage area and the special storage area from being mistaken for unused storage area.

[2-3] The usage data stored in the normal storage area may include turn-off control data that can be used to turn off the light-emitting means.
Here, the light emitting means may be, for example, the first light emitting section and the second light emitting section in the normal symbol display device 20, the first light emitting section and the second light emitting section in the first special symbol display device 4A, etc. The light-off control data may be, for example, zero data in which the storage value is 00 [H] in the normal symbol reserved memory number display table XD_FMEM, or zero data in which the storage value is 00 [H] in the first reserved memory number display table XD_TMEM1, etc.
In such a configuration, usage data indicating 0 is stored so as to prevent a normal storage area from being mistaken for an unused storage area, thereby enabling appropriate management of the storage area.

[2-4] The unused data stored in the special memory area may include state-related data corresponding to a number of rounds that is different from the number of rounds that can be executed in an advantageous state that is advantageous to the player.
Here, the advantageous state may be, for example, a big win game state, etc. The state-related data may be, for example, zero data with a stored value of 00 [H] in the right-hit round number display table XD_TOKU1.

[2-5] Normal addresses are assigned to normal memory areas so that no area of a specific number of bytes or more is continuous.
The special memory area may be assigned special addresses so that no area of a specific number of bytes or more is consecutive.
Here, the specific number of bytes may be, for example, 16 bytes.
In such a configuration, when the dump list is displayed, it is possible to appropriately manage the storage areas so that the normal storage areas and the special storage areas are prevented from being mistaken for unused storage areas.

[3-1] A gaming machine capable of playing a game,
A storage means capable of storing a program;
A control means for controlling the progress of a game by a program stored in the storage means,
The storage means is
A first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, the unused storage area being capable of storing unused data;
The unused memory area stores unused data that indicates all 0.
The second storage area is
A usage data indicating 0 is stored at the normal address,
Data indicating a value other than 0 may be stored at the start address and end address.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a gaming program area. The second storage area may be, for example, a gaming data area. The third storage area may be, for example, a non-gaming program area and a non-gaming data area. The unused storage area may be, for example, an unused area of addresses 0BD3 [H] to 11FF [H] and an unused area of addresses 1D34 [H] to 1FFF [H]. The normal address may be, for example, a storage address of zero data that becomes the data used in the setting example 003AKA11. The start address may be, for example, address 1200 [H]. The end address may be, for example, address 1D33 [H].
According to this configuration, it is possible to appropriately manage the storage area so as to prevent the second storage area from being mistaken for an unused storage area.

[3-2] The second memory area may store data indicating a value other than 0 in the address next to the start address and the address before the end address.
Here, the address next to the start address may be, for example, address 1201 [H], and the address before the end address may be, for example, address 1D32 [H].
In such a configuration, it becomes possible to appropriately manage the storage area so as to prevent the second storage area from being mistaken for an unused storage area.

(Explanation regarding characteristic part 05AK)
FIG. 12-1 shows an example of the configuration of the performance control board 12 and the backup memory board 16 provided in the pachinko game machine 1 with respect to the characteristic part 05AK. The pachinko game machine 1 of the characteristic part 05AK is provided with a backup memory board 16 configured to be detachable from the performance control board 12. For example, the performance control board 12 is provided with a connector 12C that is detachable from the connector 16C of the backup memory board 16. The backup memory board 16 is provided with a connector 16C that is detachable from the connector 12C of the performance control board 12. By coupling the connector 12C and the connector 16C, the performance control board 12 and the backup memory board 16 can be physically and electrically connected. The connector 12C provided in the performance control board 12 may include a terminal that allows the connection state with the backup memory board 16 to be confirmed.

The performance control board 12 of the characteristic part 05AK can be configured with a performance control microcomputer 100A. The performance control microcomputer 100A may be a microprocessor for performance control that integrates built-in electronic circuits. The performance control microcomputer 100A, which is a microprocessor for performance control, is also called a performance processor. The performance control microcomputer 100A includes a CPU 120A, an internal ROM 121A, an internal RAM 122A, a VDP 123A, a watchdog timer 151, a timer circuit 152, an interrupt controller 153, a serial communication circuit 154, a clock circuit 155, and a processor temperature sensor 156.

The CPU 120A corresponds to the performance control CPU 120 in the basic explanation, and can execute processing according to a computer program read from the internal ROM 121A or the like. The internal ROM 121A is included in the ROM 121 in the basic explanation, and can permanently store basic programs for processing executed by the CPU 120A, such as firmware, and system setting data specific to the performance control microcomputer 100A. The internal RAM 122A is included in the RAM 122 in the basic explanation, and can provide a temporary storage area that serves as a work area for the CPU 120A. The VDP 123A is included in the display control unit 123 in the basic explanation, and can execute data processing related to image display on the image display device 5, etc.

Watchdog timer 151 has a counter circuit that counts up or down based on the settings of an internal register, and can measure the time that has elapsed since the count start timing. When the elapsed time measured by watchdog timer 151 reaches a timeout time that is predetermined as a monitoring time, a timeout occurs. When a timeout occurs, watchdog timer 151 outputs a timeout signal that is a time-elapsed signal. CPU 120A periodically clears and restarts watchdog timer 151. When a delay occurs in the processing of CPU 120A due to some kind of failure, and watchdog timer 151 cannot be cleared and a timeout occurs, the processing by CPU 120A is reset in response to the output of the timeout signal.

The timer circuit 152 is a circuit that is configured to incorporate an 8-bit programmable counter corresponding to multiple channels, such as four channels, and is capable of generating real-time interrupts and measuring time. The timer circuit 152 starts counting down at a predetermined interval from a count initial value preset for each channel. If the count value of a channel subsequently reaches a timeout determination value such as "00", the timer interrupt flag corresponding to that channel can be set to an ON state. At this time, if the interrupt is permitted, the timer circuit 152 only needs to be able to issue an interrupt request to the CPU 120A via the interrupt controller 153. The timer circuit 152 may also have a function as an RTC (Real Time Clock). The RTC can measure the current date and time and generate date and time data. The date and time data is data indicating date and time information including date information and time information.

The interrupt controller 153 is a circuit capable of controlling various interrupt requests generated by the performance control microcomputer 100A. The interrupts controlled by the interrupt controller 153 may include multiple types of interrupts, such as an X-class interrupt (XIRQ), an I-class interrupt (IRQ), a software interrupt (SWI), and an illegal opcode trap (ILGOP). The interrupt controller 153 has multiple interrupt control registers that can set the interrupt permission and interrupt priority for each type of interrupt. For example, the multiple interrupt control registers provided in the interrupt controller 153 may be assigned in response to various interrupts, such as a serial reception interrupt, a performance control timer interrupt, a temperature detection timer interrupt, and a V-sync interrupt. The V-sync interrupt is an interrupt that is timed to the output of a vertical synchronization signal from the VDP 123A that draws performance images on the image display device 5. The interrupt control registers corresponding to each interrupt may be set to internal information data including interrupt permission data and interrupt priority data. The interrupt permission data is data that can specify whether to permit or deny the corresponding interrupt. The interrupt priority data is data that can specify the priority of the corresponding interrupt. For example, if the value of the interrupt permission data is "0", the corresponding interrupt is set to the permitted state, and if the value of the interrupt permission data is "1", the corresponding interrupt is set to the prohibited state. The interrupt priority data can specify the priority of the interrupt in 16 stages using a 4-bit numerical value, and when the bit value is "0000" and indicates 0 [H] in hexadecimal, the priority of the corresponding interrupt is the highest, and when the bit value is "1111" and indicates F [H] in hexadecimal, the priority of the corresponding interrupt is the lowest. In addition to the serial reception interrupt, the performance control timer interrupt, the temperature detection timer interrupt, and the V sync interrupt, the interrupt control register may be set in response to any interrupt related to the control of the performance, such as an external interrupt, a serial transmission interrupt, or an interrupt due to random number capture by a random number circuit.

The internal information data set in the interrupt control register of the interrupt controller 153 is stored in advance in a predetermined area, such as the program management area of the internal ROM 121A. When the power supply to the pachinko game machine 1 is started by turning on the power, the CPU 120A sets the serial communication circuit 154, sets the random number generation, sets the internal reset operation, etc., according to the stored contents of the program management area, etc. At this time, the internal information data is set for the multiple interrupt control registers provided in the interrupt controller 153. As a result, maskable interrupts such as the serial reception interrupt, the performance control timer interrupt, the temperature detection timer interrupt, and the V sync interrupt are set. For example, the interrupt permission data of the internal information data of the interrupt control registers assigned to the serial reception interrupt, the performance control timer interrupt, the temperature detection timer interrupt, and the V sync interrupt all indicate a value of "0", and each interrupt is set to an allowed state. In addition, as the interrupt priority data of the internal information data, a 4-bit value corresponding to each interrupt is stored so that the temperature detection timer interrupt is set to a higher priority than the V sync interrupt, the performance control timer interrupt is set to a higher priority than the temperature detection timer interrupt, and the serial reception interrupt is set to a higher priority than the performance control timer interrupt. A reset controller may be provided inside or outside the interrupt controller 153. The reset controller controls various resets that occur in the performance control microcomputer 100A.

The serial communication circuit 154 is a circuit capable of transmitting and receiving communication data by a serial communication method between various boards and circuits other than the performance control board 12. The serial communication circuit 154 may transmit and receive communication data corresponding to multiple types of serial communication standards, such as UART (Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit). The serial communication circuit 154 may have multiple communication processing units including a receiving unit, a transmitting unit, a communication control unit, a serial communication data register, a serial status register, and a serial control register. UART is a start-stop synchronous serial communication standard, and transfers communication data using a start bit and a stop bit. In this case, a clock signal line is not required, but the communication speed (baud rate) is relatively slow. SPI and I2C are clock synchronous serial communication standards, and transfer communication data using a clock signal. In this case, a clock signal line is required, but the communication speed (baud rate) is relatively high. In the case of SPI, signal lines are provided corresponding to the clock signal, the transmission data signal, the reception data signal, and the slave selection signal. In the case of I2C, signal lines are provided corresponding to the clock signal and the data signal. The multiple communication processing units provided in the serial communication circuit 154 may have different hardware configurations corresponding to these multiple types of serial communication standards.

The clock circuit 155 can generate a clock signal to be supplied to each circuit of the performance control microcomputer 100A, such as the CPU 120A and the VDP 123A. For example, the clock circuit 155 divides the frequency of an external clock input to a clock input terminal to generate an internal system clock signal, which it supplies to each circuit of the performance control microcomputer 100A. Alternatively, the clock circuit 155 can generate an internal system clock signal of a specific frequency using a built-in oscillator circuit.

The processor temperature sensor 156 is a temperature sensor built into the performance control microcomputer 100A, which is the performance processor, and is capable of generating temperature data indicating the internal temperature of the performance processor and supplying it to the CPU 120A. For example, it is sufficient that the temperature data can be output from the processor temperature sensor 156 to the CPU 120A by using a thermal diode with a PN junction for temperature measurement to convert the voltage value when a constant current is passed through it into digital data. The temperature data output from the processor temperature sensor 156 indicates processor temperature information that can identify the current temperature of the performance processor. The processor temperature sensor 156 may be built into the CPU 120A. The processor temperature sensor 156, which is the first detection means, is capable of detecting a first temperature related to the performance control microcomputer 100A, which is the performance control means.

The performance control board 12 of characteristic part 05AK can be configured to include, in addition to the performance control microcomputer 100A, an external ROM 121B, an external RAM 122B, and a board temperature sensor 160. The external ROM 121B can store in a fixed manner, as specific content of the performance control by the performance control microcomputer 100A, command codes contained in system programs and user programs executable by the CPU 100A, management codes, table data, various data constituting performance control patterns, and the like. The external RAM 122B temporarily stores various data and the like as an auxiliary area for the internal RAM 122A.

The substrate temperature sensor 160 is configured using, for example, a single-chip digital temperature sensor IC, and can generate temperature data indicating the temperature at a predetermined position on the substrate of the performance control substrate 12 and supply it to the CPU 120A. For example, when a current mirror using a MOSFET (Metal Oxide Silicon Field Effect Transistor) is combined with a Widlar current source using a bipolar transistor to operate the transistor in the forward active region, a current proportional to the thermal voltage flows through the detection resistor, providing a voltage corresponding to the detected temperature. The substrate temperature sensor 160 can generate digital data corresponding to this voltage and supply the temperature data to the CPU 120A of the performance control microcomputer 100A. The substrate temperature sensor 160 can obtain the detected temperature multiple times, for example, over a period of 100 to 200 [ms (milliseconds)], and store the temperature data indicating the average value in an internal register at a period of 1 [s (seconds)]. When temperature data is stored in the internal register of the substrate temperature sensor 160, the data ready flag, which is an internal flag of the substrate temperature sensor 160, turns on. In this case, the CPU 120A needs to wait up to 1 s (seconds) before acquiring the temperature data from the substrate temperature sensor 160. The substrate temperature sensor 160, which serves as the second detection means, is capable of detecting a second temperature related to the performance control board 12 on which the performance control microcomputer 120, which serves as the performance control means, is provided.

In the performance control microcomputer 100A, the CPU 120A can execute a first process related to performance control and a second process related to temperature detection. The first process related to performance control is, for example, a performance control timer interrupt process. The second process related to temperature detection is, for example, a temperature detection timer interrupt process. The CPU 120A that executes the temperature detection timer interrupt process can store information related to the temperature detected by the processor temperature sensor 156 and the board temperature sensor 160 in a storage means such as the internal RAM 122A. The CPU 120A that executes the performance control timer interrupt process can monitor the information related to the temperature stored in the storage means by the temperature detection timer interrupt process.

The backup memory board 16 can be configured by mounting a memory controller 200, an RTC 201, a serial communication circuit 202, an inspection connection section 203, and a backup data memory 210. The RTC 201 does not have to be mounted on the backup memory board 16, for example, when an RTC included in a timer circuit of the performance control microcomputer 120 is used. The inspection connection section 203 may be provided on the performance control board 12. In this way, the configuration of the backup memory board 16 may not include at least a part of the components. Alternatively, for example, multiple memory chips may be added as the backup data memory 210. Furthermore, instead of the serial communication circuit 202, a parallel communication circuit that enables communication using address signals and data signals transmitted in a parallel signal system may be mounted. In this way, the configuration of the backup memory board 16 may include a configuration different from that shown in FIG. 12-1.

The memory controller 200 is a storage processing circuit capable of executing write processing and read processing of backup data. In response to a backup control signal from the performance control board 12, the memory controller 200 can execute write processing and read processing. The backup control signal may include a part or all of the backup target data. The backup target data is data to be saved by backup storage in the backup memory board 16, and may indicate progress and control of games and performances, occurrence of errors, and other historical information. The backup data write processing by the memory controller 200 may be included in a backup processing that can store the backup target data in the backup data memory 210. The backup data read processing by the memory controller 200 may be included in a data acquisition processing that can acquire the backup target data from the backup data memory 210.

The RTC 201 can measure the current date and time, and supply date and time information including date information and time information to the memory controller 200. The memory controller 200, to which the date and time information is supplied from the RTC 201, controls so that date and time data indicating the date and time information can be stored in the backup data memory 210 together with the data to be backed up. In this way, the data stored in the backup data memory 210 only needs to be able to include the data to be backed up indicating information regarding the progress and control of the game and presentation, and date and time data corresponding to the date and time information indicating the date and time.

The serial communication circuit 202 is a circuit that enables communication data to be sent and received via serial communication with the performance control board 12. The serial communication circuit 202 only needs to be able to send and receive communication data that corresponds to a specific serial communication standard, such as SPI. The serial communication circuit 202 only needs to be equipped with a communication processing unit with a hardware configuration that corresponds to the specific serial communication standard.

The inspection connection 203 may be formed as a specific conductor including a terminal capable of inputting and outputting an inspection signal, such as a test point. When the inspection connection 203 is a test point, it is sufficient that the inspection device as an external device can be physically and electrically connected by contacting the inspection connection 203 with a test probe. The inspection device connected to the inspection connection 203 may input and output inspection signals and read backup data between the performance control microcomputer 120 of the performance control board 12. The inspection connection 203 may be capable of inputting and outputting inspection signals and reading backup data between the inspection device and the memory controller 200 or backup data memory 210 of the backup memory board 16 without going through the performance control microcomputer 120 of the performance control board 12. In this way, the inspection connection 203 can provide an interface for data communication between the inspection device as an external device in the backup memory board 16.

The backup data memory 210 may be partially or entirely composed of a nonvolatile ferroelectric memory such as FRAM (registered trademark), partially or entirely composed of a battery-equipped SRAM (Static RAM), partially or entirely composed of a flash memory such as NAND-ROM, an EEPROM, or a hard disk drive (HDD). The nonvolatile ferroelectric memory has memory cells using a ferroelectric film as a capacitor insulating film, and the stored data written in the memory cells is not lost even when the operating power supply is turned off. In the case of the backup data memory 210 using a nonvolatile ferroelectric memory, data can be retained without the need for battery backup, and compared to nonvolatile memories such as flash memory, EEPROM, and HDD, it has high speed writing, high rewrite count, and low power consumption. This prevents an increase in the installation area, simplifies the device configuration, improves operating efficiency, and allows the backup data to be properly stored and saved. In addition, there is no need to discard the battery, the loss of memory contents due to battery replacement is prevented, and the backup data can be properly stored and saved. The backup data memory 210 may be backed up by a backup power supply mounted on the power supply board. In this way, the backup data memory 210 can retain the stored contents even if the power supply to the pachinko gaming machine 1 is stopped.

In the backup memory board 16, various log information can be stored and saved in a log area provided in the backup data memory 210 using the date and time data output by the RTC 201. The memory controller 200 can execute write and read processes of stored data in the backup data memory 210 in response to commands and instructions indicated in the backup control signal sent from the performance control microcomputer 100A of the performance control board 12. In this case, by executing write and read processes of stored data indicating log information, including the date and time data indicating the date and time information, it is possible to store the operation history, setting history, error history, etc. of multiple electronic components used for play and performance in the pachinko game machine 1 so that they can be verified after the fact.

Figure 12-2 (A) is a flowchart showing the main processing S_MAIN for performance control executed in the characteristic part 05AK. The main processing S_MAIN for performance control can be executed by the CPU 120A provided in the performance control microcomputer 100A mounted on the performance control board 12 of the characteristic part 05AK. Among the processes shown in Figure 12-2 (A), the performance control initialization processing S_INIT in step S71 and the initial operation control processing S_SYOKI in step S72 are the same as the processes shown in Figure 8 in the basic explanation. In the main processing S_MAIN for performance control corresponding to the characteristic part 05AK, the power-on information processing S_STRINF is executed after the initial operation control processing S_SYOKI in step S72 is executed (step 05AKS01). Next, the interrupt initial setting processing S_INTINI is executed (step 05AKS02). After that, the interrupt is set to be permitted (step 05AKS03), and then the loop processing is entered.

The power-on information processing S_STRINF of step 05AKS01 may include a power-on backup processing and a power-on data acquisition processing. The power-on backup processing is a processing for backing up and storing data that is predetermined as data to be backed up at the time of power-on in response to the start of power supply by powering on the pachinko game machine 1. The data to be backed up at the time of power-on may be data indicating log information including the power-on date and time. For example, the CPU 120A sends a backup control signal to the memory controller 200 of the backup memory board 16 to instruct backup storage at the time of power-on. The memory controller 200 may store and save the power-on history data indicating the start of power supply together with the date and time data acquired from the RTC 201 in the log area of the backup data memory 210. The power-on data acquisition processing is a processing for acquiring data that is predetermined as data to be acquired at the time of power-on from the backup storage. The data to be acquired at the time of power-on may include the latest maximum temperature data stored in the backup data memory 210. For example, CPU 120A sends a backup control signal to memory controller 200 of backup memory board 16, requesting the latest maximum temperature data. Memory controller 200 retrieves the latest maximum temperature data from the backup data stored in the log area of backup data memory 210 by searching or the like, and supplies it as a response to CPU 120A of performance control microcomputer 100A.

The interrupt initial setting process S_INTINI of step 05AKS02 may include the initial setting of the timer circuit 152 and the initial setting of the interrupt controller 153. The initial setting of the timer circuit 152 may include the setting of a first count initial value so that a timer interrupt occurs at a period of 1 [ms (milliseconds)], for example, corresponding to the channel used to execute the timer interrupt process for performance control. The initial setting of the timer circuit 152 may include the setting of a second count initial value so that a timer interrupt occurs at a period of 1 [s (seconds)], for example, corresponding to the channel used to execute the timer interrupt process for temperature detection. In this way, the first count initial value may be a count initial value that enables the timer interrupt process to be executed at a period shorter than the second count initial value. As a result, the first period in which the timer interrupt process for performance control, which is the first process, can be executed is set to a shorter period than the second period in which the timer interrupt process for temperature detection, which is the second process, can be executed. Note that it is only necessary to be able to set any first period and second period so that the first period is shorter than the second period. The initial setting of the interrupt controller 153 may be, for example, to store internal information data obtained from the program management area of the internal ROM 121A in multiple interrupt control registers provided in the interrupt controller 153, and to set whether or not to allow an interrupt and its priority.

Figure 12-2 (B) shows an example of setting the processing priority in the performance control microcomputer 100A. The processing priority in the performance control microcomputer 100A can be specified in advance based on the specifications of the performance control microcomputer 100A along with the priority of the maskable interrupt controlled by the interrupt controller 153. As an example, the processing priority can be set in advance so that the processing when a CPU exception event occurs has the highest priority, followed by the priority of the error interrupt processing, and then the priority corresponding to the interrupt controlled by the interrupt controller 153. Note that the error interrupt processing may be executed based on the occurrence of an interrupt cause that the interrupt controller 153 can control. In this case, for example, the interrupt priority can be set by the interrupt initial setting processing S_INTINI in step 05AKS02 so that the priority of the error interrupt is the highest.

The CPU exception event processing is processing executed when an exception event occurs in the CPU 120A of the performance control microcomputer 100A due to an abnormality in the internal state, etc. An exception event in the CPU 120A may occur in response to decoding an undefined instruction that is not defined in the instruction set, executing an invalid operation such as division by zero or overflow, a memory protection violation in virtual memory, a TLB (Translation Lookaside Buffer) miss that causes an abnormality in the translation from virtual address to physical address, or any of a number of events including a combination of any or all of these.

The error interrupt process is a process that can be executed when a predetermined error event occurs in the performance control microcomputer 100A. For example, when an error interrupt request occurs in the VDP 123A of the performance control microcomputer 100A due to an abnormality in the internal state, it is sufficient to be able to execute an error interrupt process corresponding to the error event. The error interrupt request of the VDP 123A may occur in response to an exception event of the VDP 123A, as in the case of the CPU 100A. In addition, the error interrupt request of the VDP 123A may occur in response to a setting abnormality of the clock signal (dot clock) used for display control of the image display device 5, a decoding abnormality of moving image data, a decoding abnormality of audio data, a system reset in the VDP 123A, or any of a plurality of events including a combination of some or all of these. In addition to the VDP 123A, an error interrupt request may occur in response to any error event inside the performance control microcomputer 100A. In this way, when the conditions for an exception event occurring due to the internal state of CPU 120A are met, processing at the time of the occurrence of a CPU exception event can be executed. Also, when the conditions for an error event occurring including the internal state of VDP 123A are met, error interrupt processing can be executed. Processing at the time of the occurrence of a CPU exception event and error interrupt processing only need to be executable when the conditions for an event occurring that can be met due to the internal state of a control device or processing device, such as CPU 100A or VDP 123A, are met.

In the interrupt initial setting process S_INTINI of step 05AKS02, the initial setting of the interrupt controller 153 may include, for example, a first setting for storing the first internal information data in an interrupt control register corresponding to the timer interrupt process for performance control. Also, the initial setting of the interrupt controller 153 may include, for example, a second setting for storing the second internal information data in an interrupt control register corresponding to the timer interrupt process for temperature detection. In this case, the first internal information data stored by the first setting may include interrupt priority data indicating a higher priority than the second internal information data stored by the second setting. In this way, the first internal information data may be internal information data that enables the timer interrupt process to be executed with a higher priority than the second internal information data. As a result, the timer interrupt process for performance control, which is the first process, is set to a higher priority than the timer interrupt process for temperature detection, which is the second process. Note that any process priority may be set so that the first process has a higher priority than the second process.

Figure 12-3 shows an example of the configuration of the temperature-related data storage area 05AK100 secured in the storage area of the internal RAM 122A. The temperature-related data storage area 05AK100 is provided with a plurality of storage areas capable of storing a plurality of types of temperature-related data indicating information related to temperature based on the detection results by a detection means capable of detecting temperature, such as the processor temperature sensor 156 and the substrate temperature sensor 160. The internal RAM 122A provided with such a temperature-related data storage area 05AK100 can constitute a storage means capable of storing information related to temperature. Note that a part or all of the temperature-related data storage area 05AK100 may be provided in the external RAM 122B. In this case, the external RAM 122B provided with a part or all of the temperature-related data storage area 05AK100 can constitute a storage means capable of storing information related to temperature. The temperature-related data storage area 05AK100 includes a current temperature storage area capable of storing current temperature data, a maximum temperature storage area capable of storing maximum temperature data, and a temperature-related flag storage area capable of storing flag data.

In the temperature-related data storage area 05AK100, the current temperature data that can be stored in the current temperature storage area indicates information related to the current temperature. The current temperature storage area includes a storage area 05AK101A that can store processor current temperature data and a storage area 05AK101B that can store board current temperature data. The processor current temperature data indicates the current temperature detected by the processor temperature sensor 156. The board current temperature data indicates the current temperature detected by the board temperature sensor 160. The current temperature detected by the processor temperature sensor 156 is included in the first temperature related to the performance control microcomputer 100A that serves as the performance control means, and can be stored as processor current temperature information by the processor current temperature data. The current temperature detected by the board temperature sensor 160 is included in the second temperature related to the performance control board 12 on which the performance control microcomputer 100A that serves as the performance control means is provided, and can be stored as board current temperature information by the board current temperature data. Therefore, the processor current temperature information becomes first temperature information indicating the processor current temperature included in the first temperature detected by the processor temperature sensor 156 that serves as the first detection means. The current substrate temperature information is second temperature information indicating the current substrate temperature included in the second temperature detected by the substrate temperature sensor 160, which serves as the second detection means. The memory area 05AK101A can store first temperature information indicating the first temperature in correspondence with the current processor temperature data. The memory area 05AK101B can store second temperature information indicating the second temperature in correspondence with the current substrate temperature data.

In the temperature-related data storage area 05AK100, the maximum temperature data that can be stored in the maximum temperature storage area indicates information related to the maximum temperature. The maximum temperature storage area includes a storage area 05AK102A that can store processor maximum temperature data and a storage area 05AK102B that can store board maximum temperature data. The processor maximum temperature data indicates the maximum temperature that is the highest temperature among the temperatures detected by the processor temperature sensor 156. The board maximum temperature data indicates the maximum temperature that is the highest temperature among the temperatures detected by the board temperature sensor 160. The maximum temperature detected by the processor temperature sensor 156 is included in the first special temperature related to the performance control microcomputer 100A that serves as the performance control means, and can be stored as processor maximum temperature information by the processor maximum temperature data. The maximum temperature detected by the board temperature sensor 160 is included in the second special temperature related to the performance control board 12 on which the performance control microcomputer 100A that serves as the performance control means is provided, and can be stored as board maximum temperature information by the board maximum temperature data. Therefore, the processor maximum temperature information becomes first special temperature information indicating the processor maximum temperature included in the first special temperature detected by the processor temperature sensor 156, which serves as the first detection means. The board maximum temperature information becomes second special temperature information indicating the board maximum temperature included in the second special temperature detected by the board temperature sensor 160, which serves as the second detection means. The memory area 05AK102A can store first special temperature information indicating the first special temperature in correspondence with the processor maximum temperature data. The memory area 05AK102B can store second special temperature information indicating the second special temperature in correspondence with the board maximum temperature data.

In the temperature-related data storage area 05AK100, the flag data that can be stored in the temperature-related flag storage area indicates a flag related to temperature. The temperature-related flag storage area includes a storage area 05AK103A that can store a processor maximum temperature update flag, a storage area 05AK103B that can store a board maximum temperature update flag, a storage area 05AK103C that can store a processor temperature error notification flag, a storage area 05AK103D that can store a board temperature error notification flag, and a storage area 05AK103E that can store a temperature display flag. The processor maximum temperature update flag makes it possible to determine whether data indicating a new processor maximum temperature has been acquired as the processor maximum temperature data that can be stored in the storage area 05AK102A. For example, when the processor current temperature, which is the temperature detected by the processor temperature sensor 156, exceeds the processor maximum temperature indicated in the processor maximum temperature data in the storage area 05AK102A, the processor maximum temperature update flag can be set to an on state. The maximum substrate temperature update flag makes it possible to determine whether or not data indicating a new maximum substrate temperature has been acquired as the maximum substrate temperature data that can be stored in the memory area 05AK102B. For example, when the substrate current temperature, which is the temperature detected by the substrate temperature sensor 160, exceeds the substrate maximum temperature indicated in the substrate maximum temperature data in the memory area 05AK102B, the maximum substrate temperature update flag can be set to an ON state. The processor temperature error notification flag makes it possible to determine whether or not a processor temperature error has occurred based on the processor current temperature, which is the temperature detected by the processor temperature sensor 156. For example, when the processor current temperature detected by the processor temperature sensor 156 exceeds the error temperature indicated in the temperature error determination data, the processor temperature error notification flag can be set to an ON state. The substrate temperature error notification flag makes it possible to determine whether or not a substrate temperature error has occurred based on the substrate current temperature, which is the temperature detected by the substrate temperature sensor 160. For example, when the substrate current temperature detected by the substrate temperature sensor 160 exceeds the error temperature indicated in the temperature error determination data, the substrate temperature error notification flag can be set to an ON state. The temperature display flag makes it possible to determine whether or not the temperature display screen is being displayed as the display screen of the image display device 5. The processor maximum temperature update flag, the substrate maximum temperature update flag, the processor temperature error notification flag, and the substrate temperature error notification flag are included in the information related to temperature, in that they can be set to the ON state based on the temperature detection results by the processor temperature sensor 156, which is the first detection means, and the substrate temperature sensor 160, which is the second detection means.

Figure 12-4 is a flow chart showing an example of a process that can be executed as a temperature detection timer interrupt process. The temperature detection timer interrupt process is a process related to the detection of temperature using the processor temperature sensor 156 and the board temperature sensor 160, and enables information related to the detected temperature to be stored in the temperature-related data storage area 05AK100. The CPU 120A of the performance control microcomputer 100A can execute the temperature detection timer interrupt process in a second period, for example, 1 s (second), in response to the settings of the timer circuit 152 and the interrupt controller 153.

When the CPU 120A executes the temperature detection timer interrupt process, it acquires processor temperature data (step 05AKS21). The processor temperature data is data indicating the temperature detection result output from the processor temperature sensor 156. Next, the substrate temperature data is acquired (step 05AKS22). The substrate temperature data is data indicating the temperature detection result output from the substrate temperature sensor 160. Note that the acquisition of the processor temperature data and the acquisition of the substrate temperature data can be performed in any order. The substrate temperature sensor 160 requires a waiting period of up to 1 s (seconds) before it can acquire data indicating the temperature that will become the substrate temperature data. The CPU 120A must wait until the data ready flag, which is an internal flag of the substrate temperature sensor 160, is turned on, so it may acquire the processor temperature data during this waiting period. In this way, the temperature detection timer interrupt process, which is the second process, includes an information acquisition process in which processor temperature data indicating the processor current temperature information, which becomes the first temperature information, is acquired in step 05AKS21, and then substrate current temperature data indicating the substrate current temperature information, which becomes the second temperature information, is acquired in step 05AKS22. Before acquiring the processor temperature data, the substrate temperature data may be acquired first, and then the processor temperature data may be acquired later, in response to the data ready flag of the substrate temperature sensor 160 being on.

Following step 05AKS22, the current temperature data is stored (step 05AKS23). The current temperature data includes the processor temperature data acquired in step 05AKS21 and the substrate temperature data acquired in step 05AKS22. The CPU 120A may store the processor temperature data acquired in step 05AKS21 in memory area 05AK101A as the processor current temperature data. The CPU 120A may also store the substrate temperature data acquired in step 05AKS22 in memory area 05AK101B as the substrate current temperature data.

In this way, the timer interrupt process for temperature detection, which is the second process, can acquire the processor current temperature information shown in the processor current temperature data as the first temperature information indicating the processor current temperature, which is the first temperature, from the processor temperature sensor 156, which is the first detection means, and store it in the memory area 05AK101A provided in the memory means. Also, the timer interrupt process for temperature detection, which is the second process, can acquire the board current temperature information shown in the board current temperature data as the second temperature information indicating the board current temperature, which is the second temperature, from the board temperature sensor 160, which is the second detection means, and store it in the memory area 05AK101B provided in the memory means. Therefore, the CPU 120A that executed the timer interrupt process for temperature detection, which is the second process, can acquire both the first temperature information and the second temperature information from the processor temperature sensor 156 and the board temperature sensor 160 included in the detection means in the second period and store them in the current temperature memory area provided in the memory means. This makes it possible to grasp the operating environment in the performance control board 12 and the like in detail and perform appropriate control. In addition, the second process, the temperature detection timer interrupt process, includes an information storage process in step 05AKS23 that stores both the processor current temperature information, which is the first temperature information, and the board current temperature information, which is the second temperature information, in a current temperature storage area provided in the storage means, after the information acquisition process in steps 05AKS21 and 05AKS22. By including these information acquisition processes and information storage processes, information related to temperature can be appropriately managed.

After step 05AKS23, a temperature detection determination process is executed (step 05AKS24), and then the temperature detection timer interrupt process is terminated. The temperature detection determination process of step 05AKS24 makes it possible to execute a determination regarding the update of the maximum temperature and a determination regarding the occurrence of a temperature error when temperature detection is performed using the processor temperature sensor 156 or the board temperature sensor 160.

Figure 12-5 is a flowchart showing an example of a process that can be executed as the temperature detection determination process. The temperature detection determination process is called in the temperature detection timer interrupt process shown in Figure 12-4, and can be executed in step 05AKS23 after the current temperature data is stored in step 05AKS22. By executing the temperature detection determination process, the CPU 120A can determine whether or not to update the maximum processor temperature stored as the previous maximum temperature when processor temperature data is acquired. Also, by executing the temperature detection determination process, the CPU 120A can determine whether or not to update the maximum substrate temperature stored as the previous maximum temperature when substrate temperature data is acquired.

When the CPU 120A executes the temperature detection judgment process, it acquires the maximum temperature data (step 05AKS101). The maximum temperature data acquired in step 05AKS101 may include the processor maximum temperature data stored in memory area 05AK102A and the board maximum temperature data stored in memory area 05AK102B. Next, the processor temperatures are compared (step 05AK102). For example, the current temperature indicated in the processor temperature data acquired in step 05AKS21 of the temperature detection timer interrupt process is compared with the maximum temperature indicated in the processor maximum temperature data acquired in step 05AKS101. The current temperature indicated in the processor temperature data is also called the processor current temperature. The maximum temperature indicated in the processor maximum temperature data is also called the processor maximum temperature. Then, it is determined whether the current temperature exceeds the maximum temperature (step 05AKS103). In step 05AKS103, if the processor current temperature exceeds the processor maximum temperature, it is determined that the current temperature exceeds the maximum temperature.

When the current temperature exceeds the maximum temperature in response to step 05AKS103 (step 05AKS103; Yes), the count value of the processor update counter is incremented by 1 (step 05AKS104). The processor update counter may be provided, for example, in the counter area of the internal RAM 122A or the external RAM 122B, or may be configured using an internal register of the CPU 120A. Next, the count value of the processor update counter is compared with a judgment value that is preset as a maximum update judgment value (step 05AKS105). The maximum update judgment value is used for chattering judgment to prevent updates due to erroneous information, and may be set to a value, such as "3", that corresponds to the period during which the current temperature should continuously exceed the maximum temperature. It is determined whether or not such a judgment value matches the count value of the processor update counter (step 05AKS106).

If the judgment value corresponds to step 05AKS106 and matches (step 05AKS106; Yes), the maximum processor temperature update flag is set to the ON state (step 05AKS107). The maximum processor temperature update flag is stored in memory area 05AK103A, and makes it possible to determine that the maximum temperature indicated in the maximum processor temperature data has been updated. The maximum processor temperature data is then stored (step 05AKS108). The CPU 120A simply stores the processor temperature data acquired in step 05AKS21 of the temperature detection timer interrupt process as maximum processor temperature data in memory area 05AK102A.

The temperature detection judgment process can be executed in step 05AKS24 of the temperature detection timer interrupt process, which is the second process, and includes a judgment process that can judge whether the temperature detected by the processor temperature sensor 156, which is the first detection means, exceeds the maximum temperature indicated by the processor maximum temperature data stored in the memory area 05AK102A by making the judgment in step 05AKS103. In addition, such a temperature detection judgment process includes a storage process that can store information indicating the temperature detected by the processor temperature sensor 156 as processor maximum temperature information, which becomes new special temperature information, in correspondence with the processor maximum temperature data in the memory area 05AK102A provided in the storage means by storing the processor maximum temperature data in step 05AKS108 when it is judged in the judgment in step 05AKS103 that the temperature detected by the processor temperature sensor 156, which is the first detection means, exceeds the maximum temperature. In the second process, the timer interrupt process for temperature detection, which is different from the first process, the timer interrupt process for performance control, it is possible to execute judgment and storage processes, so that the processing burden related to performance control can be reduced and special temperature information can be appropriately stored. In this case, by using the processor update counter to perform the judgment in step 05AKS106, it is possible to execute storage processes on the condition that the current temperature exceeds the maximum temperature in multiple consecutive detections. This makes it possible to prevent the maximum temperature from being updated when abnormal temperature information is obtained due to noise, and to appropriately manage the temperature.

If the current temperature does not exceed the maximum temperature in response to step 05AKS103 (step 05AKS103; No), the processor update counter is cleared (step 05AKS109). As a result, if the current temperature does not exceed the maximum temperature before it matches the judgment value in step 05AKS106, the processor maximum temperature data is not stored by step 05AKS108, so that the processor maximum temperature information can be prevented from being updated with erroneous information as new special temperature information. Note that even after it matches the judgment value in step 05AKS106, the count value by the processor update counter may be added and updated during the period when the current temperature exceeds the maximum temperature. In this case, the temperature detected by the processor temperature sensor 156 may be stored in a specified buffer area or register until the processor update counter is cleared by step 05AKS109. Then, when the processor update counter is cleared by step 05AKS109, a process of identifying the processor maximum temperature using the stored temperature may be executed. For example, during the period in which the current temperature exceeds the maximum temperature, the average of the three temperatures detected excluding the highest temperature among the stored temperatures may be identified as the new maximum processor temperature. The maximum processor temperature data indicating the identified maximum processor temperature may be stored in memory area 05AK102A, making it possible to update the maximum processor temperature information. This allows the maximum temperature to be updated appropriately.

If the judgment value does not match in step 05AKS106 (step 05AKS106; No), or after step 05AKS109, the substrate temperatures are compared (step 05AKS110). For example, the current temperature indicated in the substrate temperature data acquired in step 05AKS22 of the temperature detection timer interrupt process is compared with the maximum temperature indicated in the substrate maximum temperature data acquired in step 05AKS101. The current temperature indicated in the substrate temperature data is also called the substrate current temperature. The maximum temperature indicated in the substrate maximum temperature data is also called the substrate maximum temperature. Then, it is determined whether the current temperature exceeds the maximum temperature (step 05AKS111). If the substrate current temperature exceeds the substrate maximum temperature in step 05AKS111, it is determined that the current temperature exceeds the maximum temperature.

When the current temperature exceeds the maximum temperature in response to step 05AKS111 (step 05AKS111; Yes), the count value of the board update counter is incremented by 1 (step 05AKS112). The board update counter may be provided, for example, in the counter area of internal RAM 122A or external RAM 122B, or may be configured using an internal register of CPU 120A. Next, the count value of the board update counter is compared with a judgment value that is preset as a maximum update judgment value (step 05AKS113). As with the processor update counter, the maximum update judgment value may be set to a value that corresponds to the period during which the current temperature should continuously exceed the maximum temperature. It is determined whether or not such a judgment value matches the count value of the board update counter (step 05AKS114).

If the judgment value corresponds to step 05AKS114 and matches (step 05AKS114; Yes), the maximum substrate temperature update flag is set to the ON state (step 05AKS115). The maximum substrate temperature update flag is stored in memory area 05AK103B, and makes it possible to determine that the maximum temperature indicated in the maximum substrate temperature data has been updated. The maximum substrate temperature data is then stored (step 05AKS116). The CPU 120A simply stores the substrate temperature data acquired in step 05AKS22 of the temperature detection timer interrupt process as maximum substrate temperature data in memory area 05AK102B.

The temperature detection judgment process can be executed in step 05AKS24 of the temperature detection timer interrupt process, which is the second process, and includes a judgment process that can judge whether the temperature detected by the substrate temperature sensor 160, which is the second detection means, exceeds the maximum temperature indicated by the substrate maximum temperature data stored in the memory area 05AK102B by making the judgment in step 05AKS111. In addition, such a temperature detection judgment process includes a storage process that can store information indicating the temperature detected by the substrate temperature sensor 160 as substrate maximum temperature information, which is new special temperature information, in correspondence with the substrate maximum temperature data in the memory area 05AK102B provided in the storage means by storing the substrate maximum temperature data in step 05AKS116 when it is judged in the judgment in step 05AKS111 that the temperature detected by the substrate temperature sensor 160, which is the second detection means, exceeds the maximum temperature. In the second process, the timer interrupt process for temperature detection, which is different from the first process, the timer interrupt process for performance control, it is possible to execute judgment and storage processes, so that the processing burden related to performance control can be reduced and special temperature information can be appropriately stored. In this case, by using the board update counter to perform the judgment in step 05AKS114, it is possible to execute storage processes on the condition that the current temperature exceeds the maximum temperature in multiple consecutive detections. This makes it possible to prevent the maximum temperature from being updated when abnormal temperature information is obtained due to noise, and to appropriately manage the temperature.

When the current temperature does not exceed the maximum temperature in response to step 05AKS111 (step 05AKS111; No), the substrate update counter is cleared (step 05AKS117). As a result, when the current temperature does not exceed the maximum temperature before it matches the judgment value in step 05AKS114, the substrate maximum temperature data is not stored by step 05AKS116, so that the substrate maximum temperature information can be prevented from being updated with erroneous information as new special temperature information. Note that even after it matches the judgment value in step 05AKS114, the count value by the substrate update counter may be added and updated during the period when the current temperature exceeds the maximum temperature. In this case, the temperature detected by the substrate temperature sensor 160 may be stored in a predetermined buffer area or register until the substrate update counter is cleared by step 05AKS117. Then, when the substrate update counter is cleared by step 05AKS117, a process of identifying the substrate maximum temperature using the stored temperature may be executed. For example, during the period in which the current temperature exceeds the maximum temperature, the average of the three temperatures detected excluding the highest temperature among the stored temperatures may be identified as the new maximum substrate temperature. The maximum substrate temperature data indicating the identified maximum substrate temperature may be stored in memory area 05AK102B, making it possible to update the maximum substrate temperature information. This allows the maximum temperature to be updated appropriately.

If there is no match with the judgment value corresponding to step 05AKS114 (step 05AKS114; No), after step 05AKS117, a temperature error judgment process is executed (step 05AKS118), and then the temperature detection judgment process is terminated. The temperature error judgment process of step 05AKS118 makes it possible to execute a judgment regarding the occurrence of a temperature error when temperature detection is performed using the processor temperature sensor 156 or the board temperature sensor 160.

Figure 12-6 is a flow chart showing an example of a process that can be executed as a temperature error determination process. The temperature error determination process is called in the temperature detection determination process shown in Figure 12-5, and can be executed in step 05AKS118 after a determination regarding updating the maximum temperature and the like has been made. By executing the temperature error determination process of step 05AKS118 in the temperature detection determination process, the CPU 120A can determine whether or not a temperature error has occurred when the processor temperature data is acquired. In addition, by executing the temperature error determination process of step 05AKS118 in the temperature detection determination process, the CPU 120A can determine whether or not a temperature error has occurred when the board temperature data is acquired.

When the CPU 120A executes the temperature error determination process, it acquires data for temperature error determination (step 05AKS201). The data for temperature error determination acquired in step 05AKS201 may include data for processor temperature error determination and data for substrate temperature error determination. The data for processor temperature error determination is used to determine the occurrence of a temperature error in response to the temperature detected by the processor temperature sensor 156. The data for substrate temperature error determination is used to determine the occurrence of a temperature error in response to the temperature detected by the substrate temperature sensor 160. The data for processor temperature error determination and the data for substrate temperature error determination may indicate different determination temperatures. Alternatively, the data for temperature error determination may be data indicating a common determination temperature for the temperature detected by the processor temperature sensor 156 and the temperature detected by the substrate temperature sensor 160. For example, the data for temperature error determination may be data indicating a determination temperature of 100 degrees Celsius.

Following step 05AKS201, the processor temperatures are compared (step 05AKS202). For example, the current temperature indicated in the processor temperature data acquired in step 05AKS21 of the temperature detection timer interrupt process is compared with the judgment temperature indicated in the temperature error judgment data acquired in step 05AKS201. Then, it is determined whether or not a temperature error state exists (step 05AKS203). In step 05AKS203, if the current temperature indicated in the processor temperature data is higher than the judgment temperature indicated in the temperature error judgment data, it may be determined that a temperature error state exists.

If the temperature error state corresponds to step 05AKS203 (step 05AKS203; Yes), the count value of the processor temperature error judgment counter is incremented by 1 (step 05AKS204). The processor temperature error judgment counter may be provided, for example, in a counter area of the internal RAM 122A or the external RAM 122B, or may be configured using an internal register of the CPU 120A. Next, the count value of the processor temperature error judgment counter is compared with a judgment value that is preset as a temperature error judgment value (step 05AKS205). The temperature error judgment value is used for chattering judgment to prevent an error judgment due to erroneous information, and may be set to a value, such as "3", corresponding to the period during which the current temperature should continuously exceed the judgment temperature. It is determined whether such a judgment value matches the count value of the processor temperature error judgment counter (step 05AKS206).

If the value corresponds to step 05AKS206 and matches the judgment value (step 05AKS206; Yes), the processor temperature error notification flag is set to the on state (step 05AKS207). The processor temperature error notification flag is stored in memory area 05AK103C, making it possible to determine that a processor temperature error has occurred.

If there is no temperature error state according to step 05AKS203 (step 05AKS203; No), or after step 05AKS207, the processor temperature error judgment counter is cleared (step 05AKS208). As a result, if the current temperature no longer exceeds the judgment temperature before it matches the judgment value in step 05AKS206, the processor temperature error notification flag is not set by step 05AKS207, so it is possible to prevent a processor temperature error from being judged to have occurred due to erroneous information when noise occurs, for example.

If there is no match with the judgment value in step 05AKS206 (step 05AKS206; No), or after step 05AKS208, the substrate temperatures are compared (step 05AKS209). For example, the current temperature indicated in the substrate temperature data acquired in step 05AKS22 of the temperature detection timer interrupt process is compared with the judgment temperature indicated in the temperature error judgment data acquired in step 05AKS201. Then, it is determined whether or not a temperature error state exists (step 05AKS210). In step 05AKS210, if the current temperature indicated in the substrate temperature data is higher than the judgment temperature indicated in the temperature error judgment data, it may be determined that a temperature error state exists.

If a temperature error state is detected in response to step 05AKS210 (step 05AKS210; Yes), the count value of the substrate temperature error judgment counter is incremented by 1 (step 05AKS211). The substrate temperature error judgment counter may be provided, for example, in a counter area of the internal RAM 122A or the external RAM 122B, or may be configured using an internal register of the CPU 120A. Next, the count value of the substrate temperature error judgment counter is compared with a judgment value that is preset as a temperature error judgment value (step 05AKS212). As with the processor temperature error judgment counter, the temperature error judgment value may be set to a value corresponding to the period during which the current temperature should continuously exceed the judgment temperature. It is determined whether or not such a judgment value matches the count value of the substrate temperature error judgment counter (step 05AKS213).

If the judgment value does not match in step 05AKS213 (step 05AKS213; No), the temperature error judgment process ends. On the other hand, if the judgment value matches (step 05AKS213; Yes), the substrate temperature error notification flag is set to the on state (step 05AKS214). The substrate temperature error notification flag is stored in memory area 05AK103D, making it possible to determine that a substrate temperature error has occurred.

If there is no temperature error state according to step 05AKS210 (step 05AKS210; No), after step 05AKS214, the substrate temperature error judgment counter is cleared (step 05AKS215) and the temperature error judgment process is terminated. As a result, if the current temperature no longer exceeds the judgment temperature before it matches the judgment value in step 05AKS213, the substrate temperature error notification flag is not set by step 05AKS214, so it is possible to prevent a substrate temperature error from being judged to have occurred due to erroneous information when noise occurs, for example.

Figure 12-7 is a flowchart showing an example of processing that can be executed as a timer interrupt process for performance control. Of the processing shown in Figure 12-7, steps S75 to S79 may be the same as the main processing S_MAIN for performance control shown in Figure 8 in the basic explanation. However, the command analysis processing S_COMMAND in step S75 may include processing corresponding to characteristic part 05AK, as shown in Figure 12-9. When the timer interrupt process for performance control shown in Figure 12-7 is started, a temperature monitoring process is executed (step 05AKS31). Next, the processes corresponding to steps S75 to S78 are executed, and then a temperature display control process is executed (step 05AKS32). In addition, a backup process during performance control is executed (step 05AKS33), and the process proceeds to step S79.

The timer interrupt process for performance control is a process related to the control of performance in the pachinko gaming machine 1, and by executing the temperature monitoring process of step 05AKS31, it is possible to monitor information related to temperature. The CPU 120A of the microcomputer 100A for performance control can execute the timer interrupt process for performance control in a first period, for example, 1 ms (milliseconds), in accordance with the settings of the timer circuit 152 and the interrupt controller 153. The timer interrupt process for temperature detection shown in FIG. 12-4 can be executed in a second period, for example, 1 s (seconds). Therefore, the first period in which the timer interrupt process for performance control, which is the first process, can be executed, is set to a shorter period than the second period in which the timer interrupt process for temperature detection, which is the second process, can be executed.

The backup process during performance control in step 05AKS33 stores and saves backup data indicating various log information in a log area provided in the backup data memory 210 of the backup memory board 16 when a preset backup condition is met. The log information stored in this case may include some or all of the operation history, setting history, error history, etc., for multiple electronic components used in play and performance in the pachinko gaming machine 1. The log information may include date and time information indicating the date and time of storage corresponding to the date and time data obtained from the RTC 201.

Figure 12-8 is a flow chart showing an example of a process that can be executed as the temperature monitoring process. The temperature monitoring process is called in the performance control timer interrupt process shown in Figure 12-7, and can be executed in step 05AKS31 in the first cycle, which is the cycle in which the performance control timer interrupt process is executed. By executing the temperature monitoring process of step 05AKS31 in the performance control timer interrupt process, the CPU 120A can monitor information related to temperature stored in the temperature-related data storage area 05AK100 by the temperature detection timer interrupt process, which is the second process, as the first process related to the control of the performance.

When the CPU 120A executes the temperature monitoring process, it determines whether the processor maximum temperature update flag is on (step 05AKS141). The processor maximum temperature update flag used in the determination of step 05AKS141 is stored in memory area 05AK103A and is included in the information related to temperature. By making the determination of step 05AKS141, the CPU 120A can monitor the processor maximum temperature update flag stored in memory area 05AK103A as information related to temperature. If the processor maximum temperature update flag is on (step 05AKS141; Yes), the processor maximum temperature data is acquired (step 05AKS142). The processor maximum temperature data acquired in step 05AKS142 is stored in memory area 05AK102A. Next, the processor maximum temperature backup control is performed (step 05AKS143).

When performing the maximum processor temperature backup control of step 05AKS143, the CPU 120A sends a backup control signal to the memory controller 200 of the backup memory board 16 to instruct backup storage of the maximum processor temperature data acquired by step 05AKS142. In response to the backup control signal, the memory controller 200 of the backup memory board 16 stores the maximum processor temperature data sent from the performance control board 12 in the backup data memory 210 together with the date and time data acquired from the RTC 201. When performing such backup storage, the presence or absence of mirroring and the degree of multiplicity are set in accordance with the maximum processor temperature data and date and time data, which are the data to be backed up. Mirroring is a storage method in which the same data is copied and stored in multiple storage areas, and the degree of multiplicity is the number of storage blocks in which the same data is copied and stored in different storage areas when mirroring is performed. For example, a degree of multiplicity of 1 means that the data to be backed up is not copied to one storage block, and thus mirroring is not performed. A degree of multiplicity of 2 means that the data to be backed up is copied to two storage blocks and backed up and stored, thereby performing mirroring. Step 05: When maximum processor temperature data corresponding to new special temperature information is stored by the AKS143 maximum processor temperature backup control, the maximum processor temperature data and date and time data corresponding to the special temperature information are backed up and stored, reducing the processing load and allowing the special temperature information to be stored appropriately. The special temperature information backed up and stored at this time includes the maximum processor temperature data corresponding to the maximum temperature information and the date and time data corresponding to the date and time information. This makes it easy to check the possibility and cause of a malfunction.

After step 05AKS143, it is determined whether the backup storage of the corresponding number of blocks has been completed (step 05AKS144). The corresponding number of blocks in step 05AKS144 is the number of memory blocks corresponding to the multiplicity that is preset in response to the case where the data to be backed up is the processor maximum temperature data and the date and time data. The CPU 120A only needs to be able to determine whether the backup storage of the corresponding number of blocks has been completed based on a response signal from the memory controller 200. If the number of memory blocks in which the processor maximum temperature data, which is the data to be backed up, is backed up and stored together with the date and time data does not reach the corresponding number of blocks, the backup control by step 05AKS143 is continued in response to the fact that the backup storage of the corresponding number of blocks has not been completed (step 05AKS144; No). Note that, if the backup storage is not completed in the temperature monitoring process based on one timer interruption, the processor maximum temperature backup control of step 05AKS143 may be divided and performed in the temperature monitoring process based on multiple timer interruptions. When backup storage of the corresponding number of blocks is complete (step 05AKS144; Yes), the processor maximum temperature update flag is cleared to the off state (step 05AKS145).

If the processor maximum temperature update flag is off in response to step 05AKS141 (step 05AKS141; No), or after step 05AKS145, it is determined whether the board maximum temperature update flag is on (step 05AKS146). The board maximum temperature update flag used in the determination of step 05AKS146 is stored in memory area 05AK103B and is included in the information related to temperature. By making the determination of step 05AKS146, the CPU 120A can monitor the board maximum temperature update flag stored in memory area 05AK103B as information related to temperature. If the board maximum temperature update flag is on (step 05AKS146; Yes), the board maximum temperature data is acquired (step 05AKS147). The board maximum temperature data acquired in step 05AKS147 is stored in memory area 05AK102B. Next, board maximum temperature backup control is performed (step 05AKS148).

When performing the maximum board temperature backup control of step 05AKS148, the CPU 120A sends a backup control signal to the memory controller 200 of the backup memory board 16 to instruct backup storage of the maximum board temperature data acquired by step 05AKS147. In response to the backup control signal, the memory controller 200 of the backup memory board 16 stores the maximum board temperature data sent from the performance control board 12 in the backup data memory 210 together with the date and time data acquired from the RTC 201. When performing such backup storage, the presence or absence of mirroring and the degree of multiplicity are set in accordance with the maximum board temperature data and date and time data that are the data to be backed up. These settings may be the same as when the data to be backed up is the processor maximum temperature data and date and time data. When the maximum board temperature data corresponding to new special temperature information is stored by the maximum board temperature backup control of step 05AKS148, the maximum board temperature data corresponding to the special temperature information is backed up and stored, so that the processing load can be reduced and the special temperature information can be appropriately stored. The special temperature information backed up and stored at this time includes the maximum board temperature data corresponding to the maximum temperature information and the date and time data corresponding to the date and time information. This makes it easy to check for possible malfunctions and their causes.

After step 05AKS148, it is determined whether the backup storage of the corresponding number of blocks has been completed (step 05AKS149). The corresponding number of blocks in step 05AKS149 is the number of memory blocks corresponding to the multiplicity that is preset in response to the case where the backup target data is the maximum substrate temperature data and the date and time data. The CPU 120A only needs to be able to determine whether the backup storage of the corresponding number of blocks has been completed based on a response signal from the memory controller 200. If the number of memory blocks in which the maximum substrate temperature data, which is the backup target data, is backed up and stored together with the date and time data does not reach the corresponding number of blocks, the backup control by step 05AKS148 is continued in response to the fact that the backup storage of the corresponding number of blocks has not been completed (step 05AKS149; No). Note that, if the backup storage is not completed in the temperature monitoring process based on one timer interruption, the maximum substrate temperature backup control of step 05AKS148 may be divided and performed in the temperature monitoring process based on multiple timer interruptions. When backup storage of the corresponding number of blocks is complete (step 05AKS149; Yes), the maximum substrate temperature update flag is cleared to the off state (step 05AKS150).

If the maximum board temperature update flag is off in response to step 05AKS146 (step 05AKS146; No), or after step 05AKS150, it is determined whether the processor temperature error notification flag is on (step 05AKS151). The processor temperature error notification flag used in the determination of step 05AKS151 is stored in memory area 05AK103C and is included in the information regarding temperature. By making the determination of step 05AKS151, the CPU 120A can monitor the processor temperature error notification flag stored in memory area 05AK103C as information regarding temperature. If the processor temperature error notification flag is on (step 05AKS151; Yes), backup control at the time of processor temperature error is performed (step 05AKS152). In this case, the CPU 120A sends a backup control signal to the memory controller 200 of the backup memory board 16 to instruct backup storage corresponding to the occurrence of a processor temperature error. The memory controller 200 of the backup memory board 16 stores the date and time data acquired from the RTC 201 in the backup data memory 210 as log information of the processor temperature error corresponding to the backup control signal. In addition to the date and time data, the log information of the processor temperature error may also include an identification code indicating the occurrence of the processor temperature error.

Following the control of step 05AKS152, a temperature error notification start control is performed (step 05AKS153). For example, the CPU 120A sends a command to the VDP 123A to specify the start of displaying a temperature error notification screen as the display screen of the image display device 5. The VDP 123A only needs to be able to execute image processing for displaying a temperature error notification screen in response to a command from the CPU 120A. This allows the VDP 123A to display and notify temperature abnormality information corresponding to the occurrence of a processor temperature error. The temperature error notification may include a notification by the display screen of the image display device 5, a notification by outputting a notification sound from the speakers 8L and 8R, a notification by partial or full lighting of the game effect lamp 9, a notification by the operation of the movable body 32, or a combination of some or all of these. The temperature error notification started by the control of step 05AKS153 is not controlled to end in the performance control timer interrupt processing or the like. Therefore, when the power supply to the pachinko gaming machine 1 is stopped due to a power outage, the temperature error notification, including the display of the abnormal temperature information on the temperature error notification screen, ends, and the abnormal temperature information is hidden. Along with the control by step 05AKS153, the processor temperature error notification flag is cleared to the off state (step 05AKS154).

If the processor temperature error notification flag is off in response to step 05AKS151 (step 05AKS151; No), or after step 05AKS154, it is determined whether the substrate temperature error notification flag is on (step 05AKS155). The substrate temperature error notification flag used in the determination of step 05AKS155 is stored in memory area 05AK103D and is included in the information regarding temperature. By making the determination of step 05AKS155, the CPU 120A can monitor the substrate temperature error notification flag stored in memory area 05AK103D as information regarding temperature. If the substrate temperature error notification flag is off (step 05AKS155; No), the temperature monitoring process is terminated. If the substrate temperature error notification flag is on (step 05AKS155; Yes), backup control is performed in the event of a substrate temperature error (step 05AKS156). In this case, the CPU 120A sends a backup control signal to the memory controller 200 of the backup memory board 16 to instruct backup storage corresponding to the occurrence of the substrate temperature error. The memory controller 200 of the backup memory board 16 stores the date and time data acquired from the RTC 201 in the backup data memory 210 as log information of the substrate temperature error corresponding to the backup control signal. In addition to the date and time data, the log information of the substrate temperature error may also include an identification code indicating the occurrence of the substrate temperature error. In conjunction with the control of step 05AKS156, the substrate temperature error notification flag is cleared to the off state (step 05AKS157), and the temperature monitoring process is terminated.

In the temperature monitoring process shown in FIG. 12-8, when the processor temperature error notification flag is on in step 05AKS151, a temperature error is notified by the control of step 05AKS153, whereas when the board temperature error notification flag is on in step 05AKS155, a temperature error is not notified. When a temperature error occurs in the performance control microcomputer 100A as a performance processor, the temperature error information including date and time information is backed up and a temperature error is notified, making it easy to check the occurrence and cause of the malfunction and preventing the performance processor from breaking down. When a temperature error occurs in the performance control board 12 on which the performance control microcomputer 100A is provided, the temperature error information including date and time information is backed up and a temperature error is not notified, making it possible to check the occurrence and cause of the malfunction and preventing frequent error notifications. Note that the temperature error may be controlled to be notified when the board temperature error notification flag is on in step 05AKS155.

Figure 12-9 is a flowchart showing an example of a process that can be executed as the command analysis process S_COMMAND. The command analysis process S_COMMAND is called in the performance control timer interrupt process shown in Figure 12-7, and can be executed in step S75. By executing the command analysis process S_COMMAND in step S75 in the performance control timer interrupt process, the CPU 120A can execute settings and controls corresponding to the performance control command sent from the main board 11.

When the CPU 120A executes the command analysis process S_COMMAND shown in FIG. 12-9, it determines whether or not a received command is present by storing the received command in the command reception buffer (step 05AKS41). The command reception buffer is capable of storing performance control commands sent from the main board 11. Whether or not a received command is stored can be determined by comparing the value of the command reception number counter with the read pointer. If the two match, it is determined that no received command is present because no received command is stored (step 05AKS41; No), and the command analysis process S_COMMAND is terminated.

If there is a received command corresponding to step 05AKS41 (step 05AKS41; Yes), the received command is read from the command receiving buffer (step 05AKS42). Accordingly, the read pointer is updated (step 05AKS43). For example, the stored value of the read pointer may be updated to add 2. Then, it is determined whether the received command is a temperature display start command (step 05AKS44). The temperature display start command is a performance control command that specifies the start of displaying the temperature display screen by the image display device 5. The CPU 103 of the game control microcomputer 100 mounted on the main board 11 is capable of executing control to transmit a temperature display start command to the performance control board 12 when an action by a game center attendant that is preset in response to temperature display, such as a pressing operation for temperature display using the push button 31B, a specific operation for temperature display using an operating means other than the push button 31B, or an input operation for temperature display using any input means, is detected. If the received command is a temperature display start command in response to step 05AKS44 (step 05AKS44; Yes), the temperature display start command reception flag is set to the on state (step 05AKS45). Then, the process returns to step 05AKS41.

If the received command is not a temperature display start command (step 05AKS44; No), it is determined whether the received command is a temperature display end command (step 05AKS46). The temperature display end command is a performance control command that specifies the end of the display of the temperature display screen by the image display device 5. The CPU 103 of the game control microcomputer 100 mounted on the main board 11 may execute control to transmit a temperature display end command to the performance control board 12 when a preset action by an attendant of the game arcade corresponding to the end of the display, such as a pressing operation for ending the display by the push button 31B, a specific operation for ending the display by an operating means other than the push button 31B, or an input operation for ending the display by any input means, is detected. If the received command is a temperature display end command corresponding to step 05AKS46 (step 05AKS46; Yes), the temperature display end command reception flag is set to the on state (step 05AKS47). Then, return to step 05AKS41. If the received command in response to step 05AKS46 is not a command to end the temperature display (step 05AKS46; No), in response to receiving another command, the received performance control command is stored and a corresponding flag is set (step 05AKS48). Then, the process returns to step 05AKS41.

Figure 12-10 is a flow chart showing an example of a process that can be executed as the temperature display control process. The temperature display control process is called in the performance control timer interrupt process shown in Figure 12-7, and can be executed in step 05AKS32. By executing the temperature display control process of step 05AKS32 in the performance control timer interrupt process, the CPU 120A can control the display screen of the image display device 5 to display first temperature information related to the temperature detected by the processor temperature sensor 156, which serves as the first inspection means, and second temperature information related to the temperature detected by the board temperature sensor 160, which serves as the second detection means.

When the CPU 120A executes the temperature display control process, it determines whether the temperature display flag is on or not (step 05AKS61). The temperature display flag used in the determination of step 05AKS61 is stored in memory area 05AK103E. If the temperature display flag is off (step 05AKS61; No), it determines whether the temperature display start command reception flag is on or not (step 05AKS62). If the temperature display start command reception flag is off (step 05AKS62; No), it ends the temperature display control process.

If the temperature display start command reception flag is on in response to step 05AKS62 (step 05AKS62; Yes), the temperature display start command reception flag is cleared to an off state (step 05AKS63). In this case, current temperature data is acquired (step 05AKS64). The current temperature data acquired in step 05AKS64 may include the processor current temperature data stored in memory area 05AK101A and the board current temperature data stored in memory area 05AK101B. Next, maximum temperature data is acquired (step 05AKS65). The maximum temperature data acquired in step 05AKS65 may include the processor maximum temperature data stored in memory area 05AK102A and the board maximum temperature data stored in memory area 05AK102B.

After step 05AKS65, temperature display start control is performed (step 05AKS66). The temperature display start control of step 05AKS66 uses the current temperature data acquired in step 05AKS64 and the maximum temperature data acquired in step 05AKS65 to display a temperature display screen as the display screen of the image display device 5. The temperature display screen enables the processor current temperature information indicated in the processor current temperature data to be displayed as first temperature information acquired when a specified condition is met. The temperature display screen enables the board current temperature information indicated in the board current temperature data to be displayed as second temperature information acquired when a specified condition is met. The temperature display screen enables the processor maximum temperature information indicated in the processor maximum temperature data to be displayed as first temperature information indicating the maximum temperature acquired before the specified condition is met. The temperature display screen enables the board maximum temperature information indicated in the board maximum temperature data to be displayed as second temperature information indicating the maximum temperature acquired before the specified condition is met. Therefore, when a predetermined condition is met, for example, when a command to start displaying a temperature is received from the performance control board 12, the image display device 5 can display both the first temperature information and the second temperature information. In accordance with the control of step 05AKS66, the temperature display flag is set to the on state (step 05AKS67), and the temperature display control process is terminated.

If the temperature display flag is on in response to step 05AKS61 (step 05AKS61; Yes), it is determined whether the temperature display end command reception flag is on (step 05AKS68). If the temperature display end command reception flag is off (step 05AKS68; No), temperature display control is performed (step 05AKS69), and the temperature display control process is terminated. The temperature display control in step 05AKS69 may be a control that causes the temperature display screen to be continuously displayed on the image display device 5. In this case, when the storage of the current temperature data or the maximum temperature data is updated, new current temperature data or maximum temperature data may be obtained to update the display of temperature information on the temperature display screen. For example, the CPU 120A may read the processor current temperature data from the memory area 05AK101A and read the board current temperature data from the memory area 05AK101B every time 1 [s (seconds)] has elapsed, and update the display of the processor current temperature information and the board current temperature information on the temperature display screen. Furthermore, when the processor maximum temperature update flag or the board maximum temperature update flag is on, the CPU 120A may read the processor maximum temperature data stored in memory area 05AK102A or the board maximum temperature data stored in memory area 05AK102B, and update the display of the processor maximum temperature information or the board maximum temperature information on the temperature display screen.

When the temperature display end command reception flag is on in response to step 05AKS68 (step 05AKS68; Yes), the temperature display end command reception flag is cleared to an off state (step 05AKS70). In this case, temperature display end control is performed (step 05AKS71). For example, the CPU 120A sends a command to the VDP 123A to specify the end of displaying the temperature display screen by the image display device 5. The VDP 123A only needs to be able to execute image processing or the like to end the display of the temperature display screen in response to a command from the CPU 120A. As a result, when a specific condition is met that a temperature display end command has been received, the display of the processor current temperature information and processor maximum temperature information, which are the first temperature information, and the board current temperature information and board maximum temperature information, which are the second temperature information, can be ended. Therefore, when a specific condition is met, for example, when the power supply to the pachinko gaming machine 1 is not stopped and a command to end the temperature display is received from the performance control board 12, the image display device 5 hides the first temperature information and the second temperature information. In addition to the control of step 05AKS71, the temperature display flag is cleared to the off state (step 05AKS72), and the temperature display control process is terminated.

The temperature display start command and the temperature display end command may be transmitted by an inspection device as an external device that can be connected to the performance control board 12, unlike the main board 11. In this case, the temperature display start command and the temperature display end command may be included in an inspection control command for inspection that enables various inspection processes to be performed, unlike the game control command transmitted from the game control microcomputer 100 of the main board 11 to the performance control microcomputer 100A of the performance control board 12 as the game progresses. The inspection control command for inspection may have multiple types of orders predefined as the order of receiving multiple test commands predefined in correspondence with various check processes that are inspection processes, and one or multiple inspection processes may be performed in correspondence with the order of receiving a combination of multiple test commands. The temperature display control process shown in FIG. 12-10 may be included in an inspection process that can be executed in correspondence with the order of receiving a combination of multiple test commands. When receiving a combination of multiple test commands, a restriction may be set so that the inspection process is not executed if a command other than the test command corresponding to the inspection process is received, or if a combination of multiple test commands is received in an order other than the predetermined order corresponding to the inspection process. It is assumed that an information processing device other than the inspection device is connected as an external device and a command other than the predetermined multiple test commands is transmitted, or a combination of multiple test commands is transmitted in an order other than the predetermined order. In response to this, a restriction is set so that the inspection process is not executed, so that information related to the pachinko gaming machine 1 can be prevented from being illegally output and obtained.

Figure 12-11 is a sequence diagram showing a first processing example 05AKC01 for managing data and information relating to temperature in a pachinko gaming machine 1 of characteristic part 05AK. This first processing example 05AKC01 can be executed using temperature data 05AKA01, update flag 05AKA02, presentation control 05AKA03, temperature detection 05AKA04, and temperature sensor 05AKA05 as components for processing data and information relating to temperature.

The temperature data 05AKA01 can be configured in the temperature-related data storage area 05AK100 to include the processor current temperature data stored in the storage area 05AK101A, the board current temperature data stored in the storage area 05AK101B, the processor maximum temperature data stored in the storage area 05AK102A, and the board maximum temperature data stored in the storage area 05AK102B. The update flag 05AKA02 can be configured in the temperature-related data storage area 05AK100 to include the processor maximum temperature update flag stored in the storage area 05AK103A, and the board maximum temperature update flag stored in the storage area 05AK103B. The performance control 05AKA03 can be configured as a first thread by executing the performance control timer interrupt process shown in FIG. 12-7. The temperature detection 05AKA04 can be configured as a second thread by executing the temperature detection timer interrupt process shown in FIG. 12-4. Temperature sensor 05AKA05 can be configured to include a processor temperature sensor 156 built into the performance control microcomputer 100A, which serves as the performance processor, and a board temperature sensor 160 arranged at a predetermined position on the performance control board 12 outside the performance control microcomputer 100A.

When the CPU 120A of the performance control microcomputer 100A executes the temperature detection timer interrupt process shown in FIG. 12-4 at a second period, such as 1 s (seconds), it acquires processor temperature data in step 05AKS21. For example, the temperature detection 05AKA04 shown in FIG. 12-11 transmits a message that is a processor temperature request to the processor temperature sensor 156 included in the temperature sensor 05AKA05 (step 05AKP01). In response to the processor temperature request from the CPU 120A, the processor temperature sensor 156 of the temperature sensor 05AKA05 replies with a message that is a processor temperature response (step 05AKP02). As a result, the processor temperature data indicating the current processor temperature is acquired in the temperature detection 05AKA04. The message that is the processor temperature request by step 05AKP01 may be a read access from the CPU 120A to a data register built into the processor temperature sensor 156. In this case, the CPU 120A may output an address signal and a read control signal corresponding to the data register of the processor temperature sensor 156, and may be controlled to receive a data signal corresponding to the processor temperature data read from the data register of the processor temperature sensor 156.

CPU 120A, which executes the temperature detection timer interrupt process shown in FIG. 12-4, acquires substrate temperature data in step 05AKS22 following step 05AKS21. For example, temperature detection 05AKA04 shown in FIG. 12-11 transmits a message that serves as a substrate temperature request to substrate temperature sensor 160 included in temperature sensor 05AKA05 following step 05AKP02 (step 05AKP03). In response to the substrate temperature request from CPU 120A, substrate temperature sensor 160 of temperature sensor 05AKA05 returns a message that serves as a substrate temperature response (step 05AKP04). As a result, substrate temperature data indicating the current substrate temperature is acquired in temperature detection 05AKA04. The message that serves as a substrate temperature request in step 05AKP03 may be a read access from CPU 120A to a data register built into substrate temperature sensor 160. In this case, the CPU 120A may output an address signal and a read control signal corresponding to the data register of the substrate temperature sensor 160, and may control the substrate temperature sensor 160 to receive a data signal corresponding to the substrate temperature data read from the data register of the substrate temperature sensor 160.

The CPU 120A executing the temperature detection timer interrupt process shown in FIG. 12-4 stores the current temperature data in step 05AKS23 after step 05AKS22. For example, the temperature detection 05AKA04 shown in FIG. 12-11 sends a message to the temperature-related data storage area 05AK100 in which the temperature data 05AKA01 is stored, to store the current temperature data (step 05AKP05). In this case, the processor temperature data acquired by the temperature detection 05AKA04 in step 05AKP02 is stored as the processor current temperature data in storage area 05AK101A. Also, the substrate temperature data acquired by the temperature detection 05AKA04 in step 05AKP04 is stored as the substrate current temperature data in storage area 05AK101B. The message that stores the current temperature data in step 05AKP05 may include a data signal corresponding to the processor temperature data when CPU 120A outputs an address signal or a storage control signal corresponding to storage area 05AK101A. The message that stores the current temperature data in step 05AKP05 may include a data signal corresponding to the substrate temperature data when CPU 120A outputs an address signal or a storage control signal corresponding to storage area 05AK101B.

In the temperature detection timer interrupt process shown in FIG. 12-4, a restriction is set so that the processor temperature data acquired in step 05AKS21 is not stored in memory area 101A until the substrate temperature data is acquired in step 05AKS22. The acquisition of substrate temperature data in step 05AKS22 requires a certain period of time, such as a waiting period of up to 1 s (seconds). If the processor temperature data acquired in step 05AKS21 is stored in memory area 101A as the processor current temperature data before this waiting period has elapsed, the difference in storage timing between the substrate current temperature data in memory area 101B and the data may become large, and the current temperature may become a temporarily deviated value. In response to this, as the information storage process in step 05AKS23, after the information acquisition process in steps 05AKS21 and 05AKS22, both the processor current temperature data and the substrate current temperature data, which become the current temperature data, are stored, thereby synchronizing the storage of information related to the current temperature. In this way, by synchronizing the timing of storing temperature-related information, temperature-related information can be managed appropriately.

The temperature detection timer interrupt processing shown in FIG. 12-4 includes a temperature detection judgment processing of step 05AKS24. The CPU 120A executing the temperature detection judgment processing shown in FIG. 12-5 judges that the current temperature has exceeded the maximum temperature in response to the case where the current processor temperature has exceeded the maximum processor temperature in step 05AKS103 and the case where the current board temperature has exceeded the maximum board temperature in step 05AKS111. In response to these, the temperature detection 05AKA04 shown in FIG. 12-11 adds 1 to the count value of the update counter when the current temperature exceeds the maximum temperature (step 05AKP06). The update counters that can add a count value in step 05AKP06 include an update counter for the processor and an update counter for the board. In the temperature detection judgment process shown in FIG. 12-5, if it is determined in step 05AKS103 that the current temperature has exceeded the maximum temperature, the count value of the processor update counter is incremented by 1 in step 05AKS104. In the temperature detection judgment process shown in FIG. 12-5, if it is determined in step 05AKS111 that the current temperature has exceeded the maximum temperature, the count value of the board update counter is incremented by 1 in step 05AKS112.

The CPU 120A executing the temperature detection judgment process shown in FIG. 12-5 judges that the update counter has matched the maximum update judgment value when the count value of the processor update counter matches the maximum update judgment value in step 05AKS106 and when the count value of the board update counter matches the maximum update judgment value in step 05AKS114. In response to these, the temperature detection 05AKA04 shown in FIG. 12-11 sets the update flag 05AKA02 to the on state when the update counter reaches the maximum update judgment value (step 05AKP07). The update flag 05AKA02 that can be set by step 05AKP07 includes the processor maximum temperature update flag stored in memory area 05AK103A and the board maximum temperature update flag stored in memory area 05AK103B. When the CPU 120A that executes the temperature detection judgment process shown in FIG. 12-5 determines in step 05AKS106 that the judgment value matches, it sets the processor maximum temperature update flag to the ON state in step 05AKS107. When the CPU 120A that executes the temperature detection judgment process shown in FIG. 12-5 determines in step 05AKS114 that the judgment value matches, it sets the board maximum temperature update flag to the ON state in step 05AKS115.

The CPU 120A executing the temperature detection judgment process shown in FIG. 12-5 stores and saves the processor maximum temperature data in memory area 102A in step 05AKS108 following step 05AKS107, and stores and saves the board maximum temperature data in memory area 102B in step 05AKS116 following step 05AKS115. Correspondingly, following step 05AKP07, the temperature detection 05AKA04 shown in FIG. 12-11 sends a message to the temperature-related data memory area 05AK100 in which the temperature data 05AKA01 is stored, indicating that the maximum temperature data will be stored (step 05AKP08). In this case, the processor temperature data acquired by the temperature detection 05AKA04 in step 05AKP02 is stored as the processor maximum temperature data in memory area 05AK102A. In addition, the substrate temperature data acquired by the temperature detection 05AKA04 in step 05AKP04 is stored as substrate maximum temperature data in the storage area 05AK102B. The message for storing maximum temperature data in step 05AKP08 may include a data signal corresponding to the processor temperature data when the CPU 120A outputs an address signal or a storage control signal corresponding to the storage area 05AK102A. The message for storing maximum temperature data in step 05AKP08 may include a data signal corresponding to the substrate temperature data when the CPU 120A outputs an address signal or a storage control signal corresponding to the storage area 05AK102B. The CPU 120A executing the temperature detection determination process shown in FIG. 12-5 clears the processor update counter in step 05AKS109 following step 05AKS108, and clears the substrate update counter in step 05AKS117 following step 05AKS116. In response to this, the temperature detector 05AKA04 shown in FIG. 12-11 clears the update counters after step 05AKP08 (step 05AKP09). The update counters that can be cleared by step 05AKP09 include the processor update counter and the board update counter.

The CPU 120A executing the temperature detection judgment process shown in FIG. 12-5 judges that the current temperature does not exceed the maximum temperature in response to the case where the processor current temperature does not exceed the processor maximum temperature in step 05AKS103 and the case where the board current temperature does not exceed the board maximum temperature in step 05AKS111. In response to these, the temperature detection 05AKA04 shown in FIG. 12-11 clears the update counter when the current temperature does not exceed the maximum temperature (step 05AKP10). The update counters that can be cleared in step 05AKP10 include the processor update counter and the board update counter. In the temperature detection judgment process shown in FIG. 12-5, when it is determined in step 05AKS103 that the current temperature does not exceed the maximum temperature, the processor update counter is cleared in step 05AKS109. In the temperature detection judgment process shown in FIG. 12-5, if step 05AKS111 determines that the current temperature does not exceed the maximum temperature, the board update counter is cleared in step 05AKS117.

In this way, the CPU 120A that executes the temperature detection judgment process shown in FIG. 12-5 can execute the temperature detection judgment process included in the temperature detection timer interrupt process, which is the second process, in the second cycle. The temperature detection judgment process included in the second process can store information about the temperature detected by the detection means, such as the processor temperature sensor 156 and the substrate temperature sensor 160, in the temperature-related data storage area 05AK100 provided in the storage means, such as the internal RAM 122A. In addition, the temperature detection judgment process included in the second process can execute a judgment process and a storage process. The judgment process here can determine whether the current processor temperature detected by the processor temperature sensor 156 or the current substrate temperature detected by the substrate temperature sensor 160, as the temperature detected by the detection means, exceeds the maximum temperature. In the storage process here, when it is determined that the processor current temperature or the substrate current temperature exceeds the maximum temperature, the processor maximum temperature data corresponding to the information indicating the processor maximum temperature can be stored in the storage area 05AK102A as new special temperature information, and the substrate maximum temperature data corresponding to the information indicating the substrate maximum temperature can be stored in the storage area 05AK102B. The temperature detection determination process included in the second process can acquire data corresponding to both of the temperature information, the processor current temperature data indicating the processor current temperature detected by the processor temperature sensor 156 corresponding to the first temperature information indicating the first temperature, and the substrate current temperature data indicating the substrate current temperature detected by the substrate temperature sensor 160 corresponding to the second temperature information indicating the second temperature, in a second period, and store the data in the storage areas 05AK101A and 05AK101B. The temperature detection determination process included in the second process makes it possible to execute the information acquisition process and the information storage process. In the information acquisition process here, after acquiring processor temperature data from the processor temperature sensor 156 in response to the first temperature information within the second period, substrate temperature data can be acquired from the substrate temperature sensor 160 in response to the second temperature information. In the information storage process here, after the information acquisition process, both the processor temperature data corresponding to the first temperature information and the substrate temperature data corresponding to the second temperature information can be stored in the memory area 05AK101A and the memory area 05AK101B as the processor current temperature data and the substrate current temperature data. In addition, when the count value by the update counter matches the maximum update judgment value, both or one of the processor temperature data corresponding to the first temperature information and the substrate temperature data corresponding to the second temperature information can be stored in both or one of the memory areas 05AK102A and 05AK102B as both or one of the processor maximum temperature data and the substrate maximum temperature data.

The temperature detection timer interrupt process, which is the second process, is set to a lower priority than the performance control timer interrupt process, which is the first process. Therefore, if a performance control timer interrupt occurs during the execution of the temperature detection timer interrupt process, the temperature detection timer interrupt process is interrupted and the performance control timer interrupt process is started. Then, when the performance control timer interrupt process ends, the temperature detection timer interrupt process can be resumed. The performance control timer interrupt process can be executed in a first cycle, for example, 1 ms (milliseconds), but the process can be completed in a period shorter than the first cycle. Therefore, after the execution of the performance control timer interrupt process ends, the temperature detection timer interrupt process can be resumed and the remaining process can be progressed during the period until the next performance control timer interrupt occurs due to the passage of the period corresponding to the first cycle.

Figure 12-12 is a sequence diagram showing a second processing example 05AKC02 for managing data and information related to temperature in a pachinko gaming machine 1 of the characteristic part 05AK. This second processing example 05AKC02 can be executed using temperature data 05AKA01, update flag 05AKA02, performance control 05AKA03, and temperature detection 05AKA04 as components common to the first processing example 05AKC01. In addition, the second processing example 05AKC02 can be executed using backup data 05AKA06 as a component different from the first processing example 05AKC01. The backup data 05AKA06 is stored in the backup data memory 210 and is the target data of backup storage that can retain the memory contents even if the power supply is stopped. Note that the second processing example 05AKC02 may be executed without using temperature detection 05AKA04, which is the second thread. The first processing example 05AKC01 shown in FIG. 12-11 may be executable without using the performance control 05AKA03, which is the first thread. In this way, the second processing example 05AKC02 may be executable using components in common with the first processing example 05AKC01 and components that are different from the first processing example 05AKC01.

The CPU 120A of the performance control microcomputer 100A can execute the temperature monitoring process of step 05AKS31 when the performance control timer interrupt process shown in FIG. 12-7 is executed at a first period, for example, 1 ms (milliseconds). The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 performs a flag check to check the update flag in response to the case where the processor maximum temperature update flag is determined to be on or not in step 05AKS141 and the case where the board maximum temperature update flag is determined to be on or not in step 05AKS146. In response to these, the performance control 05AKA03 shown in FIG. 12-12 transmits a message that is a flag check for the update flag 05AKA02 (step 05AKP21). The update flag 05AKA02 that can be checked by step 05AKP21 includes the processor maximum temperature update flag stored in the memory area 05AK103A and the board maximum temperature update flag stored in the memory area 05AK103B. The processor maximum temperature update flag and the board maximum temperature update flag are stored in the memory area 05AK103A or memory area 05AK103B of the temperature related data memory area 05AK100 by the temperature detection judgment process of step 05AKS24 in the temperature detection timer interrupt process, which is the second process, and are included in the information about temperature. Therefore, the CPU 120A that executes the temperature monitoring process of step 05AKS31 in the performance control timer interrupt process can execute the performance control timer interrupt process, which is the first process related to the control of the performance, in the first period, and can monitor the information about temperature stored by the temperature detection judgment process of step 05AKS24 in the temperature detection timer interrupt process, which is the second process. The message that is the flag confirmation of step 05AKP21 may be a read access from the CPU 120A to the memory area 05AK103A or memory area 05AK103B. In this case, the CPU 120A may output an address signal and a read control signal corresponding to the memory area 05AK103A, and may control so as to be able to receive a data signal corresponding to the maximum processor temperature update flag read from the memory area 05AK103A. The CPU 120A may output an address signal and a read control signal for the memory area 05AK103B, and may control so as to be able to receive a data signal corresponding to the maximum board temperature update flag read from the memory area 05AK103B.

The CPU 120A executing the temperature monitoring process shown in Figure 12-8 determines that the update flag is on when the processor maximum temperature update flag is on in step 05AKS141 and when the board maximum temperature update flag is on in step 05AKS146. In response to these, when the update flag is on, the performance control 05AKA03 shown in Figure 12-12 sends a message to the temperature-related data memory area 05AK100 in which the temperature data 05AKA01 is stored to acquire maximum temperature data (step 05AKP22). The maximum temperature data that can be acquired by step 05AKP22 includes the processor maximum temperature data stored in memory area 05AK102A and the board maximum temperature data stored in memory area 05AK102B. The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 acquires the processor maximum temperature data in step 05AKS142 when it is determined in step 05AKS141 that the processor maximum temperature update flag is on. The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 acquires the substrate maximum temperature data in step 05AKS147 when it is determined in step 05AKS146 that the substrate maximum temperature update flag is on. The message for acquiring the maximum temperature data in step 05AKP22 may be a read access from the CPU 120A to the memory area 05AK102A or the memory area 05AK102B. In this case, the CPU 120A may output an address signal and a read control signal corresponding to the memory area 05AK102A, and control so as to be able to receive a data signal corresponding to the processor maximum temperature data read from the memory area 05AK102A. The CPU 120A may output an address signal and a read control signal corresponding to the memory area 05AK102B, and may be controlled to receive a data signal corresponding to the maximum substrate temperature data read from the memory area 05AK102B.

The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 performs maximum temperature backup in response to the case where processor maximum temperature backup control is performed in step 05AKS143 following step 05AKS142, and the case where substrate maximum temperature backup control is performed in step 05AKS148 following step 05AKS147. When processor maximum temperature backup control is performed in step 05AKS143, it is determined in step 05AKS144 whether backup storage of the corresponding number of blocks has been completed, and the processor maximum temperature backup control of step 05AKS143 continues until completion. When substrate maximum temperature backup control is performed in step 05AKS148, it is determined in step 05AKS149 whether backup storage of the corresponding number of blocks has been completed, and the substrate maximum temperature backup control of step 05AKS148 continues until completion. In response to these, the performance control 05AKA03 shown in FIG. 12-12 transmits a message indicating the highest temperature backup to the backup data memory 210 of the backup memory board 16 in which the backup data 05AKA06 is stored until the backup storage of the number of blocks corresponding to the degree of multiplicity is completed (step 05AKP23). The message indicating the highest temperature backup in step 05AKP23 may include a data signal corresponding to the processor maximum temperature data when the CPU 120A outputs a backup control signal of the processor maximum temperature to the memory controller 200 of the backup memory board 16, and a data signal corresponding to the date and time data acquired by the memory controller 200 from the RTC 201. The message indicating the highest temperature backup in step 05AKP23 may include a data signal corresponding to the board maximum temperature data when the CPU 120A outputs a backup control signal of the board maximum temperature to the memory controller 200 of the backup memory board 16, and a data signal corresponding to the date and time data acquired by the memory controller 200 from the RTC 201.

When the CPU 120A executing the temperature monitoring process shown in FIG. 12-8 determines in step 05AKS144 that the corresponding number of blocks has been completed, it clears the processor maximum temperature update flag in memory area 05AK103A to the OFF state in step 05AKS145. When the CPU 120A executing the temperature monitoring process shown in FIG. 12-8 determines in step 05AKS149 that the corresponding number of blocks has been completed, it clears the board maximum temperature update flag in memory area 05AK103B to the OFF state in step 05AKS150. In response to this, the performance control 05AKA03 shown in FIG. 12-12 sends a message to clear the update flag 05AKA02 (step 05AKP24). The update flag 05AKA02 that can be cleared by step 05AKP24 includes a processor maximum temperature update flag stored in memory area 05AK103A and a board maximum temperature update flag stored in memory area 05AK103B.

The CPU 120A that executes the timer interrupt process for performance control shown in FIG. 12-7 can execute the backup process during performance control in step 05AKS33. The CPU 120A that executes the backup process during performance control in step 05AKS33 performs various data backups when the backup conditions are met. In response to this, the performance control 05AKA03 shown in FIG. 12-12 transmits a message that serves as various data backup to the backup data memory 210 of the backup memory board 16 in which the backup data 05AKA06 is stored (step 05AKP25). The message that serves as various data backup in step 05AKP25 may include a data signal corresponding to the backup target data and a data signal corresponding to the date and time data acquired by the memory controller 200 from the RTC 201 when the CPU 120A outputs a backup control signal corresponding to the backup target data for which the backup conditions are met to the memory controller 200 of the backup memory board 16.

In this way, the CPU 120A executing the temperature monitoring process shown in FIG. 12-8 can execute the temperature monitoring process included in the performance control timer interrupt process, which is the first process, in the first cycle. The performance control timer interrupt process, which is the first process, is a process related to the control of the performance. The temperature monitoring process included in the first process can monitor the processor maximum temperature update flag in memory area 05AK103A and the board maximum temperature update flag in memory area 05AK103B, etc., as information related to the temperature stored in the temperature-related data memory area 05AK100 by the temperature detection time judgment process included in the second process. The performance control timer interrupt process, which is the first process, is set to a higher priority than the temperature detection timer interrupt process, which is the second process. Also, the first cycle in which the performance control timer interrupt process can be executed is set to a shorter cycle than the second cycle in which the temperature detection timer interrupt process can be executed. In this way, by making it possible to execute the second process capable of storing information related to temperature and the first process related to controlling the presentation, the processing load related to temperature and control can be distributed and reduced, preventing delays and control malfunctions in the control-related processing, and enabling appropriate control.

The temperature monitoring process included in the first process includes a backup process. In the backup process here, when processor maximum temperature data corresponding to information indicating the processor maximum temperature or board maximum temperature data corresponding to information indicating the board maximum temperature is stored as new special temperature information in the temperature-related data storage area 05AK100 provided in a storage means such as the internal RAM 122A, the processor maximum temperature data or board maximum temperature data corresponding to the special temperature information can be stored in the backup data memory 210 serving as a backup storage means. The backup target data corresponding to the special temperature information stored in such backup data memory 210 may include processor maximum temperature data corresponding to processor maximum temperature information indicating the temperature detected by the processor temperature sensor 156 when the processor maximum temperature is exceeded, and date and time data acquired from the RTC 201 corresponding to date and time information indicating the date and time when the temperature was detected by the processor temperature sensor 156. Alternatively, the backup target data corresponding to the special temperature information stored in the backup data memory 210 may include maximum board temperature data corresponding to maximum board temperature information indicating the temperature detected by the board temperature sensor 160 when the maximum board temperature is exceeded, and date and time data acquired from the RTC 201 corresponding to date and time information indicating the date and time when the temperature was detected by the board temperature sensor 160. The maximum processor temperature data stored in the memory area 05AK102A corresponds to the maximum processor temperature information indicating the maximum processor temperature as the maximum temperature among the first temperature information indicating the first temperature regarding the performance control microcomputer 100A serving as the performance control means based on the temperature detected by the processor temperature sensor 156 serving as the first detection means. The maximum board temperature data stored in the memory area 05AK102B corresponds to the maximum board temperature information indicating the maximum board temperature as the maximum temperature among the second temperature information indicating the second temperature regarding the performance control board 12 serving as the board on which the performance control microcomputer 100A serving as the performance control means is provided based on the temperature detected by the board temperature sensor 160 serving as the second detection means. The temperature monitoring process included in the first process can monitor both the processor maximum temperature data stored in memory area 05AK102A and the substrate maximum temperature data stored in memory area 05AK102B in a first cycle by determining using the processor maximum temperature update flag and the substrate maximum temperature update flag.

Figure 12-13 shows a setting example 05AKM01 of data to be backed up. In the temperature monitoring process shown in Figure 12-8, maximum processor temperature data and date and time data are specified in response to the maximum processor temperature backup control of step 05AKS143, and maximum substrate temperature data and date and time data are specified in response to the maximum substrate temperature backup control of step 05AKS148. In the temperature monitoring process shown in Figure 12-8, when backup control at the time of a processor temperature error of step 05AKS152 is performed, date and time data corresponding to a processor temperature error is specified as data to be backed up. The date and time data corresponding to a processor temperature error is also called processor temperature error date and time data. In the temperature monitoring process shown in Figure 12-8, when backup control at the time of a substrate temperature error of step 05AKS156 is performed, date and time data corresponding to a substrate temperature error is specified as data to be backed up. The date and time data corresponding to a substrate temperature error is also called substrate temperature error date and time data.

The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 can execute the maximum processor temperature backup control in step 05AKS143 in response to the determination in step 05AKS141 that the processor maximum temperature update flag is on. Therefore, the backup conditions for the processor maximum temperature data and the date and time data are established when the processor maximum temperature is updated, and the data are backed up and stored as data to be backed up. The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 can execute the maximum substrate temperature backup control in step 05AKS148 in response to the determination in step 05AKS146 that the substrate maximum temperature update flag is on. Therefore, the backup conditions for the substrate maximum temperature data and the date and time data are established when the substrate maximum temperature is updated, and the data are backed up and stored as data to be backed up. The CPU 120A executing the temperature monitoring process shown in FIG. 12-8 can execute the processor temperature error backup control in step 05AKS152 in response to the determination in step 05AKS151 that the processor temperature error notification flag is on. Therefore, the backup condition is met when a processor temperature error occurs, and the processor temperature error date and time data is backed up and stored as the data to be backed up. The CPU 120A that executes the temperature monitoring process shown in FIG. 12-8 can execute backup control in the event of a substrate temperature error in step 05AKS156 in response to the determination in step 05AKS155 that the substrate temperature error notification flag is on. Therefore, the backup condition is met when a substrate temperature error occurs, and the substrate temperature error date and time data is backed up and stored as the data to be backed up.

When executing the maximum processor temperature backup control of step 05AKS143, the CPU 120A that executes the temperature monitoring process shown in FIG. 12-8 sets mirroring to ON and multiplicity to 3, since the data to be backed up is maximum processor temperature data and date and time data. When executing the maximum substrate temperature backup control of step 05AKS148, the CPU 120A that executes the temperature monitoring process shown in FIG. 12-8 sets mirroring to ON and multiplicity to 3, since the data to be backed up is maximum substrate temperature data and date and time data. When executing the processor temperature error backup control of step 05AKS152, the CPU 120A that executes the temperature monitoring process shown in FIG. 12-8 sets no mirroring and multiplicity to 1, since the data to be backed up is processor temperature error date and time data. When executing the substrate temperature error backup control of step 05AKS156, the CPU 120A that executes the temperature monitoring process shown in FIG. 12-8 sets no mirroring and multiplicity to 1, since the data to be backed up is substrate temperature error date and time data. In this way, it would be good if you could set whether or not to mirror and the degree of multiplicity according to the specified data to be backed up.

When the power supply is started by turning on the pachinko game machine 1, the temperature-related data storage area 05AK100 may be initialized using information on the maximum temperature that is backed up and stored. For example, the CPU 120A that executes the main processing S_MAIN for performance control shown in FIG. 12-2 (A) may set the maximum temperature information in the power-on information processing S_STRINF of step 05AKS01. This maximum temperature setting includes setting the maximum processor temperature data in the storage area 05AK102A and setting the maximum board temperature data in the storage area 05AK102B. The maximum processor temperature data setting may be obtained by reading out the latest maximum processor temperature data that was last backed up and stored among the maximum processor temperature data backed up and stored in the backup data memory 210, and may be stored in the storage area 05AK102A. The CPU 120A may output a read control signal for the maximum processor temperature to the memory controller 200 of the backup memory board 16, and may be able to obtain the latest maximum processor temperature data read out from the backup data memory 210. The setting of the maximum board temperature data may be performed by reading and acquiring the most recent maximum board temperature data that was last backed up among the maximum board temperature data backed up and stored in the backup data memory 210, and storing it in the memory area 05AK102B. The CPU 120A may output a read control signal for the maximum board temperature to the memory controller 200 of the backup memory board 16, and may acquire the most recent maximum board temperature data read from the backup data memory 210. In this way, the CPU 120A of the performance control microcomputer 100A, which serves as the processing means, can execute a start-time storage process in which the processor maximum temperature data and the maximum board temperature data corresponding to the special temperature information read from the backup data memory 210, which serves as the backup storage means, are stored in the storage areas 05AK102A and 05AK102B of the temperature-related data storage area 05AK100 provided in the storage means such as the internal RAM 122A when the power supply to the pachinko game machine 1 is stopped. This makes it possible to appropriately manage information related to temperature and prevent malfunctions from occurring.

The CPU 120A executing the power-on information processing S_STRINF in step 05AKS01 may be capable of executing different maximum temperature information settings in response to the processor maximum temperature data and the board maximum temperature data corresponding to the special temperature information backed up and stored in the backup data memory 210. In this case, the CPU 120A judges whether the processor maximum temperature indicated in the processor maximum temperature data read and acquired from the backup data memory 210, for example, exceeds the upper limit temperature for use preset in response to the processor temperature error. The CPU 120A also judges whether the board maximum temperature indicated in the board maximum temperature data read and acquired from the backup data memory 210, for example, exceeds the upper limit temperature for use preset in response to the board temperature error. The upper limit temperature for use preset in response to the processor temperature error and the upper limit temperature for use preset in response to the board temperature error may be set to a common temperature, for example, 100 degrees Celsius. Alternatively, different temperatures may be set, for example, the upper limit temperature for use preset in response to the processor temperature error is 100 degrees Celsius, and the upper limit temperature for use preset in response to the board temperature error is 80 degrees Celsius. It is sufficient that the processor maximum temperature data indicating a temperature preset as the processor maximum temperature initial value can be stored in the memory area 05AK102A when the acquired processor maximum temperature exceeds the upper limit temperature. It is sufficient that the substrate maximum temperature data indicating a temperature preset as the substrate maximum temperature initial value can be stored in the memory area 05AK102B when the acquired substrate maximum temperature exceeds the upper limit temperature. The processor maximum temperature initial value and the substrate maximum temperature initial value may both be set to a common temperature, for example, 50 degrees Celsius. Alternatively, different temperatures may be set, for example, the processor maximum temperature initial value being 60 degrees Celsius and the substrate maximum temperature initial value being 50 degrees Celsius. In this way, the CPU 120A of the performance control microcomputer 100A, which serves as a processing means, may acquire maximum processor temperature data and maximum board temperature data corresponding to the special temperature information from the backup data memory 210, which serves as a backup storage means, when the power supply to the pachinko gaming machine 1 is stopped, and may store maximum processor temperature data and maximum board temperature data indicating different initial temperature information in memory area 05AK102A or memory area 05AK102B of the temperature-related data storage area 05AK100 provided in a storage means such as the internal RAM 122A, depending on whether the acquired special temperature information indicates a temperature abnormality.

Figure 12-14 (A) shows a display example 05AKD01 of the temperature error notification screen. The temperature error notification screen can be displayed as a display screen of the image display device 5 by the temperature error notification start control of step 05AKS153 when it is determined that the processor temperature error notification flag is on in step 05AKS151 of the temperature monitoring process shown in Figure 12-8. The processor temperature error notification flag can be stored in the memory area 05AK103C as information related to the temperature stored in the temperature related data memory area 05AK100 provided in a memory means such as the internal RAM 122A. After it is determined that the processor temperature is in a temperature error state in step 05AKS203 of the temperature error determination process shown in Figure 12-6, such a processor temperature error notification flag is set to the on state in step 05AKS207 in response to the determination in step 05AKS206 that the count value of the processor temperature error determination counter matches the temperature error determination value. The temperature error determination process shown in FIG. 12-6 can be executed in step 05AKS118 of the temperature detection determination process shown in FIG. 12-5, and the temperature detection determination process shown in FIG. 12-5 can be executed in step 05AKS24 of the temperature detection timer interrupt process, which is the second process shown in FIG. 12-4. Therefore, the temperature error determination process included in the second process can set the processor temperature error notification flag to an on state as information stored in a storage means such as the internal RAM 122.

The temperature error notification screen of the display example 05AKD01 includes a display of the notification information image 05AKG01. The display of the notification information image 05AKG01 shows temperature abnormality information corresponding to the occurrence of a temperature error related to the performance control microcomputer 100A, which is the performance processor. The temperature error notification screen including the display of the notification information image 05AKG01 can display and notify temperature abnormality information corresponding to the occurrence of a processor temperature error. Therefore, the image display device 5 can display a temperature error notification screen including temperature abnormality information when the temperature detected by the processor temperature sensor 156 included in the detection means is an abnormal temperature in response to the processor temperature error notification flag being on. This makes it easy to check the occurrence and cause of the malfunction. The temperature error notification including the display of temperature abnormality information by the temperature error notification screen such as the display example 05AKD01 ends when the power supply to the pachinko game machine 1 is stopped due to a power cut. That is, if the power supply to the pachinko gaming machine 1 is stopped while the image display device 5 is displaying a temperature error notification screen including the temperature abnormality information, the image display device 5 does not display the temperature abnormality information. This prevents games or performances from being played in a state where a temperature error has occurred, and thus prevents malfunctions from occurring.

Figure 12-14 (B) shows a display example 05AKD02 of the temperature display screen. The temperature display screen can be displayed as the display screen of the image display device 5 by the temperature display start control of step 05AKS66 when it is determined that the temperature display start command reception flag is on by step 05AKS62 of the temperature display control process shown in Figure 12-10. The temperature display start command reception flag is set to the on state by step 05AKS45 in response to the reception of the temperature display start command by step 05AKS44 of the command analysis process S_COMMAND shown in Figure 12-9. Therefore, the image display device 5 can display the temperature display screen when a predetermined condition is met, such as the reception of a temperature display start command transmitted from the main board 11 or the like. The temperature display screen of the display example 05AKD02 includes the display of the current temperature information image 05AKG11 and the display of the maximum temperature information image 05AKG12. The current temperature information image 05AKG11 and maximum temperature information image 05AKG12 may be displayed as an overlay on the normal screen of the image display device 5.

The display of the current temperature information image 05AKG11 includes, as information related to the current temperature, a display of processor current temperature information, which is the first temperature information indicated in the processor temperature data acquired from the processor temperature sensor 156, and a display of substrate current temperature information, which is the second temperature information indicated in the substrate temperature data acquired from the substrate temperature sensor 160. The temperature display control process shown in FIG. 12-10 acquires the current temperature data in step 05AKS64, and then performs the temperature display start control in step 05AKS66, thereby making it possible to display the processor current temperature information corresponding to the processor temperature data acquired when a predetermined condition for starting the display of the temperature display screen is met, and the substrate current temperature information corresponding to the substrate temperature data. The display of the maximum temperature information image 05AKG12 includes, as information related to the maximum temperature, a display of processor maximum temperature information, which is the first temperature information indicated in the processor maximum temperature data acquired from memory area 05AK102A, and a display of substrate maximum temperature information, which is the second temperature information indicated in the substrate maximum temperature data acquired from memory area 05AK102B. The temperature display control process shown in FIG. 12-10 performs temperature display start control in step 05AKS66 after acquiring maximum temperature data in step 05AKS65, thereby making it possible to display maximum processor temperature information corresponding to maximum processor temperature data acquired before the establishment of a predetermined condition for starting the display of the temperature display screen, and maximum board temperature information corresponding to maximum board temperature data. Therefore, when a predetermined condition is established, the image display device 5 can display current processor temperature information and current board temperature information, which are the first and second temperature information acquired at the time the predetermined condition is established, and can display maximum processor temperature information and maximum board temperature information, which are the first and second temperature information indicating the maximum temperature acquired before the predetermined condition is established. This makes it easy to check the cause of a malfunction that occurs. It also makes it possible to check the temperature appropriately.

Temperature information notification, including the display of the first temperature information and the second temperature information by a temperature display screen such as display example 05AKD02, ends when the power supply to the pachinko gaming machine 1 is not stopped due to a power outage and a specific condition is met. The temperature display screen can be erased from the display screen of the image display device 5 by the temperature display end control of step 05AKS71 when it is determined in step 05AKS68 of the temperature display control process shown in FIG. 12-10 that the temperature display end command reception flag is on. The temperature display end command reception flag is set to the on state in step 05AKS47 in response to the reception of the temperature display end command in step 05AKS46 of the command analysis process S_COMMAND shown in FIG. 12-9. Therefore, when the image display device 5 displays a temperature display screen including the first temperature information and the second temperature information, if a specific condition is met, such as when the power supply to the pachinko gaming machine 1 is not stopped and a temperature display end command transmitted from the main board 11 or the like is received, the image display device 5 hides the first temperature information and the second temperature information.

(Modifications regarding characteristic portion 05AK)
In addition to the board temperature sensor 160, or instead of the board temperature sensor 160, a temperature sensor capable of detecting the temperature of any electronic component or other component included in the pachinko game machine 1 may be provided. For example, a drive unit temperature sensor capable of detecting temperature may be provided in the motor or solenoid of the movable body 32. In this case, a memory area capable of storing drive unit current temperature data and drive unit maximum temperature data in response to information on the temperature detected by the drive unit temperature sensor may be provided, and drive unit temperature data related to the temperature detected by the drive unit temperature sensor may be stored in the memory area in the temperature detection timer interrupt process, similar to the board temperature data related to the temperature detected by the board temperature sensor 160. In addition, in the performance control timer interrupt process, information on the temperature detected by the drive unit temperature sensor may be monitored in the same manner as the board temperature information related to the temperature detected by the board temperature sensor 160. In addition, information on the temperature detected by any temperature sensor may be stored by the temperature detection timer interrupt process, which is the second process, and may be monitored by the performance control timer interrupt process, which is the first process.

Either or both of the processing of data or information corresponding to the update of the maximum temperature or the occurrence of a temperature error may be included in the performance control timer interrupt processing. In this case, for example, the temperature-related data storage area 05AK100 includes a storage area for a current temperature update flag. When the current temperature data is stored by step 05AKS23, the CPU 120A executing the temperature detection timer interrupt processing shown in FIG. 12-4 sets the current temperature update flag to an on state. In addition, while the temperature detection timer interrupt processing shown in FIG. 12-4 does not include the temperature detection judgment processing of step 05AKS24, the performance control timer interrupt processing shown in FIG. 12-7 makes it possible to execute a judgment processing similar to the temperature detection judgment processing. For example, the CPU 120A executing the temperature monitoring processing shown in FIG. 12-8 judges whether the current temperature update flag is on or not before step 05AKS141. If the current temperature update flag is on, the current temperature update flag is cleared to the off state, and a judgment process similar to the temperature detection judgment process is executed using the processor current temperature data read and acquired from the memory area 101A and the board current temperature data read and acquired from the memory area 101B. This judgment process may include the temperature error judgment process executed in step 05AKS118 of the temperature detection judgment process shown in FIG. 12-5, or it may not include the temperature error judgment process. The temperature error judgment process may be included in the temperature detection timer interrupt process or may be included in the performance control timer interrupt process. In this way, the temperature detection timer interrupt process, which is the second process related to temperature detection, may include a judgment process related to updating the maximum temperature or the occurrence of a temperature error, or it may not include one or both. The performance control timer interrupt process, which is the first process related to performance control, may include one or both of the judgment processes related to updating the maximum temperature and the occurrence of a temperature error.

The second process executable in the second cycle is not limited to a timer interrupt process for temperature detection capable of storing information related to temperature, but may be a process capable of storing any information. For example, a process capable of storing information related to the detection result for any physical quantity detectable in the pachinko gaming machine 1, such as voltage, current, position, amount of movement, speed, weight, time, or a combination of all or part of these, may be executable as the second process in the second cycle. In this case, the first process executable in the first cycle is a timer interrupt process for performance control related to the control of the performance, and the first process may be set to a higher priority than the second process, and the first cycle may be set to a shorter cycle than the second cycle. The timer interrupt process for performance control, which is the first process, may be capable of monitoring information related to the detection result stored by the second process.

The first process executable in the first cycle is not limited to timer interrupt processing for controlling the effects, but may be any control or setting process. For example, any control or setting process executable in the pachinko gaming machine 1, such as playing, paying out, communication, information output, or a combination of all or part of these, may be executable as the first process in the first cycle. In this case, the second process executable in the second cycle is timer interrupt processing for temperature detection capable of storing information regarding temperature, and the first process may be set to a higher priority than the second process, and the first cycle may be set to a shorter cycle than the second cycle. The first process may be capable of monitoring information regarding temperature stored by the second process. Alternatively, the second process executable in the second cycle may be a process capable of storing any information. Therefore, when the first process is set to a higher priority than the second process, and the first cycle is set to a shorter cycle than the second cycle, the first process may be capable of monitoring information regarding any detection result stored by the second process.

(Means for solving the problem and effects of characteristic part 05AK)
[1] A gaming machine capable of playing a game,
A processing means capable of executing a process according to a program;
A detection means capable of detecting a temperature;
A storage means capable of storing information related to temperature,
The processing means includes:
A first process for controlling the performance can be executed in a first period,
A second process capable of storing information related to the temperature detected by the detection means in the storage means is executable in a second period;
The first process has a higher priority than the second process,
The first period is shorter than the second period,
The first process can monitor the information relating to temperature stored in the storage means by the second process.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The processing means may be, for example, a CPU 120A of a performance control microcomputer 100A. The detection means may be, for example, a processor temperature sensor 156, a board temperature sensor 160, etc. The storage means may be, for example, an internal RAM 122A provided with a temperature-related data storage area 05AK100. The first processing may be, for example, a performance control timer interrupt processing. The first period may be, for example, 1 [ms (milliseconds)]. The second processing may be, for example, a temperature detection timer interrupt processing. The second period may be, for example, 1 [s (seconds)]. The high priority may be, for example, the processing priority shown in FIG. 12-2 (B). The ability to monitor information related to temperature may be, for example, the ability to execute the temperature monitoring processing of step 05AKS31.
With this configuration, the processing load regarding temperature and control can be reduced and appropriate control can be performed.

[2] A backup storage means capable of retaining stored contents even if the power supply is stopped,
The storage means is capable of storing special temperature information indicating a maximum temperature,
The second process is
a determination process capable of determining whether or not the temperature detected by the detection means exceeds a maximum temperature indicated in the special temperature information;
A storage process capable of storing information indicating the temperature detected by the detection means as new special storage information in the storage means when it is determined that the temperature detected by the detection means exceeds the maximum temperature,
The first process may include a backup process capable of storing new special temperature information in the backup storage means when new special temperature information is stored in the storage means.
Here, the backup storage means may be, for example, the backup data memory 210. The special temperature information may be, for example, the processor maximum temperature information indicated in the processor maximum temperature data or the board maximum temperature information indicated in the board maximum temperature data. The determination process may be, for example, steps 05AKS101 to 05AKS103, 05AKS110, 05AKS111, etc. The storage process may be, for example, steps 05AKS108, 05AKS116, etc. The backup process may be, for example, steps 05AKS143, 05AKS148, etc.
In such a configuration, the processing load can be reduced and the special temperature information can be appropriately stored.

[3] The special temperature information stored in the backup storage means is
When it is determined that the temperature detected by the detection means exceeds the maximum temperature, maximum temperature information indicating the temperature is displayed; and
and date and time information indicating the date and time when the temperature was detected by the detection means.
For example, in the backup target data setting example 05AKM01, the backup target data may be processor maximum temperature data and date and time data, or board maximum temperature data and date and time data.
In such a configuration, the possibility and cause of a malfunction can be easily identified.

[4] The detection means comprises:
A first detection means capable of detecting a first temperature related to the performance control means;
A second detection means capable of detecting a second temperature related to the board on which the performance control means is provided,
The second process may be capable of acquiring both first temperature information indicating the first temperature and second temperature information indicating the second temperature from the detection means in a second period and storing the information in the storage means.
Here, the performance control means may be, for example, a performance control microcomputer 100A. The first temperature may be, for example, a processor temperature. The first detection means may be, for example, a processor temperature sensor 156. The board may be, for example, a performance control board 12. The second temperature may be, for example, a board temperature. The second detection means may be, for example, a board temperature sensor 160. The first temperature information may be, for example, processor current temperature information indicated in the processor current temperature data. The second temperature information may be, for example, board current temperature information indicated in the board current temperature data.
In such a configuration, the operating environment can be grasped in detail and appropriately controlled.

[5] The second process is
an information acquisition process of acquiring second temperature information after acquiring first temperature information within a second period;
The method may include, after the information acquisition process, an information storage process for storing both the first temperature information and the second temperature information in the storage means.
Here, the information acquisition process may be, for example, steps 05AKS21, 05AKS22, etc. The information storage process may be, for example, step 05AKS23, etc.
In such a configuration, information relating to temperature can be appropriately managed.

[6] The first process may be capable of monitoring, in a first period, both the first temperature information and the second temperature information stored in the storage means.
For example, the temperature monitoring process of step 05AKS31 may include steps 05AKS141, 05AKS146, 05AKS151, and 05AKS155.
In such a configuration, the operating environment can be appropriately grasped and controlled.

[7] A display means capable of displaying information is provided,
The display means is
According to the information stored in the storage means by the second process, when the temperature detected by the detection means is an abnormal temperature, temperature abnormality information can be displayed;
When a predetermined condition is met, both the first temperature information and the second temperature information may be displayed.
Here, the display means may be, for example, an image display device 5. In the case of an abnormal temperature, it may be, for example, that the processor temperature is in a temperature error state. The ability to display abnormal temperature information may be, for example, display example 05AKD01 of a temperature error notification screen. The predetermined condition may be, for example, that a command to start displaying temperature has been received. The ability to display both the first temperature information and the second temperature information may be, for example, display example 05AKD02 of a temperature display screen.
In such a configuration, the occurrence and cause of a malfunction can be easily confirmed.

[8] When a specified condition is satisfied, the display means may be capable of displaying the first temperature information and the second temperature information acquired at the time the specified condition is satisfied, and may be capable of displaying the first temperature information indicating the maximum temperature acquired before the specified condition is satisfied and the second temperature information indicating the maximum temperature.
For example, the display example 05AKD02 of the temperature display screen may include a display of a current temperature information image 05AKG11 and a display of a maximum temperature information image 05AKG12.
In this configuration, if a problem occurs, the cause can be easily identified.

[9] The display means includes:
When power supply to the gaming machine is stopped while the temperature abnormality information is being displayed, the temperature abnormality information is hidden;
If the power supply to the gaming machine is not stopped while the first temperature information and the second temperature information are displayed and a specific condition is met, the first temperature information and the second temperature information may be hidden.
Here, the temperature abnormality information may be hidden, for example, if the end control is not performed until the power supply is stopped after the temperature error notification start control by step 05AKS153. The specific condition may be, for example, the receipt of a temperature display end command.
In such a configuration, the temperature can be appropriately checked while preventing malfunctions.

[10] The processing means may be capable of executing a start-time storage process for storing the special temperature information read from the backup storage means in the storage means when power supply to the gaming machine is started.
Here, the start time storage process may be, for example, the power-on information process S_STRINF of step 05AKS01.
In such a configuration, temperature-related information can be appropriately managed to prevent the occurrence of malfunctions.

REFERENCE SIGNS LIST 1 ... Pachinko game machine 4A ... First special symbol display device 4B ... Second special symbol display device 11 ... Main board 12 ... Performance control board 16 ... Backup memory board 100 ... Game control microcomputer 100A ... Performance control microcomputer 101, 121 ... ROM
102, 122...RAM
103, 120A...CPU
104, 104A, 104B ... Random number circuit 120 ... Performance control CPU
121A ... Internal ROM
121B ... External ROM
122A ... Internal RAM
122B... External RAM
123A...VDP
200: Memory controller 210: Backup data memory 05AK 100: Temperature related data storage area

Claims (1)

A gaming machine capable of playing a game,
A processing means capable of executing a process according to a program;
A detection means capable of detecting a temperature;
A storage means capable of storing information related to temperature,
The processing means includes:
A first process for controlling the performance can be executed in a first period,
a second process capable of storing information about the temperature detected by the detection means in the storage means in a second period;
The first process has a higher priority than the second process,
The first period is shorter than the second period,
The first process can monitor information related to temperature stored in the storage means by the second process.
A gaming machine characterized by:

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