JP7775017B2 - gaming machines - Google Patents

Description

The present invention relates to a gaming machine capable of playing games.

A gaming machine has been proposed that allows for easy identification of unused areas when referencing a dump list (see, for example, Patent Document 1).

Patent No. 6034903

The technology described in Patent Document 1 leaves room for improvement in storage area management.

This invention was made in consideration of the above situation, and aims to provide a gaming machine that is capable of appropriate memory area management.

The gaming machine of claim 1 comprises:
A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means for controlling the progress of the game by the program stored in the storage means;
The storage means
a first storage area in which a program related to game control is stored;
a second storage area in which usage data used in the execution of the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, in which unused data can be stored;
the unused data stored in the unused storage area is zero data indicating all 0;
the total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area;
The second storage area is
The use data includes a normal storage area in which the zero data is stored,
the total storage capacity of the normal storage areas is smaller than the total storage capacity of the unused storage areas,
the normal storage area includes an area in which a plurality of the zero data are stored and to which discontinuous addresses are assigned,
a second unused storage area between the second storage area and the third storage area has a storage capacity greater than a specific number of bytes ;
the storage capacity of one of the plurality of areas in which the zero data is stored and to which discontinuous addresses are assigned, which is included in the second storage area, is smaller than the specific number of bytes ;
It is characterized by:

FIG. 1 is a front view of a pachinko gaming machine. FIG. 2 is a configuration diagram showing various control boards and the like. FIG. 10 is a diagram showing an example of a random number for gaming. 10 is a flowchart showing a main process for game control. 10 is a flowchart showing an example of a timer interrupt process for game control. 10 is a flowchart illustrating an example of a special symbol process. A diagram showing an example of the configuration of a special pattern process jump table. 10 is a flowchart showing a main process for performance control. 10 is a flowchart showing an example of a performance control process. FIG. 2 is a diagram showing an example of the configuration of a game control microcomputer. FIG. 10 is a diagram illustrating an example of an address map. FIG. 10 is a diagram showing an example of main setting of addresses included in a function setting register area. 10A and 10B are diagrams illustrating examples of main setting of addresses included in a function control register area. A diagram for explaining an example of settings for gaming random numbers. FIG. 10 is a diagram for explaining a random number update period. 10 is a flowchart illustrating an example of a power supply start response process. FIG. 10 is a diagram illustrating an example of the configuration of a function setting register stored value table. FIG. 10 is a diagram illustrating an example of the configuration of an RWM access protection register. 10 is a flowchart illustrating an example of a power-off process. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart illustrating an example of a random number update process. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart illustrating an example of an initial value change random number update process. 10 is a flowchart illustrating an example of an initial value determination random number update process. 10 is a flowchart showing an example of a start port switch passing process. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart showing an example of a normal special symbol processing. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart showing an example of a special symbol determination process. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart showing an example of a special symbol information setting process. A flowchart showing an example of a jackpot information data selection process. FIG. 10 is a diagram for explaining an example of use of a data configuration. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart showing an example of a variation pattern setting process. This is a flowchart showing an example of a winning fluctuation pattern type table selection process. This is a flowchart showing an example of a process for selecting a variation pattern type table when a winning combination is lost. A diagram for explaining an example of the configuration of a fluctuation pattern type allocation table. FIG. 10 is a diagram illustrating an example of the configuration of a fluctuation pattern allocation table. FIG. 10 is a diagram illustrating an example of the configuration of a fluctuation pattern allocation table. FIG. 10 is a diagram illustrating an example of the configuration of a fluctuation pattern allocation table. 10 is a flowchart showing an example of normal symbol process processing. FIG. 10 is a diagram for explaining an example of use of a data configuration. 10 is a flowchart illustrating an example of a gate switch passing process. 10 is a flowchart showing an example of normal processing for normal symbols. FIG. 10 is a diagram for explaining an example of use of a data configuration. FIG. 2 is a diagram showing memory areas of a ROM. FIG. 10 is a diagram illustrating an example of unused data settings. FIG. 10 is a diagram illustrating an example of the configuration of a RST instruction. FIG. 10 is a diagram illustrating an example of a description of a program module. FIG. 10 is a diagram illustrating an example of storage of table data. FIG. 10 is a diagram illustrating an example of setting zero data. FIG. 10 is a diagram illustrating an example of storage of table data. FIG. 10 is a diagram illustrating an example of an output of a dump list.

(Basic explanation)
First, the basic configuration and control of the pachinko gaming machine 1 will be described.

(Configuration of Pachinko Game Machine 1, etc.)
1 is a front view of a pachinko gaming machine 1, showing the layout of the main components. The pachinko gaming machine (gaming machine) 1 is broadly composed of a gaming board (gauge board) 2 that forms the gaming board surface, and a gaming machine frame (base frame) 3 that supports and fixes the gaming board 2. A gaming area is formed on the gaming board 2, and gaming balls, which serve as gaming media, are launched into this gaming area by a predetermined ball launching device.

A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions on the gaming board 2. In the example shown in Figure 1, they are provided on the right side of the gaming area. The first special symbol display device 4A and the second special symbol display device 4B can each variably display special symbols as multiple types of special identification information. Special symbols are also called "special symbols." The variably displayed special symbols are also called "special symbol games." Both the first special symbol display device 4A and the second special symbol display device 4B are configured using 7-segment LEDs or the like. Special symbols are represented by numbers "0" to "9," symbols indicating "-," or any other lighting pattern. Special symbols may include a pattern in which all LEDs are turned off.

The "variable display" of special symbols refers to, for example, the variable display of multiple types of special symbols. For other symbols, such as performance symbols, small symbols, and regular symbols, "variable display" also refers to the variable display of multiple types of symbols. Performance symbols are also called decorative symbols or ornamental symbols. Variable display is also called variable display, or simply "variation." Variations include updating the display of multiple symbols, scrolling multiple symbols, and deforming, enlarging, or reducing one or more symbols. Variations may also include flashing a symbol. In the variable display of special symbols or regular symbols, multiple types of special or regular symbols are displayed in a variable manner. In the variable display of performance symbols, multiple types of performance symbols are scrolled or updated, or one or more performance symbols are deformed, enlarged, or reduced. In the variable display of any symbol, a predetermined symbol is ultimately displayed as a static display. The static display is also called a derived display, or simply "derivation." The symbol that finally stops and is displayed in a variable display is also called the final stop symbol or the confirmed symbol. The symbol that finally stops in a special symbol game is also called the confirmed special symbol. The display result of the variable display includes the display result of the special symbol, and is also called the variable display result. The display result of the special symbol is also called the special symbol display result. The execution time of the variable display includes the special symbol change time, which is the time during which the special symbol changes, and is also called the variable display time. The special symbol change time can be set to a different time depending on the change pattern of the special symbol, of which multiple patterns are prepared in advance.

The special pattern variably displayed on the first special pattern display device 4A is also called the "first special pattern." The special pattern variably displayed on the second special pattern display device 4B is also called the "second special pattern." A special pattern game using the first special pattern is also called the "first special pattern game." A special pattern game using the second special pattern is also called the "second special pattern game." There may be only one type of special pattern display device that variably displays special patterns.

A normal symbol display 20 is provided at a predetermined position on the game board 2. In the example shown in Figure 1, it is provided on the left side of the game area. The normal symbol display 20 can variably display normal symbols as multiple types of normal identification information different from special symbols. Normal symbols are also called "normal symbols." The variable display of normal symbols is also called a "normal symbol game." The normal symbol display 20 is constructed using 7-segment LEDs, etc. Normal symbols are represented by numbers "0" to "9," symbols indicating "-," or other arbitrary lighting patterns. Normal symbols may include patterns in which some or all of the multiple LEDs are lit, or patterns in which all of the multiple LEDs are turned off. The final stopping symbol in a normal symbol game is also called a confirmed normal symbol. The display result of the normal symbol is also called a normal symbol display result. The execution time during which the normal symbol is variably displayed in a normal symbol game is also called a normal symbol fluctuation time. The normal symbol variation time can be set to a different time depending on the normal symbol variation pattern, of which multiple patterns are prepared in advance.

An image display device 5 is provided near the center of the play area on the game board 2. The image display device 5 may be configured using a mechanism capable of forming any image, such as an LCD (liquid crystal display), organic EL (electroluminescence), dot matrix LED, projector and screen, 3D image projection device, or any other device. The image display device 5 is capable of displaying various types of effect images. Furthermore, the image display device 5 is not limited to effect images, and can also display any control-related image, such as an inspection image or a setting image.

For example, on the screen of the image display device 5, variable display of effect symbols can be performed in synchronization with the first special symbol game and the second special symbol game. The effect symbols are display symbols that show numbers or the like, and are multiple types of decorative identification information different from special symbols and normal symbols. On the screen of the image display device 5 shown in FIG. 1, there are provided effect symbol display areas 5L, 5C, and 5R for "left," "center," and "right," respectively. Variable display of effect symbols is performed, for example, by scrolling or updating the effect symbols vertically in synchronization with the first special symbol game or the second special symbol game. Synchronization of the variable display may be achieved as long as the timing at which the symbol change begins and the timing at which the change ends and the symbol is finally displayed stationary are common for different types of symbols. The final stopped symbol in the variable display of effect symbols is also referred to as the confirmed effect symbol, confirmed decorative symbol, or confirmed decorative symbol. The variable display of the effect symbols is synchronized with the first and second special symbol games, so the variable display time of the effect symbols is the same as the special symbol variation time.

The screen of the image display device 5 may be provided with a display area capable of displaying effect images corresponding to pending displays and active displays. A pending display is a display corresponding to a variable display that has not yet been executed and is on hold. An active display is a display corresponding to a variable display that is being executed. The pending display and active display are also collectively referred to as variable display-compatible displays that correspond to variable displays. A display area that displays a pending display is also referred to as a pending display area. A display area that displays an active display is also referred to as an active display area. The number of pending variable displays is also referred to as the number of pending memories. The number of pending memories corresponding to the first special game is also referred to as the first number of pending memories. The number of pending memories corresponding to the second special game is also referred to as the second number of pending memories. The sum of the first number of pending memories and the second number of pending memories is also referred to as the total number of pending memories.

Above the first special symbol display device 4A and the second special symbol display device 4B shown in Figure 1, there are provided a first reserve indicator 25A and a second reserve indicator 25B, each composed of a plurality of LEDs. The first reserve indicator 25A displays the first reserve memory number by the number of lit LEDs. The second reserve indicator 25B displays the second reserve memory number by the number of lit LEDs. Above the normal symbol display device 20 shown in Figure 1, there is provided a normal symbol reserve indicator 25C, composed of a plurality of LEDs. The normal symbol reserve indicator 25C displays the normal symbol reserve number by the number of lit LEDs. The normal symbol reserve number is the reserve memory number corresponding to the normal symbol game.

Below the image display device 5 are provided a winning ball device 6A and a variable winning ball device 6B. The winning ball device 6A forms a first starting winning opening that is always kept in a constant open state, allowing game balls to enter, for example, by a specified ball receiving member. The variable winning ball device 6B forms a second starting winning opening that can be switched between a closed state and an open state by a normal electric device solenoid 81 shown in Figure 2 as a normal electric device. The variable winning ball device 6B is equipped with, for example, an electric tulip-type device with a pair of movable wings. When the normal electric device solenoid 81 is in the off state, the movable wings are in a vertical position, causing the second starting winning opening to be in a closed state that prevents game balls from entering, or in a normal open state that makes it difficult for game balls to enter. When the normal electric device solenoid 81 is on, the variable winning ball device 6B tilts the movable wing piece to an open state where the second starting winning port can be entered by game balls, or to an expanded open state where the second starting winning port can be easily entered by game balls. The open state where the second starting winning port can be entered by game balls or the expanded open state where it can be easily entered by game balls is also referred to as the first variable state. The closed state where the second starting winning port cannot be entered by game balls or the normal open state where it is difficult for game balls to enter is also referred to as the second variable state. Note that the variable winning ball device 6B is not limited to devices equipped with an electric tulip-type device, as long as it can be changed between the first variable state and the second variable state.

The entry of a gaming ball into the first start entry port formed by the winning ball device 6A is also referred to as a first start entry. The entry of a gaming ball into the second start entry port formed by the variable winning ball device 6B is also referred to as a second start entry. A gaming ball that enters the first start entry port is detected by the first start entry port switch 22A shown in FIG. 2. A gaming ball that enters the second start entry port is detected by the second start entry port switch 22B shown in FIG. 2. Upon the occurrence of a first start entry, a predetermined number of prize balls, for example, three, are paid out, and the first reserved memory count can be updated to increment by one. However, if the first reserved memory count has reached its upper limit, the first reserved memory count will not be updated even if a first start entry occurs. When the first reserved memory count is incremented by one, the first start condition is met, and a first special symbol game in which special symbols are variably displayed by the first special symbol display device 4A becomes playable. When a second start win occurs, a predetermined number of prize balls, such as three, are paid out, and the second reserved memory count can be updated to increment by one. However, if the second reserved memory count has reached its upper limit, the second reserved memory count will not be updated even if a second start win occurs. When the second reserved memory count is incremented by one, the second start condition is met, and a second special symbol game can be played in which special symbols are variably displayed by the second special symbol display device 4B.

General winning openings 10 are provided at predetermined positions on the gaming board 2, and are always kept in a constant open state by a predetermined ball receiving member. In the example shown in Figure 1, general winning openings 10 are provided in two locations on the lower left of the gaming area. When a gaming ball enters one of the general winning openings 10, a predetermined number of prize balls, such as 10, are paid out.

In the play area formed by the playboard 2, a first path and a second path are provided as paths along which game balls flow down. The first path is mainly provided in the area to the left of the image display device 5 when viewed from the front. The second path is mainly provided in the area to the right of the image display device 5 when viewed from the front. The area to the left of the image display device 5 is also referred to as the left play area or left play area. The area to the right of the image display device 5 is also referred to as the right play area or right play area. The left play area and the right play area may be separated, for example, by the end face of the image display device 5 in the play area or the arrangement of the game pegs. Firing a game ball toward the left play area to cause it to flow down the first path is also referred to as a left hit. Firing a game ball toward the right play area to cause it to flow down the second path is also referred to as a right hit. The first path is also referred to as the left hit path. The second path is also referred to as the right hit path. The first path and the second path may be separate paths, or may be paths that are partially shared.

In response to operation of a ball operating handle provided on the ball launching device, a gaming ball is launched from the ball launching device and launched into the gaming area. When a gaming ball launched into the gaming area is guided to the left gaming area and flows down the first path, it is guided, for example, along the arrangement of gaming pins, making it impossible or difficult to guide it to the second path in the right gaming area. When a gaming ball launched into the gaming area is guided to the right gaming area and flows down the second path, it is guided, for example, along the arrangement of gaming pins, making it impossible or difficult to guide it to the first path in the left gaming area.

The winning ball device 6A is provided on the first path in the left-side play area, allowing game balls flowing down the first path to enter. The variable winning ball device 6B is provided on the second path in the right-side play area, allowing game balls flowing down the second path to enter. Note that the variable winning ball device 6B may also be able to accept game balls flowing down the first path in the left-side play area. The variable winning ball device 6B may also be positioned so that game balls flowing down the second path in the right-side play area have an easier time entering than game balls flowing down the first path in the left-side play area.

The second path in the right-side game area is provided with a passing gate 41 and a special variable winning ball device 50. The passing gate 41 forms a passing area through which game balls can pass. Game balls that pass through the passing gate 41 are detected by the gate switch 21 shown in Figure 2. Based on the game ball passing through the passing gate 41, the number of normal reserved memories can be added or updated, and variable display of normal symbols by the normal symbol display device 20 can be executed as a normal symbol game. The passing gate 41 can be configured as a normal symbol activation port through which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol activation port switch that can detect game balls that have entered the normal symbol activation port.

The special variable prize ball device 50 is a special electric device that forms a large prize opening that can be switched between a closed and an open state by a large prize opening solenoid 82. The upper part of the special variable prize ball device 50 has a guide passageway that is wide enough in the front-to-back direction to allow game balls to pass through. This guide path slopes downward from right to left, with walls provided on both the front and back sides of the extended passageway. A device entrance that serves as the large prize opening is formed in the center of the guide passageway. In the special variable prize ball device 50, a movable member 52 that can move in the front-to-back direction is provided as a large prize opening opening/closing member at a position where the large prize opening can be opened and closed. In the special variable prize ball device 50, a fixed member 53 that forms a fixed passageway is provided in the portion of the guide passage where the large prize opening is not formed.

The movable member 52 is driven by the large prize opening solenoid 82 and can move back and forth to open and close the special device entrance, which serves as the large prize opening. In the special variable prize ball device 50, game balls that enter the device through the large prize opening are detected by the count switch 23. Inside the special variable prize ball device 50, a V prize area 51, which serves as a specific area and serves as a prize area through which game balls can pass, is provided. Also, inside the special variable prize ball device 50, a normal area different from the V prize area 51 is provided. Above the V prize area 51, a plate-shaped distribution member is provided as a V prize opening opening/closing member that can switch the V prize area 51 between an open state and a closed state. The distribution member is driven by the specific area solenoid 83 and can move back and forth to open and close the V prize area 51. When the V prize area 51 is in the open state, game balls can pass through it, and when it is in the closed state, game balls cannot pass through it. Gaming balls that pass through the V winning area 51 are detected by the specific area switch 24. Gaming balls that do not pass through the V winning area 51 pass through the normal area. Gaming balls that pass through the V winning area 51 and gaming balls that do not pass through the V winning area 51 but pass through the normal area are both detected by the outlet switch 26 and then discharged outside the special variable winning ball device 50.

In addition to the above features, the surface of the gaming board 2 is equipped with a windmill that changes the direction and speed of the gaming balls as they flow down, as well as numerous obstacle nails. At the bottom of the gaming area is an outlet that takes in gaming balls that do not enter any of the winning holes. Speakers 8L and 8R are provided at the upper left and right positions of the gaming machine frame 3 to play and output sound effects, and gaming effect lamps 9 are provided around the periphery of the gaming area to light up the effects. The gaming effect lamps 9 are composed of LEDs. A movable body 32 that operates according to the effects is provided at a predetermined position on the gaming board 2.

A ball operation handle is provided at the lower right of the gaming machine frame 3, which is operated by the player to launch gaming balls toward the playing area using the ball launching device. The ball operation handle is also called an operation knob. A ball supply tray is provided at a specified position on the gaming machine frame 3 below the playing area, which holds gaming balls dispensed as prize balls or gaming balls loaned from a specified ball lending machine so that they can be supplied to the ball launching device. The ball supply tray is also called the upper tray. Below the upper tray is a prize ball storage tray into which prize balls dispensed when the upper tray is full flow down and are stored. The prize ball storage tray is also called the lower tray.

A stick controller 31A and a push button 31B are provided at predetermined positions on the gaming machine frame 3 below the gaming area. The stick controller 31A can be held and tilted by the player, and is equipped with a trigger button that the player can push and pull. Operation of the stick controller 31A is detected by the controller sensor unit 35A shown in FIG. 2. The push button 31B can be pressed by the player. Operation of the push button 31B is detected by the push sensor 35B shown in FIG. 2. In the pachinko gaming machine 1, the stick controller 31A and push button 31B are used as detection means for detecting player operations and other actions, but other detection means may also be used.

(Outline of game progress)
The game ball is launched toward the game area by the player's rotation of the ball-hitting control handle provided on the pachinko game machine 1. When the game ball passes through the passage gate 41, a normal game is initiated by the normal symbol display device 20. Note that, if the previous normal game is still being played, the normal game based on the passage of the game ball through the passage gate 41 cannot be immediately played. Therefore, the normal game based on the passage is suspended up to a predetermined upper limit, such as "4." In the normal game, if a specific normal symbol, such as a normal winning symbol, is displayed as a confirmed normal symbol, the display result of the normal symbol is "normal winning." In contrast, if a normal symbol other than a normal winning symbol, such as a normal losing symbol, is displayed as a confirmed normal symbol, the display result of the normal symbol is "normal losing." In the case of a "normal winning," opening control is performed to place the variable winning ball device 6B in an open state or an expanded open state for a predetermined period of time. At this time, the second starting winning port is in an open state or an enlarged open state.

When a gaming ball passes through and enters the first start entry opening formed in the winning ball device 6A, the first special symbol game can be initiated by the first special symbol display device 4A. When a gaming ball passes through and enters the second start entry opening formed in the variable winning ball device 6B, the second special symbol game can be initiated by the second special symbol display device 4B. Note that even if a gaming ball enters the start entry opening and a start entry occurs during a period when a special symbol game is being played or during a period when the game is controlled to a jackpot game state or a small jackpot game state, the special symbol game based on the start entry cannot be immediately executed. Therefore, the special symbol game based on the start entry is suspended up to a predetermined upper limit, such as "4." In a special symbol game, when a specific special symbol, such as a jackpot symbol, is displayed as a fixed special symbol, the display result of the special symbol is "jackpot." In contrast, when a predetermined special pattern different from a jackpot pattern, such as a small win pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern will be "small win." Also, when a special pattern different from a jackpot pattern or a small win pattern, such as a loss pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern will be "loss." Furthermore, when a special pattern different from a jackpot pattern, small win pattern, or loss pattern, such as a time-saving pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern may be "time-saving." Special patterns may not include time-saving patterns. In other words, the display result of the special pattern may not include "time-saving."

In a special game, once the special symbol display results in a "jackpot," the game is controlled to a jackpot game state, which is advantageous to the player. In the jackpot game state, the large prize opening formed in the special variable prize ball device 50 can be opened in a predetermined manner. This open state continues until either a predetermined period of time, such as 29 seconds or 1.8 seconds, has elapsed, or until the number of game balls entering the large prize opening reaches a predetermined number, whichever occurs first. The predetermined period during which the large prize opening can be controlled to be open is the maximum period during which the large prize opening can be opened in one round, also referred to as the maximum opening period. In the jackpot game state, one cycle in which the large prize opening is open is called a round or round play. In the jackpot game state, such rounds can be repeated until a predetermined maximum number of times is reached, such as 15 or 2 times. In the jackpot game state, the player can win prize balls by entering game balls into the large prize opening. Therefore, a jackpot gaming state is an advantageous state for the player. The more rounds played in a jackpot gaming state, and the longer the upper limit unlock period, the more advantageous it is for the player.

When the display result of a special symbol is a "jackpot," this includes multiple jackpot types. For example, the opening mode of the jackpot slot, such as the number of rounds or maximum opening period, and the game state after the jackpot game state ends, such as normal state, time-saving state, or probability variable state, can be set to multiple different types, and a jackpot type is specified corresponding to each setting. The multiple jackpot types may include some or all of the jackpot types with many prize balls, jackpot types with few prize balls, or jackpot types with almost no prize balls, or they may include jackpot types with similar numbers of prize balls that can be obtained. Controlling to a jackpot game state based on the display result of a special symbol being a "jackpot" is also called a pattern jackpot, a special symbol jackpot, a variable display jackpot, or a direct hit jackpot.

In a special game, after the display result of the special symbol indicates a "small win," the game is controlled to a small win game state. In the small win game state, the large prize opening formed in the special variable prize ball device 50 can be opened in a predetermined opening mode. For example, in the small win game state, the large prize opening may be opened in the same opening mode as the large prize opening in the large win game state for certain large win types. The large prize opening may be opened in the same opening mode by sharing the same number of openings and opening period. Alternatively, in the small win game state, the large prize opening may be opened in a different opening mode from the large win game state. As with the large win type, when the display result of the special symbol indicates a "small win," multiple small win types may be included. The large win type and small win type are also collectively referred to as the win type. The operation of opening and closing the large prize opening in the small win game state is also referred to as the start operation. When in the small win gaming state, the special variable winning ball device 50's role entrance, which serves as the large winning opening, is opened and the gaming ball passes through the V winning area 51 and is detected by the specific area switch 24, the conditions for a big win are met and control to the big win gaming state is possible. When in the small win gaming state the gaming ball passes through the V winning area 51, causing a V winning, and the game is controlled to the big win gaming state, this is also called a small win via big win.

After the jackpot game state ends, the game state can be controlled to a time-saving state or a probability variable state depending on the type of jackpot. Also, in a special symbol game, after the display result of the special symbol becomes "time-saving," the game state is controlled to the time-saving state instead of being controlled to the jackpot game state. The time-saving state is a game state in which the second special symbol game by the second special symbol display device 4B is more likely to be executed than in the normal state. A game state in which the second special symbol game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to pass through and enter the second start winning hole than in the normal state. Control of whether or not the game ball is more likely to pass through the second start winning hole is also referred to as base control. Base control in the normal state is also referred to as normal base control or low base control. Base control in the time-saving state includes high base control. In addition to high base control, the time-saving state may also include medium base control. Medium base control is a base control that makes it easier for the game ball to pass through the second start winning port than low base control, but makes it harder for the game ball to pass through the second start winning port than high base control. A game state in which medium base control is performed is also called a medium base state. A game state in which high base control is performed is also called a high base state. High base control is also called high opening control.

In the normal state, medium base state, and high base state, it is possible for a time-saving symbol to be displayed as a static result of the display of a special symbol. However, in the medium base state and high base state, even if a time-saving symbol is displayed as a static result of the display of a special symbol, base control based on the time-saving symbol is not performed, and new control to transition to the medium base state or high base state is not initiated. In the time-saving state, it is possible to perform time-saving control that shortens the average variable display time more than in the normal state. For this reason, the time-saving state is also called the time-shortening state.

The time-saving state is a state in which the fluctuation efficiency of special symbols, especially the second special symbol, is improved, and therefore is included in special states that are advantageous to players and different from jackpot gaming states. When the gaming state is a probability variable state, in addition to time-saving control, probability variable control is possible, which increases the probability that the display result of the special symbol will be a "jackpot" compared to the normal state. As a result, the probability variable state is also referred to as a probability variable state. The probability variable state is a state in which the fluctuation efficiency of special symbols is improved and a "jackpot" is more likely to occur, and therefore is included in special states that are advantageous to players and different from jackpot gaming states. The time-saving state and probability variable state continue until one of the predetermined termination conditions is met first, such as the execution of a predetermined number of special symbol games or control to the next jackpot gaming state. The termination condition is the execution of a predetermined number of special symbol games, and is also referred to as a count-cut state. A count-cut time-saving state is also referred to as a count-cut time-cut state. A count-cut probability variable state is also referred to as a count-cut probability variable state.

The normal game state is a game state that is not included in advantageous states such as a jackpot game state that are advantageous to the player, predetermined states such as a small jackpot game state, or special states such as a time-saving state or a probability variable state. The normal state is a game state in which the probability that the display result in a normal game will be a "normal hit" and the probability that the display result in a special game will be a "jackpot" are controlled to be the same as the initial setting state of the pachinko game machine 1. The initial setting state of the pachinko game machine 1 is the control state after the initial setting process is performed without executing the specified recovery process after power is turned on, such as when a system reset is performed.

A state in which probability variable control is being executed is also called a high probability state, and a state in which probability variable control is not being executed is also called a low probability state. A state in which time-saving control is being executed is also called a high base state, and a state in which time-saving control is not being executed is also called a low base state. Combining these, the time-saving state is also called a low probability high base state, the probability variable state is a high probability high base state, and the normal state is a low probability low base state. A high probability state and a low base state are also called a high probability low base state. Note that the pachinko gaming machine 1 may not include a probability variable state as a gaming state.

After the small win gaming state ends, there are cases where the game state is controlled to a big win gaming state based on the occurrence of a V win, and cases where a V win does not occur and the gaming state before the small win gaming state is entered remains unchanged. However, if the display result of the special symbol game is a "small win" and the specified number of special symbol games have been played in the count limit, control of the time-saving state and the probability variable state may end and the game state may return to normal. Note that the pachinko gaming machine 1 may not include a small win gaming state as a gaming state. In other words, the display result of the special symbol may not include a "small win."

When a time-saving condition based on the number of times the variable display is executed is met, the game state may be controlled to a time-saving state. Such a time-saving state is also called a rescue time-saving state. The time-saving condition may be a condition that can be met when, after the power to the pachinko gaming machine 1 is turned on, after a jackpot occurs, or after the display result of the special game shows "time-saving," a new jackpot game state or control to a time-saving state is not performed even if the variable display is executed a specific number of times.

(Progression of the production, etc.)
The pachinko gaming machine 1 can execute various effects in accordance with the progress of the game. These effects include effects that notify the progress of the game and effects that add excitement to the game. These effects include displaying various effect images on the image display device 5, outputting sound effects from the speakers 8L and 8R, turning on the game effect lamp 9, operating the movable body 32, vibrating the stick controller 31A or the push button 31B, or a combination of some or all of these, and may be executed using any effect device.

Effects that can be executed in accordance with the progress of the game include variable display of effect symbols. In response to the start of the first or second special symbol game, variable display of effect symbols begins in the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R provided on the screen of the image display device 5. When the determined special symbol that will be the display result in the first or second special symbol game is displayed as a stopped symbol, the determined effect symbol that will be the display result is displayed as a stopped symbol in the variable display of effect symbols. The determined effect symbol is composed of a combination of three effect symbols corresponding to the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R. During the period from the start to the end of the variable display of effect symbols, the display mode in the variable display of effect symbols may become a reach mode. A reach mode is a mode in which, when the effect symbols that have stopped on the screen of the image display device 5 form part of a jackpot combination, the effect symbols that have not yet stopped continue to change. When the display mode of the variable display of the performance symbols becomes a reach mode, it is also said that a reach has been achieved.

A reach effect can be executed in response to the variable display of the effect symbol reaching a reach state. The pachinko gaming machine 1 can execute multiple types of reach effects so that the probability that the display result of the variable display will be a "jackpot" varies depending on the effect state. The "jackpot" probability corresponding to the effect state is also referred to as the jackpot reliability or jackpot expectation. Reach effects include, for example, normal reach and super reach, which has a higher jackpot reliability than normal reach. Additionally, depending on the execution time of the reach effect, it may also include short reach and long reach, which has a longer execution time than short reach.

When the display result of the special symbol is a "jackpot," a fixed effect symbol that forms a predetermined jackpot combination is displayed as a static display result on the screen of the image display device 5. As an example, identical effect symbols, such as a symbol showing the number "7," are displayed statically on a predetermined valid line in the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R. In the case of a "probability jackpot" that is controlled to a probability jackpot state after the jackpot gaming state ends, odd-numbered effect symbols, such as a symbol showing the number "7," may be displayed statically. In the case of a "non-probability jackpot" that is not controlled to a probability jackpot state after the jackpot gaming state ends, even-numbered effect symbols, such as a symbol showing the number "6," may be displayed statically. A "non-probability jackpot" is also called a "normal jackpot." In this case, odd-numbered effect symbols are also called probability jackpot symbols. Even-numbered symbols are also called non-variable symbols or normal symbols. After a non-variable symbol reaches a reach state, an upgraded symbol may be executed, ultimately resulting in a "variable jackpot."

When the display result of the special pattern is a "small win," a fixed effect pattern that is a predetermined small win combination is displayed as a stopped effect pattern display result on the screen of the image display device 5. As an example, the same effect pattern, such as an effect pattern showing a number other than "7," may be displayed stopped on a predetermined valid line in the "left," "center," and "right" effect pattern display areas 5L, 5C, and 5R. A common fixed effect pattern may be displayed when the display result of the special pattern is a "big win" and a "small win."

When the display result of the special pattern is a "miss," the display result may be a static display without the variable display of the effect pattern becoming a reach state. In this case, the display result of the effect pattern is a static display of the confirmed effect pattern of the non-reach combination. A display result in which the confirmed effect pattern of the non-reach combination is displayed without becoming a reach state is also called a non-reach miss. When the display result of the special pattern is a "miss," the variable display of the effect pattern may become a reach state, and the display result may be a static display after the reach effect is executed. In this case, the display result of the effect pattern is a static display of the confirmed effect pattern of the reach combination that is not a big hit combination or a small hit combination. A display result in which the confirmed effect pattern of the reach combination is displayed after becoming a reach state is also called a reach miss.

The effects that the pachinko gaming machine 1 can execute include variable display compatible displays such as hold displays and active displays. In addition, for example, preview effects that predict the reliability of a jackpot can be executed while the display symbols are variable. Preview effects may include variable preview effects that predict the reliability of a jackpot corresponding to the currently executing variable display, and pre-read preview effects that predict the reliability of a jackpot corresponding to the variable display before execution, whose execution is on hold. Pre-read preview effects may be capable of executing change effects that change the display mode of variable display compatible displays such as hold displays and active displays to a mode that is different from normal.

On the screen of the image display device 5, it may be possible to temporarily stop the effect symbols while they are being displayed in a variable manner, and then resume the variable display, thereby executing a pseudo consecutive effect that makes a single variable display appear as if it were multiple variable displays. The pseudo consecutive effect may be set so that the reliability of a jackpot is higher when the effect symbols are temporarily stopped and then the variable display is resumed a large number of times, compared to when the number of times the variable display is reduced. The variable display of the effect symbols may include cases where the pseudo consecutive effect is executed before the reach state is reached, and cases where the pseudo consecutive effect is executed after the reach state is reached. Additionally, the pseudo consecutive effect may be executed at multiple times when the variable display of the effect symbols is displayed in a variable manner.

While controlling the jackpot gaming state, it is possible to execute a jackpot effect that notifies the player of the jackpot gaming state. The jackpot effect may include an effect that notifies the number of rounds and an advancement effect that suggests or notifies that the advantage of the jackpot gaming state is improving. While controlling the small jackpot gaming state, it is possible to execute a small jackpot effect that notifies the player of the small jackpot gaming state. By executing a common effect during control of the jackpot gaming state and during control of the small jackpot gaming state, it may be possible to make it impossible or difficult for the player to recognize whether the current gaming state is a jackpot gaming state or a small jackpot gaming state.

In a non-playing state where no special game or the like is being played and no game is in progress, a demonstration effect image can be displayed on the screen of the image display device 5. A demonstration effect image is also called a demo image. The display of a demo image is also called a demo display. The effect produced by a demo display is also called a customer waiting demo effect.

(Board configuration)
2, the pachinko gaming machine 1 is equipped with a main board 11, a performance control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17, etc. In addition, various boards such as a payout control board, an information terminal board, and a firing control board are arranged on the back of the pachinko gaming machine 1.

The main board 11 is the main control board and has the ability to control the progress of play in the pachinko gaming machine 1. The progress of play includes the execution of various games and transitions between game states, such as the execution of special games with reserved ball management, the execution of regular games with reserved ball management, jackpot game states, small jackpot game states, time-saving states, and probability variable states. The main board 11 is equipped with a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

The game control microcomputer 100 provided on the main board 11 is, for example, a single-chip microcomputer and can be configured with a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, a random number circuit 104, and an I/O (Input/Output port) 105. Some or all of the ROM 101, RAM 102, and random number circuit 104 may be external to the game control microcomputer 100, or may be built into the game control microcomputer 100. The switch circuit 110 receives detection signals from various switches used for game ball detection and transmits them to the game control microcomputer 100. The various switches used for game ball detection include, for example, a gate switch 21, start port switches such as a first start port switch 22A and a second start port switch 22B, a count switch 23, a specific area switch 24, and an outlet switch 26. The detection signal indicates that a game ball has passed or entered and turned on a switch. Transmission of the detection signal indicates that the game ball has passed or entered. The solenoid circuit 111 can supply solenoid drive signals from the game control microcomputer 100 to the normal electric role solenoid 81, the big prize opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

The ROM 101 provided in the game control microcomputer 100 is a non-volatile storage device that stores computer programs and data used for game control. The data stored in ROM 101 includes table data constituting tables used for variation patterns, presentation control commands, and various other settings, judgments, and decisions. The RAM 102 provided in the game control microcomputer 100 is a temporary storage device that provides a work area used for game control and a stack for saving data. RAM 102 may serve as backup RAM that stores the contents of some or all of the memory area so that they can be restored within a specified period of time even if the power supply to the pachinko gaming machine 1 is interrupted. RAM 102 is also referred to as RWM (Read/Write Memory). The work area of RAM 102 includes memory areas capable of storing various data used for game control, such as counters, timers, buffers, and storage areas for various codes and numerical values. The CPU 103 provided in the game control microcomputer 100 can control the progress of games on the pachinko gaming machine 1 by executing processes corresponding to the programs stored in the ROM 101.

The random number circuit 104 provided in the game control microcomputer 100 counts updatable numerical data indicating various random number values used to control the progress of the game. The random numbers used to control the progress of the game are also called game random numbers. Some or all of the game random numbers may be updated by hardware using a dedicated circuit, or they may be updated by software such as a computer program executed by the CPU 103.

Figure 3 shows an example of a gaming random number. The gaming random numbers include a random number MR1-1 for determining special symbols, a random number MR1-2 for winning symbols, a random number MR1-3 that serves as the initial value for winning symbols, a random number MR2-1 for winning normal symbols, a random number MR2-2 that serves as the initial value for winning normal symbols, a random number MR3-1 for normal symbol variation patterns, a random number MR3-2 for selecting a losing effect, a random number MR3-3 for selecting the variation pattern type, and a random number MR3-4 for the variation pattern.

The random number MR1-1 for determining special symbols is used to determine the display result of a special symbol, such as whether the display result of a special symbol is a "jackpot" or a "small hit." The random number MR1-2 for winning symbols is used to select a confirmed special symbol from multiple special symbols, such as a jackpot symbol when the display result of a special symbol is a "jackpot," or a small hit symbol when the display result of a special symbol is a "small hit." The random number MR1-3, which serves as the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The random number MR2-1 for the winning normal symbol is used to select a confirmed normal symbol from multiple normal symbols to be displayed when the display result of the variable display of normal symbols is a "normal hit." The random number MR2-2, which serves as the initial value for the winning normal symbol, is used to set the initial value of the random number MR2-1. The random number MR3-1 for normal symbol variation patterns is used to determine the normal symbol variation pattern as one of several pre-prepared patterns. The random number MR3-2 for selecting a miss effect is used to select whether or not the variable display of the effect patterns will be in a reach state when the display result of the special symbol is a "miss." The random number MR3-3 for selecting a variation pattern type is used to select the type of variation pattern for the special symbol. The variation pattern type for special symbols is a group that pre-classifies the variation patterns of special symbols based on, for example, the presentation state during the variable display of the effect patterns, and may be configured to include one or more variation patterns. The random number MR3-4 for a variation pattern is used to select the variation pattern for the special symbol.

When making various judgments and decisions based on random number values, such as numerical data indicating the value of a gaming random number, the CPU 103 reads and references various tables from ROM 101. Even when random number values are not used, the necessary tables may be read and referenced from ROM 101 to make various judgments, decisions, settings, etc.

The I/O 105 provided in the game control microcomputer 100 includes an input port into which various signals are input and an output port from which various signals are output. The various signals input to the input port of the I/O 105 may include detection signals from various switches transmitted via the switch circuit 110. The various signals output from the output port of the I/O 105 may include signals for controlling the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first hold indicator 25A, the second hold indicator 25B, the normal hold indicator 25C, etc., and solenoid drive signals for driving the normal electric gimmick solenoid 81, the large prize opening solenoid 82, the specific area solenoid 83, etc.

The main board 11 transmits presentation control commands corresponding to the progress of the game to the presentation control board 12 as part of the operation of controlling the progress of the game using the game control microcomputer 100. Presentation control commands are commands that specify or notify the progress of the game. The presentation control commands output from the main board 11 are relayed by the relay board 15 and supplied to the presentation control board 12. Presentation control commands may include commands that specify various determination results on the main board 11, such as the display results of the special game, the type of win, and the variation pattern; commands that specify the status of the game, such as the start and end of the variable display, the opening status of the big prize slot, the occurrence of a win, the number of reserved memories, and the game status; and commands that specify the occurrence of an error, etc.

The effect control board 12 is a sub-control board independent of the main board 11, and has the function of receiving effect control commands and controlling the effects based on the received effect control commands. The effects that can be controlled by the effect control board 12 include various effects that correspond to the progress of the game, such as driving the movable body 32, as well as various notifications such as error notifications and notifications when power is restored. The effect control board 12 comprises a effect control CPU 120, ROM 121, RAM 122, display control unit 123, random number circuit 124, and I/O 125.

The effect control CPU 120 executes programs stored in ROM 121 to perform processing to control the execution of effects together with the display control unit 123. This processing is for realizing the various functions of the effect control board 12, and includes determining the effects to be executed. The effect control CPU 120 uses various data stored in ROM 121, such as data from various tables, and also uses RAM 122 as its main memory. The effect control CPU 120 may instruct the display control unit 123 to execute effects based on detection signals from the controller sensor unit 35A and push sensor 35B. The detection signal here is a signal that is output when an operation by the player is detected, and may be a signal that appropriately indicates the content of the operation.

The display control unit 123 includes a VDP (Video Display Processor), CGROM (Character Generator ROM), VRAM (Video RAM), etc., and controls the execution of mainly display-related effects based on instructions to execute effects from the effect control CPU 120. The display control unit 123 displays effect images on the screen of the image display device 5 by supplying a video signal corresponding to the effect to be executed to the image display device 5. The display control unit 123 also supplies a sound designation signal to the audio control board 13 and a lamp signal to the lamp control board 14. The sound designation signal designates the sound to be output from speakers 8L and 8R. The lamp signal designates the on/off state of the game effect lamp 9. The supply of the sound designation signal and lamp signal enables sound output from speakers 8L and 8R and the turning on or off of the game effect lamp 9 in synchronization with the display of the effect image. The display control unit 123 may be capable of supplying a signal to operate the movable body 32 to the motor or solenoid of the movable body 32, or to a driver circuit that drives the movable body 32. A driver board for driving the movable body 32 may be provided separately from the performance control board 12.

The random number circuit 124 counts updatable numerical data indicating various random number values used when controlling the execution of various performances. Random numbers used when controlling the execution of performances are also called performance random numbers. Performance random numbers may be updated by software such as a computer program executed by the performance control CPU 120. When making various judgments and decisions based on random number values, such as numerical data indicating the values of performance random numbers, the performance control CPU 120 reads and references various tables from ROM 121. Even when random number values are not used, the performance control CPU 120 may read and reference the necessary tables from ROM 121 to make various judgments, decisions, settings, etc.

The I/O 125 includes an input port for receiving, for example, performance control commands transmitted from the main board 11, and an output port for transmitting various signals. The input port of the I/O 125 may include an input terminal for a detection signal supplied from the controller sensor unit 35A and an input terminal for a detection signal supplied from the push sensor 35B. The output port of the I/O 125 may include an output terminal for a video signal supplied to the image display device 5, an output terminal for a sound designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14.

The audio control board 13 is equipped with various circuits that drive the speakers 8L and 8R, and drives the speakers 8L and 8R based on a sound designation signal from the display control unit 123, causing the speakers 8L and 8R to output the sound designated by the sound designation signal. The lamp control board 14 is equipped with various circuits that drive the game effect lamp 9, and drives the game effect lamp 9 based on a lamp signal from the display control unit 123, turning the game effect lamp 9 on or off in the manner designated by the lamp signal. In this way, the audio output from the speakers 8L and 8R and the turning on and off of the game effect lamp 9 can be controlled based on signals from the display control unit 123. Note that the performance control CPU 120 may perform some or all of the control of audio output and lamp on and off, such as supplying sound designation signals and lamp signals, and the control of the movable body 32, such as supplying signals to operate the movable body 32. Boards other than the main board 11, such as the performance control board 12, audio control board 13, and lamp control board 14, are also called sub-boards. As in the configuration example shown in Figure 2, multiple sub-boards may be provided for different functions, or, unlike the configuration example shown in Figure 2, one sub-board may be configured to have multiple functions.

The power supply board 17 can supply power from an AC power source, such as an external power source like a commercial power supply, such as 100V AC, to electrical components including various control boards such as the main board 11 and the performance control board 12. The power supply board 17 includes, for example, a rectifier circuit for converting AC to DC, and a power supply circuit for converting a predetermined DC voltage to a specific DC voltage (e.g., 12V DC or 5V DC). The pachinko gaming machine 1 can switch between power-on and power-off by operating the power switch 91. The switch circuit 110 of the main board 11 receives a reset signal, power-off signal, and clear signal from the power supply board 17 and transmits them to the game control microcomputer 100. The reset signal is an operation stop signal that stops operation of control circuits such as the game control microcomputer 100, and can be output using a power supply monitoring circuit, a watchdog timer IC, or a system reset IC. The power-off signal turns off when the specified power supply voltage used in the pachinko gaming machine 1 exceeds a specified value, and turns on when the specified power supply voltage remains below the specified value for a period of time that exceeds the power-off reference time. The clear signal turns on, for example, in response to pressing the clear switch 92 on the power supply board 17.

(operation)
Next, the operation (action) of the pachinko gaming machine 1 will be described.

(Major operations of the main board 11)
First, we will explain the main operations of the main board 11. When power supply to the pachinko gaming machine 1 starts, the game control microcomputer 100 starts up, and the CPU 103 executes main processing for game control.

Figure 4 is a flowchart showing the game control main processing P_MAIN executed by the CPU 103 on the main board 11. When the game control main processing P_MAIN shown in Figure 4 starts, the CPU 103 executes the power supply start response processing P_POWER_ON (step S1), followed by the RWM check processing P_RWM_CHK (step S2). The power supply start response processing P_POWER_ON in step S1 can execute initial settings of the game control microcomputer 100 in response to the start of power supply to the pachinko gaming machine 1. The initial settings of the game control microcomputer 100 may include initialization of output ports, setting interrupt vectors, setting internal device registers, and setting specific registers. The RWM check processing P_RWM_CHK in step S2 includes a checksum calculation process, which compares the checksum data obtained as a result of the process with the data stored in the checksum buffer. If the two data match, it is determined that the contents stored in the RAM 102 are correct.

Next, it is determined whether a predetermined recovery condition is met (step S3). The recovery condition can be met when the clear signal corresponding to the operation of the clear switch 92 is in the OFF state, the checksum buffer contains normal stored data, and the stored contents of the RAM 102 (which serves as backup RAM) are normal. When the pachinko gaming machine 1 is powered on, if the clear switch 92, for example, located on the power supply board 17, is pressed, an ON clear signal is input to the gaming control microcomputer 100. If such an ON clear signal is input, it is determined in step S3 that the recovery condition is not met. The checksum buffer stores the checksum data calculated in the checksum calculation process when the backup monitoring timer measures the backup judgment time during the previous power outage. If the time value of the backup monitoring timer does not match the specific value corresponding to the backup judgment time, it is determined in step S3 that the recovery condition is not met. The backup data may be data stored in the gaming work area of the RAM 102 (which serves as backup RAM for gaming control). In step S3, it is determined whether the recovery conditions can be met based on the results of checking or inspecting the presence or absence of backup data and data errors using the RWM check process P_RWM_CHK in step S2.

If the recovery conditions are met (Step S3: Yes), the backup setting process P_BACKUP_SET is executed (Step S4). The backup setting process P_BACKUP_SET uses the backup command transmission table to enable the performance control commands corresponding to the backup time to be sent from the main board 11 to the performance control board 12. The backup setting process P_BACKUP_SET also clears the process codes, timers, counters, and flags specified in the backup setting table, enabling them to be initialized.

If the recovery condition is not met (Step S3: No), the initialization setting process P_INIT_SET is executed (Step S5). The initialization setting process P_INIT_SET enables the transfer of clear data to the game work area, which serves as a working area in RAM 102. This initializes the game work area in RAM 102. The initialization setting process P_INIT_SET then uses the initialization command transmission table to enable the transmission of corresponding performance control commands from the main board 11 to the performance control board 12 at the time of initialization. The initialization setting process P_INIT_SET also clears the buffers, timers, pointers, and counters specified in the initialization setting table, enabling them to be initialized.

Then, the control start setting process P_STACON is executed (step S6). The control start setting process P_STACON may include a wait process. The wait process executes a loop process and waits until a set waiting time has elapsed, ensuring that sub-boards such as the performance control board 12 can be started. The control start setting process P_STACON may also include a specific count command transmission process or a command transmission process for individual chip number information. The specific count command transmission process enables a performance control command specifying the count value of a specific count counter to be transmitted from the main board 11 to the performance control board 12 when the power is turned on. The specific count counter is located at a specified address in RAM 102 and is sufficient as long as it can count the remaining number of times until the number of executions of the variable display reaches the specific number corresponding to the time-saving condition. The command transmission process for individual chip number information enables a performance control command specifying the stored value of a chip individual number register to be transmitted from the main board 11 to the performance control board 12. The chip individual number register is included in the built-in register of the game control microcomputer 100, and is capable of storing a different value assigned to each chip as the chip individual number.

The control start setting process P_STACON may include startup out-of-area processing. The startup out-of-area processing is executed by reading a program stored in the non-game program area of ROM 101 in response to startup due to the start of power supply to the pachinko gaming machine 1. The startup out-of-area processing may be, for example, performance display RWM initial value setting processing. The performance display RWM initial value setting processing makes it possible to set initial values for initial display using the 7-segment LEDs that make up the performance display monitor. The performance display monitor may be mounted, for example, on the main board 11, and may be capable of displaying content related to setting values and content related to the base. The setting value can be changed to one of multiple levels, such as six levels, when the pachinko gaming machine 1 is in a setting change state in which the settings can be changed, making it possible to set the probability that the display result of the special pattern will be a "jackpot." The base is calculated by dividing the number of prize balls paid out when a game ball passes through each prize slot, such as the start prize slot, general prize slot, or special prize slot, by the number of game balls launched into the game area.

After the control start setting process P_STACON in step S6, a timer interrupt counter is set (step S7). In step S7, the PTC counter output value is set so that a periodic timer interrupt occurs every predetermined time, such as every 4 ms (milliseconds). The game control main process P_MAIN then enters a loop. In this loop, interrupts are disabled (step S8), the initial value determination random number update process P_TFINIT is executed (step S9), the loop out-of-area process P_REGOUT is executed (step S10), interrupts are enabled (step S11), and the process returns to step S8. Then, whenever an interrupt request signal is input from the PTC to the CPU 103 while the interrupt is enabled, the CPU 103 is enabled to execute timer interrupt processing. This allows the CPU 103 to execute timer interrupt processing every time a predetermined time, such as every 4 ms, has elapsed.

Figure 5 is a flowchart showing an example of timer interrupt processing P_PCT for game control. In the timer interrupt processing P_PCT shown in Figure 5, power-off processing P_POWER_OFF is executed (step S51). Next, it is determined whether the fraudulent activity monitoring flag is "0" (step S52). The fraudulent activity monitoring flag is set to "1", which corresponds to the ON state, when magnetism is detected by the magnet sensor or when radio waves are detected by the frame radio wave sensor. In all other cases, the fraudulent activity monitoring flag is set to "0", which corresponds to the OFF state.

If the fraud monitoring flag is "1" (Step S52: No), the game stop process P_GAME_STOP is executed (Step S53). The game stop process P_GAME_STOP simply initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and if it is turned off, the execution of the payout process on the payout control board is stopped.

If the fraud monitoring flag is "0" (Step S52; Yes), switch processing P_SW is executed (Step S54), switch error notification processing P_CON_CHK is executed (Step S55), random number update processing P_RANDOM is executed (Step S56), and initial value determination random number update processing P_TFINIT is executed (Step S57). Also, special symbol process processing P_TPROC is executed (Step S58), normal symbol process processing P_FPROC is executed (Step S59), information output processing P_JYOUHOU is executed (Step S60), prize ball processing P_PAY is executed (Step S61), and display processing P_HYOUZI is executed (Step S62). Furthermore, other timer interrupt response processing is executed (Step S63). After that, interrupt permission is set (Step S64), and timer interrupt processing P_PCT ends.

The power-off process P_POWER_OFF in step S51 judges the power confirmation signal transmitted from the power supply board 17, enabling checksum calculation processes and other processes to be executed when power is off. The switch process P_SW in step S54 judges the status of the input port, enabling updates to the switch-on buffer and other processes. The switch error notification process P_CON_CHK in step S55 can update the count value of a sensor-on counter specified, for example, by a switch error notification judgment table, and can display an error notification when the count value reaches a sensor abnormality error judgment value. The random number update process P_RANDOM in step S56 enables software random numbers among the game random numbers to be updated by software. The random number update process P_TFINIT for initial value determination in step S57 enables software to update game random numbers used as random number initial values.

The special symbol process P_TPROC in step S58 includes processing related to the variable display of special symbols and game states, such as managing the execution and reservation of special symbol games, controlling the jackpot and small jackpot game states, and controlling the game state. The normal symbol process P_FPROC in step S59 includes processing related to the variable display of normal symbols and controlling the state of the second start winning slot, such as managing the execution and reservation of normal symbol games based on the detection signal from the gate switch 21 and controlling the opening and closing of the variable winning ball device 6B based on a "normal symbol win." The information output process P_JYOUHOU in step S60 sets the information output signal. The information output signal is a signal corresponding to information such as jackpot information, start information, and probability fluctuation information supplied to, for example, a hall management computer installed outside the pachinko gaming machine 1. Jackpot information indicates the number of jackpots that have occurred. Start information indicates the number of start wins. Probability fluctuation information indicates the number of times the probability variable state has occurred. The prize ball processing P_PAY in step S61 includes a prize ball command output counter increment process and a prize ball control process. The prize ball command output counter increment process uses a prize ball number table to determine whether a switch is on, and when on is detected, updates the prize ball command output counter and the winning information output counter. The prize ball control process selects the process corresponding to the prize ball process code and controls the payout of prize balls based on the detection of game balls. The display process P_HYOUZI in step S62 sets the display for the first reserve indicator 25A, second reserve indicator 25B, regular reserve indicator 25C, and various other status indicator lights.

Figure 6 is a flowchart showing an example of processing that can be executed in step S58 of Figure 5 as the special symbol process P_TPROC. In the special symbol process P_TPROC, the CPU 103 sets a first start winning corresponding flag (step S101). The first start winning corresponding flag is set by executing a logical operation instruction or the like to reflect the state of the first start winning port switch 22A contained in the switch-on buffer in the flag register of the CPU 103. At this time, a zero flag in the flag register being in the on state indicates that the first start winning corresponding flag is in the off state. Conversely, a zero flag being in the off state indicates that the first start winning corresponding flag is in the on state. Next, a transfer instruction for setting the table pointer is issued to set the first start winning corresponding table (step S102). Then, it is determined whether the first start winning corresponding flag is on (step S103). If the first start winning flag is on (step S103; Yes), the start port switch passing process P_TZU_ON is executed (step S104).

If the first start winning corresponding flag is off in response to step S103 (step S103; No), or after the start winning switch passing process P_TZU_ON in step S104, the second start winning corresponding flag is set (step S105). The second start winning corresponding flag is set by executing a logical operation instruction or the like to reflect the state of the second start winning switch 22B contained in the switch-on buffer in the flag register of the CPU 103. At this time, a zero flag in the flag register being on indicates that the second start winning corresponding flag is off. Conversely, a zero flag being off indicates that the second start winning corresponding flag is on. Next, a transfer instruction for setting the table pointer is issued to set the second start winning corresponding table (step S106). After that, it is determined whether the second start winning corresponding flag is on (step S107). If the second start winning flag is on (step S107; Yes), the start port switch passing process P_TZU_ON is executed (step S108).

The start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102 to update the first reserved memory count and total reserved memory count by incrementing them by 1 if the first reserved memory count is less than the upper limit, extracts a random number MR1-1 for determining a special symbol, a random number MR3-2 for selecting a miss effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern, stores these in their respective random number buffers, and then transfers them to the first special symbol reserved buffer. Additionally, the first reserved memory information designation command transmission table is used to enable a first reserved memory information designation command that specifies the first reserved memory count to be sent from the main board 11 to the effect control board 12. A value indicating "1" is then stored in the start port winning buffer as the start port winning designation value.

The start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106 to update the second reserved memory count and total reserved memory count by incrementing them by 1 if the second reserved memory count is less than the upper limit, extracts the random number MR1-1 for determining the special symbol, the random number MR3-2 for selecting a miss effect, the random number MR3-3 for selecting the variation pattern type, and the random number MR3-4 for the variation pattern, stores these in their respective random number buffers, and then transfers them to the second special symbol reserved buffer. Additionally, the second reserved memory information designation command transmission table is used to enable the second reserved memory information designation command, which specifies the second reserved memory count, to be sent from the main board 11 to the effect control board 12. A value indicating "2" is then stored in the start port winning buffer as the start port winning designation value.

A common start port switch passing process P_TZU_ON can be executed in steps S104 and S108. Meanwhile, the start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102, while the start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106. In this way, the common start port switch passing process P_TZU_ON is executed using different start port winning tables. Therefore, different data settings and controls are possible when the gaming ball enters the first start port and when it enters the second start port, using common processing. The start port switch passing process P_TZU_ON may also include winning performance processing using the extracted gaming random number.

If the second start winning flag is off in step S107 (step S107; No), or after the start gate switch passing process P_TZU_ON in step S108, a transfer command that sets a pointer sets the special symbol process processing jump table (step S109). The special symbol process processing jump table is an address management table that selects and executes the process corresponding to the read value of the special symbol process code. The special symbol process code can be updated to any of 00 [H] to 0B [H] in accordance with the progress of game control in the pachinko gaming machine 1, and is also called the special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] can also be used to indicate a binary number.

Following step S109, a transfer command to read stored data is used to load the special symbol process code (step S110). Next, the 2-byte data selection process P_ABXEXEC is executed (step S111) to obtain the address of the process selected in accordance with the special symbol process code. The obtained address is set in a pointer. A subroutine call command is then issued to execute the process pointed to by the pointer (step S112), making the process selected in accordance with the special symbol process code executable. When the selected process is completed and a return command is issued to return to the special symbol process process P_TPROC, this special symbol process process P_TPROC also ends, and a return command is issued to return to the game control timer interrupt process P_PCT.

Figure 7 shows an example configuration TT01 of the special symbol process processing jump table used in the special symbol process processing P_TPROC. The special symbol process processing jump table is configured to include table data that can be set in an internal register of the CPU 103 used as a pointer to the address of the process selected corresponding to the special symbol process code. The special symbol process processing jump table of example configuration TT01 includes special symbol normal processing P_TNORMAL when the special symbol process code is 00 [H], special symbol change processing P_TSTART when the special symbol process code is 01 [H], special symbol stop processing P_TSTOP when the special symbol process code is 02 [H], pre-small win opening processing P_TLFAN when the special symbol process code is 03 [H], small win opening processing P_TLOPEN when the special symbol process code is 04 [H], post-small win opening processing P_TLCLSF when the special symbol process code is 05 [H], and .... It includes table data that allows the pointer to be set to an address value corresponding to: small win ejection ball waiting process P_TLOUT when the other symbol process code is 06 [H]; small win end process P_TLEND when the special symbol process code is 07 [H]; pre-large prize opening process P_TINT when the special symbol process code is 08 [H]; large prize opening opening process P_TOPEN when the special symbol process code is 09 [H]; post-large prize opening process P_TCLSF when the special symbol process code is 0A [H]; and big win end process P_TEND when the special symbol process code is 0B [H].

The normal special symbol processing P_TNORMAL determines whether to start a special symbol game based on the presence or absence of stored reserved information, determines the special symbol display result using the random number MR1-1 for determining the special symbol, determines the confirmed special symbol to be displayed in a static state in the variable special symbol display, and determines the special symbol variation pattern. The special symbol display result includes "jackpot," "minor hit," "miss," etc., and if it is determined to be a "jackpot," it is determined that the game will be controlled to a jackpot game state that is advantageous to the player. Furthermore, if the special symbol display result is a "jackpot," it is determined which of several jackpot game states with different degrees of advantage to the player the game will be controlled to, depending on the jackpot symbol that becomes the confirmed special symbol. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether to control the state to an advantageous state that is advantageous to the player, and can decide which of several advantageous states with different degrees of advantage to the player to control to. Furthermore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can decide on one of several types of variation patterns.

The special pattern change processing P_TSTART measures the time elapsed since the special pattern began to change on the first special pattern display device 4A or the second special pattern display device 4B, making it possible to determine whether the special pattern change time corresponding to the change pattern has elapsed. The special pattern stop processing P_TSTOP measures the time elapsed since the special pattern stopped changing on the first special pattern display device 4A or the second special pattern display device 4B, making it possible to determine whether the pattern stop time has elapsed. The pattern stop time can be set as the time for which the special pattern is stopped and displayed when it is determined in the special pattern change processing P_TSTART that the special pattern change time has elapsed. When the pattern stop time has elapsed, the special pattern process code is updated and various settings are made according to the special pattern display result. For example, if the special symbol display result is a "big hit," the special symbol process code can be updated to 08 [H]; if the special symbol display result is a "small hit," the special symbol process code can be updated to 03 [H]; and if the special symbol display result is a "miss," the special symbol process code can be updated to 00 [H].

Processing before small win opening P_TLFAN, processing during small win opening P_TLOPEN, processing after small win opening P_TLCLSF, waiting for small win balls to be discharged P_TLOUT, and processing after small win end P_TLEND are processes for controlling the progress of play in the small win game state. Processing before large win opening P_TINT, processing during large win opening P_TOPEN, processing after large win opening P_TCLSF, and processing after big win end P_TEND are processes for controlling the progress of play in the big win game state.

(Major operations of the performance control board 12)
Next, we will explain the main operations of the performance control board 12. When the performance control board 12 receives a supply of power voltage from the power supply board 17 or the like, the performance control CPU 120 starts up and executes the performance control main process.

Figure 8 is a flowchart showing the main processing for performance control S_MAIN executed by the performance control CPU 120 on the performance control board 12. When the main processing for performance control S_MAIN shown in Figure 8 starts, the performance control CPU 120 executes the performance control initialization processing S_INIT (step S71). The performance control initialization processing S_INIT includes clearing RAM 122, setting various initial values, and setting registers for the timer circuit mounted on the performance control board 12. Next, the initial operation control processing S_SYOKI is executed (step S72). The initial operation control processing S_SYOKI enables control of the initial operation of the movable body 32, such as driving the movable body 32 to return it to its initial position and performing predetermined operation checks. Then, it determines whether the timer interrupt flag is on (step S73). The timer interrupt flag is set to the on state every time a predetermined time, such as 2 ms (milliseconds), elapses based on the register settings for the timer circuit. If the timer interrupt flag is off (step S73; No), step S73 is repeated and the system waits.

When the timer interrupt flag is on (step S73; Yes), the timer interrupt flag is cleared to the off state (step S74), command analysis processing S_COMMAND is executed (step S75), performance control process processing S_CPROC is executed (step S76), performance random number update processing S_RANDOM is executed (step S77), and performance output processing S_OUT is executed (step S78). Then, other timer interrupt response processing is executed (step S79), and the process returns to step S73.

The command analysis process S_COMMAND in step S75 enables the reading of the effect control commands stored in the effect control command receiving buffer and the setting and control corresponding to the read effect control commands. By executing the command analysis process S_COMMAND, the effect control CPU 120 can update stored data indicating the status of flags, stored data in registers, and other stored data in the working area of RAM 122 in response to the effect control commands transmitted from the main board 11. The effect control process process S_CPROC in step S76 enables control of the execution of effects using various effect devices, including, for example, the display of effect images on the screen of the image display device 5, audio output from the speakers 8L and 8R, the lighting or extinguishing of decorative light sources such as the game effect lamp 9 and decorative LEDs, and drive control of the movable body 32. The control content of effects using various effect devices can be determined, decided, and set based on the effect control commands transmitted from the main board 11 and the results of processing by the effect control CPU 120. The performance random number update process S_RANDOM in step S77 enables at least a portion of the performance random numbers used on the performance control board 12 to be updated by executing a software program.

Figure 9 (A) is a flowchart showing an example of processing that can be executed in step S76 shown in Figure 8 as the performance control process processing S_CPROC. The performance control CPU 120 executes the look-ahead performance setting processing S_SAKI_SET in the performance control process processing (step S151). The look-ahead performance setting processing S_SAKI_SET enables judgment, determination, and setting regarding the execution of a look-ahead preview performance, for example, based on the performance control command sent from the main board 11 at the time of the initial winning. The look-ahead performance setting processing S_SAKI_SET also makes it possible to update the hold display based on the number of hold memories specified from the performance control command.

After the pre-read effect setting process S_SAKI_SET in step S151, a transfer command that sets a pointer sets the effect control process jump table (step S152). The effect control process jump table is an address management table that selects and executes the process corresponding to the read value of the effect control process code. The effect control process code can be updated to any value between 00 [H] and 0A [H] depending on the progress of effect control in the pachinko gaming machine 1, and is also referred to as the effect process code. The effect control process code is loaded using a transfer command to read stored data (step S153). The address of the process selected corresponding to the effect control process code thus obtained is set in the effect control pointer (step S154). Therefore, by executing the process pointed to by the effect control pointer (step S115), the process selected corresponding to the effect control process code becomes executable.

Figure 9 (B) shows an example configuration TT02 of the performance control process jump table used in the performance control process processing S_CPROC. The performance control process jump table is composed of table data that can set the address of the process selected corresponding to the performance control process code in a register used as a performance control pointer. The effect control process processing jump table of configuration example TT02 includes table data that can set address values in the effect control pointer corresponding to: waiting for a change pattern command when the effect control process code is 00 [H]; start of effect pattern change processing when the effect control process code is 01 [H]; processing during effect pattern change when the effect control process code is 02 [H]; stop of effect pattern change processing when the effect control process code is 03 [H]; small win display processing when the effect control process code is 04 [H]; small win open processing when the effect control process code is 05 [H]; small win end effect processing when the effect control process code is 06 [H]; big win display processing when the effect control process code is 07 [H]; processing during a round when the effect control process code is 08 [H]; post-round processing when the effect control process code is 09 [H]; and big win end effect processing when the effect control process code is 0A [H].

The variation pattern command reception waiting process makes it possible to determine whether a variation pattern designation command transmitted from the game control microcomputer 100 on the main board 11 has been received. If it is determined that a variation pattern designation command has been received, the presentation control process code is updated to 01 [H], which corresponds to the presentation pattern variation start process. If it is determined that a variation pattern designation command has not been received, the demo display can be controlled. The presentation pattern variation start process makes it possible to start a variation-time presentation corresponding to a special game. For example, in response to a variation pattern command transmitted from the main board 11, it makes it possible to select a presentation pattern to use to control the variation-time presentation and start updating the presentation process timer that measures the presentation execution time. The presentation pattern variation in progress process makes it possible to control the switching timing of each presentation element that makes up the presentation pattern and to determine whether the presentation execution time has elapsed based on the timing value of the presentation process timer. If it is determined that the presentation execution time has elapsed, the presentation control process code is updated to 03 [H], which corresponds to the presentation pattern variation stop process. The effect pattern change stop process enables control of the end of the effect during change and control of the display of the effect result corresponding to the confirmed special pattern based on the establishment of the end condition for the effect during change, such as the elapse of the effect execution time or the receipt of a effect pattern confirmation command. At this time, the effect control process code is updated and various settings are made in accordance with the display result of the variable display. For example, if the display result of the variable display is a "big hit," the effect control process code can be updated to 07 [H]; if the display result of the variable display is a "small hit," the effect control process code can be updated to 04 [H]; and if the display result of the variable display is a "miss," the effect control process code can be updated to 00 [H].

The small hit display process, small hit opening process, and small hit end presentation process are processes for controlling the progression of presentations corresponding to the small hit game state. The big hit display process, round process, post-round process, and big hit end presentation process are processes for controlling the progression of presentations corresponding to the big hit game state.

(Variations of the basic explanation, etc.)
The pachinko gaming machine 1 is not limited to the configuration, functions, processing, and operation described in the basic description and other explanations, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not need to have all of the technical features described in the embodiments, but may have some of the configurations described in the embodiments so as to solve at least one problem in the prior art. When a subordinate concept is described in the embodiments, an invention of a generic concept using homologous or similar matters, or an invention of a generic concept using common properties, is included in the present invention, and may have some of the structure or characteristics described in the embodiments so as to solve at least one problem in the prior art.

Pachinko gaming machine 1 may be a payout gaming machine that pays out a predetermined number of gaming media as prizes when a prize is won, or it may be an enclosed gaming machine that encloses gaming media and awards points when a prize is won.

During the variable display of the special symbol, only one type of symbol, such as a "-" symbol, may be displayed, and this symbol may be displayed and extinguished repeatedly. One type of symbol may be displayed during the variable display, and this symbol may not be displayed when the variable display stops. For example, the display result may not be a "-" symbol, and a non-display state may be displayed in which no special symbol is displayed.

The pachinko gaming machine 1 may be configured to change the probability of winning a jackpot and the payout rate in response to multiple setting values. For example, in the normal special symbol processing of the special symbol process, the probability of winning a jackpot and the payout rate may be changed by using a different jackpot determination value for each setting value. As a specific example, the setting values are divided into six levels, from 1 to 6, with 6 representing the highest probability of winning a jackpot, and the probability of winning a jackpot decreasing as the value decreases in the order of 6, 5, 4, 3, 2, and 1. In this case, setting 6 as the setting value provides the highest advantage to the player, and the advantage gradually decreases as the value decreases in the order of 6, 5, 4, 3, 2, and 1. If the probability of winning a jackpot changes depending on the setting value, the payout rate may also change depending on the setting value. While the probability of winning a jackpot remains constant regardless of the setting value, the number of rounds in the jackpot game state may change depending on the setting value. The pachinko gaming machine 1 may be configured to be able to set one of a plurality of setting values that differ in the degree of advantage to the player. The setting value set in the pachinko gaming machine 1 may be notified by a setting value designation command being sent from the main board 11 to the effect control board 12. While the variable display is being executed, a setting suggestion effect may be executed at a predetermined rate, suggesting the setting value in the pachinko gaming machine 1. The suggestion regarding the setting value in the pachinko gaming machine 1 is not limited to suggesting the setting value in the pachinko gaming machine 1, and may, for example, suggest whether the setting value in the pachinko gaming machine 1 has been changed. The setting suggestion effect may suggest the likelihood of a jackpot through any effect, and may also be able to provide suggestions regarding the setting value in the pachinko gaming machine 1.

In place of some or all of the suggestions regarding control of the jackpot gaming state, or in addition to some or all of the suggestions regarding control of the jackpot gaming state, suggestions regarding control of a state that is advantageous to the player and different from the jackpot gaming state may be made. For example, suggestions regarding a probability variable state that is controlled after the jackpot gaming state ends may be made. In addition, suggestions regarding whether or not a state in which any gaming value that is advantageous to the player is awarded as an advantageous state may be made, depending on whether or not it is controlled.

The invention relating to gaming machines is not limited to pachinko gaming machines 1, but can also be applied to slot machines as appropriate. A slot machine can execute a game in which medals are inserted, a predetermined bet amount is set, multiple types of symbols are rotated in response to the player's operation of a control lever, and when the symbols are stopped in response to the player's operation of a stop button, a predetermined number of medals is paid out to the player if a specific combination of symbols is formed. In a slot machine, advantageous states that are advantageous to the player may include, for example, one or more of so-called bonuses, such as a big bonus, regular bonus, RT, AT, ART, and CZ.

Programs and data for implementing various controls, including game progress and performance effects, may be distributed and provided to a computer device included in a gaming machine such as pachinko machine 1 via a removable recording medium, or may be distributed and provided by being pre-installed on a storage device of the computer device. Furthermore, the machine may be equipped with a communications processing unit that can connect to an external device on a network via a communications line or the like, and may distribute and provide programs and data by downloading them from the external device. Games and performance effects may also be executed by inserting a removable recording medium, or by temporarily storing programs and data downloaded via a communications line or the like in internal memory or the like, or by directly using hardware resources in an external device on a network connected via a communications line or the like, or by exchanging data with other computers or the like via a network.

When comparing various percentages, such as the decision percentage of processing or data, or the execution percentage of a performance, expressions such as "high," "low," and "different" may include cases where one is a "0%" or "100%" percentage. For example, for one decision result or execution content, this may include a "0%" percentage where there is no decision or execution, or a "100%" percentage where there is always a decision or execution.

(Explanation of characteristic part 01AK)
FIG. 10-1 shows an example of the configuration of a game control microcomputer 100 with respect to feature section 01AK. In addition to ROM 101, RAM 102, and CPU 103, the game control microcomputer 100 includes an external bus interface 131, a clock circuit 132, a unique information storage circuit 133, a reset controller 134, an interrupt controller 135, a timer circuit 136, an address decode circuit 137, a free-running counter 138, and a serial communication circuit 139. The random number circuit 104 shown in FIG. 2 includes a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I/O 105 shown in FIG. 2 includes a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

The external bus interface 131 is a bus interface that has functions such as interfacing between the external bus and internal bus of the chips that make up the game control microcomputer 100, and directional control functions for the address bus, data bus, and various control signals. For example, the external bus interface 131 may be connected to an external memory or external input/output device attached to the game control microcomputer 100, and may be capable of sending and receiving address signals, data signals, various control signals, and the like, to and from these external devices. The external bus interface 131 may also include an internal resource access control circuit that controls access from external devices to the game control microcomputer 100's internal data.

The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the external control clock terminal EXC. A control clock generated by a control clock generation circuit provided in the game control microcomputer 100 may be input to the external control clock terminal EXC. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, the 16-bit random number circuit 104A, and the 8-bit random number circuit 104B. The internal system clock SCLK can also be output from the system clock output terminal CLKO to the outside of the game control microcomputer 100. Alternatively, the internal system clock SCLK can be restricted from being output to the outside of the game control microcomputer 100, making it difficult to externally identify the operating state of the game control microcomputer 100.

The unique information storage circuit 133 can store multiple types of unique information that become internal information of the game control microcomputer 100, for example. For example, the unique information storage circuit 133 may store a ROM code, an individual chip number, and an ID number as unique information that differs for each chip of the game control microcomputer 100. The ROM code is numerical data that can be generated from data stored in a specified area of ROM 101. The individual chip number and ID number are numbers assigned to the game control microcomputer 100 when it is manufactured, and represent different values for each chip. The individual chip number can be read by a user program such as a game program, while the ID number can be set so that it cannot be read by a user program. The unique information storage circuit 133 may be included in a specified area of ROM 101, or may be included in an internal register of the game control microcomputer 100.

The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100. Resets that can be controlled by the reset controller 134 include system resets and user resets. A system reset occurs when the input signal to the external system reset terminal XSRST remains low for a certain period of time. A user reset occurs due to certain factors, such as the generation of a timeout signal from the watchdog timer 134A or the occurrence of an IAT (Independent Autonomous Travel Away) alarm. The reset controller 134 includes a watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to the monitoring time and can count down by periodically decrementing the timer value by one. When the timer value reaches "0" and a timeout occurs, the watchdog timer 134A can output a timeout signal to reset the game control microcomputer 100 and restart it. This allows the watchdog timer 134A to measure the monitoring time and reset the game control microcomputer 100 when it determines that the monitoring time has elapsed. The watchdog timer 134A can be set to enable or disable operation, for example, according to the game program.

The interrupt controller 135 can control various interrupt requests generated inside and outside the game control microcomputer 100. Interrupts that can be controlled by the interrupt controller 135 include the non-maskable interrupt NMI and the maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that can be accepted unconditionally even when the CPU 103 is in an interrupt-disabled state, and is generated when the input signal to the external non-maskable interrupt terminal XNMI (also used as input port PI6) is at a low level for a certain period of time. The maskable interrupt INT is an interrupt that can allow or prohibit the acceptance of interrupt requests by a setting command from the CPU 103, and multiple interrupts can be executed by setting priority levels. The maskable interrupt INT can be caused by any or all of the multiple types of interrupt causes, including the input signal to the external maskable interrupt terminal XINT (also used as input port PI5) being low for a certain period of time, a timeout occurring in the timer circuit 136, or numeric data indicating a random number value being stored in the random number value register by the 16-bit random number circuit 104A or 8-bit random number circuit 104B.

The timer circuit 136 includes a PTC (Programmable Timer Counter) that serves as a timer counter corresponding to three channels PTC0 to PTC2, enabling real-time interrupts and time measurement. Each of the timer circuit 136's channels PTC0 to PTC2 uses a count clock generated based on the internal system clock SCLK, and is only required to be able to update the timer value in response to signal changes in the count clock, such as the falling edge when the clock signal changes from high to low.

The address decode circuit 137 can decode various signals obtained from each functional block within the game control microcomputer 100, and can output a chip select signal, which is a decoded signal for external devices. The chip select signal selectively enables the internal circuits of the game control microcomputer 100 or external devices that serve as peripheral devices, allowing them to be accessed by the CPU 103. The output terminals that the address decode circuit 137 can use are multi-function terminals that can selectively output a parallel output signal from POP 105B, a serial transmission signal from the serial communication circuit 139, a clock output signal from the clock circuit 132, and the chip select signal generated by the address decode circuit 137.

The free-running counter 138 is configured to include counter circuits corresponding to four channels FRC0 to FRC3, and can update its count value independently of the operation of the CPU 103. Each channel FRC0 to FRC3 of the free-running counter 138 can be activated by an independent update clock, and its operation can be stopped or changed, for example, according to a gaming program. The count value of the free-running counter 138 can be stored in a hard latch register in response to a latch signal transmitted from an input terminal that serves as a latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a gaming program, etc.

The serial communication circuit 139 is configured to include serial communication units corresponding to three channels, SCU0, SCU1, and STU2, enabling communication with external devices via serial communication. Each channel, SCU0, SCU1, and STU2, of the serial communication circuit 139, can process communication data in, for example, full-duplex, asynchronous, or standard NRZ (Non Return to Zero) format. Channels SCU0 and SCU1 of the serial communication circuit 139 are included in a first channel transceiver circuit capable of bidirectionally transmitting and receiving serial data with an external circuit. Channel STU2 of the serial communication circuit 139 is included in a second channel transmitter circuit capable of unidirectionally transmitting serial data with an external circuit. For example, channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. Channel SCU1 of the serial communication circuit 139 is used for data communication with the performance control board 12. Instead of channel SCU1 of serial communication circuit 139, channel STU2 of serial communication circuit 139 may be used for data communication with the performance control board 12.

The 16-bit random number circuit 104A is composed of random number generation units corresponding to four channels RL0-RL3, each of which operates independently to generate random numbers ranging from 0 to 65535 using numerical data representing 16-bit pseudo-random numbers. The maximum value of the random numbers generated by each channel RL0-RL3 in the 16-bit random number circuit 104A can be set to any value between 256 and 65535. Setting such a maximum value allows for initial setup to select a random number startup method so that the numerical data representing the random number value begins updating. Alternatively, each channel RL0-RL3 in the 16-bit random number circuit 104A can be initially setup to select a random number startup method so that it is automatically started when the gaming control microcomputer 100's operating mode transitions from security mode to user mode. The 16-bit random number circuit 104A can update the random number MR1-1 used to determine special symbols using channel RL0, and can update the random number MR3-2 used to select losing effects using channel RL2.

The 8-bit random number circuit 104B is configured with random number generation units corresponding to four channels RS0 to RS3, each of which operates independently to generate random numbers ranging from 0 to 255 using numerical data representing 8-bit pseudo-random numbers. The maximum value of the random numbers generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value between 16 and 255. Setting such a maximum value allows for initial setup to select a random number startup method so that the numerical data representing the random number value begins to be updated. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B may be initially set to select a random number startup method so that it is automatically started when the operating mode of the game control microcomputer 100 transitions from security mode to user mode. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the variation pattern type using channel RS1, the random number MR3-4 for the variation pattern using channel RS2, and the random number MR3-1 for the normal symbol variation pattern using channel RS3.

PIP105A incorporates, for example, an 8-bit wide input-only port, allowing various signals to be input from outside the game control microcomputer 100. PIP105A can use input terminals corresponding to input ports PI0 to PI7. Input port PI5 uses a multi-function terminal that can also be used as the external maskable interrupt terminal XINT. Input port PI6 uses a multi-function terminal that can also be used as the external non-maskable interrupt terminal XNMI. Input port PI7 uses a multi-function terminal that can also be used as the receiving terminal for channel SCU0 in the serial communication circuit 139. POP105B incorporates, for example, an 11-bit wide output-only port, allowing various signals to be output outside the game control microcomputer 100. POP105B can supply parallel output signals corresponding to output ports PO0 to PO7 and PO10 to PO12 to the address decode circuit 137.

Figure 10-2 shows an example of an address map in the game control microcomputer 100. In the example shown in Figure 10-2, the area from addresses 0000 [H] to 3FFF [H] is allocated to ROM 101 and includes a game program area, game data area, non-game program area, non-game data area, ROM comment area, program management area, and other unused areas. The area from addresses F000 [H] to F3FF [H] is allocated to RAM 102 and includes a game work area, game stack area, non-game work area, non-game stack area, and other unused areas. The area from addresses FE00 [H] to FEBF [H] is a function setting register area allocated to the built-in registers of the game control microcomputer 100. The area from addresses FF00 [H] to FFFF [H] is a function control register area allocated to the built-in registers of the game control microcomputer 100.

In ROM 101, the game program area can store game programs, which are computer programs related to the progress of games. The game data area can store game data used by game programs. The non-game program area can store non-game programs, which are computer programs related to control and processing other than the progress of games. The non-game data area can store non-game data used by non-game programs. These programs and data stored in ROM 101 were designed and created in advance by the manufacturer of the pachinko gaming machine 1, who is the user of the game control microcomputer 100. Therefore, game programs and non-game programs are included in user programs. Game data and non-game data are included in user data.

ROM 101's storage area is divided into a game program area capable of storing game programs related to game progress, and a non-game program area for control and processing unrelated to game progress. The area before the non-game program area, which is assigned a later address, is an unused area with a storage area equal to or greater than the boundary byte number, such as 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to game progress, and the non-game program area capable of storing non-game programs related to control and processing unrelated to game progress, facilitating the design and management of programs and data stored in ROM 101.

The memory area of ROM 101 is provided with a separate game program area capable of storing game programs related to game progress, and a game data area capable of storing game data used by the game programs. Of the game program area and game data area, the area before the game data area assigned a later address is an unused area with a memory area equal to or larger than the boundary byte number, for example, 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to game progress, and the game data area capable of storing game data used by the game programs, facilitating the design and management of the programs and data stored in ROM 101.

The memory area of ROM 101 is provided with adjacent non-game program areas capable of storing non-game programs related to control and processing unrelated to game progress, and non-game data areas capable of storing non-game data used by non-game programs. Of the non-game program area and non-game data area, the area behind the non-game program area assigned an earlier address is the non-game data area, and the area before the non-game data area assigned a later address is the non-game program area. This allows the non-game program area capable of storing non-game programs related to control and processing unrelated to game progress and the non-game data area capable of storing non-game data used by the non-game program to be located in memory areas assigned consecutive addresses, thereby enhancing integration and facilitating the design and management of programs and data stored in ROM 101. An unused area of memory space equal to or greater than the boundary byte count may be provided between the non-game program area and the non-game data area to make it easier to identify the non-game program area and the non-game data area.

In the memory areas of ROM 101, unused memory areas may store data indicating a value of "0" in all areas. This makes it easy to distinguish between game program areas and game data areas, non-game program areas and non-game data areas, and unused areas. Furthermore, if invalid data is stored in an unused area, this data can be easily discovered. Note that unused memory areas may store data indicating a value of "1" in all areas. In other words, unused memory areas can simply have data indicating the same value stored in all areas. This makes it easy to distinguish between multiple types of memory areas, and to easily discover invalid stored data.

In RAM 102, the gaming work area can be used as a work area when CPU 103 executes a gaming program. The gaming stack area can be used as a stack area when CPU 103 executes a gaming program. The non-gaming work area can be used as a work area when CPU 103 executes a non-gaming program. The non-gaming stack area can be used as a stack area when CPU 103 executes a non-gaming program.

The game program area and game data area provided in the memory area of ROM 101, and the game work area and game stack area provided in the memory area of RAM 102 are included in the memory area for game control. The non-game program and non-game data area provided in the memory area of ROM 101, and the non-game work area and non-game stack area provided in the memory area of RAM 102 are included in the memory area for non-game control.

The ROM comment area provided in the storage area of ROM 101 stores data indicating arbitrary program-specific information, such as the program title and version. The program management area provided in the storage area of ROM 101 can store setting information necessary for the internal settings of the game control microcomputer 100 so that the CPU 103 can execute game programs and non-game programs.

Figure 10-3 shows a main setting example AKA01 of addresses included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function setting register area is the first area for setting functions using various circuits included in the game control microcomputer 100, such as the watchdog timer 134A of the reset controller 134, the interrupt controller 135, the timer circuit 136, and the serial communication circuit 139.

In setting example AKA01, the setting values of the WDT start register at address FE1A [H] and the WDT clear register at addresses FE1B [H] to FE1C [H] are invalid values corresponding to unused status. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. Because the setting value of the interrupt mask register at address FE00 [H] is 7E [H], the interrupt control function using the interrupt controller 135 is set to an enabled state for maskable interrupt IR0. Because the setting values of the registers related to channel PTC0 of the timer circuit 136 at addresses FE01 [H] to FE03 [H] are valid values, the time measurement function using channel PTC0 of the timer circuit 136 is set to an enabled state. Because the register settings for channels PTC1 and PTC2 of timer circuit 136 at addresses FE04[H] to FE09[H] are invalid values corresponding to unused channels, the timing function using channels PTC1 and PTC2 of timer circuit 136 is set to an unused state.

Since the register setting values for channels SCU0 and SCU1 of serial communication circuit 139 at addresses FE0A[H] to FE11[H] are valid, the serial communication function using channels SCU0 and SCU1 of serial communication circuit 139 is set to an available state. Since the register setting values for channel STU2 of serial communication circuit 139 at addresses FE12[H] to FE14[H] are invalid, corresponding to unused status, the serial communication function using channel STU2 of serial communication circuit 139 is set to an unused state.

When the register settings for the input ports of PIP 105A at addresses FE2C[H] to FE2E[H] are valid, the signal input function using each input port is enabled. When the register settings for the random number circuit 104 at addresses FE36[H] to FE4A[H] include valid and invalid values, the random number generation function using the random number circuit 104 is enabled for channels corresponding to valid values and set to unused for channels corresponding to invalid values. For example, of the four channels RL0 to RL3 in the 16-bit random number circuit 104A, channels RL0 and RL2, whose corresponding maximum value setting registers are valid, have their random number generation function enabled, while channels RL1 and RL3, whose corresponding maximum value setting registers are invalid, have their random number generation function set to unused. Furthermore, of the four channels RS0 to RS3 in the 8-bit random number circuit 104B, channels RS1 to RS3 whose corresponding maximum value setting registers have valid settings have their random number generation function set to an enabled state, while channel RS0 whose corresponding maximum value setting register has an invalid setting has its random number generation function set to an unused state.

In this way, the various circuits included in the game control microcomputer 100 only need to be able to set the various functions using each circuit to either an enabled state or an unused state, corresponding to the setting value in the function setting register area. The function setting register area is not limited to the various circuits included in the game control microcomputer 100, and may also be a first area for setting any function.

Figure 10-4 shows an example of the main address setting, AKA02, included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function control register area is a second area for function control using various circuits included in the game control microcomputer 100, such as the RAM 102, random number circuit 104, PIP 105A, and serial communication circuit 139.

In setting example AKA02, the RWM access protect register at address FF00[H] corresponds to a setting value of 00[H] or 01[H], enabling function control to prohibit or allow access to the RWM RAM 102. The internal information register at address FF01[H] is set to an invalid value corresponding to unused status, and function control using the corresponding circuit is in an unused state. The internal information register can store data indicating internal information such as abnormal random number update status, abnormal random number update clock frequency, system reset occurrence, WDT timeout occurrence, and IAT occurrence, but in this embodiment it is not used in an unused state.

Each register at addresses FF25[H] to FF28[H] can store a setting value used to control the serial communication function when the serial communication function using channel SCU0 of serial communication circuit 139 is enabled. Each register at addresses FF29[H] to FF2C[H] can store a setting value used to control the serial communication function when the serial communication function using channel SCU1 of serial communication circuit 139 is enabled.

Each register at addresses FF60[H] to FF67[H] can store random numbers that can be obtained using the soft-latch random number acquisition function of the 16-bit random number circuit 104A. Of these, the RL0 soft-latch random number register at addresses FF60[H] to FF61[H] can store random numbers that can be generated by channel RL0 of the 16-bit random number circuit 104A when numerical data indicating that value is acquired by the soft latch. The RL1 soft-latch random number register at addresses FF62[H] to FF63[H] can store random numbers that can be generated by channel RL1 of the 16-bit random number circuit 104A when numerical data indicating that value is acquired by the soft latch. The RL2 soft latch random number register at addresses FF64[H] to FF65[H] can store random numbers that can be generated by channel RL2 of the 16-bit random number circuit 104A when numeric data indicating that value is acquired by the soft latch. The RL3 soft latch random number register at addresses FF66[H] to FF67[H] can store random numbers that can be generated by channel RL3 of the 16-bit random number circuit 104A when numeric data indicating that value is acquired by the soft latch.

Each register at addresses FF68[H] through FF6B[H] can store random numbers that can be obtained using the soft-latch random number acquisition function of the 8-bit random number circuit 104B. Of these, the RS0 soft-latch random number register at address FF68[H] can store random numbers that can be generated by channel RS0 of the 8-bit random number circuit 104B when numerical data indicating that value is acquired by the soft-latch. The RS1 soft-latch random number register at address FF69[H] can store random numbers that can be generated by channel RS1 of the 8-bit random number circuit 104B when numerical data indicating that value is acquired by the soft-latch. The RS2 soft-latch random number register at address FF6A[H] can store random numbers that can be generated by channel RS2 of the 8-bit random number circuit 104B when numerical data indicating that value is acquired by the soft-latch. The RS3 soft latch random number register at address FF6B[H] can store the random numbers that can be generated by channel RS3 of the 8-bit random number circuit 104B when numerical data indicating the value is obtained by the soft latch.

RL0 hard latch random number register number "0" at addresses FF88[H] to FF89[H] and RL0 hard latch random number register number "1" at addresses FF98[H] to FF99[H] can store random numbers generated by channel RL0 of the 16-bit random number circuit 104A when numerical data indicating the value of the random number is acquired by the hard latch. Here, the RL0 hard latch random number register includes multiple storage areas corresponding to multiple register numbers, and different hard latch conditions can be set corresponding to the storage areas of different register numbers. For example, the RL0 hard latch random number register number "0," which is the RL0 hard latch random number register corresponding to register number "0," can establish a hard latch condition when the game ball detection signal from the first start switch 22A is in the ON state. In contrast, RL0 hard latch random number register number "1", which is the RL0 hard latch random number register corresponding to register number "1", can satisfy the hard latch condition when the game ball detection signal from second start switch 22B is in the ON state. As a result, RL0 hard latch random number register number "0" can store numerical data indicating the value of random number MR1-1 for determining a special symbol, which is obtained in response to the occurrence of a first start winning, when the hard latch acquires that value. RL0 hard latch random number register number "1" can store numerical data indicating the value of random number MR1-1 for determining a special symbol, which is obtained in response to the occurrence of a second start winning, when the hard latch acquires that value.

Each register with addresses FFF0[H] to FFF2[H] and FF35[H] can store the signal value input at each input port, corresponding to the enabled state of the signal input function using the input port of PIP 105A. Of these, the input port number "0" register with address FFF0[H] can store the signal value input for the input port with port number "0" provided in PIP 105A. The input port number "1" register with address FFF1[H] can store the signal value input for the input port with port number "1" provided in PIP 105A. The input port number "2" register with address FFF2[H] can store the signal value input for the input port with port number "2" provided in PIP 105A. The input port number "3" register with address FF35[H] can store the signal value input for the input port with port number "3" provided in PIP 105A.

In this way, the various circuits included in the game control microcomputer 100 only need to be able to control their respective operating states in response to the values stored in the function control register area. Furthermore, the various circuits included in the game control microcomputer 100 may also be able to update the values stored in the function control register area in response to their respective operating states. The function control register area is not limited to the various circuits included in the game control microcomputer 100, but may also be a second area for controlling any function.

Figure 10-5 is a diagram illustrating an example of the settings in this embodiment for the gaming random numbers shown in Figure 3. The gaming random numbers shown in Figure 3 can be classified into random numbers used to determine the display results in the variable display of special symbols, random numbers used to determine the display results in the variable display of normal symbols, and random numbers used to determine the display mode in the variable display of special symbols and normal symbols, depending on their respective uses.

Figure 10-5 (A) shows a setting example AKA11 of gaming random numbers used to determine the display result in the variable display of special symbols. The gaming random numbers in setting example AKA11 include a random number MR1-1 for determining special symbols, a random number MR1-2 for winning symbols, and a random number MR1-3 that serves as the initial value for the winning symbol. For example, the random number MR1-1 for determining special symbols can be used to determine whether the special symbol display result is a "big hit" or a "small hit." The random number MR1-2 for winning symbols can be used to determine the designated big hit symbol value or small hit symbol value corresponding to the confirmed special symbol when the special symbol display result is a "big hit" or a "small hit." The random number MR1-3 that serves as the initial value for the winning symbol can be used to set the initial value of the random number MR1-2.

The range of random number MR1-1 is the range of values within which random number MR1-1 can be updated, from 0 to 65535. The magnitude of random number MR1-1 is the total number of random values included in the update range of random number MR1-1, and is 65536, corresponding to the range of 0 to 65535 for random number MR1-1. Because the magnitude of random number MR1-1 is 65536, the total number of random values included in the update range is not a prime number. The number of bytes of numeric data used to update the value of random number MR1-1 is 2. The maximum value of random number MR1-1 is set by initializing a register associated with the 16-bit random number circuit 104A. The random number MR1-1 is updated by hardware updating using the 16-bit random number circuit 104A. The update condition for random number MR1-1 is the system clock input to the 16-bit random number circuit 104A. The conditions for obtaining the random number MR1-1 include a hard latch corresponding to the start winning and software reading into the random number buffer corresponding to that start winning. The period of the random number MR1-1 is 4.369 ms.

The range of random number MR1-2 is the range of values within which random number MR1-2 can be updated, from 0 to 199. The magnitude of random number MR1-2 is the total number of random values included in the update range of random number MR1-2, and is 200, which corresponds to the range of 0 to 199 for random number MR1-2. Because the magnitude of random number MR1-2 is 200, the total number of random values included in the update range is not a prime number. The number of bytes of numerical data used to update the value of random number MR1-2 is 1. The maximum value of random number MR1-2 is set by setting an immediate value in the program code. The method for updating random number MR1-2 is software update SA1. The update condition for random number MR1-2 is a timer interrupt after a specified time has elapsed. The acquisition condition for random number MR1-2 is reading it by software corresponding to the start winning. The period of the random numbers MR1-2 is 800 ms.

The range of random number MR1-3 is the range of values within which random number MR1-3 can be updated, and is the same as random number MR1-2, from "0" to "199." The magnitude of random number MR1-3 is the total number of random values included in the update range of random number MR1-3, and is the same as random number MR1-2, "200," corresponding to the range of random number MR1-3, which is "0" to "199." Because random number MR1-3 has a magnitude of "200," the total number of random values included in the update range is not a prime number. For random number MR1-3, the number of bytes of numeric data used to update its value is "1." The maximum value of random number MR1-3 is set by setting an immediate value in the program code. The method for updating random number MR1-3 is software update SA2. The update conditions for random numbers MR1-3 include a timer interrupt due to the passage of a predetermined time, and the presence of a loop process that serves as standby processing within the main game control process P_MAIN. The acquisition condition for random numbers MR1-3 is when random numbers MR1-2 have completed one cycle. The period for random numbers MR1-3 is indefinite due to the update conditions.

Figure 10-5 (B) shows setting example AKA12 of the gaming random numbers used to determine the display result in the variable display of normal symbols. The gaming random numbers in setting example AKA12 include random number MR2-1 for the symbol per normal symbol and random number MR2-2, which serves as the initial value for the symbol per normal symbol. For example, random number MR2-1 for the symbol per normal symbol can be used to determine the normal symbol designation value corresponding to the confirmed normal symbol as the display result of the normal symbol. Random number MR2-2, which serves as the initial value for the symbol per normal symbol, can be used when setting the initial value of random number MR1-2.

The range of random number MR2-1 is the range of values within which random number MR2-1 can be updated, from 0 to 198. The magnitude of random number MR2-1 is the total number of random numbers included in the update range of random number MR2-1, and is 199, corresponding to the range of 0 to 198 for random number MR2-1. Because the magnitude of random number MR2-1 is 199, the total number of random numbers included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR2-1 is 1. The maximum value of random number MR2-1 is set by immediate value setting in the program code. The method for updating random number MR2-1 is software update SA1. The update condition for random number MR2-1 is a timer interrupt upon the passage of a predetermined time. The acquisition condition for random number MR2-1 is a software readout in response to a gaming ball passing through pass gate 41, which can be configured as a normal symbol activation port. The period of the random number MR2-1 is 796 ms.

The range of random number MR2-2 is the range of values with which random number MR2-2 can be updated, and is the same as random number MR2-1, from "0" to "198." The magnitude of random number MR2-2 is the total number of random values included in the update range of random number MR2-2, and is the same as random number MR2-1, "199," corresponding to the range of random number MR2-2, which is "0" to "198." Since random number MR2-2 has a magnitude of "199," the total number of random values included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR2-2 is "1." The maximum value of random number MR2-2 is set by setting an immediate value in the program code. The method for updating random number MR2-2 is software update SA2. The update conditions for random number MR2-2 include a timer interrupt due to the passage of a predetermined time, and the presence of a loop process that serves as standby processing within the main processing P_MAIN for game control. The acquisition condition for random number MR2-2 is when random number MR2-1 has completed one cycle. The period of random number MR2-2 is indefinite due to the update conditions.

Figure 10-5 (C) shows a setting example AKA13 of a gaming random number used to determine the display mode for the variable display of special and normal symbols. The gaming random numbers in setting example AKA13 include a random number MR3-1 for a normal symbol variation pattern, a random number MR3-2 for selecting a miss effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern. For example, the random number MR3-1 for a normal symbol variation pattern can be used to determine a normal symbol variation pattern corresponding to the variable display of a normal symbol. The random number MR3-2 for selecting a miss effect can be used to determine the variable display mode corresponding to the variable display of a special symbol for which the special symbol display result is "miss." The random number MR3-3 for selecting a variation pattern type can be used to select a variation pattern type corresponding to the variable display of a special symbol. The random numbers MR3-4 for the variation patterns can be used to determine the variation patterns corresponding to the variable display of special symbols.

The range of random number MR3-1 is the range of values within which random number MR3-1 can be updated, from 0 to 232. The magnitude of random number MR3-1 is the total number of random values included in the update range of random number MR3-1, and is 233, which corresponds to the range of random number MR3-1, from 0 to 232. Because the magnitude of random number MR3-1 is 233, the total number of random values included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-1 is 1. The maximum value of random number MR3-1 is set by initializing a register associated with the 8-bit random number circuit 104B. The random number MR3-1 is updated by hardware updating using the 8-bit random number circuit 104B. The update condition for random number MR3-1 is the system clock input to the 8-bit random number circuit 104B. The condition for obtaining the random number MR3-1 is the start of fluctuations in the variable display of normal symbols. The period of the random number MR3-1 is 0.249 [ms].

The range of random number MR3-2 is the range of values within which random number MR3-2 can be updated, from 0 to 65518. The magnitude of random number MR3-2 is the total number of random values included in the update range of random number MR3-2, and is 65519, which corresponds to the range of 0 to 65518 for random number MR3-2. Because the magnitude of random number MR3-2 is 65519, the total number of random values included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-2 is 2. The maximum value of random number MR3-2 is set by initializing a register associated with the 16-bit random number circuit 104A. The random number MR3-2 is updated by hardware updating using the 16-bit random number circuit 104A. The update condition for random number MR3-2 is the system clock input to the 16-bit random number circuit 104A. The conditions for obtaining the random number MR3-2 include reading it into the random number buffer using software that corresponds to the initial winnings. The period of the random number MR3-2 is 139.774 [ms].

The range of random number MR3-3 is the range of values within which random number MR3-3 can be updated, from 0 to 240. The magnitude of random number MR3-3 is the total number of random values included in the update range of random number MR3-3, and is 241, which corresponds to the range of 0 to 240 for random number MR3-3. Because the magnitude of random number MR3-3 is 241, the total number of random values included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-3 is 1. The maximum value of random number MR3-3 is set by initializing a register associated with the 8-bit random number circuit 104B. The random number MR3-3 is updated by hardware updating using the 8-bit random number circuit 104B. The update condition for random number MR3-3 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining the random number MR3-3 include reading it into the random number buffer using software that corresponds to the initial winnings. The period of the random number MR3-3 is 0.257 [ms].

The range of random number MR3-4 is the range of values within which random number MR3-4 can be updated, from 0 to 250. The magnitude of random number MR3-4 is the total number of random values included in the update range of random number MR3-4, and is 251, which corresponds to the range of 0 to 250 for random number MR3-4. Because the magnitude of random number MR3-4 is 251, the total number of random values included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-4 is 1. The maximum value of random number MR3-4 is set by initializing a register associated with the 8-bit random number circuit 104B. The random number MR3-4 is updated by hardware updating using the 8-bit random number circuit 104B. The update condition for random number MR3-4 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining random numbers MR3-4 include reading them into a random number buffer using software that corresponds to the initial winnings. The period of random numbers MR3-4 is 0.268 [ms].

Software update SA1, which is the method for updating random numbers MR1-2 and MR2-1, can be updated by adding 1 to the previous value each time the software update process is executed. If the updated value exceeds the maximum random number value, it is changed to "0," the minimum random number value. Furthermore, if the updated value matches the random number initial value, the corresponding initial random number is used to set the current random number value and stored as the new random number initial value. For example, for random number MR1-2, if the updated value matches the random number initial value, random number MR1-3, which is the initial value for the winning symbol, is used to set the current random number value, and this random number value is stored as the new random number initial value. For random number MR2-1, if the updated value matches the random number initial value, random number MR2-2, which is the initial value for the winning normal symbol, is used to set the current random number value, and this random number value is stored as the new random number initial value.

Software update SA2, which is the method for updating random numbers MR1-3 and MR2-2, can update the previous value by adding 1 each time the software update process is executed. If the updated value exceeds the maximum random number value, it is changed to "0," the minimum random number value. In this case, unlike software update SA1, no initial random number value is used, so the updated value will be either the previous value plus 1, or the minimum random number value of "0."

Figure 10-6 is a diagram illustrating the random number update period when updating random numbers using the 16-bit random number circuit 104A and the 8-bit random number circuit 104B included in the random number circuit 104. Here, the random numbers that can be generated by channels RL0 to RL4 provided in the 16-bit random number circuit 104A are referred to as 16-bit random numbers RLn. Also, the random numbers that can be generated by channels RS0 to RS4 provided in the 8-bit random number circuit 104B are referred to as 8-bit random numbers RSn. The period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A completes one cycle is determined by different relational expressions depending on whether the maximum value of the 16-bit random number RLn is a specific maximum value expressed using a power of 2. The cycle in which the 8-bit random number RSn, which can be updated by the 8-bit random number circuit 104B, completes one cycle is determined by a different relational equation depending on whether the maximum value of the 8-bit random number RSn is a specific maximum value expressed using a power of 2.

10-6(A) shows a 16-bit random number period setting example AKA21 in the 16-bit random number circuit 104A. The 16-bit random number period is the period in which the 16-bit random number RLn, which can be updated by the 16-bit random number circuit 104A, completes one cycle. In the 16-bit random number period setting example AKA21, if the maximum value of the 16-bit random number RLn corresponds to 2 ^m -1 where m = 9 to 16, the period in which the 16-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., the count clock period. The maximum value plus 1, i.e., the value obtained by adding 1 to the maximum value, becomes a linear function where the magnitude of the 16-bit random number RLn is used as a variable. In contrast, when the maximum value of the 16-bit random number RLn does not correspond to 2 ^m -1 when m is any of 9 to 16, the period in which the 16-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., 32 times the count clock period. The value obtained by adding 1 to the maximum value, i.e., the value is a linear function with the magnitude of the 16-bit random number RLn as a variable. Thus, when the maximum value of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, i.e., the update speed of the random number value is faster.

FIG. 10-6(B) shows an example AK22 of an 8-bit random number period setting in the 8-bit random number circuit 104B. The 8-bit random number period is the period in which the 8-bit random numbers RSn, which can be updated by the 8-bit random number circuit 104B, complete one cycle. In the example AK22 of the 8-bit random number period setting, if the maximum value of the 8-bit random numbers RSn corresponds to 2 ^m -1 when m = 5 to 8, the period in which the 8-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., the count clock period. The value obtained by adding 1 to the maximum value, i.e., the magnitude of the 8-bit random number RSn, is a linear function with the variable being the magnitude of the 8-bit random number RSn. In contrast, if the maximum value of the 8-bit random numbers RSn does not correspond to 2 ^m -1 when m = 5 to 8, the period in which the 8-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., 16 times the count clock period. The value obtained by adding 1 to the maximum value, i.e., the value is a linear function when the magnitude of the 8-bit random number RSn is used as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, i.e., the update speed of the random number value is faster.

Figure 10-6 (C) shows a comparative random number example AKA23, comparing the random number values that can be updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B. The 16-bit random number circuit 104A can update the random number values corresponding to the random number MR1-1 for determining a special symbol and the random number MR3-2 for selecting a losing effect. The 8-bit random number circuit 104B can update the random number values corresponding to the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for a variation pattern.

The random number MR1-1 has a maximum value of "65535", which corresponds to 2 ^m -1 when m = 16. This results in a period of 4.369 [ms], and an update rate of 15,000 [times/ms]. The random number MR3-2 has a maximum value of "65518", which does not correspond to 2 ^m -1 when m = 9 to 16. This results in a period of 139.774 [ms], and an update rate of 469 [times/ms]. The random number MR3-3 has a maximum value of "240", which does not correspond to 2 ^m -1 when m = 5 to 8. This results in a period of 0.257 [ms], and an update rate of 938 [times/ms]. The maximum value of random number MR3-4 is "250", which does not correspond to 2 ^m -1 when m is any of m = 5 to 8. As a result, the period of random number MR3-4 is 0.268 [ms], and the update speed at this time is 938 [times/ms].

As such, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include random number MR1-1 for determining special symbols and random number MR3-2 for selecting a losing effect. Both random numbers MR1-1 and MR3-2 have a numeric data byte count of "2," consisting of a specific number of bytes. Since the size of random number MR1-1 is "65536" and the size of random number MR3-2 is "65519," if the total number of random numbers included in the update range of random number MR1-1 is a specific number, the total number of random numbers included in the update range of random number MR3-2 is a predetermined number smaller than the specific number. The update rate of random number MR1-1 is 15,000 times/ms, and the update rate of random number MR3-2 is 469 times/ms, meaning that random number MR1-1 has a faster update rate than random number MR3-2. This prevents random numbers from being generated synchronously, allowing for appropriate updates to random numbers.

Furthermore, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include the random number MR3-2 for selecting a losing effect. The gaming random numbers that can be updated by the 8-bit random number circuit 104B include the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for a variation pattern. For all of these random numbers MR3-2 to MR3-4, the total number of random numbers included in the update range is a prime number. The update rate for random number MR3-2 is 469 times/ms, while the update rate for random numbers MR3-3 and MR3-4 is 938 times/ms. In other words, the update rate for random numbers MR3-3 and MR3-4 is twice the update rate for random number MR3-2, which is an integer multiple of that. Therefore, if random number MR3-2 is the first random number value and random numbers MR3-3 and MR3-4 are the second random number values, the first random number value has an update speed of the first speed, and the second random number value has an update speed of the second speed, which is an integer multiple of the first speed. The update range for random number MR3-2 is "0" to "65518", the update range for random number MR3-3 is "0" to "240", and the update range for random number MR3-4 is "0" to "250". Therefore, the total number of random number values included in each update range is different for the first random number value and the second random number value, and the total number of random number values included in both update ranges is a prime number. This prevents synchronization of random number values and enables appropriate random number value updates.

The CPU 103 is provided with multiple registers, including a program counter, interrupt register, stack pointer, index register, flag register, address register, and general-purpose registers including an accumulator. The index register, flag register, and general-purpose register may be provided as main registers and sub-registers. The registers included in the main registers and sub-registers, and the stack pointer may be provided so that multiple register banks can be configured. The multiple register banks may include a first register bank for use within an area that can be used when executing a game program, and a second register bank for use outside an area that can be used when executing a non-game program. This eliminates the need to save and restore values stored in general-purpose registers, etc., to and from the stack area when switching between executing a game program and a non-game program, for example, thereby preventing an increase in program size and processing load.

The program counter, also known as the PC register, holds the address value of the next instruction to be executed by the CPU 103. The value stored in the program counter is counted up sequentially each time an instruction is executed, and is set to the address value of the branch destination of a branch instruction. The interrupt register, also known as the I register, can hold the upper address value of the interrupt vector table. The value stored in the I register is set in response to the start of power supply to the pachinko gaming machine 1.

The stack pointer, also known as the SP register, can hold address values corresponding to game stack areas and non-game stack areas. The value stored in the stack pointer can specify a destination address for saving and holding a stored value or immediate value in a predetermined register (including the program counter) or a register specified by an instruction in response to an interrupt occurrence, execution of a PUSH instruction, or execution of a subroutine call instruction such as a CALL instruction, a CALLF instruction, or a RST instruction. Upon saving, the value is updated to indicate the start address of the storage area holding the stored value. The value stored in the stack pointer can also specify a read address for restoring a saved register value in response to the end of interrupt processing, execution of a POP instruction, or the end of subroutine processing. Upon this restoration, the value is updated to indicate the address corresponding to the read value. The stack pointer can also be set to the stored value or immediate value of a register specified by a load instruction such as an LD instruction.

Index registers include the IX register and the IY register, each with 2 bytes of storage capacity capable of storing 16-bit data. The accumulator is also called the A register. Other general-purpose registers include multiple registers with 1 byte of storage capacity capable of storing 8-bit data, such as the B register, C register, D register, E register, H register, and L register. The B register and C register can be used as the BC register of a pair of registers capable of storing 16-bit data. The D register and E register can be used as the DE register of a pair of registers capable of storing 16-bit data. The H register and L register can be used as the HL register of a pair of registers capable of storing 16-bit data.

The internal registers of the CPU 103 can update stored values in response to calculation instructions and transfer instructions executed by the CPU 103, and are used to specify program addresses, data addresses, or built-in register addresses provided in the game control microcomputer 100, and to hold calculation data and transfer data.

In the game control microcomputer 100, the instruction set for causing the CPU 103 to execute a program is composed of transfer instructions such as load instructions, subroutine call instructions, jump instructions, other calculation instructions including arithmetic operation instructions and logical operation instructions, input/output instructions, etc. Computer programs such as game programs and non-game programs that can be executed by the CPU 103 are prepared in advance as program code that describes these various instructions and are stored in ROM 101.

The load instruction is a transfer instruction that can be used to store and set data read from a memory area or internal device area of ROM 101 or RAM 102 in an internal register of CPU 103, to write and store a value stored in an internal register of CPU 103 in a memory area or internal device area of RAM 102, and to set or store a numerical value specified by an operand as an immediate value in an internal register of CPU 103 or a memory area or internal device area of RAM 102. The target to which data is transferred by a load instruction can be specified according to the instruction code and operand, and generally includes the source and destination of the data. However, if an immediate value is specified by the operand, the source of the data is not included.

Load instructions include the normal LD instruction, the special LDQ instruction, the special LDF instruction, and the special ICPLD instruction. The normal LD instruction is also called the normal transfer instruction. The special LDQ instruction is also called the first special transfer instruction. The special LDF instruction is also called the second special transfer instruction. The special ICPLD instruction is also called the third special transfer instruction.

The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can transfer data by specifying both a high-order address and a low-order address when transferring data to a storage area or built-in device area in ROM 101 or RAM 102. Furthermore, when transferring data to a storage area or built-in device area in ROM 101 or RAM 102, the LD instruction, which is a normal transfer instruction, can use a pair register such as the HL register as a pointer to specify the destination or source address using the pointer to transfer data.

The LDQ instruction, which is the first special transfer instruction, can transfer data by specifying only the lower address using the Q register, a special register included in the internal registers of the CPU 103. A value indicating the upper address is preset in the Q register, and by combining this with the lower address specified by the LDQ instruction, it is possible to specify the destination or source address and transfer data.

The LDQ instruction, which is the first special transfer instruction, can transfer data using less program code than the LD instruction, which is the normal transfer instruction. However, in programs that frequently change the value stored in the Q register, the amount of program code may actually be greater than with the normal LD instruction. Therefore, it is sufficient to be able to transfer data using the LDQ instruction, which is the first special transfer instruction, in response to processes that require multiple transfers of various data to the game work area at addresses F000 [H] to F0D7 [H], the function setting register area at addresses FE00 [H] to FEBF [H], or the function control register area at addresses FF00 [H] to FFFF [H].

The second special transfer instruction, the LDF instruction, allows data to be transferred by specifying only the lower addresses of data stored in a specific address range. The specific address range is, for example, the range from address 1200 [H] to 1DFF [H]. Therefore, by pre-setting the game data area of ROM 101 to be included in this specific address range and combining it with the lower address specified by the LDF instruction, the source address can be specified and data can be transferred. Note that the game data area of ROM 101 is read-only and not writable, so the address of the game data area cannot be specified as the destination address.

The second special transfer instruction, the LDF instruction, can transfer data using a smaller amount of program code than the normal transfer instruction, the LD instruction. However, since the specific address range is fixed by specification, it is sufficient to set a storage area for frequently used data, such as the game data area of ROM 101, to be included in the specific address range, and then be able to transfer data using the second special transfer instruction, the LDF instruction.

The third special transfer instruction, the ICPLD instruction, compares the update target value with the comparison judgment value, and updates the update target value by adding 1 if the update target value is less than the comparison judgment value, but changes the update target value to the minimum value of "0" if the update target value is equal to or greater than the comparison judgment value. The update target value may be the value indicated by the stored data at the address pointed to by the pointer, or the value stored in a register. The comparison judgment value may be the value stored in a register, or the value indicated by the operand of the ICPLD instruction.

In this way, the third special transfer instruction, the ICPLD instruction, is a single compare and add instruction that compares the update target value with the comparison judgment value, adds 1 to the update target value if the comparison result is less than the comparison judgment value, and changes the update target value to the minimum value if the comparison result is equal to or greater than the comparison judgment value.

Note that setting a stored value in an internal register of CPU 103 using an immediate value from the operand of a transfer command is also referred to as "setting." Reading stored data from the game data area of ROM 101 or the game work area of RAM 102 and storing it in an internal register of CPU 103 is also referred to as "loading." Storing a stored value in an internal register of CPU 103 in a buffer, counter, timer, or any other storage area provided in the game work area of RAM 102 is also referred to as "storing."

Figure 10-7 is a flowchart showing an example of the power supply start response processing P_POWER_ON. The power supply start response processing P_POWER_ON is included in the processing that can be called from the main processing P_MAIN for game control shown in Figure 4, and can be executed in step S1 in response to the start of power supply in the pachinko gaming machine 1. When the CPU 103 executes the power supply start response processing P_POWER_ON, it disables interrupts (step AKS1) and then sets the in-area stack pointer initial value to the stack pointer (step AKS2). The in-area stack pointer initial value may be address F200 [H], which is the final address of the gaming stack area plus 1, corresponding to the initial state in which no saved data is stored in the gaming stack area.

Following step AKS2, a connection confirmation signal ON output value is set by a transfer instruction for setting the internal register of CPU 103 (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is ON, and may be, for example, 00 [H]. At this time, a function control register upper address is set to the Q register by a transfer instruction for setting the Q register contained in the internal register of CPU 103 (step AKS4). The function control register upper address is the value FF [H] indicating the upper address of the function control register area in the setting example AKA02 shown in Figure 10-4. Once the function control register upper address is set in this way, a transfer instruction using the upper address indicated by the value stored in the Q register stores the connection confirmation signal ON output value (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set to the upper address of the function control register area by step AKS4. Therefore, by using a transfer command to write to a memory area at a specified address, such as a special 2-byte LDQ command that specifies a lower address, the connection confirmation signal ON output value set in step AKS3 can be stored in the function control register at the specified address in the function control register area. In step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. This sets the connection confirmation signal transmitted from the main board 11 to the dispensing control board to the ON state.

When the connection confirmation signal is set to the ON state in step AKS5, the SCU0 command register clear output value is stored by a transfer instruction using the upper address indicated by the value stored in the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register was set to the upper address of the function control register area in step AKS4. The SCU0 command register clear output value can be specified by the operand of the transfer instruction. Therefore, the SCU0 command register clear output value can be stored in the function control register at a specified address in the function control register area by a transfer instruction for writing to a memory area at a specified address, such as a 3-byte special LDQ instruction that specifies the lower address and the SCU0 command register clear output value. In step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register located at address FF28 [H] in the function control register area in the setting example AKA02 shown in Figure 10-4. This resets the serial communication function using channel SCU0 of serial communication circuit 139 to its initial state.

After step AKS6, the SCU1 command register clear output value is stored using a transfer instruction that uses the upper address indicated by the value stored in the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register was set to the upper address of the function control register area in step AKS4. The SCU1 command register clear output value can be specified by the operand of the transfer instruction. Therefore, the SCU1 command register clear output value can be stored in the function control register at the specified address in the function control register area by a transfer instruction that writes to a memory area at a specified address, such as a 3-byte special LDQ instruction that specifies the lower address and the SCU0 command register clear output value. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register located at address FF2C[H] in the function control register area in the setting example AKA02 shown in Figure 10-4. This resets the serial communication function using channel SCU1 of the serial communication circuit 139 to its initial state.

When these serial communication functions are controlled to their initial state, a transfer command for setting the internal registers of CPU 103 sets the interrupt vector table upper address (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of ROM 101. The interrupt vector table stores the top address at a table position corresponding to the interrupt priority for, for example, the timer interrupt process P_PCT for game control, which is executed in response to the occurrence of a timer interrupt. This interrupt vector table upper address is set in the I register by a transfer command for setting the internal registers of CPU 103 (step AKS9).

After step AKS9, the value stored in the Q register is updated by subtracting 1 (step AKS10). The value stored in the Q register was set to the upper address of the function control register area in step AKS4. When this stored value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in Figure 10-3 becomes stored in the Q register. In this way, after the function control registers in the function control register area are set, the function setting registers in the function setting register area become configurable. At this time, a transfer command for setting the pointer is used to set the function setting register storage value table address (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of ROM 101. Then, a transfer command for reading the stored data at the address pointed to by the pointer is used to load the processing count (step AKS12). Furthermore, a function setting register store command is used to set the function setting register storage value table (step AKS13). The function setting register store instruction is merely an instruction that specifies the function setting register based on the data stored at the address obtained by adding 1 to the address pointed to by the pointer, stores the function setting register setting value indicated by the data stored at the address obtained by adding 2 to the address pointed to by the pointer in the specified function setting register, adds 2 to the value stored in the pointer, and subtracts 1 from the number of processes, repeating this process until the number of processes is 0. In this way, the function setting register can be initialized.

Once the initial setting of the function setting register is completed in step AKS13, an access permission output value is stored in the RWM access protect register (step AKS14). The access permission output value of the RWM access protect register is set to, for example, 01 [H] by a transfer command for setting an internal register of the CPU 103. This access permission output value is stored in the RWM access protect register by a transfer command for writing to the memory area at the top address in the function setting register area. The RWM access protect register enables function control to allow access to RAM 102, which is the RWM, in response to the setting of the access permission output value 01 [H]. Therefore, by storing the access permission output value in the RWM access protect register in step AKS14, access to RAM 102 is permitted in response to the start of power supply to the pachinko gaming machine 1.

After step AKS14, the upper address of the game work area, which serves as the working area of RAM 102, is set in the Q register (step AKS15), and the power supply start response process P_POWER_ON is then terminated. In this way, after access to RAM 102 is permitted in step AKS14, the value F0 [H] indicating the upper address of the game work area in RAM 102 is set in the Q register. After step AKS15, when the LDQ instruction, which is the first special transfer instruction, is executed, the value F0 [H] stored in the Q register can be used as the upper address of the transfer destination or transfer source without being specified by an operand. This reduces the program size for processing using the game work area in RAM 102, improving the marketability of the gaming machine.

Figure 10-8 shows an example configuration AKT01 of the function setting register storage value table used in the power supply start response process P_POWER_ON. In the power supply start response process P_POWER_ON, for example, the function setting register storage table whose address was set in step AKS11 is used to load the number of processes in step AKS12, and the stored values of each function setting register are stored by a function setting register store command in step AKS13. The function setting register storage value table of example configuration AKT01 stores a value of 18 [H] indicating the number of processes at a starting address of 1200 [H]. In step AKS12, this table data is read and loaded into an internal register of CPU 103. Thereafter, the function setting register store command in step AKS13 sequentially reads table data that combines the lower addresses and stored values of the function setting registers, making it possible to store the stored values in the function setting registers corresponding to each lower address.

In the function setting register storage value table of configuration example AKT01, the table data is configured so that the stored value of a function setting register with a smaller value indicating a lower address can be set first, and the stored value of a function setting register with a larger value indicating a lower address can be set later. As a result, in the function setting register area, the stored values of each function setting register are set in the order of the stored value of the function setting register closest to the first address being set first, and the stored value of the function setting register closest to the last address being set last. This makes it easier to design and manage the data indicating the stored values of the function setting registers, improving the marketability of the gaming machine.

The 16-bit random number circuit 104A corresponds to four channels RL0 to RL3 and can start updating from the channel whose maximum value setting register has a value indicating the maximum random number value set. The 8-bit random number circuit 104B corresponds to four channels RS0 to RS3 and can start updating from the channel whose maximum value setting register has a value indicating the maximum random number value set. The function setting register area for the setting example AKA01 shown in Figure 10-3 includes an RL0 maximum value setting register at addresses FE3F[H] to FE40[H], an RL1 maximum value setting register at addresses FE41[H] to FE42[H], an RL2 maximum value setting register at addresses FE43[H] to FE44[H], and an RL3 maximum value setting register at addresses FE45[H] to FE46[H], each corresponding to the four channels RL0 to RL3 of the 16-bit random number circuit 104A. Furthermore, this function setting register area includes an RS0 maximum value setting register at address FE47[H], an RS1 maximum value setting register at address FE48[H], an RS2 maximum value setting register at address FE49[H], and an RS3 maximum value setting register at address FE4A[H], which correspond to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. The function setting register storage value table of configuration example AKT01 is configured so that, of these maximum value setting registers, the stored value of the RL0 maximum value setting register is set first, then the stored value of the RL2 maximum value setting register, then the stored value of the RS1 maximum value setting register, then the stored value of the RS2 maximum value setting register, and finally the RS3 maximum value setting register. Therefore, updating of channel RL0 in the 16-bit random number circuit 104A starts first, then updating of channel RL2 in the 16-bit random number circuit 104A starts next, then updating of channel RS1 in the 8-bit random number circuit 104B starts next, then updating of channel RS2 in the 8-bit random number circuit 104B starts next, and finally updating of channel RS3 in the 8-bit random number circuit 104B starts last. In this way, because updates start in order from the random number value for which the maximum random number value is set, the uncertainty of the random number value is increased depending on the timing at which the update of the random number value starts, reducing the processing load and enabling appropriate updating of the random number value.

The power supply start response processing P_POWER_ON is included in the processing that can be called from the game control main processing P_MAIN, which is a startup processing executed based on the start of power supply to the pachinko gaming machine 1. It uses the function setting register storage value table of the example configuration AKT01 to set storage values in the function setting register area, which serves as a storage area for functions. Since the maximum random number value updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, the power supply start response processing P_POWER_ON can be executed as a maximum value setting processing. The 16-bit random number circuit 104A can update a first random number value consisting of 16 bits, which corresponds to a specific number of bytes (2 bytes). The 8-bit random number circuit 104B can update a second random number value consisting of 8 bits, which corresponds to a predetermined number of bytes (1 byte) smaller than the specific number of bytes. When the power supply start response process P_POWER_ON is executed, the function setting register storage value table of configuration example AKT01 is used to set the maximum random number value of the first random number value that can be updated by the 16-bit random number circuit 104A, and then the maximum random number value of the second random number value that can be updated by the 8-bit random number circuit 104B. In this way, by setting the first random number value of a specific number of bytes and then setting the second random number value of a predetermined number of bytes, the first random number value and second random number value can be stably updated, making it possible to update the random number values appropriately.

Figure 10-9 shows an example of the configuration of the RWM access protection register. The RWM access protection register is located at address FF00[H] in the example configuration AKA02 of the function control register area shown in Figure 10-4. The value stored in the RWM access protection register will be different depending on whether access to the RAM 102 that serves as the RWM is permitted or prohibited.

Figure 10-9 (A) shows an example of the bit configuration of the RWM access protection register. The RWM access protection register can store 8-bit data RAP with bit numbers "0" to "7", and bit data RAP0 with bit number "0" can be set to 0 [B] or 1 [B]. In contrast, bit data with bit numbers "1" to "7" are always set to 0 [B] and represent fixed values that are never set to "1".

Figure 10-9 (B) is a diagram illustrating an example of the use of bit data RAP of the RWM access protection register. In bit data RAP, bit data RAP0 with bit number "0" is an RWM access control bit; setting it to 0 [B] prohibits access to the RWM, and setting it to 1 [B] allows access to the RWM. When power supply to the pachinko gaming machine 1 begins, bit data RAP0 with bit number "0" is set to its initial value, 0 [B]. This makes it possible to prohibit access to RAM 102, which serves as the RWM, when power supply to the pachinko gaming machine 1 begins.

Figure 10-10 is a flowchart showing an example of power-off processing P_POWER_OFF. Power-off processing P_POWER_OFF is included in the processing that can be called from the game control timer interrupt processing P_PCT shown in Figure 5, and can be executed in step S51 each time a timer interrupt occurs. When power-off processing P_POWER_OFF is executed, the CPU 103 sets the backup monitoring timer address using a transfer command to set a pointer (step AKS31). The backup monitoring timer address is the address of the backup monitoring timer located in the game work area of RAM 102.

Input port number "3" is input (step AKS32). Input port number "3" is an input port assigned port number "3" and includes a power check signal input bit. Therefore, a logical AND operation is performed using the input data for input port number "3" and the check data corresponding to the bit position of the power check signal input bit. At this time, whether the power check signal input bit is "0" is determined based on whether the zero flag is on (step AKS33). When the power check signal input bit's bit value is 0 [B], which corresponds to "0," it indicates that the power check signal is in the off state, and when the bit value is 1 [B], which corresponds to "1," it indicates that the power check signal is in the on state.

If the power check signal input bit is "1" rather than "0" (step AKS33; No), backup monitoring timer clear data is stored using a transfer command that can update the stored data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing the clear data in the backup monitoring timer, the backup monitoring timer can be cleared when the power check signal is in the ON state, in response to a state other than power-off determination being made.

If the power check signal input bit is "0" in response to step AKS33 (step AKS33; Yes), the backup monitoring timer's time count is updated by adding 1 (step AKS35). The backup monitoring timer is loaded using a transfer command to read the stored data at the address pointed to by the pointer (step AKS36). Then, a calculation return command that compares the backup monitoring timer's time count with the judgment value corresponding to the backup judgment time (step AKS37) confirms that the backup monitoring timer does not indicate the backup judgment time (step AKS38). This calculation return command corresponds to a zero flag that turns off when the backup monitoring timer's time count differs from the judgment value corresponding to the backup judgment time, thereby terminating the power-off process and enabling a return to the special symbol process. Thus, if the backup monitoring timer does not indicate the backup judgment time (step AKS38; Yes), the power-off process is terminated.

If the backup monitoring timer indicates the backup determination time in response to step AKS38 (step AKS38; No), the checksum calculation process P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC in step AKS39 may be the same process as the checksum calculation process included in the RWM check process P_RWM_CHK in step S2 in the main game control process P_MAIN shown in FIG. 4. In this way, by executing the same checksum calculation process in response to the start and stop of power supply to the pachinko gaming machine 1, it becomes possible to determine whether recovery using backup data is possible based on whether the contents stored in the game work area of RAM 102 are retained unchanged. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer command to write it to the memory area at the address pointed to by the pointer (step AKS40).

After step AKS40, an exclusive OR instruction is executed to set clear data to the output value data (step AKS41). This exclusive OR instruction executes an exclusive OR on the stored values of a single register, resulting in all bit values being the exclusive OR of the same value. This allows the stored value to be initialized to clear data 00 [H]. This clear data is stored in the RWM access protect register by a transfer instruction to write it to the memory area at the top address in the function setting register area (step AKS42). The RWM access protect register enables function control to prohibit access to the RWM RAM 102 in response to the setting of the clear data 00 [H]. Therefore, by storing the clear data in the RWM access protect register in step AKS42, access to the RAM 102 is prohibited in response to a power outage in the pachinko gaming machine 1.

After step AKS42, output port numbers "0" through "10" are cleared (step AKS43). Output port numbers "0" through "10" are the output ports with port numbers "0" through "10," and represent all of the output ports in the gaming control microcomputer 100. Therefore, step AKS43 clears all of the output ports in the gaming control microcomputer 100 in response to the power supply cutoff in the pachinko gaming machine 1. At this time, a transfer command for setting an internal register in the CPU 103 sets a connection confirmation signal OFF output value (step AKS44). The connection confirmation signal OFF output value is a value indicating that the connection confirmation signal is OFF, and may be, for example, 01 [H]. This connection confirmation signal OFF output value is stored in the output port number "1" register by a transfer command for writing it to a memory area at a specified address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to OFF.

Following step AKS45, a PTC0 interrupt disable output value is set by a transfer command for setting an internal register in the CPU 103 (step AKS46). The PTC0 interrupt disable output value is an output value for disabling timer interrupts using channel PTC0 of the timer circuit 136. This PTC0 interrupt disable output value is stored in the PTC0 control register by a transfer command for writing to a function setting register at a specified address in the function setting register area (step AKS47). The PTC0 control register can set the usage state of the timing function using channel PTC0 of the timer circuit 136. In step AKS47, the PTC0 interrupt disable output value set in step AKS46 is stored in the PTC0 control register, thereby disabling timer interrupts for game control in response to a power outage in the pachinko gaming machine 1.

Once this setting corresponding to the elapse of the backup determination time has been made, the system transitions to a standby state by executing a loop process. In this standby state, input port number "3" is input (step AKS48), and it is determined whether the power supply confirmation signal input bit is "0" (step AKS49). If the power supply confirmation signal is in the OFF state and the power supply confirmation signal input bit is "0" (step AKS49; Yes), the system continues the loop process returning to step AKS48. This allows the system to maintain a standby state until operation is halted due to a power outage in response to an interruption in the power supply to the pachinko gaming machine 1, thereby preventing inappropriate changes to stored data and runaway processing by the CPU 103.

If the power check signal input bit is "1" and not "0" in response to step AKS49 (step AKS49; No), the power interruption recovery vector table address is set to the stack pointer (step AKS50), and then the power interruption processing P_POWER_OFF is terminated by an interrupt return instruction. The power interruption recovery vector table address is the address of the power interruption recovery vector table provided in the game program area of ROM 101. The interrupt return instruction can use the stack pointer as a pointer to set the data stored in the memory area indicated by the address specified by the stored value of the stack pointer to the program counter. For example, the data stored in the memory area indicated by the address specified by the stored value of the stack pointer is set to the lower byte of the program counter, and the data stored in the memory area indicated by the address specified by the value obtained by adding 1 to the stored value of the stack pointer is set to the upper byte of the program counter.

Figures 10-11 are diagrams illustrating an example of the data structure used for power-off processing P_POWER_OFF. In power-off processing P_POWER_OFF, for example, step AKS38 executes branch processing using the time value of the backup monitoring timer, and step AKS40 saves checksum data using a checksum buffer. Furthermore, step AKS50 sets a vector table address for power-off recovery, enabling game control programs to be executed from the beginning if normal power supply is resumed without halting operation after a power-off interruption is detected in the pachinko gaming machine 1. In this way, power-off processing P_POWER_OFF uses the backup monitoring timer, checksum buffer, and power-off recovery vector table to enable control when the power supply to the pachinko gaming machine 1 is interrupted.

Figure 10-11 (A) shows a configuration example AKB01 of a memory area that serves as a backup data area. The backup data area of configuration example AKB01 can store backup setting data that is used when backing up data stored in the game work area of RAM 102. This backup data area includes a backup monitoring timer at address F000[H] and a checksum buffer at address F0DE[H]. Address F000[H] is the starting address of the game work area, and address F0DE[H] is the ending address of the game work area. In this way, providing a backup data area at the starting address and ending address of the game work area enables appropriate backup of data stored in the game work area of RAM 102.

Figure 10-11 (B) shows an example configuration AKT11 of a power failure recovery vector table. The power failure recovery vector table of configuration AKT11 can specify a return address from power failure processing in response to an interrupt return command when normal power supply is resumed. The power failure recovery vector table is composed of table data containing lower address designation data 00 [H] stored at address 0016 [H] in the game program area of ROM 101 and upper address designation data 00 [H] stored at address 0017 [H] in the game program area of ROM 101. In step AKS50 of the power failure processing P_POWER_OFF, data indicating address 0016 [H] is set in the stack pointer as the power failure recovery vector table address. Thereafter, an interrupt return command is issued to set the stored value of the program counter to 0000 [H], thereby restoring processing and enabling the game control main processing P_MAIN to be executed from the beginning.

Figure 10-12 is a flowchart showing an example of the random number update process P_RANDOM. The random number update process P_RANDOM is included in the processes that can be called from the game control timer interrupt process P_PCT shown in Figure 5, and can be executed in step S56 in response to the occurrence of a periodic timer interrupt after a predetermined time has elapsed, for example, 4 ms. On the other hand, the random number update process P_RANDOM is not included in the processes that can be called from the game control main process P_MAIN shown in Figure 4, and is not executed in the loop process that is repeated until a timer interrupt occurs after step S7. Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt after a predetermined time has elapsed, it is not included in the second process that can be repeatedly executed until the first process is executed. Furthermore, although the random number update process P_RANDOM can be called and executed in the game control timer interrupt process P_PCT that controls the progress of the game, it cannot be called and executed in the standby process that serves as a repeated loop process after startup processes such as the power supply start response process P_POWER_ON in step S1 in the game control main process P_MAIN that is executed based on the start of power supply to the pachinko gaming machine 1.

The random number update process P_RANDOM uses internal registers of the CPU 103, such as the B register, DE register, and HL register, to update the numerical data indicating the values of the random number MR1-2 for the winning symbol and the random number MR2-1 for the winning normal symbol. The random number MR1-2 for the winning symbol is used to determine the confirmed special symbol that results in the display of the special symbol in a special symbol game, which is a variable display of special symbols on the first special symbol display device 4A or the second special symbol display device 4B. The random number MR2-1 for the winning normal symbol is used to determine the confirmed normal symbol that results in the display of the normal symbol in a normal symbol game, which is a variable display of normal symbols on the normal symbol display device 20. The random number update process P_RANDOM can update the random number values for both the winning symbol random number MR1-2 and the normal winning symbol random number MR2-1 using the B register, DE register, and HL register as common internal registers.

When the CPU 103 executes the random number update process P_RANDOM, it sets the winning symbol random number counter address using a transfer command to set the HL register used as a random number pointer (step AKS61). The winning symbol random number counter address is the address of the winning symbol random number counter provided in the game work area of RAM 102. The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, the LDQ command is used to store the address of the winning symbol random number counter in the random number pointer, thereby setting the winning symbol random number MR1-2 as the random number value to be updated.

Following step AKS61, a transfer command is issued to set register B, which is used as the random number maximum register, to set a random number maximum value corresponding to the maximum random number determination value for the winning symbol (step AKS62). The random number maximum register can store the maximum value that the random number to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for random number MR1-2 for the winning symbol, the maximum value included in the update range of random number MR1-2, such as C7 [H] corresponding to "199", is stored in the random number maximum register using the LD command. This allows the maximum random number value for random number MR1-2, which was set as the random number to be updated in step AKS61, to be set.

After step AKS62, a transfer command is issued to set the DE register used as the initial value pointer, setting the random number initial value data buffer address for the winning symbol (step AKS63). The random number initial value data buffer address for the winning symbol is the address of the random number initial value data buffer for the winning symbol located in the game work area of RAM 102. The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and setting the stored value makes it possible to obtain or change the random number initial value. In step AKS63, the LDQ command is used to store the address of the random number initial value data buffer for the winning symbol in the initial value pointer, thereby making the random number initial value obtainable and changeable corresponding to the random numbers MR1-2 selected as the random numbers to be updated in step AKS61. Next, a subroutine call command is issued to execute the initial value change random number update process P_RANCP (step AKS64). The initial value change random number update process P_RANCP in step AKS64 updates the random numbers MR1-2 for winning symbols, which are the random number values to be updated, and changes the random number initial value, based on the settings in steps AKS61-AKS63.

After the initial value change random number update process P_RANCP in step AKS64, a transfer command is issued to set the HL register used as a random number pointer, setting the random number counter address for the normal symbol (step AKS65). The random number counter address for the normal symbol is the address of the random number counter for the normal symbol located in the game work area of RAM 102. In step AKS65, the LDQ command is used to store the address of the random number counter for the normal symbol in the random number pointer, thereby setting the random number MR2-1 for the normal symbol as the random value to be updated.

Following step AKS65, a transfer instruction is issued to set register B, which is used as the random number maximum register, to set a random number maximum value corresponding to the random number maximum judgment value for the normal symbol per symbol (step AKS66). In step AKS66, for random number MR2-1 for the normal symbol per symbol, the maximum value included in the update range of random number MR2-1, such as C6[H] corresponding to the maximum value "198", is stored in the random number maximum register using the LD instruction. This allows the maximum random number value for random number MR2-1, which was selected as the random number value to be updated in step AKS65, to be set.

Following step AKS66, a transfer instruction is issued to set the DE register used as the initial value pointer, thereby setting the random number initial value data buffer address for the normal symbol (step AKS67). The random number initial value data buffer address for the normal symbol is the address of the random number initial value data buffer for the normal symbol provided in the game work area of RAM 102. In step AKS67, the LDQ instruction is used to store the address of the random number initial value data buffer for the normal symbol in the initial value pointer, thereby setting the random number initial value for random number MR2-1, which was set as the random number value to be updated in step AKS65, to be obtainable and changeable. Next, a subroutine call instruction, which is common to step AKS64, is issued to execute the initial value change random number update process P_RANCP (step AKS68). The initial value change random number update process P_RANCP in step AKS68 updates the random number value to be updated, MR2-1, for the normal winning symbol, and changes the random number initial value, based on the settings in steps AKS65 to AKS67.

Figure 10-13 is a diagram illustrating an example of the use of data configuration related to the random number update process P_RANDOM. In the random number update process P_RANDOM, the initial value change random number update process P_RANCP is executed in step AKS64 using the winning symbol random number counter whose address was set in the random number pointer in step AKS61 and the winning symbol random number initial value data buffer whose address was set in the initial value pointer in step AKS63. Furthermore, in the random number update process P_RANDOM, the initial value change random number update process P_RANCP is executed in step AKS68 using the normal symbol winning symbol random number counter whose address was set in the random number pointer in step AKS65 and the normal symbol winning symbol random number initial value data buffer whose address was set in the initial value pointer in step AKS67. The winning symbol random number counter is provided in the special symbol random number buffer area and is capable of storing numerical data corresponding to the winning symbol random numbers MR1-2. The random number initial value data buffer for winning symbols is provided in the random number data area for winning symbols and can store numerical data corresponding to the random number initial value of the random number MR1-2. The random number counter for winning normal symbols is provided in the random number data area for winning symbols and can store numerical data corresponding to the random number MR2-1 for winning normal symbols. The random number initial value data buffer for winning normal symbols is provided in the random number data area for winning symbols and can store numerical data corresponding to the random number initial value of the random number MR2-1. In this way, the random number update process P_RANDOM enables software to update the random numbers MR1-2 and MR2-1 using the winning symbol random number initial value data buffer provided in the winning symbol random number data area, the normal symbol winning symbol random number counter, the normal symbol winning symbol random number initial value data buffer, and the winning symbol random number counter provided in the special symbol random number buffer area.

Figure 10-13 (A) shows a configuration example AKB11 of a random number data area for winning symbols. The winning symbol random number data area of configuration example AKB11 includes a random number initial value data buffer for winning symbols at address F050 [H], a winning symbol initial value random number counter at address F051 [H], a random number counter for normal winning symbols at address F052 [H], a random number initial value data buffer for normal winning symbols at address F053 [H], and a normal winning symbol initial value random number counter at address F054 [H]. Of these, address F050[H] of the random number initial value data buffer for winning symbols is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, address F052[H] of the random number counter for normal symbols is set to the random number pointer by step AKS65 of the random number update process P_RANDOM, and address F053[H] of the random number initial value data buffer for normal symbols is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The winning symbol initial value random number counter can store numerical data corresponding to random numbers MR1-3, which are the initial values for winning symbols. The normal symbol initial value random number counter can store numerical data corresponding to random numbers MR2-2, which are the initial values for normal symbols.

Figure 10-13 (B) shows an example configuration AKB12 of the special symbol random number buffer area. The special symbol random number buffer area of example configuration AKB12 includes a special symbol determination random number buffer at address F07F[H], a winning symbol random number counter at address F081[H], a variation pattern type selection random number buffer at address F082[H], a variation pattern random number buffer at address F083[H], and a losing effect selection random number buffer at address F084[H]. Of these, the winning symbol random number counter address F081[H] is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The special symbol determination random number buffer is capable of storing numerical data corresponding to the special symbol determination random number MR1-1 obtained from the 16-bit random number circuit 104A. The random number buffer for selecting a variation pattern type can store numerical data corresponding to the random number MR3-3 for selecting a variation pattern type obtained from the 8-bit random number circuit 104B. The random number buffer for variation patterns can store numerical data corresponding to the random number MR3-4 for variation patterns obtained from the 8-bit random number circuit 104B. The random number buffer for selecting a losing effect can store numerical data corresponding to the random number MR3-2 for selecting a losing effect obtained from the 16-bit random number circuit 104A.

Figure 10-14 is a flowchart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the processes that can be called from the random number update process P_RANDOM shown in Figure 10-12, and can be executed in step AKS64 after the random numbers MR1-2 for winning symbols have been set in steps AKS61 to AKS63, and can be executed in step AKS68 after the random numbers MR2-1 for normal and winning symbols have been set in steps AKS65 to AKS67. Such initial value change random number update process P_RANCP makes it possible to update the values of the random numbers MR1-2 using numerical data corresponding to the random numbers MR1-2 for winning symbols in step AKS64. Additionally, the initial value change random number update process P_RANCP uses the numerical data corresponding to the random number MR2-1 for the normal symbol in step AKS68 to update the value of the random number MR2-1.

When the CPU 103 executes the initial value change random number update process P_RANCP, it first executes a compare and add instruction (step AKS101). This compare and add instruction uses the stored data at the address indicated by the stored value of the HL register, which is a random number pointer, as the update target value, and the stored value of the B register, which is a random number maximum value register, as the comparison judgment value. It can be executed by a single ICPLD instruction, which is a third special transfer instruction. The stored value of the HL register, which is a random number pointer, indicates the address of the random number counter in which numerical data corresponding to the random number value to be updated is stored. The stored value of the B register, which is a random number maximum value register, indicates the random number maximum value set corresponding to the random number value to be updated. If the count value of the random number counter indicating the random number value to be updated is less than the stored value of the random number maximum value register, the count value of the random number counter is updated to increment by 1, thereby incrementing the random number value to be updated by 1. In contrast, if the count value of the random number counter indicating the random number value to be updated is equal to or greater than the value stored in the maximum random number register, the random number counter is cleared and initialized to "0," changing the random number value to the minimum random number value. Therefore, the compare and add instruction of step AKS101 is a single instruction that includes comparing the random number value to be updated with the maximum random number value, incrementing the random number value to be updated by 1 if the comparison result is less than the maximum random number value, and changing the random number value to the minimum random number value if the comparison result is equal to or greater than the maximum random number value. In this way, when updating the random number value to be updated using the initial value change random number update process P_RANCP, a single compare and add instruction is executed first. By executing this single compare and add instruction first, it is possible to prevent malfunctions and update the random number value appropriately.

When the compare and add instruction is executed in step AKS101, a transfer instruction for reading stored data is used to load the random number value pointed to by the random number pointer (step AKS102). The random number pointer and initial value pointer are also exchanged (step AKS103). The random number value loaded in step AKS102 is then compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). It is determined whether the compared random number value is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random number value to be updated. Therefore, in step AKS104, after the compare and add instruction of step AKS101 is executed, the random number value to be updated after being updated by the compare and add instruction is compared with the random number initial value.

If the random number value corresponding to step AKS105 differs from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the compare and add instruction of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated will indicate the updated random number value to be updated. Then, when the initial value change random number update process P_RANCP ends due to the judgment result of step AKS105, the stored value of the random number counter indicating the updated random number value to be updated is stored as the current random number value. Therefore, in step AKS105, if the updated random number value to be updated does not match the random number initial value, the initial value change random number update process P_RANCP ends, allowing the updated random number value to be stored as the current random number value.

If the random number value is the same as the value stored in the random number initial value data buffer pointed to by the initial value pointer in response to step AKS105 (step AKS105; No), the initial value random number counter pointed to when the value stored in the initial value pointer is incremented by 1 is loaded (step AKS106). In the example configuration AKB11 of the winning symbol random number data area shown in Figure 10-13 (A), when 1 is incremented from address F050 [H] where the winning symbol random number initial value data buffer is located, the next address F051 [H] is provided with an initial value random number counter for the winning symbol. Furthermore, when 1 is incremented from address F053 [H] where the normal symbol winning symbol random number initial value data buffer is located, the next address F054 [H] is provided with an initial value random number counter for the normal symbol winning symbol. Therefore, in step AKS106, if the value stored in the initial value pointer indicates the address of the random number initial value data buffer for the winning symbol, the count value of the initial value random number counter for the winning symbol is read out. Also, in step AKS106, if the value stored in the initial value pointer indicates the address of the random number initial value data buffer for the normal winning symbol, the count value of the initial value random number counter for the normal winning symbol is read out. In this way, in step AKS106, the count value of the initial value random number counter can be read out as the initial value random number value.

When the initial value random number counter is loaded in step AKS106, the count value of the initial value random number counter read thereby is stored in the random number counter pointed to by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 can store the count value of the initial value random number counter as the current random number value to be updated. Therefore, if the result of step AKS105 is that the updated random number value to be updated matches the random number initial value, step AKS107 can store the initial value random number value read in step AKS106 as the current random number value.

Following step AKS107, the count value of the initial value random number counter read in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), and then the initial value change random number update process P_RANCP ends. Because the value stored in the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, step AKS108 can store the count value of the initial value random number counter as a new random number initial value. Therefore, if the result of step AKS105 indicates that the updated random number value to be updated matches the random number initial value, step AKS107 stores the random number value for initial value as the current random number value, and step AKS108 can store the random number value for initial value read in step AKS106 as the new random number initial value. In this way, setting a new random number initial value increases the uncertainty of the random number value, and storing it as the current random number value also prevents an increase in data volume, enabling appropriate random number updating.

The random number update process P_RANDOM shown in Figure 10-12 executes the initial value change random number update process P_RANCP in step AKS64 after setting the target random number value, maximum random number value, and initial random number value for the random numbers MR1-2 for winning symbols in steps AKS61 to AKS63. The initial value change random number update process P_RANCP enables the update of the target random number value and the change of the initial random number value based on the settings for the target random number value, maximum random number value, and initial random number value. The initial value change random number update process P_RANCP in step AKS64 enables the update of the target random number value for the winning symbol MR1-2, which was set as the target random number value for update in step AKS61, using the maximum random number set in step AKS62 and the initial random number set in step AKS63. Additionally, the initial value change random number update process P_RANCP in step AKS64 allows the random number initial value to be changed for the random number MR1-2 for the winning symbol that was set as the random number value to be updated in step AKS61 if that value matches the random number initial value set in step AKS63. In this way, appropriate random number values can be updated by updating the set random number value to be updated.

The random number update process P_RANDOM executes the initial value change random number update process P_RANCP in step AKS68 after setting the random number value to be updated, the maximum random number value, and the initial random number value for the random number MR2-1 for the normal symbol per symbol in steps AKS65 through AKS67. The initial value change random number update process P_RANCP in step AKS68 enables the random number MR2-1 for the normal symbol per symbol, which is set as the random number value to be updated in step AKS65, to be updated using the maximum random number value set in step AKS66 or the initial random number value set in step AKS67. Furthermore, the initial value change random number update process P_RANCP in step AKS68 enables the initial random number value to be changed for the random number MR2-1 for the normal symbol per symbol, which is set as the random number value to be updated in step AKS65, if the value matches the initial random number value set in step AKS67. In this way, by updating the set target random number value, it is possible to update the random number value appropriately. Also, by updating the set target random number value or changing the initial random number value, it is possible to update the random number value appropriately.

The random number update process P_RANDOM can update the random number MR1-2 for the winning symbol, which is used when determining the display result of the special symbol, through a first update process consisting of steps AKS61 to AKS64, and can update the random number MR2-1 for the winning normal symbol, which is used when determining the display result of the normal symbol, through a second update process consisting of steps AKS65 to AKS68. Steps AKS61 to AKS64 update the random number MR1-2 for the winning symbol as the first random number value, and then steps AKS65 to AKS68 update the random number MR2-1 for the winning normal symbol as the second random number value. The confirmed special symbol that results in the display of the special symbol corresponds to the maximum number of times the jackpot opening occurs during jackpot gaming. Additionally, the confirmed special symbol, which is the display result of the special symbol, may correspond to whether or not the game is controlled to a high probability state after the jackpot game state ends, or the maximum number of variable display times that can be performed in the time-saving state after the jackpot game state ends. In contrast, the confirmed normal symbol, which is the display result of the normal symbol, corresponds to the opening time and number of times the second large prize opening is opened. Therefore, the display result of the special symbol attracts more attention from players than the display result of the normal symbol. The random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2 as the first random number value and then updates the random number MR2-1 as the second random number value. By updating the first random number value used to determine the display result that attracts the player's attention before the second random number value, the occurrence of malfunctions is suppressed and the random number value can be updated appropriately.

In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2, which will be the first random number value, and steps AKS65 to AKS68 can update the random number MR2-1, which will be the second random number value. The initial value change random number update process P_RANCP of step AKS64 can be called and executed in response to the random number MR1-2, which will be the first random number value, and the initial value change random number update process P_RANCP of step AKS68 can be called and executed in response to the random number MR2-1, which will be the second random number value. In this way, the random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2, which will be the first random number value, and the random number MR2-1, which will be the second random number value, thereby making their initial values changeable. This common update process, the initial value change random number update process P_RANCP, prevents an increase in program size, stably updates the first random number value and second random number value, and enables appropriate random number value updates.

In the random number update process P_RANDOM, steps AKS61 to AKS64, which enable updating of random number MR1-2, which will become the first random number value, constitute the first update process, and steps AKS65 to AKS68, which enable updating of random number MR2-1, which will become the second random number value, constitute the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM updates random number MR1-2, which will become the first random number value, and random number MR2-1, which will become the second random number value, thereby enabling their initial values to be changed by calling the initial value change random number update process P_RANCP as a common update process in both the first and second update processes. This common update process, the initial value change random number update process P_RANCP, prevents an increase in program size, stably updates the first random number value and second random number value, and enables appropriate random number value updates.

In the random number update process P_RANDOM, steps AKS61 to AKS64, which enable updating of random number MR1-2, which will become the first random number value, constitute the first update process, and steps AKS65 to AKS68, which enable updating of random number MR2-1, which will become the second random number value, constitute the second update process. The first and second update processes use the HL register, B register, and DE register of CPU 103, which are common internal storage means, to enable updating of random number MR1-2, which will become the first random number value, and random number MR2-1, which will become the second random number value. In this way, the first and second random number values can be stably updated using the common internal storage means, enabling appropriate random number updating.

In the random number update process P_RANDOM, before step AKS64 executes the initial value change random number update process P_RANCP, steps AKS61 to AKS63 store reference information such as the winning symbol random number counter address, the winning symbol random number maximum judgment value, and the winning symbol random number initial value data buffer address in the HL register, B register, and DE register of CPU 103, which are internal storage means. In addition, in the random number update process P_RANDOM, before step AKS68 executes the initial value change random number update process P_RANDCP, steps AKS65 to AKS67 store reference information such as the normal symbol winning symbol random number counter address, the normal symbol winning symbol random number maximum judgment value, and the normal symbol winning symbol random number initial value data buffer address in the HL register, B register, and DE register of CPU 103, which are internal storage means. The instruction used to update random number MR1-2, which becomes the first random number value in step AKS61, and the instruction used to update random number MR2-1, which becomes the second random number value in step AKS65, are common instructions in that they set the HL register of CPU 103, and since step AKS61 sets the random number counter address for the winning symbol but step AKS65 sets the random number counter address for the normal symbol, different reference information can be set. The instruction used to update random number MR1-2, which becomes the first random number value, and the instruction used to update random number MR2-1, which becomes the second random number value in step AKS66 are common instructions in that they set the B register of CPU 103, and since step AKS62 sets the random number maximum value corresponding to the random number maximum judgment value for the winning symbol but step AKS66 sets the random number maximum value corresponding to the random number maximum judgment value for the normal symbol, different reference information can be set. The instruction used to update random number MR1-2, which becomes the first random number value in step AKS63, and the instruction used to update random number MR2-1, which becomes the second random number value in step AKS67, are common instructions in that they set the DE register of CPU 103. Step AKS63 sets the random number initial value data buffer address for the winning symbol, while step AKS67 sets the random number initial value data buffer address for the winning symbol, so different reference information can be set. These steps AKS61 to AKS63 and steps AKS65 to AKS67 use common instructions, such as the LD instruction and the LDQ instruction, which are transfer instructions for setting the internal registers of CPU 103, to enable different reference information to be set. Then, steps AKS64 and AKS68 call and execute the initial value change random number update process P_RANCP using a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is a specific update process, the instruction used to update the random number MR1-2, which becomes the first random number value, and the instruction used to update the random number MR2-1, which becomes the second random number value, are the same. By using a common instruction to make it possible to update the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value, the first random number value and the second random number value can be stably updated, making it possible to update the random number values appropriately.

The random number update process P_RANDOM enables the update of random number MR1-2, which will be the first random number value, through steps AKS61 to AKS64, which constitute the first update process, and enables the update of random number MR2-1, which will be the second random number value, through steps AKS65 to AKS68, which constitute the second update process. Steps AKS64 and AKS68 then call and execute the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP shown in Figure 10-14 first executes a single compare and add instruction, making the compare and add instruction executable first in both cases of updating random number MR1-2 as the first random number value and updating random number MR2-1 as the second random number value. By executing this compare and add instruction first, it is possible to prevent errors from occurring in the first or second random number value and update the random number values appropriately.

When the initial value change random number update process P_RANCP is executed in step AKS64 of the random number update process P_RANDOM, it can update the random number MR1-2 for the winning symbol, and can change the random number initial value corresponding to the random number MR1-2 for the winning symbol using the random number MR1-3, which becomes the initial value for the winning symbol. Furthermore, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM, it can update the random number MR2-1 for the winning normal symbol, and can change the random number initial value corresponding to the random number MR2-1 for the winning normal symbol using the random number MR2-2, which becomes the initial value for the winning normal symbol. Therefore, the random number MR1-3, which serves as the initial value for the winning symbol, is a first initial value random number value used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR1-2 for the winning symbol, which becomes the first random number value, when the initial value change random number update process P_RANCP is executed in step AKS64 of the random number update process P_RANDOM. The random number MR2-2, which serves as the initial value for the winning normal symbol, is a second initial value random number value used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR2-1 for the winning normal symbol, which becomes the second random number value, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM.

Figure 10-15 is a flowchart showing an example of the random number update process P_TFINIT for determining initial values. The random number update process P_TFINIT for determining initial values is included in the process that can be called from the main process P_MAIN for game control shown in Figure 4, and can be executed in step S9 of the loop process that is repeated after step S7 until a timer interrupt occurs. The random number update process P_TFINIT for determining initial values is also included in the process that can be called from the timer interrupt process P_PCT for game control shown in Figure 5, and can be executed in step AKS57 in response to the occurrence of a periodic timer interrupt upon the lapse of a predetermined time, for example, 4 ms. Therefore, the random number update process P_TFINIT for determining initial values is included in a first process that can be executed in response to a timer interrupt upon the lapse of a predetermined time, and a second process that can be executed repeatedly until the first process is executed. Furthermore, the initial value determination random number update process P_TFINIT can be called and executed in the game control timer interrupt process P_PCT that controls the progress of the game, and can also be called and executed in step S9, which is included in the standby process as a repeated loop process, after startup processes such as the power supply start response process P_POWER_ON in step S1 in the game control main process P_MAIN that is executed based on the start of power supply to the pachinko gaming machine 1. In this way, the initial value determination random number update process P_IFINIT is included in processes that can be executed in response to periodic timer interrupts as initial value random number update process, and is also included in processes that can be executed repeatedly at irregular intervals. This makes the update period and update speed of the initial value random number variable uncertain, thereby increasing the uncertainty of the initial value random number variable and enabling appropriate random number value updating.

When the CPU 103 executes the initial value determination random number update process P_TINIT, it sets the winning symbol initial value random number counter address using a transfer instruction to set a pointer (step AKS81). The winning symbol initial value random number counter address is address F051 [H] assigned to the winning symbol initial value random number counter in the winning symbol random number data area configuration example AKB11 shown in Figure 10-13 (A). With the pointer set in this manner, the count value of the winning symbol initial value random number counter can be updated within the update range of "0" to "199" using a compare and add instruction (step AKS82). This compare and add instruction uses the stored data at the address pointed to by the pointer as the update target value and the immediate value specified by the operand as the comparison judgment value. It can be executed by a single ICPLD instruction, which is the third special transfer instruction. The value stored in the pointer indicates the address of the random number counter where the numerical data corresponding to the initial value random number to be updated is stored. The immediate value specified by the operand indicates the maximum random number value for the initial value that is set corresponding to the random number value for the initial value to be updated. If the count value of the random number counter indicating the random number value for the initial value to be updated is less than the maximum random number value for the initial value, the count value of the random number counter is updated to increment by 1, thereby incrementing the random number value for the initial value to be updated by 1. On the other hand, if the count value of the random number counter indicating the random number value for the initial value to be updated is equal to or greater than the value stored in the maximum random number register for the initial value, the random number counter is cleared and initialized to "0", thereby changing the random number value for the initial value to be updated to the minimum random number value. Therefore, the compare and add instruction in step AKS82 is a single instruction that sets random numbers MR1-3, which serve as the initial values for the winning symbols, to the random number value for the initial value to be updated, compares the random number value for the initial value to the maximum random number for the initial value, increments the random number value for the initial value to be updated by 1 if the comparison result is less than the maximum random number value for the initial value, and changes the random number value for the initial value to the minimum random number if the comparison result is equal to or greater than the maximum random number value for the initial value. Note that the compare and add instruction is not limited to an ICPLD instruction in which the address of the stored data indicating the update value is specified by a pointer. For example, it could be an ICPLDQ instruction in which the upper address is set using the Q register and the lower address is set using an immediate value specified in the first operand of the compare and add instruction. In this case, the immediate value specified in the second operand of the compare and add instruction can be set as the comparison judgment value. Using such a compare and add instruction to update the random number value for the initial value to be updated reduces the occurrence of errors and enables appropriate random number updating.

After step AKS82, a transfer command for setting a pointer is issued to set the address of the initial random number counter for the normal symbol (step AKS83). The address of the initial random number counter for the normal symbol is address F054[H] assigned to the initial random number counter for the normal symbol in the example configuration AKB11 of the random number data area for winning symbols shown in Figure 10-13(A). With the pointer set in this manner, a comparison and addition command is issued to update the count value of the initial random number counter for the normal symbol within the update range of "1" to "198" (step AKS84), thereby completing the initial value determination random number update process P_TFINIT. The comparison and addition command for step AKS84 may be the same as the comparison and addition command for step AKS82. However, in the compare and add instruction of step AKS84, random number MR2-2, which serves as the initial value for the normal symbol, is set as the random number value for the initial value to be updated, and therefore the immediate value specified by the operand indicating the maximum random number value for the initial value is set to a different value than in the compare and add instruction of step AKS82. Therefore, the compare and add instruction of step AKS84 is a single instruction that sets random number MR2-2, which serves as the initial value for the normal symbol, as the random number value for the initial value to be updated, compares the random number value for the initial value to the maximum random number value for the initial value, increments the random number value for the initial value to be updated by 1 if the result of the comparison is less than the maximum random number value for the initial value, and changes the random number value for the initial value to the minimum random number value if the result of the comparison is equal to or greater than the maximum random number value for the initial value. Using such a compare and add instruction to update the random number value for the initial value to be updated prevents malfunctions and enables appropriate random number updating.

The random number update process for determining initial values P_TFINIT updates random number MR1-3, which serves as the initial value for the winning symbol, in steps AKS81 and AKS82 as an update to the random number value for the first initial value. At the same time, the random number update process for determining initial values P_TFINIT updates random number MR2-2, which serves as the initial value for the winning normal symbol, in steps AKS83 and AKS84 as an update to the random number value for the second initial value. The random number MR1-3, which serves as the initial value for the winning normal symbol, is the first random number value used to change the random number initial value when the random number value to be updated is the random number MR1-2 for the winning normal symbol, which is the first random number value. The random number MR2-2, which serves as the initial value for the winning normal symbol, is the second random number value used to change the random number initial value when the random number value to be updated is the random number MR2-1 for the winning normal symbol, which is the second random number value. Steps AKS81 and AKS82 of the random number update process P_TFINIT for determining initial values constitute a first initial value update process that can update the random number value for the first initial value. Steps AKS83 and AKS84 of the random number update process P_TFINIT for determining initial values constitute a second initial value update process that can update the random number value for the second initial value. By updating the random number values for the first initial value and the second initial value in this way, it becomes possible to update the random number values appropriately so as to reliably increase the uncertainty of the first random number value and the second random number value.

In addition, the initial value determination random number update process P_TFINIT updates random number MR1-3, which will be the initial value for the winning symbol, as the first initial value random number value in steps AKS81 and AKS82, and then updates random number MR2-2, which will be the initial value for the winning normal symbol, as the second initial value random number value in steps AKS83 and AKS84. Therefore, the initial value determination random number update process P_TFINIT updates random number MR1-3, which will be the initial value for the winning symbol and the first initial value random number value in steps AKS81 and AKS82, which is the first initial value update process, and then updates random number MR2-1, which will be the initial value for the winning normal symbol and the second initial value random number value in steps AKS83 and AKS84, which is the second initial value update process.

Figure 10-16 is a flowchart showing an example of the start port switch passing process P_TZU_ON. The start port switch passing process P_TZU_ON is included in the processes that can be called from the special pattern process process P_TPROC shown in Figure 6, and can be executed in step S104 if the first start winning corresponding flag is on in step S103, and can be executed in step S108 if the second start winning corresponding flag is on in step S107. When the CPU 103 executes the start port switch passing process P_TZU_ON, it sets the start port winning memory counter address using a transfer command to set a pointer (step AKS201). The start port winning memory counter address is the address of the first start port winning memory counter or the second start port winning memory counter provided in the game work area of RAM 102. In step AKS201, a different address in the game work area can be specified corresponding to the first or second starting gate winning table set by the special symbol process P_TPROC. For example, the upper address F0[H] of the game work area, which serves as the working area, is set to the upper byte of the pointer using a transfer command, and the lower address of the starting gate winning memory counter stored in the first or second starting gate winning table pointed to by the table pointer is set to the lower byte of the pointer using a transfer command. As a result, the value indicating the address of the first or second starting gate winning memory counter is stored in the internal register of CPU 103, which serves as the pointer. Next, the starting gate winning memory counter is loaded using a transfer command to read the stored data at the address pointed to by the pointer (step AKS202).

Following step AKS202, a determination is made as to whether the count value of the start port winning memory counter is equal to or greater than the counter's maximum value (step AKS203). For example, a comparison and return command can compare the value loaded in step AKS202 with a counter maximum value, such as "4." If the value is equal to or greater than the counter maximum value (step AKS203; Yes), the start port switch passing process P_TZU_ON ends and the process returns to the special symbol process process P_TPROC. On the other hand, if the value is less than the counter maximum value (step AKS203; No), the count value of the start port winning memory counter is updated by adding 1 (step AKS204). In this case, an arithmetic and logic operation command that increments the stored data at the address pointed to by the pointer can update the count value of the first start port winning memory counter or the second start port winning memory counter by adding 1.

After step AKS204, the special symbol determination buffer address is set as the transfer destination (step AKS205). The special symbol determination buffer address is the address of the first special symbol determination buffer contained in the first special symbol reserve buffer or the second special symbol determination buffer contained in the second special symbol reserve buffer provided in the game work area of RAM 102. In step AKS205, different addresses in the game work area can be specified corresponding to the first start port winning table or second start port winning table set by the special symbol process processing P_TPROC and the count value of the first start port winning counter or second start port winning counter loaded in step AKS202.

The first special symbol reserve buffer is a first reserve memory buffer comprising a first special symbol determination buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first losing effect selection buffer. It is allocated as a plurality of memory areas, for example, five memory areas corresponding to buffer numbers "0" to "4", corresponding to cases where the variable display of the first special symbol is being executed and the number of first reserve memories that have not yet been executed. The second special symbol reserve buffer is a second reserve memory buffer comprising a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second losing effect selection buffer. It is allocated as a plurality of memory areas, for example, five memory areas corresponding to buffer numbers "0" to "4", corresponding to cases where the variable display of the second special symbol is being executed and the number of second reserve memories that have not yet been executed.

In step AKS205, the value corresponding to the buffer size of the first reserved memory buffer or the second reserved memory buffer is multiplied by the count value of the start port winning counter, and the multiplied value is added to the lower address of the first reserved memory buffer or the second reserved memory buffer with buffer number "1". By setting this added value as the transfer destination pointer, the special pattern determination buffer address can be set as the transfer destination.

Following step AKS205, the RL0 hard latch random number register address is set (step AKS206). The RL0 hard latch random number register address is the address of the RL0 hard latch random number register located in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer using a transfer command, and the lower address of the RL0 hard latch random number register stored in the first start port winning table or second start port winning table pointed to by the table pointer is set to the lower byte of the pointer using a transfer command. The first start port winning table stores the lower address of the RL0 hard latch random number register, which has buffer number "0." The second start port winning table stores the lower address of the RL0 hard latch random number register, which has buffer number "1." As a result, different addresses are stored in the internal register of CPU 103, which serves as the pointer, as the address of the RL0 hard latch random number register for the first start port winning event and the second start port winning event.

After step AKS206, the RL0 hard latch random number register is loaded with a transfer command to read the stored data at the address pointed to by the pointer (step AK207). The value thus obtained from the RL0 hard latch random number register is stored in the special symbol determination random number buffer with a transfer command to write it to a memory area at a specified address in the gaming work area of RAM 102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random number register in the special symbol determination random number buffer, numerical data indicating the value of the special symbol determination random number MR1-1 is extracted, and the value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

After step AKS208, the RL2 soft latch random number register is loaded by a transfer command to read stored data from a memory area at a specified address in the function control register area (step AKS209). The value stored in the RL2 soft latch random number register obtained at this time is stored in the random number buffer for selecting a losing effect by a transfer command to write it to a memory area at a specified address in the game work area of RAM 102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random number register in the random number buffer for selecting a losing effect, numerical data indicating the value of random number MR3-2 for selecting a losing effect is extracted, and the value of random number MR3-2 can be stored in the random number buffer for selecting a losing effect.

After step AKS210, the RS1 soft latch random number register is loaded by a transfer command to read stored data from a memory area at a specified address in the function control register area (step AKS211). The value stored in the RS1 soft latch random number register obtained at this time is stored in the random number buffer for selecting a variation pattern type by a transfer command to write it to a memory area at a specified address in the game work area of RAM 102 (step AKS212). In this way, by storing the numerical data obtained from the RS1 soft latch random number register in the random number buffer for selecting a variation pattern type, numerical data indicating the value of the random number MR3-3 for selecting a variation pattern type is extracted, and the value of the random number MR3-3 can be stored in the random number buffer for selecting a variation pattern type.

After step AKS212, the RS2 soft latch random number register is loaded by a transfer command to read stored data from a memory area at a specified address in the function control register area (step AKS213). The value stored in the RS2 soft latch random number register obtained at this time is stored in the random number buffer for variation patterns by a transfer command to write it to a memory area at a specified address in the game work area of RAM 102 (step AKS214). In this way, by storing the numerical data obtained from the RS2 soft latch random number register in the random number buffer for variation patterns, numerical data indicating the value of random numbers MR3-4 for variation patterns is extracted, and the values of random numbers MR3-4 can be stored in the random number buffer for variation patterns.

Following step AKS214, a block transfer is performed from the random number buffer to the special symbol determination buffer (step AKS215). The random number buffer includes a special symbol determination random number buffer in which the value of random number MR1-1 is stored in step AKS208, a loss effect selection random number buffer in which the value of random number MR3-2 is stored in step AKS210, a variation pattern type selection random number buffer in which the value of random number MR3-3 is stored in step AKS212, and a variation pattern random number buffer in which the value of random number MR3-4 is stored in step AKS214. In step AKS215, the address of the special symbol determination random number buffer is set as the transfer source, and a value corresponding to the buffer size of the random number buffer is set as the number of transfers. The special symbol determination buffer address, which is the transfer destination, was set in step AKS205. Based on these settings, by executing a block transfer command, the values of each random number temporarily stored in the random number buffer can be stored as new reserved information in the first reserved storage buffer or the second reserved storage buffer.

Once the new memory information is stored in step AKS215, it is determined whether the winning effect conditions are met (step AKS216). The winning effect conditions may be preset as conditions that enable the pre-reading effect. For example, if the starting gate winning designation value is "2," it is determined that the winning effect conditions are met. Furthermore, if the starting gate winning designation value is "1," it is determined that the winning effect conditions are met if the time-saving function flag is "0" corresponding to the non-time-saving state, and the special pattern process code is less than 03 [H] corresponding to the non-small win or big win game state. If it is determined that the winning effect conditions are met (step AKS216; Yes), the winning effect process P_GAME_CHK is executed (step AKS217). The winning effect processing P_GAME_CHK includes determining whether a special symbol has been hit, selecting effect specification values corresponding to the result of the determination, and enabling the sending of a winning effect command.

If it is determined in step AKS216 that the winning effect conditions are not met (step AKS216; No), or after executing the winning effect processing in step AKS217, a transfer command for setting a pointer is issued to set the effect memory information designation command transmission table address (step AKS218). The effect memory information designation command transmission table address is the address of the effect memory information designation command transmission table stored in the game data area of ROM 101. Then, by executing the command set processing P_COM_SET (step AKS219), the first effect memory information designation command or the second effect memory information designation command can be transmitted as the start winning command. The first effect memory information designation command is a presentation control command that designates the first reserved memory number indicated by the count value of the first starting gate winning memory counter. The second effect memory information designation command is a presentation control command that designates the second reserved memory number indicated by the count value of the second starting gate winning memory counter. In this way, the command set process P_COM_SET in step AKS219 allows the performance control command, which becomes the command at the time of the initial winning, to be sent from the main board 11 to the performance control board 12.

After step AKS219, a transfer command for setting a pointer is used to set the start port winning buffer memory counter address (step AKS220). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter located in the game work area of RAM 102. In this way, the count value of the start port winning buffer memory counter whose address has been set is updated by incrementing it by one (step AKS221). Furthermore, a composite transfer command for setting a register or pointer is used to update the pointer corresponding to the start port winning buffer memory counter (step AKS222). For example, the count value of the start port winning buffer memory counter after update in step AKS221 is loaded into an internal register of CPU 103, and the stored value of the pointer is updated by incrementing it by one, thereby storing a value indicating the starting address of the start port winning buffer in the pointer. Furthermore, the count value of the loaded start port winning buffer memory counter is added to the stored value of the pointer, thereby making it possible to identify the storage area of the buffer number to be updated in the start port winning buffer.

After updating the pointer in step AKS222, the start port winning designation value is loaded (step AKS223). The start port winning designation value can be set to "1" indicating a first start port winning or "2" indicating a second start port winning, corresponding to the first start port winning table or second start port winning table set by the special symbol process processing P_TPROC. In step AKS223, a transfer command is issued to read table data from the first start port winning table or second start port winning table, making it possible to obtain the start port winning designation value. The start port winning designation value thus obtained is stored in the start port winning buffer by a transfer command to write it to the memory area indicated by the pointer (step AKS224), and the start port switch passing processing P_TZU_ON ends.

Figure 10-17 is a diagram illustrating an example of the use of data configuration related to the start port switch passing process P_TZU_ON. In the start port switch passing process P_TZU_ON, various settings and controls are performed using the first start port winning table set in step S102 or the second start port winning table set in step S106 of the special pattern process process P_TPROC shown in Figure 6. For example, the first start port winning memory counter and the second start port winning memory counter, whose count values can be updated in step AKS204, are provided in the special pattern control data area and can store data corresponding to the first and second reserved memory numbers. The start port winning buffer memory counter, whose count values can be updated by AKS221, and the start port winning buffer, in which the start port winning designation value is stored by AKS224, are provided in the start port winning buffer area and can store the total number of first and second start port winnings and the order in which they occur. Additionally, the command set process P_COM_SET in step AKS219 uses the first effect memory information designation command transmission table or the second effect memory information designation command transmission table whose address was set in step AKS218.

In this way, the start port switch passing process P_TZU_ON enables control of the special symbol game, which is a variable display of special symbols, using the first start port winning table or the second start port winning table, the first start port winning memory counter or the second start port winning memory counter provided in the special symbol control data area, the start port winning buffer memory counter or the start port winning buffer provided in the start port winning buffer area, and the first effect memory information designation command transmission table or the second effect memory information designation command transmission table.

Figure 10-17 (A1) shows an example configuration AKT21 of the first start port winning table. The first start port winning table of configuration example AKT21 is configured to include table data indicating the lower address of the first start port winning memory counter, the lower address of the RL0 hard latch random number register number "0", the lower address of the first special symbol determination buffer number "1", the address of the first effect memory information designation command transmission table, and the start port winning designation value "1".

The first start gate winning memory counter is located in the game work area of RAM 102 and is capable of storing data corresponding to the first reserved memory number. RL0 hard latch random number register number "0" is an RL0 hard latch random number register with register number "0" located in the function control register area. It is capable of acquiring and storing numerical data indicating the value of the special symbol determination random number MR1-1, which can be generated by channel RL0 located in the 16-bit random number circuit 104A, via hard latch. First special symbol determination buffer number "1" is a first special symbol determination buffer included in the first reserved memory buffer with buffer number "1" in the first special symbol reserved buffer. The first effect memory information designation command transmission table is stored in the game data area of ROM 101 and is used when transmitting a first effect memory information designation command that specifies the first reserved memory number. Start gate winning designation value "1" is a designated value that identifiably indicates that a first start win has occurred.

Figure 10-17 (A2) shows an example configuration AKT22 of the second start port winning table. The second start port winning table of configuration example AKT22 is configured to include table data indicating the lower address of the second start port winning memory counter, the lower address of the RL0 hard latch random number register number "1", the lower address of the second special symbol determination buffer number "1", the address of the second effect memory information designation command transmission table, and the start port winning designation value "2".

The second start gate winning memory counter is located in the game work area of RAM 102 and is capable of storing data corresponding to the second reserved memory number. RL0 hard latch random number register number "1" is an RL0 hard latch random number register with register number "1" located in the function control register area. It is capable of acquiring and storing numerical data indicating the value of the special symbol determination random number MR1-1, which can be generated by channel RL0 located in the 16-bit random number circuit 104A, via hard latch. Second special symbol determination buffer number "1" is a second special symbol determination buffer included in the second reserved memory buffer with buffer number "1" in the second special symbol reserved buffer. The second effect memory information designation command transmission table is stored in the game data area of ROM 101 and is used when transmitting a second effect memory information designation command that specifies the second reserved memory number. Start gate winning designation value "2" is a designated value that specifically indicates that a second start gate winning has occurred.

Figure 10-17 (B1) shows a configuration example AKB21 of the special symbol control data area. The special symbol control data area of configuration example AKB21 can store various data related to control by the special symbol process processing P_TPROC, such as the special symbol game, which is a variable display of special symbols, and the small hit game state and big hit game state that can be controlled based on the display results. This special symbol control data area includes a special symbol process timer at address F030[H], a win flag at address F032[H], a special symbol process code at address F033[H], a first start port winning memory counter at address F034[H], a big win symbol determination buffer at address F035[H], a small win symbol determination buffer at address F036[H], a large prize port winning number counter at address F037[H], a large prize port opening count counter at address F038[H], a large prize port opening pattern timer at address F039[H], a large prize port opening pattern table pointer at address F03B[H], a demo display flag at address F03D[H], and a second start port winning memory counter at address F099[H].

The special pattern process timer can store a timing value corresponding to the control time by the special pattern process processing P_TPROC. The special pattern process code can specify the processing selected in the special pattern process processing P_TPROC. The first start port winning memory counter can store a count value corresponding to the first reserved memory number. The jackpot pattern determination buffer can store data corresponding to the jackpot pattern specified value. The jackpot pattern specified value is a specified value corresponding to the confirmed special pattern displayed when the display result in the variable display of the special pattern is "jackpot", and makes it possible to set the type of jackpot game state. The small jackpot pattern determination buffer can store data corresponding to the small jackpot pattern specified value. The small jackpot pattern specified value is a specified value corresponding to the confirmed special pattern displayed when the display result in the variable display of the special pattern is "small jackpot", and makes it possible to set the type of alcohol in the small jackpot game state. The large prize opening number counter can store a count value corresponding to the number of game balls that have passed through the large prize opening formed by the special variable prize ball device 50. The large prize opening number counter can store a count value corresponding to the number of times the large prize opening has been opened in a small prize game state or a big prize game state. The large prize opening pattern timer can store a time value corresponding to the remaining time for controlling the large prize opening to an open state in a small prize game state or a big prize game state. The large prize opening pattern table pointer can specify a storage address in the large prize opening pattern table in which the opening time of the large prize opening is set. The demo display flag can store a flag value corresponding to an on or off state depending on whether a demonstration display is being executed. The second start opening memory counter can store a count value corresponding to the second reserved memory number.

Figure 10-17 (B2) shows a configuration example AKB22 of the start port winning buffer area. The start port winning buffer area of configuration example AKB22 can store various data related to the first start winning and second start winning that occur when the gaming ball enters the first start winning port or second start winning port. This start port winning buffer area includes a start port winning buffer storage counter at address F0BA[H] and start port winning buffer numbers "0" to "8" at addresses F0BB[H] to F0C3[H].

The start port winning buffer storage counter can store a count value corresponding to the number of valid start port winning designation values stored in the start port winning buffer area. Therefore, the count value of the start port winning buffer storage counter indicates the total number of first start winnings and second start winnings. Start port winning buffer numbers "0" to "8" are start port winning buffers assigned buffer numbers "0" to "8", and can store start port winning designation values in the order in which the first start winnings and second start winnings occurred. As a result, the information stored in the start port winning buffer indicates the order in which the first start winnings and second start winnings occurred.

Figure 10-17 (C1) shows an example configuration AKT23 of the first effect memory information designation command transmission table. The first effect memory information designation command transmission table of configuration example AKT23 is configured to include table data indicating the upper byte of the first effect memory information designation command and the first start port winning memory counter reference designation value. The command set process P_COM_SET in step AKS219 enables the first effect memory information designation command to be transmitted when the first effect memory information designation command transmission table is used. The first effect memory information designation command can set the lower byte corresponding to the count value of the first start port winning memory counter. By transmitting such a first effect memory information designation command, the first pending memory number can be notified to the effect control board 12.

Figure 10-17 (C2) shows an example configuration AKT24 of the second effect memory information designation command transmission table. The second effect memory information designation command transmission table of configuration example AKT24 is configured to include table data indicating the upper bytes of the second effect memory information designation command and the second start port winning memory counter reference designation value. The command set process P_COM_SET in step AKS219 enables the second effect memory information designation command to be transmitted when the second effect memory information designation command transmission table is used. The second effect memory information designation command can set the lower bytes corresponding to the count value of the second start port winning memory counter. By transmitting such a second effect memory information designation command, the second pending memory number can be notified to the effect control board 12.

The start port switch passing process P_TZU_ON shown in Figure 10-16 stores the value stored in the RL2 soft latch random number register loaded in step AKS209 in the random number buffer for selecting a losing effect in step AKS210, thereby enabling the extraction of numerical data indicating the value of the random number MR3-2 for selecting a losing effect. Furthermore, the start port switch passing process P_TZU_ON stores the value stored in the RS1 soft latch random number register loaded in step AKS211 in the random number buffer for selecting a variation pattern type in step AKS212, thereby enabling the extraction of numerical data indicating the value of the random number MR3-3 for selecting a variation pattern type. Furthermore, the start port switch passing process P_TZU_ON stores the value stored in the RS2 soft latch random number register loaded in step AKS213 in the random number buffer for variation patterns in step AKS214, thereby enabling the extraction of numerical data indicating the value of the random number MR3-4 for the variation pattern. Here, if the random number MR3-2 for selecting a losing effect is the first random number value, the random number MR3-3 for selecting a variation pattern type is the second random number, and the random number MR3-4 for the variation pattern is the third random number value, the start port switch passing process P_TZU_ON is executed in response to the occurrence of a starting winning, so the first random number value, the second random number value, and the third random number value can be extracted when the common extraction condition of the occurrence of a starting winning is met. The random number MR3-2 for selecting a losing effect is included in the gaming random numbers that can be updated by the 16-bit random number circuit 104A, and the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for the variation pattern are included in the gaming random numbers that can be updated by the 8-bit random number circuit 104B, and the total number of random numbers included in the update range for each is a prime number. The update rate of random number MR3-2 is 469 times/ms, while the update rates of random numbers MR3-3 and MR3-4 are 938 times/ms. In other words, the update rates of random numbers MR3-3 and MR3-4 are twice the update rate of random number MR3-2, which is an integer multiple of that rate. The update range of random number MR3-2 is "0" to "65518," the update range of random number MR3-3 is "0" to "240," and the update range of random number MR3-4 is "0" to "250." Therefore, the total number of random numbers included in each update range is different, and the total number of random numbers included in each update range is a prime number. In this way, when the update rates of the second random number value and the third random number value are an integer multiple of the update rate of the first random number value, the total number of random numbers included in each update range is different, and the total number of random numbers included in each update range is a prime number. This prevents synchronization between the first, second, and third random number values, enabling appropriate random number updates.

Figure 10-18 is a flowchart showing an example of the special symbol normal processing P_TNORMAL. The special symbol normal processing P_TNORMAL is included in the processing that can be called from the special symbol process processing P_TPROC shown in Figure 6, and can be executed in step S112 if the special symbol process code loaded in step S110 is 00 [H]. When the special symbol normal processing P_TNORMAL is executed, the CPU 103 sets the start port winning buffer memory counter address using a transfer command to set a pointer (step AKS241). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of RAM 102. In this way, it is determined whether the count value of the start port winning buffer memory counter whose address has been set is "0" (step AKS242). For example, an arithmetic jump instruction branches processing depending on whether the stored data at the address pointed to by the pointer is 00 [H], which corresponds to "0," making it possible to execute different processing content when the count value of the start port winning buffer storage counter is "0" and when it is other than "0."

If the count value of the start port winning buffer storage counter is not "0" in response to step AKS242 (step AKS242; No), the count value of the start port winning buffer storage counter is updated to subtract 1 (step AKS243). A block transfer for shifting the start port winning buffer is also performed (step AKS244). In step AKS244, the destination address is set to the lower address BB[H] of start port winning buffer number "0," the source address is set to the lower address BC[H] of start port winning buffer number "1," and the number of transfers is set to "8," which is the buffer size of the start port winning buffer. Then, by executing a block transfer command, the contents of the start port winning buffer are shifted by transferring them one unit at a time to the previous buffer. Then, the memory area of start port winning buffer number "8" is initialized by clearing it.

After step AKS244, a transfer command for setting the table pointer is issued to set the second special symbol determination control table address (step AKS245). The second special symbol determination control table address is the address of the second special symbol determination control table stored in the game data area of ROM 101. At this time, a start port winning check process is executed to determine whether the start port winning designation value is "1" (step AKS246). For example, in the start port winning check process, if the start port winning designation value is "1," the zero flag is turned on, and if the start port winning designation value is "2," the zero flag is turned off. After this start port winning check process is executed, a jump command is issued to branch the process depending on whether the zero flag is off, allowing different processing to be executed depending on whether the start port winning designation value is "1" or "2."

If the start gate winning designation value is "1" in response to step AKS246 (step AKS246; Yes), a transfer command for setting the table pointer is issued to set the first special symbol determination control table address (step AKS247). The first special symbol determination control table address is the address of the first special symbol determination control table stored in the game data area of ROM 101. In step AKS247, a transfer command for setting the table pointer is issued to overwrite the value of the table pointer. Thus, in the normal special symbol processing P_TNORMAL, after the second special symbol determination control table address is set in step AKS245, the start gate winning designation value corresponds to "1" in step AKS246, and the first special symbol determination control table address is re-set by overwriting in step AKS247. As a result, when the second special symbol determination control table is used more frequently than the first special symbol determination control table, the program capacity required for table setting can be reduced, improving the marketability of the pachinko gaming machine 1. Furthermore, when the second special symbol determination control table is used more frequently than the first special symbol determination control table, processing using jump commands as branch commands can be simplified, making it easier to check at the design stage and improving the marketability of the pachinko gaming machine 1.

If the starting gate winning designation value is "2" and not "1" in response to step AKS246 (step AKS246; No), after step AKS247, the special symbol determination process P_TDECISION is executed (step AKS248), and the variable pattern setting process P_TPATSET is executed (step AKS249), after which the normal special symbol processing ends.

If the count value of the start slot winning buffer memory counter is "0" in response to step AKS242 (step AKS242; Yes), it is determined whether the demo display flag is on (step AKS250). The demo display flag is a flag indicating that a demonstration display is being executed. If the demo display flag is on (step AKS250; Yes), the normal special pattern processing ends. In contrast, if the demo display flag is off (step AKS250; No), a transfer command to set the demo display flag is issued to store the demo display designated value 01 [H] in the demo display flag (step AKS251). This sets the demo display flag to the on state. In addition, a transfer command to set the pointer is issued to set the standby command transmission table address (step AKS252). The standby command transmission table address is the address of the standby command transmission table stored in the game data area of ROM 101. Then, the command set process P_COM_SET is executed (step AKS253), and the normal special symbol processing ends.

Figure 10-19 is a diagram illustrating an example of the use of data configuration related to the normal special symbol processing P_TNORMAL. In the normal special symbol processing P_TNORMAL, the special symbol determination processing in step AKS248 is executed using the second special symbol determination control table whose address was set in step AKS245 or the first special symbol determination control table whose address was set in step AKS247. Furthermore, the command set processing P_COM_SET in step AKS253 uses the standby command transmission table whose address was set in step AKS252. In this way, the normal special symbol processing P_TNORMAL enables control of the special symbol game, which is the variable display of special symbols, using the first special symbol determination control table, second special symbol determination control table, or standby command transmission table.

Figure 10-19 (A1) shows an example configuration AKT31 of the first special symbol determination control table. The first special symbol determination control table of the example configuration AKT31 is configured to include table data indicating the address of the first special symbol buffer shift control table, the lower address of the first special symbol determination buffer number "0", the lower address of the first winning symbol buffer number "0", the lower address of the first special symbol buffer, and the address of the work setting table after the first special symbol win determination. The first special symbol buffer shift control table is stored in the game data area of ROM 101 and is used when shifting the memory contents of the first special symbol reserve buffer. The first special symbol determination buffer number "0" is the first special symbol determination buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserve buffer. The first winning symbol buffer number "0" is the first winning symbol buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer. The first special symbol buffer is provided in the game work area of RAM 102 and is capable of storing special symbol pattern designation values corresponding to the confirmed special symbols stopped and displayed in the first special symbol game by the first special symbol display device 4A. The first special symbol post-winning symbol determination work setting table is stored in the game data area of ROM 101 and is used when initializing data in response to the end of the special symbol determination process P_TDECISION.

Figure 10-19 (A2) shows an example configuration AKT32 of the second special symbol determination control table. The second special symbol determination control table of the example configuration AKT32 is configured to include table data indicating the address of the second special symbol buffer shift control table, the lower address of the second special symbol determination buffer number "0", the lower address of the second winning symbol buffer number "0", the lower address of the second special symbol buffer, and the address of the work setting table after the second special symbol win determination. The second special symbol buffer shift control table is stored in the game data area of ROM 101 and is used when shifting the memory contents of the second special symbol reserve buffer. The second special symbol determination buffer number "0" is the second special symbol determination buffer included in the second reserved memory buffer with buffer number "0" in the second special symbol reserve buffer. The second winning symbol buffer number "0" is a buffer for the second winning symbol included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. The second special symbol buffer is provided in the game work area of RAM 102, and is capable of storing special symbol pattern designation values corresponding to the confirmed special symbols stopped and displayed in the second special symbol game by the second special symbol display device 4B. The second special symbol post-winning symbol determination work setting table is stored in the game data area of ROM 101, and is used when initializing data in response to the end of the special symbol determination process P_TDECISION.

Figure 10-19 (B) shows an example configuration AKT33 of the standby command transmission table AKT33. The standby command transmission table of configuration example AKT33 is configured to include table data indicating the number of processes, the upper byte of the second specific count specification command, the specific count command buffer reference value, the upper byte of the background color specification command, the special symbol state specification code reference value, the upper byte of the customer waiting demo command, and the lower byte of the customer waiting demo command. The command set process P_COM_SET in step AKS253 uses the standby command transmission table of configuration example AKT33 to enable the transmission of the second specific count specification command, the background color specification command, and the customer waiting demo command. The second specific count specification command can have its lower byte set to correspond to the value stored in the specific count command buffer. The background color specification command can have its lower byte set to correspond to the special symbol state specification code. The customer waiting demo command can have its lower byte set to use the fixed value 03 [H].

Figure 10-20 is a flowchart showing an example of the special symbol determination process P_TDECISION. The special symbol determination process P_TDECISION is included in the processes that can be called from the normal special symbol process P_TNORMAL shown in Figure 10-18, and can be executed in step AKS248 when variable display of special symbols is started. When the CPU 103 executes the special symbol determination process P_TDECISION, it sets the special symbol buffer shift control table address using a transfer command to set a pointer (step AKS301). The special symbol buffer shift control table address is the address of the first special symbol buffer shift control table or the second special symbol buffer shift control table stored in the game data area of ROM 101. In step AKS301, a different address in the game data area can be specified corresponding to the first special symbol determination control table or the second special symbol determination control table set by the normal special symbol process P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the address 13C2[H] of the first special symbol buffer shift control table is set in the pointer. Also, when the second special symbol determination control table is set, a value indicating the address 13C8[H] of the second special symbol buffer shift control table is set in the pointer.

Following step AKS301, special symbol buffer shift processing P_TBUFSHIFT is executed (step AKS302). The special symbol buffer shift processing P_TBUFSHIFT in step AKS302 can shift the contents of the first special symbol reserve buffer or the second special symbol reserve buffer using the first special symbol buffer shift control table or the second special symbol buffer shift control table whose address was set in step AKS301. For example, by setting the destination address, source address, and number of transfers, and then executing a block transfer command, the contents of the first reserve memory buffer of the first special symbol buffer or the second reserve memory buffer of the second special symbol buffer can be shifted by transferring them one unit at a time to the previous buffer.

Following step AKS302, the special symbol determination buffer with buffer number "0" is loaded (step AKS303). The special symbol determination buffer with buffer number "0" is the first special symbol determination buffer or the second special symbol determination buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserve buffer. In step AKS303, the stored values of the special symbol determination buffer can be read from the first special symbol reserve buffer or the second special symbol reserve buffer in accordance with the first special symbol determination control table or the second special symbol determination control table set by the special symbol normal processing P_TNORMAL. For example, the upper address F0 [H] of the game work area, which serves as the work area, can be set to the upper byte of the pointer using a transfer command, and the lower address of the first special pattern determination buffer number "0" or the second special pattern determination buffer number "0" stored in the first special pattern determination control table or the second special pattern determination control table pointed to by the table pointer can be set to the lower byte of the pointer using a transfer command. Then, by reading the stored data at the address in the game work area pointed to by the pointer, it is possible to read the random number MR1-1 for special pattern determination stored in the special pattern determination buffer with buffer number "0".

After step AKS303, the special symbol jackpot determination process P_TFVR_CHK is executed (step AKS304). The special symbol jackpot determination process P_TFVR_CHK in step AKS304 can determine whether the special symbol display result is a "jackpot" by comparing the value of the special symbol determination random number MR1-1 read in step AKS303 with the jackpot determination value. The determination of whether the special symbol display result is a "jackpot" is also referred to as the special symbol jackpot determination, and is a determination of whether to control the game to a favorable jackpot gaming state. If the special symbol jackpot determination determines the special symbol display result to be a "jackpot," the jackpot designated value 01 [H] is stored in the hit flag. The hit flag is located in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1) and is assigned address F032 [H]. The special symbol jackpot determination process of step AKS304 simply stores the specified jackpot value in the hit flag using a transfer command to write to a memory area at a specified address in the game work area of RAM 102. Note that the hit flag only needs to be able to be set to its initial value of 00 [H] using a clear command executed in response to the start of the special symbol jackpot determination process P_TFVR_CHK in step AKS304.

The special symbol small win determination process P_TLITTLE_CHK is executed in conjunction with the special symbol big win determination process P_TFVR_CHK in step AKS304 (step AKS305). The special symbol small win determination process P_TLITTLE_CHK in step AKS305 can determine whether the special symbol display result is a "small win" by comparing the value of the special symbol determination random number MR1-1, read by loading the special symbol determination buffer in step AKS303, with the small win determination value. The determination of whether the special symbol display result is a "small win" is also referred to as the special symbol small win determination, and is a determination of whether to control the game to a predetermined small win gaming state. Then, if the special symbol small win determination determines that the special symbol display result is a "small win," the small win designated value 02 [H] is stored in the win flag. The special symbol small win determination process P_TLITTLE_CHK in step AKS305 simply stores the small win designated value in the win flag using a transfer command to write it to a memory area at a designated address in the game work area of RAM 102.

In the special symbol small hit determination process P_TLITTLE_CHK in step AKS305, the small hit determination value is included in a range different from the big hit determination value. Therefore, after the special symbol big hit determination determines the special symbol display result as a "big hit," the special symbol small hit determination will not determine the special symbol display result as a "small hit." However, if, for example, an error occurs, after the special symbol big hit determination determines the special symbol display result as a "big hit," the special symbol small hit determination determines the special symbol display result as a "small hit," the small hit specified value will be stored in the hit flag. Therefore, in the event of a conflict between the special symbol big hit determination determining the special symbol display result as a "big hit" and the special symbol small hit determination determining the special symbol display result as a "small hit," fraudulent behavior due to a malfunction in the determination process is prevented, enabling appropriate game control so that the game is not controlled to a big hit game state, which is more advantageous than a small hit game state.

When the special symbol small win determination process P_TLITTLE_CHK in step S305 is executed, the winning symbol buffer with buffer number "0" is loaded (step AKS306). The winning symbol buffer with buffer number "0" is the first winning symbol buffer contained in the first reserved memory buffer with buffer number "0" in the first special symbol buffer, or the second winning symbol buffer contained in the second reserved memory buffer with buffer number "0" in the second special symbol buffer. In step AKS306, the stored value of the winning symbol buffer can be read from the first special symbol buffer or the second special symbol buffer corresponding to the first special symbol determination control table or the second special symbol determination control table whose address was set by the special symbol normal process P_TNORMAL. For example, the upper address F0 [H] of the game work area, which serves as the working area, is set to the upper byte of the buffer pointer using a transfer command, and the lower address of the special symbol determination buffer stored in the first special symbol determination control table or second special symbol determination control table pointed to by the table pointer is set to the lower byte of the buffer pointer using a transfer command. Then, by reading the stored data at the address in the game work area pointed to by the buffer pointer, it is possible to read the random number MR1-2 for the winning symbol stored in the winning symbol buffer with buffer number "0".

After step AKS306, the special symbol buffer lower address is loaded (step AKS307). The special symbol buffer lower address is the address of the first or second special symbol buffer provided in the game work area of RAM 102. In step AKS307, a different lower address can be specified corresponding to the first or second special symbol determination control table whose address was set by the normal special symbol processing P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating the lower address B8 [H] of the first special symbol buffer is set in the lower byte of the buffer pointer. Also, when the second special symbol determination control table is set, a value indicating the lower address B9 [H] of the second special symbol buffer is set in the lower byte of the buffer pointer. The upper address F0 [H] of the game work area has already been stored in the upper byte of the buffer pointer by step AKS306.

Following step AKS307, the special symbol information setting process P_TZU_SET is executed (step AKS308). The special symbol information setting process P_TZU_SET makes it possible to determine the confirmed special symbol to be displayed in the special symbol game and to store the special symbol pattern designation value corresponding to the determined result in the special symbol buffer. Following the special symbol information setting process P_TZU_SET, the post-special symbol hit determination work setting table address is set (step AKS309). The post-special symbol hit determination work setting table address is the address of the first special symbol hit determination work setting table or the second special symbol hit determination work setting table stored in the game data area of ROM 101. In step AKS309, a different address in the game data area can be specified corresponding to the first special symbol hit determination control table or the second special symbol hit determination control table whose address was set by the special symbol normal process P_TNORMAL. For example, when the first special symbol determination control table is set, a value indicating address 12BB [H] of the work setting table after the first special symbol win determination is set in the pointer. Also, when the second special symbol determination control table is set, a value indicating address 12C0 [H] of the work setting table after the second special symbol win determination is set in the pointer.

Following step AKS309, data set processing P_DATASET is executed (step AKS310), and the special symbol determination processing P_TDECISION is completed. Data set processing P_DATASET in step AKS310 uses the special symbol post-win determination work setting table whose address was set in step AKS309 to clear the special symbol determination buffer and the winning symbol buffer in the first reserved memory buffer or second reserved memory buffer with buffer number "0," thereby enabling initialization. For example, when the first special symbol post-win determination work setting table is set, the first special symbol determination buffer and the first winning symbol buffer are initialized in the first reserved memory buffer with buffer number "0," which is included in the first special symbol reserve buffer. Additionally, when the work setting table is set after determining that the second special symbol has been won, the second special symbol determination buffer and the second winning symbol buffer are initialized in the second reserved memory buffer with buffer number "0" included in the second special symbol reserved buffer.

Figure 10-21 is a diagram illustrating an example of the use of data configuration related to the special symbol determination process P_TDECISION. In the special symbol determination process P_TDECISION, the special symbol big hit determination process P_TFVR_CHK in step AKS304 and the special symbol small hit determination process P_TLITTLE_CHK in step AKS305 use the special symbol determination random number MR1-1 to determine whether the display result in the variable display of the special symbol is a "big hit" or a "small hit" in response to the start of the variable display. Furthermore, the special symbol information setting process P_TZU_SET in step AKS308 uses the special symbol buffer whose lower address was loaded in step AKS307. In this way, the special symbol determination process P_TDECISION uses the special symbol determination random number MR1-1 and the special symbol buffer to enable control of the special symbol game, which is the variable display of special symbols.

Figure 10-21 (A) shows a special symbol determination example AKC01 by the special symbol jackpot determination process P_TFVR_CHK in step AKS304 and the special symbol minor jackpot determination process P_TLITTLE_CHK in step AKS305. The special symbol jackpot determination process P_TFVR_CHK in step AKS304 enables a comparison operation to be performed with the jackpot determination value for the special symbol determination random number MR1-1 to determine whether its value is within the jackpot determination range. The jackpot determination value includes a jackpot lower limit determination value and an jackpot upper limit determination value. When the value of random number MR1-1 is subtracted from the jackpot lower limit determination value, if the carry flag is off, the value of random number MR1-1 is a value below the jackpot lower limit determination value, and if the carry flag is on, the value of random number MR1-1 is a value above the jackpot lower limit determination value. If the value of random number MR1-1 is equal to or less than the lower limit of the jackpot determination value, it is not within the jackpot determination range, and the special symbol jackpot determination process P_TFVR_CHK is terminated, returning to the special symbol determination process P_TDECISION. On the other hand, if the value of random number MR1-1 exceeds the lower limit of the jackpot determination value, the value of random number MR1-1 is subtracted from the upper limit of the jackpot determination value. At this time, if the carry flag is off, the value of random number MR1-1 is equal to or less than the upper limit of the jackpot determination value, and if the carry flag is on, the value of random number MR1-1 exceeds the upper limit of the jackpot determination value. Therefore, if the value of random number MR1-1 is equal to or less than the upper limit of the jackpot determination value, it is within the jackpot determination range, and the value 01 [H], which is the designated jackpot value, is stored in the hit flag. If the value of random number MR1-1 exceeds the upper jackpot judgment value, it is not within the jackpot judgment range, and the special symbol jackpot judgment process P_TFVR_CHK is terminated, returning to the special symbol judgment process P_TDECISION.

As an example, the lower limit jackpot judgment value may be preset to "60000" and the upper limit jackpot judgment value to "60285." As a result, as in special symbol judgment example AKC01, when the starting slot winning designation value corresponds to "1" and "2" and the value of random number MR1-1 is within the jackpot judgment range of "60001" to "60285," the judgment result for the special symbol display result will be "jackpot."

The special symbol small win determination process P_TLITTLE_CHK in step AKS305 enables a comparison operation to be performed with the small win determination value for the random number MR1-1 used for determining the special symbol to determine whether its value is within the small win determination range. The small win determination value includes a small win lower limit determination value and a small win upper limit determination value. When the value of the random number MR1-1 is subtracted from the small win lower limit determination value, if the carry flag is off, the value of the random number MR1-1 is a value below the small win lower limit determination value; if the carry flag is on, the value of the random number MR1-1 is a value above the small win lower limit determination value. If the value of the random number MR1-1 is below the small win lower limit determination value, it is not within the small win determination range, and the process terminates the special symbol small win determination process P_TLITTLE_CHK and returns to the special symbol determination process P_TDECISION. In contrast, if the value of random number MR1-1 exceeds the small win lower limit judgment value, the value of random number MR1-1 is subtracted from the small win upper limit judgment value. At this time, if the carry flag is off, the value of random number MR1-1 is a value equal to or less than the small win upper limit judgment value, and if the carry flag is on, the value of random number MR1-1 is a value equal to or less than the small win upper limit judgment value. Therefore, if the value of random number MR1-1 is a value equal to or less than the small win upper limit judgment value, it is within the small win judgment range, and 02 [H], which is the small win designation value, is stored in the win flag. If the value of random number MR1-1 exceeds the small win upper limit judgment value, it is not within the small win judgment range, and the process returns to the special pattern small win determination process P_TDECISION by terminating the special pattern small win determination process P_TLITTLE_CHK. The small win upper limit judgment value may be set to a different value depending on whether the start gate winning designation value is "1" or "2."

As an example, the small win lower limit judgment value may be preset to "21000," which is the same whether the starting port winning designation value is "1" or "2." The small win upper limit judgment value may be preset to "21285" when the starting port winning designation value is "1," and "29282" when the starting port winning designation value is "2." As a result, as in special symbol judgment example AKC01, when the starting port winning designation value corresponds to "1" and the value of random number MR1-1 is within the small win judgment range of "21001" to "21285," or when the starting port winning designation value corresponds to "2" and the value of random number MR1-1 is within the small win judgment range of "21001" to "29282," the judgment result for the special symbol display will be "small win."

Figure 10-21 (B) shows a configuration example AKB31 of the special symbol buffer area. The special symbol buffer area of configuration example AKB31 is capable of storing special symbol pattern designation values corresponding to the confirmed special symbol that is stopped and displayed as a result of the display of the special symbol. This special symbol buffer area includes a first special symbol buffer at address F0B8 [H] and a second special symbol buffer at address F0B9 [H]. The first special symbol buffer is capable of storing special symbol pattern designation values when a first special symbol game is executed by the first special symbol display device 4A. The second special symbol buffer is capable of storing special symbol pattern designation values when a second special symbol game is executed by the second special symbol display device 4B. The special symbol pattern designation value is a designation value for a display pattern corresponding to a confirmed special symbol that is the display result in the variable display of special symbols by the first special symbol display device 4A or the second special symbol display device 4B, and includes a big win special symbol pattern designation value and a small win special symbol pattern designation value. The big win special symbol pattern designation value is a designation value for a display pattern corresponding to a confirmed special symbol that is displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result in the variable display of special symbols is a "big win." The small win special symbol pattern designation value is a designation value for a display pattern corresponding to a confirmed special symbol that is displayed by the first special symbol display device 4A or the second special symbol display device 4B when the display result in the variable display of special symbols is a "small win."

Figure 10-22 is a flowchart showing an example of the special symbol information setting process P_TZU_SET. The special symbol information setting process P_TZU_SET is included in the processes that can be called from the special symbol determination process P_TDECISION shown in Figure 10-20, and can be executed in step AKS308 after the special symbol big win determination process P_TFVR_CHK in step AKS304 and the special symbol small win determination process P_LITTLE_CHK in step AKS305 are executed. When the CPU 103 executes the special symbol information setting process P_TZU_SET, it loads a win flag (step AKS321). The win flag is provided in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1), and is assigned address F032 [H]. In step AKS321, the hit flag is loaded using a transfer command to read the stored data at a specified address in the game work area of RAM 102. Then, an arithmetic jump command that can compare the hit flag with a judgment value corresponding to the designated jackpot value is used to confirm that the hit flag is not the designated jackpot value (step AKS322).

If the winning flag is set to the jackpot specified value in step AKS322 (step AKS322; No), the winning symbol buffer with buffer number "0" is set (step AKS323). The value stored in the winning symbol buffer with buffer number "0" was loaded by step AKS306 of the special symbol determination process P_TDECISION shown in Figure 10-20. This loaded content can be set as the processing target by transferring it to a processing register included in the internal registers of CPU 103. For the winning symbol buffer with buffer number "0" set in this way, the stored value is stored in the special symbol buffer (step AKS324). The special symbol buffer is the first special symbol buffer or the second special symbol buffer whose lower address was loaded by step AKS307 of the special symbol determination process P_TDECISION shown in Figure 10-20. As a result, for the random number MR1-2 for the winning symbol stored in the winning symbol buffer with buffer number "0," numerical data indicating that random number value is stored in the first special symbol buffer or the second special symbol buffer. Therefore, when the special symbol display result is "jackpot," the numerical data indicating the value of the random number MR1-2 corresponds to the special symbol whose confirmed special symbol is the jackpot symbol, and can be used as a jackpot special symbol pattern designation value.

Following step AKS324, the start port winning buffer with buffer number "0" is loaded to the start port winning designated value (step AKS325). The start port winning buffer with buffer number "0" is located in the start port winning buffer area of the configuration example AKB22 shown in Figure 10-17 (B2), and is assigned address F0BB [H]. In step AKS325, the start port winning buffer with buffer number "0" is loaded using a transfer command to read stored data from the memory area of the specified address in the game work area of RAM 102.

After step AKS325, the jackpot information data selection process P_TFVR_ZU is executed (step AKS326). The jackpot information data selection process P_TFVR_ZU determines the jackpot symbol designation value using the start-up winning designation value loaded by step AKS325 and the value stored in the winning symbol buffer loaded by step AKS306 of the special symbol determination process P_TDECISION shown in Figure 10-20, and can set the jackpot information setting data corresponding to the determined result. The jackpot information setting data is data indicating the jackpot performance designation value, the fanfare display designation value, and the jackpot end display designation value. The jackpot symbol designation value determined by this jackpot information data selection process P_TFVR_ZU is stored in the jackpot symbol determination buffer (step AKS327). The jackpot symbol determination buffer is located in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1), and is assigned address F035 [H]. In step AKS327, the jackpot symbol designation value is stored using a transfer command to write it to the memory area of the specified address in the game work area of RAM 102.

Following step AKS327, the jackpot information setting data is transferred (step AKS328). In this case, in the jackpot information setting table stored in the game data area of ROM 101, the storage address of the jackpot information setting data corresponding to the determined jackpot symbol designation value is set in a pointer specifying the transfer source. In addition, the address of the effect symbol information buffer provided in the game work area of RAM 102 is set in a buffer pointer specifying the transfer destination. Furthermore, the data size of the jackpot information setting data is set in the number of transfers. Thereafter, the block transfer command is used to transfer and store the jackpot information setting data read from the jackpot information setting table to the effect symbol information buffer, fanfare display buffer, and jackpot end display buffer. At this time, the variable command designation buffer is set (step AKS329). The variable command designation buffer is located at the next address of the jackpot end display buffer in the game work area of RAM 102, and the stored value can be set using the destination address updated by the block transfer command of step AKS327. For example, the variable command designation value 01 [H], which corresponds to the special symbol display result being determined to be a "jackpot," can be set as the stored value of the variable command designation buffer. Note that the stored value may be initialized to 00 [H] by clearing the variable command designation buffer in accordance with the presentation state after the jackpot game state has ended, the stored value of the presentation symbol information buffer, etc.

After setting the variable command designation buffer in step AKS329, the maximum number of times the special prize opening is performed is set (step AKS330). The maximum number of times the special prize opening is performed is set in the game work area of RAM 102 at the next address after the variable command designation buffer, and is capable of storing the maximum number of times the special prize opening is controlled to be open during a special prize game. In step AKS330, the maximum number of times the special prize opening is performed can be determined using the jackpot symbol designation value determined in the jackpot information data selection process P_TFVR_ZU in step AKS326 and the maximum number of times the special prize opening is performed table stored in the game data area of ROM 101. The value corresponding to the determined maximum number of times the special prize opening is performed can then be stored in the maximum number of times the special prize opening is performed buffer using a transfer command to write the value to a memory area at a specified address in the game work area of RAM 102.

If the hit flag is not the designated jackpot value in step AKS322 (step AKS322; Yes), an arithmetic jump instruction is used to compare the hit flag with a judgment value corresponding to the designated small hit value to confirm that the hit flag is not the designated small hit value (step AKS331). If the hit flag is the designated small hit value (step AKS331; No), a special small hit symbol pattern designation value is stored in the special symbol buffer (step AKS332). The special small hit symbol pattern designation value may be created by adding a preset small hit symbol addition value to the stored value read from the winning symbol buffer with buffer number "0." The special small hit symbol pattern designation value may also be a value different from the special large hit symbol pattern designation value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer into which the lower address is loaded in step AKS307 of the special symbol determination process P_TDECISION shown in Figures 10-20. In step AKS332, the small win special symbol pattern designation value created using the small win symbol addition value, etc., is stored in the first special symbol buffer or the second special symbol buffer by a transfer command to write it to the memory area of the designated address in the game work area of RAM 102.

After storing the small win special symbol pattern designation value in step AKS332, the small win symbol designation value is determined (step AKS333). The small win symbol designation value can be determined using the value stored in the winning symbol buffer loaded in step AKS306 of the special symbol determination process P_TDECISION shown in Figure 10-20 and the first small win state setting table or the second small win state setting table set corresponding to the starting gate winning designation value. The determined small win symbol designation value is stored in the small win symbol determination buffer (step AKS334). The small win symbol determination buffer is located in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1) and is assigned address F036 [H]. In step AKS334, the small win symbol designation value is stored using a transfer command to write it to the memory area of the specified address in the game work area of RAM 102.

After step AKS334, a small win effect designation value is determined (step AKS335). The small win effect designation value can be determined using the small win information setting table stored in the game data area of ROM 101 and the small win pattern designation value determined in step AKS333. The small win effect designation value determined at this time is stored in the designation pattern information buffer (step AKS336). In step AKS336, the small win effect designation value determined in step AKS335 is stored in the designation pattern information buffer by a transfer command to write it to the memory area of the specified address in the game work area of RAM 102.

Once the small win effect designation value is stored in step AKS336, the small win information setting data is transferred (step AKS337). The small win information setting data indicates the small win fanfare display designation value and the small win ending display designation value. In step AKS337, the storage address of the small win information setting data corresponding to the determined small win effect designation value in the small win information setting table stored in the game data area of ROM 101 is set as a pointer specifying the transfer source. The address of the small win fanfare display buffer provided in the game work area of RAM 102 is also set as the transfer destination. Furthermore, the data size of the small win information setting data is set as the number of transfers. Thereafter, the small win information setting data read from the small win information setting table is transferred and stored in the small win fanfare display buffer and small win ending display buffer using a block transfer command.

If the win flag is not the small win designated value in step AKS331 (step AKS331; Yes), the loss special symbol pattern designated value is stored in the special symbol buffer (step AKS338). The loss special symbol pattern designated value may be a value different from the big win special symbol pattern designated value or the small win special symbol pattern designated value, as long as it is prepared in advance. For example, F1 [H] may be set as the loss special symbol pattern designated value. The special symbol buffer is the first special symbol buffer or the second special symbol buffer, whose lower address is loaded by step AKS307 of the special symbol determination process P_TDECISION shown in Figure 10-20. In step AKS338, the loss special symbol pattern designated value prepared in advance is stored in the first special symbol buffer or the second special symbol buffer by a transfer command for writing it to the memory area of the designated address in the game work area of RAM 102.

Following step AKS338, the effect symbol information buffer is cleared (step AKS339). The effect symbol information buffer can store effect specification values corresponding to when the special symbol display result is a "big hit" or a "small hit." On the other hand, when the special symbol display result is a "miss," the effect symbol information buffer is cleared, initializing the stored value to 00 [H]. In addition, the variable command specification buffer is cleared (step AKS340).

After steps AKS330, AKS337, and AKS340, a transfer command for setting a pointer is issued to set the pre-variation command transmission table address (step AKS341). The pre-variation command transmission table address is the address of the pre-variation command transmission table stored in the game data area of ROM 101. Then, the command set process P_COM_SET is executed (step AKS342), and the special symbol information setting process P_TZU_SET ends.

Figure 10-23 is a flowchart showing an example of the jackpot information data selection process P_TFVR_ZU. The jackpot information data selection process P_TFVR_ZU is called in the special symbol information setting process P_TZU_SET shown in Figure 10-22, and can be executed in step AKS326 if the hit flag is set to the jackpot specified value in step AKS322. When the CPU 103 executes the jackpot information data selection process P_TFVR_ZU, it sets the second jackpot state setting table address using a transfer command to set a pointer (step AKS401). The second jackpot state setting table address is the address of the second jackpot state setting table stored in the game data area of ROM 101.

Following step AKS401, it is confirmed that the start gate winning designation value is not "1" (step AKS402). The start gate winning designation value is stored in an internal register of CPU 103 by step AKS325 of the special symbol information setting process P_TZU_SET shown in Figure 10-22. If this start gate winning designation value is "1" (step AKS402; No), a transfer command for setting a pointer is issued to set the table address for setting the first jackpot state (step AKS403). The table address for setting the first jackpot state is the address of the table for setting the first jackpot state stored in the game data area of ROM 101. In step AKS403, the value of the pointer is overwritten by a transfer command for setting a pointer. Thus, in the special symbol information setting process P_TZU_SET, after setting the second jackpot state setting table address in step AKS401, the starting gate winning designation value corresponds to "1" in step AKS402, and the first jackpot state setting table address is overwritten in step AKS403. This reduces the program capacity required for table setting when the second jackpot state setting table is used more frequently than the first jackpot state setting table, thereby improving the marketability of the pachinko gaming machine 1. Furthermore, when the second jackpot state setting table is used more frequently than the first jackpot state setting table, processing using a jump command as a branch command is simplified, facilitating confirmation at the design stage and improving the marketability of the pachinko gaming machine 1.

If the starting gate winning designation value is "2" and not "1" in response to step AKS402 (step AKS401: Yes), or after step AKS403, a winning symbol buffer is set (step AKS404). The winning symbol buffer is the winning symbol buffer with buffer number "0" whose stored value was loaded in step AKS306 of the special symbol determination process P_TDECISION shown in Figure 10-20. This loaded content can be set as the processing target by transferring it to a processing register included in the internal registers of CPU 103. The stored value of the winning symbol buffer set in this way is used together with the second jackpot state setting table set in step AKS401 or the first jackpot state setting table set in step AKS403 to execute the second allocation determination value comparison process P_HANTEI2 (step AKS405).

The second allocation judgment value comparison process P_HANTEI2 sets the stored data at the top address of the table as the start number data, the stored data at the next address as the processing count data, and initially sets the start number data as the allocation result data. It then compares the numeric data set as the comparison value with the allocation judgment value indicated by the stored data at the address after the processing count data, in increasing order from the top to the bottom of the table addresses, until the allocation judgment value exceeds the comparison value. If the allocation judgment value is equal to or less than the comparison value, the allocation result data is updated by incrementing it by one and the next comparison is performed. If the allocation judgment value exceeds the comparison value, the second allocation judgment value comparison process P_HANTEI2 ends. If the number of comparisons corresponds to the processing count data but the allocation judgment value does not exceed the comparison value, the process can be repeated using the stored data at the next address and subsequent addresses, starting with setting the start number data and processing count data. In the second allocation judgment value comparison process P_HANTEI2 of step AKS405, the random number MR1-2 for the winning symbol, which is the stored value in the winning symbol buffer, is set as a comparison value, and the jackpot symbol designated value indicated by the allocation result data can be determined as the type of jackpot game state corresponding to the display result by the first special symbol display device 4A or the second special symbol display device 4B, based on the stored data in the first jackpot state setting table or the second jackpot state setting table. The second allocation judgment value comparison process P_HANTEI2 only needs to be executable when the small jackpot symbol designated value is determined by step AKS333 of the special symbol information setting process P_TZU_SET. In this case, the random number MR1-2 for the winning symbol, which is the value stored in the winning symbol buffer, is set as the comparison value, and the small win designation value indicated by the allocation result data can be determined as the type of small win game state corresponding to the display result by the first special symbol display device 4A or the second special symbol display device 4B, based on the stored data in the first small win state setting table or the second small win state setting table.

When the second allocation judgment value comparison process P_HANTEI2 of step AKS405 is completed, data for setting jackpot information is determined (step AKS406). The data for setting jackpot information can be selected from multiple types of pre-prepared data sets using the jackpot information data designation table selected corresponding to the stored value in the presentation state selection buffer and the jackpot symbol designation value determined by the second allocation judgment value comparison process P_HANTEI2 of step AKS405. The presentation state selection buffer can be set to a stored value corresponding to the presentation state after the jackpot game state has ended.

Figure 10-24 is a diagram illustrating an example of the use of data configuration corresponding to the control of the jackpot game state in relation to the special symbol information setting process P_TZU_SET and the jackpot information data selection process P_TFVR_ZU. If the hit flag is set to the jackpot designated value in step AKS322 of the special symbol information setting process P_TZU_SET, the jackpot information data selection process P_TFVR_ZU can be executed in step AKS326. In this jackpot information data selection process P_TFVR_ZU, the second allocation judgment value comparison process P_HANTEI2 in step AKS405 is executed using the second jackpot state setting table whose address is set in step AKS401 or the first jackpot state setting table whose address is set in step AKS403, thereby making it possible to determine the jackpot symbol designated value. Then, in step AKS328 of the special symbol information setting process P_TZU_SET, the jackpot information setting data read from the jackpot information setting table corresponding to the jackpot symbol specified value can be transferred and stored in the effect symbol information buffer, fanfare display buffer, and jackpot end display buffer. The effect symbol information buffer, fanfare display buffer, and jackpot end display buffer are provided in the effect symbol information area and can store setting data when controlled to a jackpot gaming state. Additionally, in step AKS330 of the special symbol information setting process P_TZU_SET, the maximum number of times the jackpot opening slot can be opened can be determined corresponding to the jackpot symbol specified value using the maximum number of times the jackpot opening slot can be opened.

In this way, the jackpot information data selection process P_TFVR_ZU uses the first jackpot state setting table or the second jackpot state setting table to determine the jackpot symbol designation value. The special symbol information setting process P_TZU_SET can set the storage values of the effect symbol information buffer, fanfare display buffer, and jackpot display buffer provided in the effect symbol information area, and can determine the maximum number of times the large prize opening will be opened corresponding to the jackpot symbol designation value.

Figure 10-24 (A1) shows an example configuration of the first jackpot status setting table AKT41. The first jackpot status setting table of the example configuration AKT41 stores a value of 00 [H] corresponding to the jackpot symbol designation value "1" at the first address 1AFD [H], and a value of 0A [H] indicating the number of processes at the next address 1AFE [H]. The stored data from address 1AFF [H] onwards indicates allocation judgment values corresponding to the jackpot symbol designation values "1" to "10." When using the first jackpot status setting table of the example configuration AKT41, the second allocation judgment value comparison process P_HANTEI2 of step AKS405 can determine one of the jackpot symbol designation values "1" to "10" in accordance with the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer. For example, if the random number MR1-2 for the winning symbol is 00 [H], which corresponds to the minimum random number value of "0", the jackpot symbol designation value "1" is determined.

Figure 10-24 (A2) shows an example configuration of the second jackpot status setting table AKT42. The second jackpot status setting table of the example configuration AKT42 stores a value 0A[H] corresponding to the jackpot symbol designated value "11" at the first address 1B09[H], and a value 04[H] indicating the processing number at the next address 1B0A[H]. The stored data from address 1B0B[H] onwards indicates allocation judgment values corresponding to the jackpot symbol designated values "11" to "14." When using the second jackpot status setting table of the example configuration AKT42, the second allocation judgment value comparison process P_HANTEI2 of step AKS405 can determine one of the jackpot symbol designated values "11" to "14" in accordance with the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer. For example, if the random number MR1-2 for the winning symbol is 00 [H], which corresponds to the minimum random number value of "0", the jackpot symbol designation value "11" is determined.

Figure 10-24 (B) shows an example configuration AKB41 of the effect symbol information area. The effect symbol information area of configuration AKB41 can store various data related to game control and effect control, including variable display of effect symbols, in response to control in either the big win game state or the small win game state. This effect symbol information area includes a effect symbol information buffer at address F056 [H], a fanfare display buffer at address F057 [H], a big win end display buffer at address F058 [H], a variable command specification buffer at address F059 [H], a maximum number of large prize openings buffer at address F05A [H], a small win fanfare display buffer at address F05F [H], and a small win ending display buffer at address F060 [H].

Figure 10-24 (C) shows an example AKD01 for determining the maximum number of times a large prize opening can be performed. Step AKS330 of the special symbol information setting process P_TZU_SET determines the maximum number of times a large prize opening can be performed corresponding to the designated jackpot symbol value determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS405 of the jackpot information data selection process P_TFVR_ZU. In example AKD01 for determining the maximum number of times a large prize opening can be performed, the maximum number of times a large prize opening can be determined to be one of the following: 02 [H] corresponding to "2," 04 [H] corresponding to "4," 07 [H] corresponding to "7," and 0A [H] corresponding to "10." The first jackpot status setting table of example AKT41 is used when the designated starting symbol value is "1," allowing the designated jackpot symbol value to be determined to be one of "1" to "10." In contrast, the second jackpot status setting table of the configuration example AKT42 is used when the starting slot winning designation value is "2," and allows the determination of any of the jackpot symbol designation values "11" to "14." Meanwhile, in the example AKD01 for determining the maximum number of times a jackpot slot is opened, when the jackpot symbol designation values are 00 [H] to 09 [H], corresponding to "1" to "10," the maximum number of times a jackpot slot is opened can be determined to be either 04 [H], corresponding to "4," or 0A [H], corresponding to "10." Meanwhile, in the example AKD01 for determining the maximum number of times a jackpot slot is opened, when the jackpot symbol designation values are 0A [H] to 0D [H], corresponding to "11" to "14," the maximum number of times a jackpot slot is opened can be determined to be either 02 [H], corresponding to "2," 04 [H], corresponding to "4," 07 [H], corresponding to "7," or 0A [H], corresponding to "10."

In this way, in example AKD01 for determining the maximum number of times a large prize opening can be performed, when the jackpot symbol designated value is 00 [H], which corresponds to "1," the maximum number of times a large prize opening can be performed is 04 [H], which corresponds to "4." This corresponds to the smaller of the maximum number of times a large prize opening can be performed, "4" or "10," which can be determined when the starting prize opening designated value is "1." The jackpot symbol designated value "1" can be determined when the random number MR1-2 for the winning symbol, indicated by the value stored in the winning symbol buffer, is the smallest random number, "0." Furthermore, in example AKD01 for determining the maximum number of times a large prize opening can be performed, when the jackpot symbol designated value is 0A [H], which corresponds to "11," the maximum number of times a large prize opening can be performed is 02 [H], which corresponds to "2." This corresponds to "2," the smallest of the maximum possible values of "2," "4," "7," and "10" for the number of times the jackpot opening slot can be opened when the starting slot winning designation value is "2." The jackpot designation value "11" can be determined when the random number MR1-2 for the winning slot, indicated by the value stored in the winning slot buffer, is the minimum random number value of "0." Therefore, among special slot games in which special slots are displayed variably on the first special slot display device 4A or the second special slot display device 4B, when the random number MR1-2 for the winning slot is the minimum random number value of "0," a more advantageous display result is not determined compared to when the random number is other than the minimum random number value. This allows for the appropriate random number value to be updated to prevent fraudulent activity due to a malfunction of the first random number value when the random number MR1-2 for the winning slot is set to the first random number value.

Figure 10-25 is a diagram illustrating an example of the use of data configuration corresponding to the control of the small win game state, with regard to the special symbol information setting process P_TZU_SET, etc. If the win flag is a small win designated value in step AKS331 of the special symbol information setting process P_TZU_SET, step AKS333 makes it possible to determine the small win pattern designated value. In this case, if the starting hole winning designated value is "1", the small win pattern designated value is determined using the first small win state setting table. On the other hand, if the starting hole winning designated value is "2", the small win pattern designated value is determined using the second small win state setting table. Then, in step AKS339 of the special symbol information setting process P_TZU_SET, the small win effect designated value determined in step AKS338 is stored in the effect pattern information buffer. Then, in step AKS340 of the special symbol information setting process P_TZU_SET, the small win information setting data read from the small win information setting table corresponding to the small win symbol designation value can be transferred to and stored in the small win fanfare display buffer and small win ending display buffer. The effect symbol information buffer, small win fanfare display buffer, and small win ending display buffer are provided in the effect symbol information area shown in Figure 10-24 (B), and can store setting data when controlled to a small win gaming state. Also, in step S112 of the special symbol process process P_TPROC shown in Figure 6, when the special symbol process code corresponds to 03 [H] and the small win opening pre-processing P_TLFAN is executed, the opening time and number of times the large prize opening can be opened can be determined using the small win opening work setting table, etc.

In this way, the special symbol information setting process P_TZU_SET can determine the small win symbol designation value using the first small win state setting table or the second small win state setting table. The special symbol information setting process P_TZU_SET can also set the storage values of the effect symbol information buffer, small win fanfare display buffer, and small win ending display buffer provided in the effect symbol information area. Furthermore, the small win pre-opening process P_TLFAN, which is executed in response to control to the small win gaming state, can determine the opening time and number of times the large prize opening will be opened.

Figure 10-25 (A1) shows an example configuration of the first small win status setting table AKT43. The first small win status setting table of the example configuration AKT43 stores the value 00 [H] corresponding to the small win symbol designated value "1" at the first address 1B0B [H], and stores the value 01 [H] indicating the number of processes at the next address 1B0C [H]. The stored data at address 1B0D [H] indicates the allocation determination value corresponding to the small win symbol designated value "1." When using the first small win status setting table of the example configuration AKT43, step AKS333 of the special symbol information setting process P_TZU_SET can only determine the small win symbol designated value "1" in accordance with the random number MR1-2 for the winning symbol indicated by the value stored in the winning symbol buffer. Therefore, when the random number MR1-2 for the winning symbol is 00 [H], which corresponds to the minimum random number value of "0", the small winning symbol designation value "1" is determined.

Figure 10-25 (A2) shows an example configuration of the second small win status setting table AKT44. The second small win status setting table of the example configuration AKT44 stores the value 01 [H] corresponding to the small win symbol designated value "2" at the first address 1B0E [H], and stores the value 06 [H] indicating the number of processes at the next address 1B0F [H]. The stored data from address 1B10 [H] onwards indicates allocation judgment values corresponding to the small win symbol designated values "2" to "7." When using the second small win status setting table of the example configuration AKT44, step AKS333 of the special symbol information setting process P_TZU_SET can determine one of the small win symbol designated values "2" to "7" in accordance with the winning symbol random number MR1-2 indicated by the value stored in the winning symbol buffer. For example, if the random number MR1-2 for the winning symbol is 00 [H], which corresponds to the minimum random number value of "0", the small winning symbol designation value "2" is determined.

Figure 10-25 (B) shows example AKD02 of determining the large prize opening mode. The pre-opening process P_TLFAN for small prizes can determine the large prize opening mode corresponding to the start prize opening designated value. The large prize opening mode can be determined to one of multiple modes with different opening times and number of times the large prize opening is opened. In example AKD02 of determining the large prize opening mode, a large prize opening mode with an opening time of 36 ms and 15 openings is determined in response to a start prize opening designated value of "1." Also, in example AKD02 of determining the large prize opening mode, a large prize opening mode with an opening time of 1600 ms and 1 opening is determined in response to a start prize opening designated value of "2."

In this way, the large prize opening mode during a small win game state can be determined to have different opening times and different opening times for the large prize opening, depending on the starting prize opening designated value, regardless of the small prize symbol designated value. The small prize symbol designated value can be determined in accordance with the random number MR1-2 for the winning symbol indicated by the value stored in the winning symbol buffer. If the starting prize opening designated value is the same, a common large prize opening mode is determined whether the random number MR1-2 for the winning symbol is the minimum random number value of "0" or any other random number value. Therefore, among special symbol games in which special symbols are variably displayed on the first special symbol display device 4A or the second special symbol display device 4B, when the random number MR1-2 for the winning symbol is the minimum random number value of "0," a display result with a higher degree of advantage is not determined compared to when the random number is any other random number value. This makes it possible to update the random number value appropriately to prevent fraudulent activity due to a malfunction in the first random number value when the random number MR1-2 for the winning symbol is used as the first random number value.

Figure 10-26 is a flowchart showing an example of the variable pattern setting process P_TPATSET. The variable pattern setting process P_TPATSET is included in the processes that can be called from the normal special symbol process P_TNORMAL shown in Figure 10-18, and can be executed in step AKS249 when variable display of special symbols is initiated. When the variable pattern setting process P_TPATSET is executed, the CPU 103 loads a hit flag (step AKS361). The hit flag is provided in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1), and is assigned address F032 [H]. In step AKS361, the hit flag is loaded using a transfer command to read the stored data at a specified address in the game work area of RAM 102. Then, an arithmetic jump command that can compare the hit flag with a judgment value corresponding to the specified jackpot value is used to confirm that the hit flag is not the specified jackpot value (step AKS362).

If the hit flag is set to the jackpot specified value in step AKS362 (step AKS362; No), the jackpot symbol determination buffer is loaded (step AKS363). The jackpot symbol determination buffer is located in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1) and is assigned address F035 [H]. In step AKS363, the jackpot symbol determination buffer is loaded using a transfer command to read the stored data at the specified address in the game work area of RAM 102. At this time, a transfer command to set a pointer is used to set the state-specific jackpot selection table address (step AKS364). The state-specific jackpot selection table address is the address of the state-specific jackpot selection table stored in ROM 101. Then, the hit-time fluctuation pattern type table selection process P_TPATA is executed (step AKS365). The winning variation pattern type table selection process P_TPATA in step AKS365 makes it possible to select a variation pattern type allocation table when the special chart display result corresponds to a "jackpot."

If the hit flag is not the designated value for a big hit in response to step AKS362 (step AKS362; Yes), an arithmetic jump instruction is used to compare the hit flag with the judgment value corresponding to the designated value for a small hit, thereby confirming that the hit flag is not the designated value for a small hit (step AKS366). If the hit flag is the designated value for a small hit (step AKS366; No), the variable command designation buffer is set (step AKS367). The variable command designation buffer is located in the performance symbol information area of the configuration example AKB41 shown in Figure 10-24 (B) and is assigned address F059 [H]. In step AKS367, a transfer instruction is used to write to the memory area of the designated address in the game work area of RAM 102, and 01 [H] is simply stored in the variable command designation buffer. The small hit symbol judgment buffer is also loaded (step AKS368). The small win symbol determination buffer is located in the special symbol control data area of the configuration example AKB21 shown in Figure 10-17 (B1) and is assigned address F036 [H]. In step AKS368, the small win symbol determination buffer is loaded using a transfer command to read the stored data at a specified address in the game work area of RAM 102. At this time, a transfer command to set a pointer is used to set the state-specific small win selection table address (step AKS369). The state-specific small win selection table address is the address of the state-specific small win selection table stored in ROM 101. Then, the win-time variation pattern type table selection process P_TPATA is executed (step AKS370). The win-time variation pattern type table selection process P_TPATA in step AKS370 enables selection of a variation pattern type allocation table in response to the special symbol display result being "small win."

If the hit flag is not the small hit designated value in response to step AKS366 (step AKS366; Yes), the miss fluctuation pattern type table selection process P_TPATH is executed (step AKS371). The miss fluctuation pattern type table selection process P_TPATH of step AKS371 corresponds to the special chart display result being "miss," and enables the selection of a fluctuation pattern type allocation table.

After steps AKS365, AKS370, and AKS371, the variation pattern type selection buffer with buffer number "0" is loaded (step AKS372). The variation pattern type selection buffer with buffer number "0" is the first variation pattern type selection buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer, or the second variation pattern type selection buffer included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. In step AKS372, after setting the address of the second variation pattern type selection buffer with buffer number "0," a start gate winning check process is executed. If the start gate winning designation value is "1," the address of the first variation pattern type selection buffer with buffer number "0" is set, and then a transfer command for reading the stored data at the set address is issued, allowing the variation pattern type selection random number MR3-3 stored in the variation pattern type selection buffer with buffer number "0" to be read.

When the random number MR3-3 for selecting a variation pattern type is read in step AKS372, the variation pattern allocation table selection process P_TPATTBL is executed (step AKS373). The variation pattern allocation table selection process P_TPATTBL in step AKS373 makes it possible to select a variation pattern allocation table using the variation pattern type allocation table selected in either step AKS365, AKS370, or AKS371 and the random number MR3-3 for selecting a variation pattern type read in step AKS372.

Following step AKS373, the variation pattern buffer with buffer number "0" is loaded (step AKS374). The variation pattern buffer with buffer number "0" is the first variation pattern buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer, or the second variation pattern buffer included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. In step AKS374, after setting the address of the second variation pattern buffer with buffer number "0," a start gate winning check process is executed. If the start gate winning designation value is "1," the address of the first variation pattern buffer with buffer number "0" is set, and then a transfer command is issued to read the stored data at the set address, allowing the variation pattern random numbers MR3-4 stored in the variation pattern buffer with buffer number "0" to be read.

When the random numbers MR3-4 for the fluctuation pattern are read in step AKS374, the second allocation judgment value comparison process P_HANTEI2 is executed (step AKS375). The second allocation judgment value comparison process in step AKS375 makes it possible to determine a fluctuation pattern using the fluctuation pattern allocation table selected in step AKS373 and the random numbers MR3-4 for the fluctuation pattern read in step AKS374. At this time, fluctuation pattern designation data corresponding to the determined fluctuation pattern is stored in the effect symbol fluctuation pattern buffer (step AKS376). The effect symbol fluctuation pattern buffer is provided in the game work area of RAM 102, and is capable of storing different fluctuation pattern designation data corresponding to the result of the fluctuation pattern determination.

Following step AKS376, a variable command transmission table is selected (step AKS377). In step AKS377, a variable command transmission table is selected using the variable command transmission table selection table and the value stored in the variable command designation buffer. This allows different variable command transmission tables to be selected, for example, when the special symbol display result is a "big hit" or "small hit," and when it is a "miss." The variable command transmission table is configured to include table data indicating the number of processes, the upper byte of the pattern information designation command, the pattern information designation code reference designation value, the upper byte of the performance symbol designation command, the performance symbol designation code reference designation value, the performance symbol variation command, and the variation pattern designation data reference designation value. Then, the command set process P_COM_SET is executed (step AKS378). The command set process P_COM_SET in step AKS378 uses the variation command transmission table selected in step AKS377 to enable the transmission of pattern information specification commands, performance pattern specification commands, and performance pattern variation commands. This command set process P_COM_SET in step AKS378 enables the transmission of performance control commands, which serve as variation start commands, from the main board 11 to the performance control board 12.

When step AKS378 enables the transmission of the fluctuation start command, the special symbol fluctuation time is set (step AKS379). In step AKS379, a time data expansion process is executed using the special symbol fluctuation time table and fluctuation pattern designation data, making it possible to set different special symbol fluctuation times corresponding to the result of the fluctuation pattern determination. Next, a transfer command for setting a pointer is issued to set the post-fluctuation pattern setting work table address (step AKS380). The post-fluctuation pattern setting work table address is the address of the post-fluctuation pattern setting work table stored in the game data area of ROM 101. Next, data set process P_DATASET is executed (step AKS381), and the fluctuation pattern setting process P_TPATSET is completed. The data set processing P_DATASET in step AKS381 uses the post-variation pattern setting work table whose address was set in step AKS380 to set the special pattern process code to 01 [H], which is the special pattern variation processing designated value, and sets the value stored in the special pattern variation display buffer to 01 [H], which is the special pattern variation display data. Additionally, the special pattern display update timer, the loss effect selection buffer with buffer number "0", the variation pattern type selection buffer with buffer number "0", and the variation pattern buffer with buffer number "0" are cleared to enable initialization. By referencing different tables when the start gate winning designated value is "1" and "2", different buffers and timers can be set and cleared.

Figure 10-27 (A) is a flowchart showing an example of the winning fluctuation pattern type table selection process P_TPATA. The winning fluctuation pattern type table selection process P_TPATA is included in the processes that can be called from the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, and can be executed in step AKS365 if the winning flag is set to the designated value for a big win in step AKS362, and can be executed in step AKS370 if the winning flag is set to the designated value for a small win in step AKS366. When the CPU 103 executes the winning fluctuation pattern type table selection process P_TPATA, it loads the presentation state selection buffer (step AKS421). The presentation state selection buffer is provided in the game work area of RAM 102, and can be set to a storage value corresponding to the presentation state after the end of the big win game state. In step AKS421, it is sufficient that the value stored in the performance state selection buffer can be read using a transfer command to read the stored data at a specified address in the game work area of RAM 102.

Following step AKS421, a fluctuation pattern type selection table is determined (step AKS422). In step AKS422, the fluctuation pattern type selection table can be determined using the state-specific jackpot selection table or state-specific small jackpot selection table and the stored value of the presentation state selection buffer read in step AKS421. The address of the state-specific jackpot selection table is set in step AKS364 when the win-time fluctuation pattern type table selection process P_TPATA is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26. The address of the state-specific small jackpot selection table is set in step AKS369 when the win-time fluctuation pattern type table selection process P_TPATA is executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26. The state-specific big hit selection table and state-specific small hit selection table are configured to include table data that enables different variation pattern type selection tables to be determined in accordance with the value stored in the presentation state selection buffer. Therefore, step AKS422 enables different variation pattern type selection tables to be determined in accordance with the value stored in the presentation state selection buffer when the special chart display result is a "big hit" or a "small hit."

Once the variation pattern type selection table is determined in step AKS422, a winning symbol designation value is set (step AKS423). In step AKS423, the contents loaded from the jackpot symbol determination buffer or the small win symbol determination buffer are set as the processing target by transferring them to a processing register included in the internal registers of CPU 103. The jackpot symbol determination buffer is loaded in step AKS363 when the win-time variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in Figure 10-26. The small win symbol determination buffer is loaded in step AKS368 when the win-time variation pattern type table selection process P_TPATA is executed in step AKS370 of the variation pattern setting process P_TPATSET shown in Figure 10-26. The value stored in the jackpot symbol determination buffer indicates the jackpot symbol designation value. The value stored in the small win symbol determination buffer indicates the small win symbol designation value. The set win symbol designation value, along with the variation pattern type selection table determined in step AKS422, is used to execute the allocation determination value comparison process P_HANTEI (step AKS424).

The allocation judgment value comparison process P_HANTE compares the numerical data set as the comparison value with the allocation judgment value indicated by the table storage data, in increasing order from the top to the bottom of the table address, until the allocation judgment value exceeds the comparison value. At this time, if the allocation judgment value is equal to or less than the comparison value, it proceeds to the next comparison, and makes the table storage data readable as designated data corresponding to the allocation judgment value that exceeds the comparison value. The allocation judgment value comparison process P_HANTEI in step AKS424 sets the big hit symbol designated value or small hit symbol designated value as the comparison value, and reads out the designated data corresponding to the allocation judgment value that exceeds the comparison value from the data stored in the variation pattern type selection table.

When the allocation judgment value comparison process P_HANTEI of step AKS424 is completed, the fluctuation pattern type allocation table is determined (step AKS425), and the hit-time fluctuation pattern type table selection process P_TPATA is completed. In step AKS425, the specified data read by the allocation judgment value comparison process P_HANTEI of step AKS424 is added to the starting address of the fluctuation pattern type allocation table, and the address of the fluctuation pattern type allocation table to be used is set as a pointer, making it possible to determine the fluctuation pattern type allocation table.

Figure 10-27 (B1) shows an example AKD11 of a variation pattern type allocation table determination where the special symbol display result corresponds to "jackpot." When the special symbol display result is "jackpot," the second allocation judgment value comparison process P_HANTEI2 can determine one of the values 00 [H] to 0D [H] corresponding to the jackpot symbol designation value "1" to "14." When the win-time variation pattern type table selection process P_TPATA is executed in step AKS365 of the variation pattern setting process P_TPATSET shown in Figure 10-26, it can determine a variation pattern type allocation table in accordance with the determination result of the jackpot symbol designation value. In the variation pattern type allocation table determination example AKD11, one of the variation pattern type allocation tables AKU01 to AKU03 can be determined in accordance with the values 00 [H] to 0D [H] indicating the jackpot symbol designation value.

Figure 10-27 (B2) shows an example of a variation pattern type allocation table determination AKD12 corresponding to the special symbol display result of "small win." When the special symbol display result is "small win," step AKS333 of the special symbol information setting process P_TZU_SET shown in Figure 10-22 can determine one of the values 00 [H] to 06 [H] corresponding to the small win symbol designation value "1" to "7." When executed in step AKS370 of the variation pattern setting process P_TPATSET shown in Figure 10-26, the variation pattern type table selection process P_TPATA at the time of win can determine a variation pattern type allocation table corresponding to the determination result of the small win symbol designation value. In variation pattern type allocation table determination example AKD12, either variation pattern type allocation table AKU11 or AKU12 can be determined corresponding to the small win symbol designation value of 00 [H] to 06 [H].

Figure 10-28 (A) is a flowchart showing an example of the loss-time fluctuation pattern type table selection process P_TPATH. The loss-time fluctuation pattern type table selection process P_TPATH is included in the processes that can be called from the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, and can be executed in step AKS371 if the hit flag is not set to the small hit designated value in step AKS366. When the loss-time fluctuation pattern type table selection process P_TPATH is executed, the CPU 103 sets the state-specific loss selection table address using a transfer command to set a pointer (step AKS441). The state-specific loss selection table address is the address of the first state-specific loss selection table or the second state-specific loss selection table stored in the game data area of ROM 101. In step AKS441, different addresses in the game data area can be specified corresponding to whether the starting gate winning designated value is "1" or "2." This allows the address of the first status-specific miss selection table to be set when the start port winning designation value is "1," and the address of the second status-specific miss selection table to be set when the start port winning designation value is "2." The presentation state selection buffer is then loaded (step AKS442). The presentation state selection buffer is provided in the game work area of RAM 102, and can be set to a value corresponding to the presentation state after the jackpot game state ends.

Following step AKS442, a pending miss effect allocation selection table is determined (step AKS443). In step AKS443, the pending miss effect allocation selection table is determined using the first state-specific miss selection table or the second state-specific miss selection table whose address was set in step AKS441 and the stored value of the effect state selection buffer loaded in step AKS442. The first state-specific miss selection table or the second state-specific miss selection table is configured to include table data that enables a different pending miss effect allocation selection table to be determined in accordance with the stored value of the effect state selection buffer. Furthermore, the pending miss effect allocation selection table is configured to include table data that enables a different miss effect allocation table to be determined in accordance with the count value of the start port winning memory counter. Therefore, step AKS443 determines a different pending miss effect allocation selection table depending on whether the start port winning designation value is "1" or "2," in accordance with the value stored in the effect status selection buffer.

Following step AKS443, the start port winning memory counter is loaded (step AKS444). The start port winning memory counter is the first start port winning memory counter when the start port winning designation value is "1" or the second start port winning memory counter when the start port winning designation value is "2." In step AKS444, the second start port winning memory counter address is set to the memory pointer, and then the start port winning check process is executed. If the start port winning designation value is "1," the first start port winning memory counter address is set to the memory pointer, and then a transfer command is issued to read the stored data at the address set in the memory pointer, making it possible to obtain the count value of the first start port winning memory counter or the second start port winning memory counter.

After step AKS444, allocation judgment value comparison process P_HANTEI is executed (step AKS445). In allocation judgment value comparison process P_HANTEI of step AKS445, the count value of the first start port winning memory counter or the second start port winning memory counter obtained in step AKS444 is set as a comparison value, and designated data corresponding to the allocation judgment value that exceeds the comparison value is read out using the stored data of the pending miss effect allocation selection table determined in step AKS443.

When the allocation judgment value comparison process P_HANTEI of step AKS445 is completed, a miss effect allocation table is determined (step AKS446). In step AKS446, the specified data read by the allocation judgment value comparison process P_HANTEI of step AKS445 is added to the starting address of the miss effect allocation table, and the address of the miss effect allocation table to be used is set as a pointer, making it possible to determine the miss effect allocation table.

Following step AKS446, the losing effect selection buffer with buffer number "0" is loaded (step AKS447). The losing effect selection buffer with buffer number "0" is the first losing effect selection buffer included in the first reserved memory buffer with buffer number "0" in the first special symbol reserved buffer, or the second losing effect selection buffer included in the second reserved memory buffer with buffer number "0" in the second special symbol reserved buffer. In step AKS447, after setting the address of the second losing effect selection buffer with buffer number "0," if the starting gate winning designation value is "1" as determined by the starting gate winning check process, the address of the first losing effect selection buffer with buffer number "0" is set, and then a transfer command is issued to read the data stored at the set address, allowing the losing effect selection random number MR3-2 stored in the losing effect selection buffer with buffer number "0" to be read.

When the random number MR3-2 for selecting a losing effect is read in step AKS447, the allocation judgment value comparison process P_HANTEI is executed (step AKS448). The allocation judgment value comparison process P_HANTEI in step AKS448 uses the losing effect allocation table determined in step AKS446 and the random number MR3-2 for selecting a losing effect read in step AKS447 to determine the offset value of the variation pattern type allocation table. In this case, the random number MR3-2 for selecting a losing effect read in step AKS447 is set as the comparison value, and the stored data of the losing effect allocation table determined in step AKS446 makes it possible to read the offset value of the variation pattern type allocation table indicated by the specified data corresponding to the allocation judgment value that exceeds the comparison value.

When the allocation judgment value comparison process P_HANTEI of step AKS448 is completed, the fluctuation pattern type allocation table is determined (step AKS449), and the miss fluctuation pattern type table selection process P_TPATH is completed. In step AKS449, the offset value indicated by the specified data read by the allocation judgment value comparison process P_HANTEI of step AKS448 is added to the starting address of the fluctuation pattern type allocation table, and the address of the fluctuation pattern type allocation table to be used is set in the pointer, making it possible to determine the fluctuation pattern type allocation table.

Figure 10-28 (B1) shows an example AKD21 of determining a miss effect allocation table corresponding to a first special symbol miss. A first special symbol miss occurs when the start port winning designation value corresponds to "1" and the special symbol display result is "miss" in a special symbol game using the first special symbol by the first special symbol display device 4A. When the start port winning designation value is "1," step AKS444 of the miss time variation pattern type table selection process P_TPATH can obtain the count value of the first start port winning memory counter. The count value of the first start port winning memory counter indicates the first reserved memory number. Then, the allocation judgment value comparison process P_HANTEI in step AKS445 reads out the designated data corresponding to the count value of the first start port winning memory counter, and step AKS446 can determine a miss effect allocation table corresponding to the first reserved memory number. In the example of determining the miss effect allocation table AKD21, one of the miss effect allocation tables AKV01 to AKV04 can be determined according to the first reserved memory count "0" to "3".

Figure 10-28 (B2) shows an example AKD22 of determining a miss effect allocation table corresponding to a miss on the second special symbol. A miss on the second special symbol occurs when the start port winning designation value corresponds to "2" and the special symbol display result is "miss" in a special symbol game using the second special symbol by the second special symbol display device 4B. When the start port winning designation value is "2," step AKS444 of the miss time variation pattern type table selection process P_TPATH can obtain the count value of the second start port winning counter. The count value of the second start port winning memory counter indicates the second reserved memory number. Then, the allocation judgment value comparison process P_HANTEI in step AKS445 reads out the designated data corresponding to the count value of the second start port winning memory counter, and step AKS446 can determine a miss effect allocation table corresponding to the second reserved memory number. In the example of determining the miss effect allocation table AKD22, only the common miss effect allocation table AKV11 can be determined for the second reserved memory counts "0" to "3".

Figure 10-28 (C) shows an example AKD23 of a variation pattern type allocation table determination for the miss effect allocation table AKV01. The miss effect allocation table AKV01 can be determined when the first pending memory count is "0" in the example AKD21 of the miss effect allocation table determination when the starting port winning designation value is "1." When the starting port winning designation value is "1," step AKS447 of the miss time variation pattern type table selection process P_TPATH can read the random number MR3-2 for selecting a miss effect from the first miss effect selection buffer with buffer number "0." Then, the allocation judgment value comparison process P_HANTEI in step AKS448 reads the designation data corresponding to the random number MR3-2 for selecting a miss effect, and the variation pattern type allocation table can be determined in step AKS449. In the variation pattern type allocation table determination example AKD23, one of the variation pattern type allocation tables AKU21 to AKU25 can be selected in response to the random number MR3-2 used to select the losing effect.

Figure 10-29 is a diagram illustrating an example of the configuration of a fluctuation pattern type allocation table. When the winning fluctuation pattern type table selection process P_TPATA shown in Figure 10-27 (A) is executed in step AKS365 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, it can determine one of multiple fluctuation pattern type allocation tables, such as one of the fluctuation pattern type allocation tables AKU01 to AKU03 in the fluctuation pattern type allocation table determination example AKD11 shown in Figure 10-27 (B1), in accordance with the result of determining the jackpot symbol designation value. When the winning fluctuation pattern type table selection process P_TPATA shown in Figure 10-27 (A) is executed in step AKS370 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, it can determine one of a plurality of fluctuation pattern type allocation tables, such as one of the fluctuation pattern type allocation tables AKU11 and AKU12 in the fluctuation pattern type allocation table determination example AKD12 shown in Figure 10-27 (B2), in accordance with the result of determining the small win symbol designation value. Step AKS449 of the losing fluctuation pattern type table selection process P_TPATH shown in Figure 10-28 (A) can determine one of a plurality of fluctuation pattern type allocation tables, such as one of the fluctuation pattern type allocation tables AKU21 to AKU25 in the fluctuation pattern type allocation table determination example AKD23 shown in Figure 10-28 (C). The fluctuation pattern allocation table selection process P_TPATTBL, which is executed in step AKS373 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, can select a fluctuation pattern type by referencing the fluctuation pattern type allocation table using the random number MR3-3 for selecting the fluctuation pattern type read out in step AKS372, and can select a fluctuation pattern allocation table corresponding to the selection result.

Figure 10-29(A) shows an example of the configuration of the fluctuation pattern type allocation table AKU01. The fluctuation pattern type allocation table AKU01 is included in multiple fluctuation pattern type allocation tables that can be determined in accordance with the jackpot symbol designation value. The fluctuation pattern type allocation table AKU01 in Figure 10-29(A) is configured so that the table data can be determined to be one of the fluctuation pattern types CPA01 to CPA05 in accordance with the random number MR3-3 used to select the fluctuation pattern type.

Figure 10-29 (B1) shows an example of the configuration of the fluctuation pattern type allocation table AKU11. The fluctuation pattern type allocation table AKU11 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the small win symbol designation value. The fluctuation pattern type allocation table AKU11 in Figure 10-29 (B1) is configured so that the table data can be determined to only the common fluctuation pattern type CPB01 in response to all of the random numbers MR3-3 used to select fluctuation pattern types.

Figure 10-29 (B2) shows an example of the configuration of the fluctuation pattern type allocation table AKU12. The fluctuation pattern type allocation table AKU12 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the small win symbol designation value. The fluctuation pattern type allocation table AKU12 in Figure 10-29 (B2) is configured so that the table data can be determined to be only the common fluctuation pattern type CPB02 in response to all of the random numbers MR3-3 used to select fluctuation pattern types.

Figure 10-29 (C1) shows an example of the configuration of the fluctuation pattern type allocation table AKU21. The fluctuation pattern type allocation table AKU21 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a losing effect. The fluctuation pattern type allocation table AKU21 in Figure 10-29 (C1) has table data configured so that it can be determined to be either the fluctuation pattern type CPC01 or CPC02 in response to the random number MR3-3 for selecting the fluctuation pattern type.

Figure 10-29 (C2) shows an example of the configuration of the fluctuation pattern type allocation table AKU22. The fluctuation pattern type allocation table AKU22 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a losing effect. The fluctuation pattern type allocation table AKU22 in Figure 10-29 (C2) is configured so that only the common fluctuation pattern type CPC03 can be determined in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figure 10-29 (C3) shows an example of the configuration of the fluctuation pattern type allocation table AKU23. The fluctuation pattern type allocation table AKU23 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a losing effect. The fluctuation pattern type allocation table AKU23 in Figure 10-29 (C3) is configured so that only the common fluctuation pattern type CPC04 can be determined in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figure 10-29 (C4) shows an example of the configuration of the fluctuation pattern type allocation table AKU24. The fluctuation pattern type allocation table AKU24 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a losing effect. The fluctuation pattern type allocation table AKU24 in Figure 10-29 (C4) has table data configured so that it can be determined to be one of the fluctuation pattern types CPC05 to CPC07 in response to the random number MR3-3 for selecting a fluctuation pattern type.

Figure 10-29 (C5) shows an example of the configuration of the fluctuation pattern type allocation table AKU25. The fluctuation pattern type allocation table AKU25 is included in multiple fluctuation pattern type allocation tables that can be determined in response to the random number MR3-2 for selecting a losing effect. The fluctuation pattern type allocation table AKU25 in Figure 10-29 (C5) is configured so that only the common fluctuation pattern type CPC08 can be determined in response to all of the random numbers MR3-3 for selecting fluctuation pattern types.

Figures 10-30 to 10-32 are diagrams illustrating example configurations of fluctuation pattern allocation tables that can be used in accordance with fluctuation pattern types. In the fluctuation pattern allocation table selection process P_TPATTBL executed in step AKS373 of the fluctuation pattern setting process P_TPATSET shown in Figure 10-26, a fluctuation pattern allocation table is selected in accordance with the result of the selection of the fluctuation pattern type using the random number MR3-3 for selecting the fluctuation pattern type. Thereafter, the second allocation judgment value comparison process P_HANTEI2 in step AKS375 uses the random number MR3-4 for the fluctuation pattern read out in step AKS374 to refer to the fluctuation pattern allocation table, thereby making it possible to determine the fluctuation pattern.

Figure 10-30 (A1) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA01. When using the fluctuation pattern type allocation table AKU01, which can be determined in accordance with the jackpot symbol specified value, the fluctuation pattern type CPA01 can be determined at a predetermined rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A1), the fluctuation pattern allocation table is configured so that it can be determined as one of the fluctuation patterns PA01 to PA03, PA51, or PA52 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA01 can be determined as one of the fluctuation patterns PA01 to PA03, PA51, or PA52.

Figure 10-30 (A2) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA02. When using the fluctuation pattern type allocation table AKU01, which can be determined in accordance with the jackpot symbol designation value, the fluctuation pattern type CPA02 can be determined at a predetermined rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A2), the fluctuation pattern allocation table is configured so that the fluctuation pattern type can be determined to be one of the fluctuation patterns PA04 to PA11, PA21 to PA23, or PA54 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA02 can be determined to be one of the fluctuation patterns PA04 to PA11, PA21 to PA23, or PA54.

Figure 10-30 (A3) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA03. When using the fluctuation pattern type allocation table AKU01, which can be determined in accordance with the jackpot symbol specified value, the fluctuation pattern type CPA03 can be determined at a predetermined rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A3), the fluctuation pattern allocation table is configured so that the fluctuation pattern type can be determined to be one of the fluctuation patterns PA31 to PA38, PA24 to PA26, or PA55 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA03 can be determined to be one of the fluctuation patterns PA31 to PA38, PA24 to PA26, or PA55.

Figure 10-30 (A4) shows an example of the configuration of a fluctuation pattern allocation table corresponding to fluctuation pattern type CPA04. When using fluctuation pattern type allocation table AKU01, which can be determined in accordance with the jackpot symbol specified value, fluctuation pattern type CPA04 can be determined at a predetermined rate corresponding to random number MR3-3 for selecting fluctuation pattern type. In the configuration example of Figure 10-30 (A4), the fluctuation pattern allocation table is configured so that only the common fluctuation pattern PA41 can be determined in accordance with random numbers MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that fluctuation pattern type CPA04 can only be determined to fluctuation pattern PA41.

Figure 10-30 (A5) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPA05. When using the fluctuation pattern type allocation table AKU01, which can be determined in accordance with the jackpot symbol specified value, the fluctuation pattern type CPA05 can be determined at a predetermined rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-30 (A5), the fluctuation pattern allocation table is configured so that only the common fluctuation pattern PA42 can be determined in accordance with the random numbers MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPA05 can only be determined as fluctuation pattern PA42.

Figure 10-30 (B1) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPB01. When using the fluctuation pattern type allocation table AKU11, which can be determined in accordance with the small win symbol designation value, the fluctuation pattern type CPB01 can be determined in accordance with the random numbers MR3-3 for selecting all fluctuation pattern types. In the configuration example of Figure 10-30 (B1), the fluctuation pattern allocation table is configured so that only the common fluctuation pattern PB01 can be determined in accordance with the random numbers MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPB01 can only be determined as the fluctuation pattern PB01.

Figure 10-30 (B2) shows an example of the configuration of a fluctuation pattern allocation table corresponding to fluctuation pattern type CPB02. When using fluctuation pattern type allocation table AKU12, which can be determined in accordance with the small win symbol designation value, fluctuation pattern type CPB02 can be determined in accordance with all fluctuation pattern type selection random numbers MR3-3. In the configuration example of Figure 10-30 (B2), the fluctuation pattern allocation table is configured so that it can determine one of fluctuation patterns PB11 to PB14 in accordance with the fluctuation pattern random number MR3-4. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that fluctuation pattern type CPB02 can be determined to be one of fluctuation patterns PB11 to PB14.

Figure 10-31(A) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC01. When using the fluctuation pattern type allocation table AKU21, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC01 can be determined at a predetermined rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-31(A), the fluctuation pattern allocation table is configured so that only the common fluctuation pattern PC01 can be determined in accordance with the random numbers MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC01 can only be determined to be the fluctuation pattern PC01.

Figure 10-31(B) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC02. When using the fluctuation pattern type allocation table AKU21, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC02 can be determined at a predetermined rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-31(B), the fluctuation pattern allocation table is configured so that the fluctuation pattern type can be determined to be one of the fluctuation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, or PC49 in accordance with the fluctuation pattern random number MR3-4. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC02 can be determined to be one of the fluctuation patterns PC12, PC13, PC15, PC16, PC24, PC27, PC33, or PC49.

Figure 10-31(C) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC03. When using the fluctuation pattern type allocation table AKU22, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC03 can be determined in accordance with all of the fluctuation pattern type selection random numbers MR3-3. In the configuration example of Figure 10-31(C), the fluctuation pattern allocation table is configured so that it can be determined to be one of the fluctuation patterns PC11 to PC18, or PC101 in accordance with the fluctuation pattern random number MR3-4. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC03 can be determined to be one of the fluctuation patterns PC11 to PC18, or PC101.

Figure 10-31(D) shows an example of the configuration of a fluctuation pattern allocation table corresponding to fluctuation pattern type CPC04. When using fluctuation pattern type allocation table AKU23, which can be determined in accordance with random number MR3-2 for selecting a losing effect, fluctuation pattern type CPC04 can be determined in accordance with all fluctuation pattern type selection random numbers MR3-3. In the configuration example of Figure 10-31(D), the fluctuation pattern allocation table is configured so that it can be determined to be one of fluctuation patterns PC19 to PC27, or PC102 in accordance with fluctuation pattern random number MR3-4. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that fluctuation pattern type CPC04 can be determined to be one of fluctuation patterns PC19 to PC27, or PC102.

Figure 10-32(A) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC05. When using the fluctuation pattern type allocation table AKU24, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC05 can be determined at a first ratio corresponding to the random number MR3-3 for selecting the fluctuation pattern type. In the configuration example of Figure 10-32(A), the fluctuation pattern allocation table is configured so that it can be determined as one of the fluctuation patterns PC28 to PC43 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC05 can be determined as one of the fluctuation patterns PC28 to PC43.

Figure 10-32(B) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC06. When using the fluctuation pattern type allocation table AKU24, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC06 can be determined at a second rate different from the first rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. The second rate is a rate lower than the first rate. In the configuration example of Figure 10-32(B), the fluctuation pattern allocation table is configured so that the fluctuation pattern type CPC06 can be determined to be one of the fluctuation patterns PC44 to PC59 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC06 can be determined to be one of the fluctuation patterns PC44 to PC59.

Figure 10-32(C) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC07. When using the fluctuation pattern type allocation table AKU24, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC07 can be determined at a third rate, which is different from the first rate and second rate corresponding to the random number MR3-3 for selecting the fluctuation pattern type. The third rate is a rate lower than the first rate and the second rate. In the configuration example of Figure 10-32(C), the fluctuation pattern allocation table is configured so that it can be determined as one of the fluctuation patterns PC60 to PC75 in accordance with the random number MR3-4 for the fluctuation pattern. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC07 can be determined as one of the fluctuation patterns PC60 to PC75.

Figure 10-32(D) shows an example of the configuration of a fluctuation pattern allocation table corresponding to the fluctuation pattern type CPC08. When using the fluctuation pattern type allocation table AKU25, which can be determined in accordance with the random number MR3-2 for selecting a losing effect, the fluctuation pattern type CPC08 can be determined in accordance with the random number MR3-3 for selecting all fluctuation pattern types. In the configuration example of Figure 10-32(D), the fluctuation pattern allocation table is configured so that only the common fluctuation pattern PC02 can be determined in accordance with the random number MR3-4 for all fluctuation patterns. In this way, the allocation judgment value is set by the stored data of the fluctuation pattern allocation table so that the fluctuation pattern type CPC08 can only be determined as the fluctuation pattern PC02.

Figure 10-33 (A) is a flowchart showing an example of normal symbol process processing P_FPROC. Normal symbol process processing P_FPROC is included in the processing that can be called from the game control timer interrupt processing P_PCT shown in Figure 5, and can be executed in step AKS59 each time a timer interrupt occurs. When normal symbol process processing P_FPROC is executed, the CPU 103 sets the gate switch passing response flag (step AKS501). The gate switch passing response flag is set by, for example, executing a logical operation instruction, reflecting the state of the gate switch 21 contained in the switch-on buffer in the flag register of the CPU 103. At this time, a zero flag in the flag register being in the on state indicates that the gate switch passing response flag is in the off state. Conversely, a zero flag being in the off state indicates that the gate switch passing response flag is in the on state. It is then determined whether the gate switch passing response flag is on (step AKS502). If the gate switch passing flag is on (step AKS502; Yes), the gate switch passing process P_FZU_ON is executed (step AKS503).

If the gate switch passing flag is off in step AKS502 (step AKS502; No), or after the gate switch passing process P_FZU_ON in step AKS503, a transfer command that sets a pointer sets the normal symbol process processing jump table (step AKS504). The normal symbol process processing jump table is an address management table that selects and executes the process corresponding to the read value of the normal symbol process code. The normal symbol process code can be updated to any of 00 [H] to 04 [H] in accordance with the progress of game control in the pachinko gaming machine 1, and is also called the normal symbol process code.

Following step AKS504, a transfer command to read stored data is used to load the normal symbol process code (step AKS505). Next, the 2-byte data selection process P_ABXEXEC is executed (step AKS506) to obtain the address of the process selected corresponding to the normal symbol process code. The address obtained at this time is set in a pointer. Then, a subroutine call command is issued to execute the process pointed to by the pointer (step AKS507), making the process selected corresponding to the normal symbol process code executable. When the selected process is completed and a return command is issued to return to the normal symbol process process P_FPROC, this normal symbol process process P_FPROC also ends, and a return command is issued to return to the game control timer interrupt process P_PCT.

Figure 10-33 (B) shows an example configuration of the normal symbol process processing jump table AKT51 used in the normal symbol process processing P_FPROC. The normal symbol process processing jump table is configured to include table data that allows the address of the process selected in accordance with the normal symbol process code to be set in an internal register of the CPU 103 used as a pointer. The normal symbol process processing jump table of configuration example AKT51 includes table data that allows the pointer to be set to address values corresponding to normal symbol normal processing P_FNORM when the normal symbol process code is 00 [H], normal symbol change processing P_FSCRL when the normal symbol process code is 01 [H], normal symbol stop processing P_FSTOP when the normal symbol process code is 02 [H], normal electric role activation pre-processing P_FINT when the normal symbol process code is 03 [H], and normal electric role activation processing P_FOPEN when the normal symbol process code is 04 [H].

Normal symbol normal processing P_FNORM determines whether to start a normal symbol game based on the presence or absence of stored normal symbol pending information, determines the confirmed normal symbol to be displayed as a stopped symbol in the variable normal symbol display, and determines the normal symbol change pattern, which is the normal symbol change pattern. Normal symbol change processing P_FSCRL measures the elapsed time since the normal symbol began to change on the normal symbol display device 20, and determines whether the normal symbol change time corresponding to the normal symbol change pattern has elapsed. Normal symbol stop processing P_FSTOP measures the elapsed time since the normal symbol stopped changing on the normal symbol display device 20, and determines whether the normal symbol stop time has elapsed. When the normal symbol stop time has elapsed, the normal symbol process code can be updated and various settings can be made in accordance with the normal symbol display result. In this embodiment, it is sufficient that the normal symbol process code can be updated to 03[H] in accordance with all normal symbol display results. The normal electric device pre-activation processing P_FINT and the normal electric device activation processing P_FOPEN are processes that enable the second starting winning port formed in the variable winning ball device 6B to be changed from a closed state to an open state by controlling the normal electric device solenoid 81.

Figure 10-34 is a diagram illustrating an example of the use of data configuration related to the control of a normal symbol game, which is a variable display of normal symbols. For example, the normal symbol process processing P_FPROC shown in Figure 10-33(A) uses the normal symbol process code loaded in step AKS505 to execute the 2-byte data selection processing P_ABXEXEC in step AKS506, thereby enabling step AKS507 to execute the processing selected corresponding to the normal symbol process code. The normal symbol process code is provided in the normal symbol control data area, and its stored value can be updated corresponding to the control status of the normal symbol game and the second start winning slot. The gate switch passing processing P_FZU_ON in step AKS503 can read the random number MR2-1 for the normal symbol, and for the read random number MR2-1, the numerical data indicating its value can be stored in the normal symbol buffer for saving. The normal symbol buffer is located in the normal symbol buffer area and can store numerical data indicating the value of the read random number MR2-1 until the normal symbol reserve memory number reaches the upper limit. In this way, the normal symbol process processing P_FPROC and the processes executable in the normal symbol process processing P_FPROC use stored data in the normal symbol control data area and the normal symbol buffer area to enable control of the normal symbol game, which is a variable display of normal symbols.

Figure 10-34 (A) shows an example configuration AKB51 of the normal symbol control data area. The normal symbol control data area of configuration AKB51 can store various data related to control by the normal symbol process processing P_FPROC, such as the normal symbol game, which is a variable display of normal symbols, and the closed/open state of the second start winning gate, which can be controlled based on the display results. This normal symbol control data area includes a normal symbol process code at address F03E[H], a gate passage memory counter at address F03F[H], a normal symbol buffer at address F040[H], a normal electric feature release pattern timer at address F041[H], a normal electric feature release pointer at address F043[H], a normal electric feature winning number counter at address F045[H], and a normal symbol process timer at address F04A[H].

The normal symbol process code can specify the processing selected in the normal symbol process processing P_FPROC. The gate passage memory counter can store a count value corresponding to the number of game balls detected by the gate switch 21. The normal symbol buffer can store data corresponding to the normal symbol designation value. The normal symbol designation value is a designation value corresponding to the confirmed normal symbol that is the display result in the variable display of the normal symbol by the normal symbol display device 20, and includes a normal symbol winning symbol designation value. The normal symbol winning symbol designation value is a designation value corresponding to the confirmed normal symbol displayed by the normal symbol display device 20 when the display result in the variable display of the normal symbol is "normal winning." The normal electric device opening pattern timer can store a timing value corresponding to the remaining time for controlling the second start winning port to an open state. The normal electric device opening pointer can specify the storage address of the normal electric device opening pattern table, in which the time for controlling the second start winning port to an open state is set. The normal electric device winning number counter can store a count value corresponding to the number of game balls detected by the second start switch 22B. The normal symbol process timer can store a time value corresponding to the control time by the normal symbol process processing P_FPROC.

Figure 10-34 (B) shows a configuration example AKB52 of a buffer area for normal symbols. The buffer area for normal symbols of configuration example AKB52 can store numerical data indicating the value of the random number MR2-1 for normal symbols read when a gaming ball passes through the passing gate 41. This buffer area for normal symbols includes normal symbol buffer numbers "1" to "4" at addresses F046 [H] to F049 [H]. Normal symbol buffer numbers "1" to "4" are buffers for normal symbols assigned buffer numbers "1" to "4," and can store the values of the random number MR2-1 in the order in which the gaming ball passes through the passing gate 41. As a result, the information stored in the normal symbol buffer indicates the number of game balls that have passed through the passing gate 41, and also indicates the value of the random number MR2-1 read in response to each passage.

Figure 10-35 is a flowchart showing an example of gate switch passing processing P_FZU_ON. Gate switch passing processing P_FZU_ON is included in the processing that can be called from the normal symbol process processing P_FPROC shown in Figure 10-33 (A), and can be executed in step AKS503 if the gate switch passing flag is on in step AKS502. When the CPU 103 executes gate switch passing processing P_FZU_ON, it sets the gate passing memory counter address using a transfer command to set a pointer (step AKS601). The gate passing memory counter address is the address of the gate passing memory counter located in the game work area of RAM 102. Next, it loads the gate passing memory counter using a transfer command to read the stored data at the address pointed to by the pointer (step AKS602).

After step AKS602, it is determined whether the count value of the gate passage memory counter is greater than or equal to the counter maximum value (step AKS603). For example, a comparison and return instruction is used to compare the value loaded in step AKS602 with a counter maximum value such as "4." If the count value is greater than or equal to the counter maximum value (step AKS603; Yes), the gate switch passage processing P_FZU_ON ends and returns to the normal symbol process processing P_FPROC. On the other hand, if the count value is less than the counter maximum value (step AKS603; No), the count value of the gate passage memory counter is updated by adding 1 (step AKS604). In this case, an arithmetic and logic operation instruction that increments the stored data at the address pointed to by the pointer makes it possible to update the count value of the gate passage memory counter by adding 1.

After step AKS604, the buffer address for the normal symbol is set by a transfer command or the like to set the pointer (step AKS605). In this case, the address of the buffer for the normal symbol with buffer number "0" provided in the game work area of RAM 102 is set to the pointer. The value loaded in step AKS602 is then added to the value stored in the pointer. This allows the address of the buffer for the normal symbol, which stores the random number MR2-1 for the normal symbol in the buffer area for the normal symbol, to be set to the pointer. Following this, the random number counter for the normal symbol is stored (step AKS606), and the gate switch passing process P_FZU_ON ends. In step AKS606, a transfer command is issued to specify the lower address of the random number counter for normal symbols in the game work area of RAM 102, and write the value read to the memory area at the address indicated by the pointer. The value of random number MR2-1 obtained from the random number counter for normal symbols can then be stored in the buffer for normal symbols.

Figure 10-36 is a flowchart showing an example of normal symbol normal processing P_FNORM. Normal symbol normal processing P_FNORM is included in the processing that can be called from normal symbol process processing P_FPROC shown in Figure 10-33 (A) and can be executed in step AKS507 when the normal symbol process code loaded in step AKS505 is 00 [H]. When executing normal symbol normal processing P_FNORM, CPU 103 loads the gate passage memory counter (step AKS621). In this case, the count value of the gate passage memory counter can be obtained by a transfer command that specifies the lower address of the gate passage memory counter in the game work area of RAM 102 and sets the value read from the counter in an internal register of CPU 103. Then, a calculation return command that returns processing when the second zero flag in the flag register of CPU 103 is on determines whether the count value of the gate passage memory counter is "0" (step AKS622). At this time, if the second zero flag is on, the count value of the gate passage memory counter is "0" (step AKS622; Yes), and the normal symbol normal processing P_FNORM ends and returns to the normal symbol process processing P_FPROC.

If the count value of the gate passage memory counter is not "0" in response to step AKS622 (step AKS622; No), a transfer command for setting a pointer is used to set the table address for setting the normal symbol per symbol (step AKS623). The table address for setting the normal symbol per symbol is the address of the table for setting the normal symbol per symbol stored in the game data area of ROM 101. Then, the buffer for normal symbol per symbol with buffer number "1" is loaded (step AKS624). In step AKS624, a transfer command is used to set the value read by specifying the lower address of the buffer for normal symbol per symbol with buffer number "1" in the game work area of RAM 102 in an internal register of CPU 103. Therefore, it is sufficient if the random number MR2-1 for the normal symbol per symbol stored in the buffer for normal symbol per symbol with buffer number "1" can be read.

When the random number MR2-1 for the normal symbol winning pattern is read in step AKS624, the second allocation judgment value comparison process P_HANTEI2 is executed (step AKS625). The value of the random number MR2-1 read in step AKS624 is set as the comparison value in the second allocation judgment value comparison process P_HANTEI2 in step AKS625, and the normal symbol winning pattern designated value indicated by the allocation result data can be determined as the display result by the normal symbol display device 20 based on the stored data of the normal symbol winning pattern setting table whose address was set in step AKS623. When the normal symbol winning pattern designated value is determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS625, the normal symbol winning pattern designated value is stored in the normal symbol buffer (step AKS626). The normal symbol buffer is located in the normal symbol control data area shown in Figure 10-34 (A) and is assigned address F040 [H]. In step AKS626, the normal symbol value is stored using a transfer command to write it to the memory area of the specified address in the game work area of RAM 102.

After step AKS626, the count value of the gate passage memory counter is decremented by 1 (step AKS627). Then, the buffer for symbols corresponding to normal symbols is shifted (step AKS628). In this case, in the buffer area for symbols corresponding to normal symbols provided in the game work area of RAM 102, the address of the buffer for symbols corresponding to normal symbols with buffer number "2" is set in the pointer specifying the transfer source. Also, the address of the buffer for symbols corresponding to normal symbols with buffer number "1" is set in the buffer pointer specifying the transfer destination. Furthermore, the number of transfers corresponding to the data size of the buffer area for symbols corresponding to normal symbols is set. Thereafter, the contents of the buffer for symbols corresponding to normal symbols are sequentially transferred and shifted using a block transfer command. At this time, the buffer for symbols corresponding to normal symbols with buffer number "4" is cleared to initialize its contents.

After step AKS628, a transfer command for setting a pointer is issued to set the address of the first normal symbol variation pattern allocation table (step AKS629). The first normal symbol variation pattern allocation table address is the address of the first normal symbol variation pattern allocation table stored in the game data area of ROM 101. Furthermore, a time-saving check process is executed to confirm that the time-saving function flag is not the time-saving activation designated value (step AKS630). At this time, if the time-saving function flag is the time-saving activation designated value (step AKS630; No), a transfer command for setting a pointer is issued to set the address of the second normal symbol variation pattern allocation table (step AKS631). The second normal symbol variation pattern allocation table address is the address of the second normal symbol variation pattern allocation table stored in the game data area of ROM 101.

If the time-saving function flag is not set to the time-saving activation value in response to step AKS630 (step AKS630; Yes), or after step AKS631, the RS3 soft latch random number register is loaded (step AKS632). In this case, the address of the RS3 soft latch random number register in the function control register area is specified, and the stored value is read and set in an internal register of CPU 103 using a transfer command, making it usable as the random number MR3-1 for the normal symbol variation pattern. Then, the second allocation judgment value comparison process P_HANTEI2 is executed (step AKS633). In the second allocation judgment value comparison process P_HANTEI2 in step AKS633, the value of the random number MR3-1 read in step AKS632 is set as the comparison value, and the normal pattern variation pattern indicated by the allocation result data can be determined using the stored data in the first normal pattern variation pattern allocation table whose address was set in step AKS629 or the second normal pattern variation pattern allocation table whose address was set in step AKS631.

Once the normal symbol variation pattern is determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS633, the normal symbol variation time corresponding to that normal symbol variation pattern is set (step AKS634). In step AKS634, a time data expansion process is executed using the normal symbol variation time table and normal symbol variation pattern designation data, making it possible to set the normal symbol variation time corresponding to the determined normal symbol variation pattern. Next, a transfer command for setting a pointer is issued to set the normal symbol variation work table address (step AKS635). The normal symbol variation work table address is the address of the normal symbol variation work table stored in the game data area of ROM 101. Next, data set process P_DATASET is executed (step AKS636), and normal symbol normal process P_FNORM is terminated. The data set processing P_DATASET in step AKS636 uses the normal pattern change work table whose address was set in step AKS635 to set the normal pattern process code to 01 [H], which is the normal pattern change processing designated value, and sets the value stored in the normal pattern change display buffer to 01 [H], which is the normal pattern change display data. In addition, the normal pattern display update timer can be initialized by clearing it.

Figure 10-37 is a diagram illustrating an example of the use of data configuration related to the normal pattern normal processing P_FNORM. In the normal pattern normal processing P_FNORM, the normal pattern per symbol designation value can be determined by executing the second allocation judgment value comparison processing P_HANTEI2 in step AKS625 using the normal symbol per symbol symbol setting table whose address was set in step AKS623. Furthermore, the normal symbol symbol variation pattern can be determined by executing the second allocation judgment value comparison processing P_HANTEI2 in step AKS633 using the first normal symbol variation pattern allocation table whose address was set in step AKS629 or the second normal symbol variation pattern allocation table whose address was set in step AKS631. In step AKS634, the normal symbol variation time table can be used to set the normal symbol variation time corresponding to the result of determining the normal symbol variation pattern. Additionally, in step AKS507 of the normal symbol process processing P_FPROC shown in Figure 10-33 (A), when the normal symbol process code corresponds to 03 [H] and the normal electric device pre-activation processing P_FINT is executed, the opening time of the normal electric device provided in correspondence with the second start winning slot can be determined using a work setting table when the normal electric device is activated, etc.

In this way, normal pattern normal processing P_FNORM makes it possible to determine the pattern designation value for a normal pattern using a table for setting patterns for normal patterns. Normal pattern normal processing P_FNORM also makes it possible to determine the normal pattern change pattern using the first normal pattern change pattern allocation table or the second normal pattern change pattern allocation table. Normal pattern normal processing P_FNORM also makes it possible to determine the normal pattern change time using the normal pattern change time table. Normal electric device pre-activation processing P_FINT, which is executed in response to the execution result of the normal game, can determine the opening time of the normal electric device.

Figure 10-37 (A) shows an example configuration AKT61 of a table for setting symbols for normal symbols. The normal symbol setting table of example configuration AKT61 stores the value 00 [H] corresponding to the first normal symbol designated value at the first address 1B54 [H], and stores the value 03 [H] indicating the number of processes at the next address 1B55 [H]. The stored data from address 1B56 [H] onwards indicates allocation judgment values corresponding to the first to third normal symbol designated values. When using the normal symbol setting table of example configuration AKT61, the second allocation judgment value comparison process P_HANTEI2 of step AKS625 can determine one of the first to third normal symbol designated values in accordance with the random number MR2-1 for the normal symbol. In the example configuration AKT61, the designated symbol value for the first normal symbol is 00 [H], the designated symbol value for the second normal symbol is 01 [H], and the designated symbol value for the third normal symbol is 02 [H]. For example, when the random number MR2-1 for the normal symbol is 00 [H], which corresponds to the minimum random number value of "0", the designated symbol value for the first normal symbol is determined.

Figure 10-37 (B1) shows an example configuration of the first normal symbol variation pattern allocation table AKT62. The first normal symbol variation pattern allocation table of the example configuration AKT62 stores the value 00 [H] corresponding to the normal symbol variation pattern FPZ1 designated value at the first address 1B59 [H], and stores the value 04 [H] indicating the number of processes at the next address 1B5A [H]. The stored data from address 1B5B [H] onwards indicates allocation judgment values corresponding to the normal symbol variation patterns FPZ1 to FPZ4. When using the first normal symbol variation pattern allocation table of the example configuration AKT62, the second allocation judgment value comparison process P_HANTEI2 of step AKS633 can determine one of the normal symbol variation patterns FPZ1 to FPZ4 in accordance with the random number MR3-1 for the normal symbol variation pattern.

Figure 10-37 (B2) shows a configuration example AKT63 of the second normal symbol variation pattern allocation table. In the second normal symbol variation pattern allocation table of configuration example AKT63, the value 04 [H] corresponding to the normal symbol variation pattern FPZ5 designated value is stored at the first address 1B5F [H], and the value 04 [H] indicating the number of processes is stored at the next address 1B60 [H]. The stored data from address 1B61 [H] onwards indicates allocation judgment values corresponding to normal symbol variation patterns FPZ5 to FPZ8. When using the second normal symbol variation pattern allocation table of configuration example AKT63, the second allocation judgment value comparison process P_HANTEI2 of step AKS633 can determine one of the normal symbol variation patterns FPZ5 to FPZ8 in accordance with the random number MR3-1 for the normal symbol variation pattern.

Figure 10-37 (C) shows normal pattern fluctuation time determination example AKD61. In determination example AKD61, the normal pattern fluctuation time is determined to be 1000 [ms] corresponding to normal pattern fluctuation patterns FZP1 to FZP4, and the normal pattern fluctuation time is determined to be 100 [ms] corresponding to normal pattern fluctuation patterns FZP5 to FZP8. In step AKS634, the normal pattern fluctuation time corresponding to the normal pattern fluctuation pattern determined by the second allocation judgment value comparison process P_HANTEI2 in step AKS633 is set. Normal pattern fluctuation patterns FZP1 to FZP4 can be determined using the first normal pattern fluctuation pattern allocation table of configuration example AKT61 when the time-saving function flag is off. Normal pattern fluctuation patterns FZP5 to FZP8 can be determined using the second normal pattern fluctuation pattern allocation table of configuration example AKT62 when the time-saving function flag is on. This makes it possible to set the normal pattern variation time, which is the variable display time of the normal pattern, to be shorter when time-saving control is in effect than when time-saving control is not in effect.

Figure 10-37 (D) shows an example of determining the normal electric feature release time AKD62. The normal electric feature activation preprocessing P_FINT can determine the normal electric feature release time in accordance with the time-saving activation designated value and the normal symbol per symbol designated value. The normal electric feature release time is determined to be 16 ms in accordance with all normal symbol per symbol designated values 00 [H] to 02 [H] when the time-saving activation designated value is set to 00 [H], corresponding to "X," indicating that the time-saving activation is not in effect. In contrast, the normal electric feature activation time is determined to be 5000 ms in accordance with all normal symbol per symbol designated values 00 [H] to 02 [H] when the time-saving activation designated value is set to 01 [H], corresponding to "○," indicating that the time-saving activation is in effect.

In this way, the normal electric device opening time can be determined to a different time corresponding to the time-saving operation designated value, regardless of the value of the normal symbol per symbol designated value. The normal symbol per symbol designated value can be determined in accordance with the random number MR2-1 for the normal symbol per symbol read from the normal symbol per symbol buffer. If the time-saving operation designated value is the same, the normal electric device operation time is determined to be the same whether the random number MR2-1 for the normal symbol per symbol is the minimum random number value of "0" or any other random number value. Therefore, in correspondence with a special symbol game, which is a variable display of normal symbols on the normal symbol display device 20, when the random number MR2-1 for the normal symbol per symbol is the minimum random number value of "0," a display result with a higher degree of advantage is not determined compared to when it is any other random number value. This makes it possible to update the random number value appropriately to prevent fraudulent activity due to a malfunction in the second random number value when the random number MR2-1 for the normal winning symbol is used as the second random number value.

In the game control microcomputer 100 shown in FIG. 10-1, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can update the numerical data indicating the values of the random numbers included in the game random numbers, such as the random number MR1-1 for determining a special symbol, the random number MR3-2 for selecting a losing effect, the random number MR3-3 for selecting a variation pattern type, the random number MR3-4 for a variation pattern, and the random number MR3-1 for a normal symbol variation pattern. Furthermore, by executing the random number update process P_RANDOM shown in FIG. 10-12, the CPU 103 can update the numerical data indicating the values of the random numbers included in the game random numbers, such as the random number MR1-2 for a winning symbol, the random number MR1-3 serving as the initial value for a winning symbol, the random number MR2-1 for a normal winning symbol, and the random number MR2-2 serving as the initial value for a normal winning symbol.

When the special symbol determination process P_TDECISION shown in FIG. 10-20 is executed in step AKS248 of the normal special symbol processing shown in FIG. 10-18, the special symbol big win determination process in step AKS304 and the special symbol small win determination process in step AKS305 can use the special symbol determination random number MR1-1 to determine whether the special symbol display result is a "big win" or a "small win." Then, when the special symbol information setting process P_TZU_SET shown in FIG. 10-22 is executed in step AKS308 of the special symbol determination process P_TDECISION, the jackpot information data selection process P_TFVR_ZU in step AKS326 or step AKS333 can use the winning symbol random number MR1-2 to determine the jackpot symbol designation value or small win symbol designation value corresponding to the confirmed special symbol that results in the special symbol display. In addition, when the second allocation judgment value comparison process P_HANTEIS is executed in step AKS625 of the normal pattern normal processing shown in Figure 10-36, it becomes possible to determine the normal pattern winning symbol designated value corresponding to the confirmed normal pattern that will be the display result of the normal pattern using the random number MR2-1 for the normal pattern winning symbol. The jackpot symbol designated value determined using the random number MR1-2 for the winning symbol makes it possible to set the maximum number of times the large prize opening hole is opened in step AKS330 of the special pattern information setting process P_TZU_SET, as in the example AKD01 of determining the maximum number of times the large prize opening hole is opened shown in Figure 10-24 (C). The normal winning symbol designation value determined using the normal winning symbol random number MR2-1 enables the setting of the normal electric device opening time, as shown in the normal electric device opening time determination example AKD62 shown in FIG. 10-37(D), when the normal symbol process code corresponds to 03[H] and the normal electric device pre-activation process P_FINT is executed in step AKS507 of the normal symbol process processing P_FPROC shown in FIG. 10-33(A). Therefore, the winning symbol random number MR1-2 is used to determine the display results of the first special symbol display device 4A and the second special symbol display device 4B, enabling the setting of the type of jackpot game state advantageous to the player. The normal winning symbol random number MR2-1 is used to determine the display results of the normal symbol display device 20, enabling the setting of a change mode that changes the second starting winning hole, which serves as the starting area, to a guidance state that makes it easier for the game ball to pass through.

In this way, game control-related processing can be performed using random number values that serve as various gaming random numbers. The random number MR1-2 for the winning symbol, which serves as the first random number value, and the random number MR2-1 for the winning normal symbol, which serves as the second random number value, can be updated within their respective update ranges using a common update process, such as the initial value change random number update process P_RANCP, which can be called and executed by the random number update process P_RANDOM shown in Figures 10-12. Here, the update range for the random number MR2-1 for the winning normal symbol is "0" to "198," and the total number of random numbers included in the update range is "199," so the total number of random numbers included in the update range is a prime number. Therefore, for at least one of the first and second random number values that can be updated using the common update process, the total number of random number values included in the update range is a prime number. In this way, the shared update process prevents an increase in program size, and the total number of random numbers included in the update range is a prime number, which suppresses the occurrence of random number synchronization and enables appropriate random number updates.

The random number MR1-2 for the winning symbol, which serves as the first random number value, has an update range of "0" to "199," and the total number of random numbers included in the update range is "200," meaning that the total number of random numbers included in the update range is not a prime number. The random number MR1-2 for the winning symbol is used to determine the jackpot symbol designation value for the fixed special symbol, and the jackpot symbol designation value may determine whether or not a special state will be entered after the jackpot gaming state ends. In this case, the determination rate of the jackpot symbol designation value corresponds to the special state entry rate, which is the rate at which the special state is entered. The special state entry rate is included in important specifications of the pachinko gaming machine 1, and it is desirable for it to be a value that is clearly recognizable. However, if the total number of random numbers included in the update range of the winning symbol MR1-2 is a prime number, the denominator of the special state entry rate will be a prime number, making it difficult to express as a percentage, and thus potentially making the special state entry rate difficult to recognize. Therefore, of the random numbers MR1-2 for winning symbols and MR2-1 for normal winning symbols, which can be updated using a common update process, the total number of random numbers included in the update range for the normal winning symbols MR2-1 may be a prime number, while the total number of random numbers included in the update range for the winning symbols MR1-2 may not be a prime number. This makes it possible to appropriately update the random numbers so that the specifications of the pachinko gaming machine 1 can be clearly recognized while suppressing the occurrence of synchronization in the random numbers.

The total number of random numbers included in the update range for the winning symbol random number MR1-2, which serves as the first random number value, may also be a prime number. This more reliably prevents the synchronous occurrence of random number values that can be updated using a common update process, enabling appropriate random number value updates.

In the random number update process P_RANDOM shown in Figure 10-12, steps AKS61 to AKS64 can update random number MR1-2, which becomes the first random number value, and steps AKS65 to AKS68 can update random number MR2-1, which becomes the second random number value. The random number update process P_RANDOM can update random number MR1-2, which becomes the first random number value, and random number MR2-1, which becomes the second random number value, using the HL register, B register, and DE register of CPU 103, which are shared internal storage means. In this way, the first random number value and second random number value can be stably updated using the shared internal storage means, enabling appropriate random number value updates.

The CPU 103 executing the random number update process P_RANDOM shown in Figures 10-12 serves as a first update means capable of updating the first and second random number values within their respective update ranges through the random number update process when the random number MR1-2 for the winning symbol is set as the first random number value and the random number MR2-1 for the winning normal symbol is set as the second random number value. Furthermore, the 16-bit random number circuit 104A and the 8-bit random number circuit 104B serve as second update means capable of updating the third and fourth random number values within their respective update ranges through a system clock input that serves as a random number clock signal when the third and fourth random number values are set from among the random number MR1-1 for determining a special symbol, the random number MR3-2 for selecting a losing effect, the random number MR3-3 for selecting a variation pattern type, and the random number MR3-4 for a variation pattern. For example, the random number MR2-1 for the normal winning symbol has an update range of "0" to "198", and the total number of random numbers included in the update range is "199", so the total number of random numbers included in the update range of the second random number is a prime number. In contrast, for example, the random number MR3-2 for selecting a losing effect has an update range of "0" to "65518", and the total number of random numbers included in the update range is "65519", the random number MR3-3 for selecting a variation pattern type has an update range of "0" to "240", and the total number of random numbers included in the update range is "241", and the random number MR3-4 for the variation pattern has an update range of "0" to "250", and the total number of random numbers included in the update range is "251", so the total number of random numbers included in the update range of at least one of the third random number and the fourth random number is a prime number. In this way, the update methods used by the first update means and the second update means are different, and even if the update methods are the same, the total number of random number values included in the update range for at least one of the means is a prime number, thereby suppressing synchronization and enabling appropriate random number updating.

The 16-bit random number circuit 104A and the 8-bit random number circuit 104B function as first update means capable of updating the first and second random number values by a system clock input that serves as a random number clock signal when the first and second random number values are set from among the random number MR1-1 for determining a special symbol, the random number MR3-2 for selecting a losing effect, the random number MR3-3 for selecting a variation pattern type, and the random number MR3-4 for a variation pattern. The CPU 103, which executes the random number update process P_RANDOM shown in Figure 10-12, functions as second update means capable of updating the third random number value by the random number update process when the third random number value is set from among the random number MR1-2 for a winning symbol and the random number MR2-1 for a normal or winning symbol. When the CPU 103 executes the main processing P_MAIN for game control shown in FIG. 4 upon the start of power supply to the pachinko gaming machine 1, it executes the power supply start response processing P_POWER_ON shown in FIG. 10-7 in step S1. Then, it sets a stored value in the function setting register area by a function setting register store instruction in step AKS13. At this time, by setting a stored value in a maximum value setting register provided corresponding to the 16-bit random number circuit 104A or the 8-bit random number circuit 104B, it is possible to execute a maximum value setting process that sets the maximum random number value of the random number value updated by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B. Then, in the maximum value setting process, the 16-bit random number circuit 104A or the 8-bit random number circuit 104B, which serves as the first updating means, starts updating the first random number when the maximum random number value of the first random number is set, and then starts updating the second random number when the maximum random number value of the second random number is set. After executing the power supply start response process P_POWER_ON in step S1, the CPU 103 executing the game control main process P_MAIN shown in FIG. 4 becomes able to execute the game control timer interrupt process P_PCT shown in FIG. 5 in response to the occurrence of a timer interrupt while executing the loop process of steps S8 to S11, and starts updating the third random number value by executing the random number update process P_RANDOM in step S56. In this way, the CPU 103 executing the random number update process P_RANDOM, which serves as the second updating means, is able to update the third random number value after executing the maximum value setting process in the power supply start response process P_POWER_ON. Therefore, by starting the update of a random number value highly related to game value, such as the random number MR1-1 used to determine special symbols, first, uncertainty is increased, enabling appropriate random number value updates.

In the bit data RAP of the RWM access protect register shown in Figure 10-9 (B), bit data RAM0 with bit number "0" is set to its initial value of 0 [B] in response to the start of power supply to the pachinko gaming machine 1. As a result, access to RAM 102, which serves as the RWM, is prohibited in response to the storage value of the RWM access protect register, which is a specific storage area, being set to the first storage value. After executing the power supply start response processing P_POWER_ON shown in Figure 10-7, the CPU 103 sets the storage value of the function setting register area using the function setting register store instruction in step AKS13, and then stores the access permission output value in the RWM access protect register in step AKS14. In this way, after setting the storage value in the function setting register area, which is a storage area related to functions, a second storage value that permits access to RAM 102 as a storage means can be set in the RWM access protect register, which is a specific storage area. Then, as the next process after setting the second stored value, the RWM check process P_RWM_CHK in step S2 of the main game control process P_MAIN shown in Figure 4 can be executed to perform a confirmation process to check whether the control state can be restored based on the contents stored in RAM 102, which is the storage means. In this way, the contents stored in the storage means are not changed unnecessarily, allowing the confirmation process to be executed reliably and the random number value to be updated appropriately.

The CPU 103 executing the power-off processing P_POWER_OFF shown in FIG. 10-10 stores the checksum data created by the checksum calculation processing P_SUM_CALC in step AKS39 in the checksum buffer in step AKS40, thereby executing a stop-time storage process in which the checksum data, which serves as recovery information for restoring the control state in response to a power supply interruption, is stored in a storage area such as the checksum buffer of the storage means, RAM 102. After such stop-time storage processing is executed, the clear data set in the output value data in step AKS41 is stored in the RWM access protection register in step AKS42, thereby executing a stop-time storage process in which the first storage value is set in a specific storage area. After the stop-time storage processing is executed, the loop processing of steps AKS48 and AKS49 transitions to a standby state in which game control is not executed. In response to the power supply being restored during this standby state, if the power confirmation signal input bit is not "0" in step AKS49, the power recovery vector table address is set to the stack pointer in step AKS50, and then the power-off processing P_POWER_OFF is terminated by an interrupt return command, allowing the game control main processing P_MAIN shown in Figure 4 to be executed from the beginning as startup processing based on the startup of the pachinko gaming machine 1. This prevents unstable operation when the power supply is restored and enables appropriate random number values to be updated.

In the address map of the game control microcomputer 100 shown in Figure 10-2, the function setting register area of the built-in register assigned addresses FE00[H] to FEBF[H] is the first area for setting functions using the various circuits included in the game control microcomputer 100, and the function control register area of the built-in register assigned addresses FF00[H] to FFFF[H] is the second area for controlling functions using the various circuits included in the game control microcomputer 100. Of these, the RWM access protection register at address FF00[H] is a specific storage area in which a storage value indicating whether or not to allow access to the RWM RAM 102 can be set. When power supply to the pachinko gaming machine 1 is started, the CPU 103, which executes the game control main process P_MAIN shown in FIG. 4, executes the power supply start response process P_POWER_ON shown in FIG. 10-7 in step S1. This process can then execute steps AKS5 through AKS7 for control storage, which sets a value stored in the function control register area, which is the second area. After this control storage process is executed, steps AKS11 through AKS13 for setting a value stored in the function setting register area, which is the first area. After this setting storage process is executed, step AKS14 can set a value that permits access to the RAM 102, which is the storage means, in the RWM access protection register, which is the specific storage area. This prevents unauthorized changes to the contents of the storage means and enables appropriate random number updates.

(Means for solving the problems and effects of characteristic part 01AK)
(1-1) A gaming machine that can be controlled to an advantageous state that is advantageous to a player,
An update means capable of updating the random value;
a first display means capable of variably displaying special identification information;
and a second display means capable of variably displaying the normal identification information,
a type of advantageous state is determined in accordance with the display result by the first display means;
A change mode for changing the start area into a guidance state in which the game medium can easily pass through is determined in accordance with the display result by the second display means;
The update method is
the first random number used to determine the display result by the first display means and the second random number used to determine the display result by the second display means can be updated within their respective update ranges by a common update process;
The first random number value and the second random number value can be updated using a common internal storage means;
The first random number is the number of random numbers included in the update range that is not a prime number.
The total number of random values included in the update range of the second random value is a prime number.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The update means may be, for example, a CPU 103 that executes a random number update process P_RANDOM. The special identification information may be, for example, a special symbol. The first display means may be, for example, a first special symbol display device 4A and a second special symbol display device 4B. The normal identification information may be, for example, a normal symbol. The second display means may be, for example, a normal symbol display device 20. The display result by the first display means may be, for example, a confirmed special symbol that results in the display of a special symbol. The display result by the second display means may be, for example, a confirmed normal symbol that results in the display of a normal symbol. The type of advantageous state may be, for example, the maximum number of times the big prize opening is opened. The change mode may be, for example, the opening time of a normal electric device. The first random number value may be, for example, a random number MR1-2. The second random number value may be, for example, a random number MR2-1. The update process may be, for example, the initial value change random number update process P_RANCP. The internal storage means may be, for example, the HL register, B register, or DE register of the CPU 103. The total number of first random numbers may be, for example, "65536" for the random number MR1-2. The total number of second random numbers may be, for example, "199" for the random number MR2-1.
With this configuration, the common update process prevents an increase in program capacity, and since the total number of random number values included in the update range is a prime number, synchronization between the first random number value and the second random number value is suppressed, making it possible to update the random number values appropriately.

(1-2) When executing the update process, the update means may be capable of updating the random number value to be updated and changing the initial random number value after setting the random number value to be updated, the maximum random number value, and the initial random number value.
Here, the setting for executing the update process may be, for example, steps AKS61 to AKS63 and AKS65 to AKS67. The update of the random number value to be updated and the change of the initial value of the random number may be, for example, the part that executes the initial value change random number update process P_RANCP in steps AKS64 and AKS68.
In such a configuration, it is possible to update the random number values appropriately by updating the set random number values to be updated.

(1-3) The updating means may update the second random number value after updating the first random number value through the specific updating process.
Here, the specific update process may be, for example, a random number update process P_RANDOM.
In such a configuration, by updating the first random number value, which is used to determine the display result that attracts the player's attention, before the second random number value, the occurrence of malfunctions is suppressed and appropriate random number value updates are possible.

(1-4) The update means may be capable of updating the first random number value and the second random number value and changing the initial values of the first random number value and the second random number value by calling a common update process corresponding to the first random number value and the second random number value through the specific update process.
Here, the common update process may be, for example, the initial value change random number update process P_RANCP of steps AKS64 and AKS68 in the random number update process P_RANDOM.
In such a configuration, the common update process prevents an increase in program capacity, and the first random number value and the second random number value are stably updated, making it possible to update the random number value appropriately.

(1-5) The update means may be capable of updating the first random number value and the second random number value by a specific update process using a common internal storage means.
For example, in the random number update process P_RANDOM, the HL register is set by steps AKS61 and AKS65, the B register is set by steps AKS62 and AKS66, and the DE register is set by steps AKS63 and AKS67, and then the initial value change random number update process P_RANCP is executed by steps AKS64 and AKS68.
In such a configuration, the first random number value and the second random number value are stably updated using a common internal storage means, making it possible to update the random number values appropriately.

(1-6) When the specific update process stores the reference information in the internal storage means before the common update process, the update means may be capable of setting different reference information in the internal storage means using a common instruction corresponding to the first random number value and the second random number value.
Here, the internal storage means may be, for example, an HL register, a B register, a DE register, etc. The common instruction may be a transfer instruction such as an LD instruction or an LDQ instruction. The different reference information may be, for example, the address F081 [H] of the random number counter for the winning symbol and the address F052 [H] of the random number counter for the normal winning symbol, or the address F050 [H] of the random number initial value data buffer for the winning symbol and the address F053 [H] of the random number initial value data buffer for the normal winning symbol.
In such a configuration, by making it possible to update the first random number value and the second random number value using a common instruction, it becomes possible to stably update the first random number value and the second random number value, thereby updating the random number value appropriately.

(1-7) When executing the update process, the update means updates the random number value to be updated, and then changes the random number initial value in response to the random number value to be updated matching the random number initial value.
For example, in the initial value change random number update process P_RANCP, after updating the random number value to be updated in step AKS101, a new random number initial value is stored in step AKS108 in response to the value matching the value stored in the random number initial value data buffer in step AKS105.
In such a configuration, it is possible to update the random number values appropriately by updating the random number values to be updated and changing the initial random number values.

(1-8) When the update means executes the update process to update the random number value to be updated,
Comparing the random number value to be updated with the maximum random number value;
If the comparison result is less than the maximum random number value, add 1 to the random number value to be updated.
A single compare and add instruction may be executed first, which includes changing the random number value to be updated to the minimum random number value if the comparison result is greater than or equal to the maximum random number value.
Here, the compare and add instruction may be, for example, the part of step AKS101.
In such a configuration, by executing the compare and add instruction first, it is possible to suppress the occurrence of malfunctions and update the random number values appropriately.

(1-9) The updating means may first execute a compare and add instruction in both cases of updating the first random number value and updating the second random number value.
For example, it may be step AKS101 in the initial value change random number update process P_RANCP of steps AKS64 and AKS68.
In such a configuration, by executing the compare and add instruction first, it is possible to suppress the occurrence of errors in the first random number value and the second random number value, and to update the random number value appropriately.

(1-10) When determining the display result by the first display means, when the first random number value is the minimum random number value, the display result is not determined to be more advantageous than when the first random number value is other than the minimum random number value;
When determining the display result by the second display means, when the second random number value is the minimum random number value, the display result may not be determined to be more advantageous than when the second random number value is other than the minimum random number value.
Here, the display result that is not determined to have a high degree of advantage may be, for example, example AKD01 of determining the number of times the large prize opening is to be performed or example AKD02 of determining the mode of the large prize opening.
In such a configuration, it is possible to appropriately update the random number values so as to prevent fraudulent acts due to defects in the first random number values or the second random number values.

(1-11) The update means is
An initial value update process can be executed to update the initial random value used when changing the initial random value;
After executing the compare and add instruction, the random number value to be updated after the compare and add instruction is compared with the initial random number value;
If the updated random number value does not match the initial random number value, store the updated random number value as the current random number value.
If the updated random number value to be updated matches the random number initial value, the initial value random number value obtained by the initial value update process may be stored as the current random number value and also as a new random number initial value.
Here, the random number value for the initial value may be, for example, random number MR1-3 or random number MR2-2. The initial value update process may be, for example, random number update process P_TFINIT for determining initial value. The comparison with the random number initial value may be, for example, in step AKS105. If it does not match the random number initial value, it may be, for example, in the case of Yes in step AKS105. If it matches the random number initial value, it may be, for example, in the case of No in step AKS105, in steps AKS106 to AKS108.
In such a configuration, the uncertainty of the random number value is increased by setting a new initial value for the random number, and by storing it as the current random number value, an increase in data volume is prevented, and the random number value can be updated appropriately.

(1-12) The update means is
a first initial value update process for updating a first initial value random number value used when changing the random number initial value in response to a case where the random number value to be updated is a first random number value;
In the case where the random number value to be updated is a second random number value, it may be possible to execute an initial value update process that includes a second initial value update process that updates a random number value for a second initial value that is used when changing the random number initial value.
Here, the first random number value for initial values may be, for example, random number MR1-3. The first initial value update process may be, for example, steps AKS81 and AKS82 in the initial value determination random number update process P_TFINIT. The second random number value for initial values may be, for example, random number MR2-2. The second initial value update process may be, for example, steps AKS83 and AKS84 in the initial value determination random number update process P_TFINIT.
In such a configuration, the random number values can be updated appropriately by updating the first initial value random number values and the second initial value random number values.

(1-13) The updating means may update the second random number value for the initial value after updating the first random number value for the initial value through the initial value updating process.
For example, in the initial value determination random number update process P_TFINIT, steps AKS83 and AKS84 may be executed after steps AKS81 and AKS82.
In such a configuration, by updating the random number value for the first initial value, which has a higher priority, before the random number value for the second initial value, which has a lower priority, the occurrence of malfunctions is suppressed, and appropriate random number value updates are possible.

(1-14) When executing the initial value update process, the update means performs the following based on the settings regarding the random number value for the initial value to be updated and the maximum value of the random number for the initial value:
comparing the random number value for the initial value to be updated with the maximum random number value for the initial value;
If the comparison result is less than the maximum value of the initial value random number, add 1 to the initial value random number to be updated.
A single compare and add instruction may be executed, which includes changing the initial value random number value to be updated to the minimum random number value if the comparison result is equal to or greater than the initial value random number maximum value.
Here, the compare and add instruction may be, for example, the part of steps AKS82 and AKS84.
In such a configuration, by updating the random number value for the initial value to be updated using a compare and add instruction, it is possible to prevent the occurrence of problems and update the random number value appropriately.

(1-15) The update means is
A random number update process capable of updating the random number value to be updated;
An initial value random number update process that can update the initial value random number used when changing the random number initial value corresponding to the random number value to be updated;
The first process executable in response to a timer interrupt due to the lapse of a predetermined time includes a random number update process and an initial value random number update process,
The second process that can be repeatedly executed until the first process is executed may not include the random number update process, but may include the initial value random number update process.
Here, the random number value to be updated may be, for example, random number MR1-2 or random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number value for initial value may be, for example, random number MR1-3 or random number MR2-2. The random number update process for initial value may be, for example, random number update process P_TFINIT for initial value determination. The first process may be, for example, timer interrupt process P_PCT for game control. The second process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the initial value random number updating process increases the uncertainty of the initial value random number, making it possible to update the random number appropriately.

(1-16) The update process is
A random number update process capable of updating the random number value to be updated;
An initial value random number update process capable of updating the initial value random number used when changing the random number initial value corresponding to the random number value to be updated,
The random number update process and the initial value random number update process can be called and executed in the timer interrupt process that controls the progress of the game.
The initial value random number update process may be called and executed during standby processing that is repeated after startup processing that is executed based on the start of power supply.
Here, the random number value to be updated may be, for example, random number MR1-2 or random number MR2-1. The random number update process may be, for example, random number update process P_RANDOM. The random number value for initial value may be, for example, random number MR1-3 or random number MR2-2. The random number update process for initial value may be, for example, random number update process for initial value determination P_TFINIT. The timer interrupt process may be, for example, timer interrupt process P_PCT for game control. The startup process may be, for example, steps S1 to S7 in the main process P_MAIN for game control. The standby process may be, for example, steps S8 to S10 in the main process P_MAIN for game control.
In such a configuration, the initial value random number updating process increases the uncertainty of the initial value random number, making it possible to update the random number appropriately.

(2-1) A gaming machine that can be controlled to an advantageous state that is advantageous to a player,
An update means capable of updating the random value;
processing means for executing processing relating to game control using the random number value updated by the updating means;
the updating means is capable of updating a first random number value for determining whether or not to control to an advantageous state and a second random number value different from the first random number value;
The first random value is composed of a specific number of bytes, and the total number of random values included in the update range is a specific number,
The second random number value is a predetermined number that is composed of a specific number of bytes, and the total number of random numbers included in the update range is smaller than the specific number,
The first random number value may be updated faster than the second random number value.
Here, the advantageous state may be, for example, a jackpot gaming state. The gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or the like. The processing means may be, for example, a CPU 103 that executes special symbol process processing P_TPROC, or the like. The first random number value may be, for example, a random number MR1-1. The second random number value may be, for example, a random number MR3-2, or the like. The specific number of bytes may be, for example, 2 bytes. The specific number may be, for example, "65536", which is the size of the random number MR1-1. The predetermined number may be, for example, "65519", which is the size of the random number MR3-2. A fast update speed means that, for example, the update speed of the random number MR1-1 in the comparative random number value AKA23 is 15,000 times/ms and the update speed of the random number MR3-2 is 469 times/ms.
In such a configuration, it is possible to update the random number value appropriately so that intentional control of the advantageous state becomes difficult due to a fast update speed of the first random number value related to the advantageous state.

(2-2) A gaming machine capable of playing games,
An update means capable of updating the random value;
processing means for executing processing relating to game control using the random number value updated by the updating means;
the updating means is capable of updating a first random number value and a second random number value different from the first random number value;
The first random value is updated at a first rate,
The second random number value is a second speed at which the update speed is an integer multiple of the first speed,
The total number of random values included in the update ranges of the first random value and the second random value may be different, and the total number of random values included in both update ranges may be prime numbers.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A or an 8-bit random number circuit 104B. The processing means may be, for example, a CPU 103 that executes the special symbol process P_TPROC. The first random number value may be, for example, random number MR3-2. The second random number value may be, for example, random numbers MR3-3, MR3-4. The first speed may be, for example, 469 times/ms. The second speed may be, for example, 938 times/ms. The total number of random numbers may be, for example, "65519," which is the size of random number MR3-2, "241," which is the size of random number MR3-3, and "251," which is the size of random number MR3-4.
In such a configuration, even if the update speed becomes an integer multiple, the total number of random number values included in the update range is a different prime number, thereby suppressing synchronization between the first random number value and the second random number value, thereby enabling appropriate updating of the random number values.

(2-3) A gaming machine capable of playing games,
An update means capable of updating the random value;
processing means for executing processing relating to game control using the random number value updated by the updating means;
the updating means is capable of updating a first random number value, a second random number value different from the first random number value, and a third random number value different from the first random number value and the second random number value;
The processing means is capable of extracting the first random number value, the second random number value, and the third random number value when a common extraction condition is satisfied;
The first random value is updated at a first rate,
the second random number and the second random number are a second speed at which the update speed is an integer multiple of the first speed,
The total number of random numbers included in each update range may be different for the first random number value, the second random number value, and the third random number value, and the total number of random numbers included in each update range may be a prime number.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a 16-bit random number circuit 104A or an 8-bit random number circuit 104B. The processing means may be, for example, a CPU 103 that executes the special symbol process P_TPROC. The first random number value may be, for example, a random number MR3-2. The second random number value may be, for example, a random number MR3-3. The third random number value may be, for example, a random number MR3-4. The first speed may be, for example, 469 times/ms. The second speed may be, for example, 938 times/ms. The total number of random numbers may be, for example, "65519," which is the size of random number MR3-2, "241," which is the size of random number MR3-3, and "251," which is the size of random number MR3-4.
In such a configuration, even if the update speed becomes an integer multiple, the total number of random numbers included in the update range is a different prime number, thereby suppressing synchronization between the first random number value, the second random number value, and the third random number value, thereby enabling appropriate updating of the random number values.

(2-4) A gaming machine capable of playing games,
An update means capable of updating the random value;
processing means for executing processing relating to game control using the random number value updated by the updating means;
The update method is
a first updating means for updating the first random number value and the second random number value within their respective update ranges by a random number updating process;
a second updating means for updating the third random number value and the fourth random number value within their respective update ranges using a random number clock signal;
At least one of the first random number value and the second random number value is such that the total number of random number values included in the update range is a prime number;
At least one of the third random number value and the fourth random number value may be such that the total number of random number values included in the update range is a prime number.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The update means may be, for example, a 16-bit random number circuit 104A, an 8-bit random number circuit 104B, or a CPU 103 that executes a random number update process P_RANDOM. The processing means may be, for example, a CPU 103 that executes a special symbol process process P_TPROC or a normal symbol process process P_FPROC. The first random number value may be, for example, a random number MR2-1. The second random number value may be, for example, a random number MR1-2. The random number update process may be, for example, a random number update process P_RANDOM. The third random number value may be, for example, a random number MR3-3. The fourth random number value may be, for example, a random number MR3-4. The random number clock signal may be, for example, a system clock. The total number of random numbers included in the update range may be, for example, "199", which is the size of random number MR2-1, "200", which is the size of random number MR1-2, "241", which is the size of random number MR3-3, and "251", which is the size of random number MR3-4.
In such a configuration, the first update means and the second update means use different update methods, and even if the update methods are the same, the total number of random number values included in the update range of at least one of the means is a prime number, thereby suppressing the occurrence of synchronization and enabling appropriate updating of the random number values.

(3-1) A gaming machine capable of playing games,
An update means capable of updating the random value;
processing means for executing processing relating to game control using the random number value updated by the updating means;
a storage means including a storage area relating to the functions of the updating means and the processing means;
the processing means is capable of executing a maximum value setting process for setting a maximum value of the random numbers updated by the update means when a storage value is set in a storage area related to a function by a startup process executed based on the start of power supply;
The update method is
a first updating means capable of updating a first random number value consisting of a specific number of bytes;
a second updating means capable of updating a second random number value that is configured with a predetermined number of bytes that is smaller than the specific number of bytes,
When executing the maximum value setting process, the processing means may set the maximum random number value for the first random number value and then set the maximum random number value for the second random number value.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a random number circuit 104. The processing means may be, for example, a CPU 103 that executes the special symbol process P_TPROC. The storage area related to the function may be, for example, a function setting register area of setting example AKA01 or a function control register area of setting example AKA02. The storage means may be, for example, an internal register of the gaming control microcomputer 100. The startup processing may be, for example, the main processing P_MAIN for gaming control. The maximum value setting processing may be, for example, steps AKS11 to AKS13 in the power supply start response processing P_POWER_ON. The specific number of bytes may be, for example, 2 bytes. The first random number value may be, for example, the random number MR3-2. The first updating means may be, for example, a 16-bit random number circuit 104A. The predetermined number of bytes may be, for example, 1 byte. The second random number value may be, for example, random numbers MR3-3, MR3-4, etc. The second updating means may be, for example, an 8-bit random number circuit 104B, etc. Setting the maximum random number value for the first random number value and setting the maximum random number value for the second random number value may be performed by executing step AKS13 using the function setting register stored value table AKT01, etc.
In such a configuration, by setting a first random number value of a specific number of bytes and then setting a second random number value of a predetermined number of bytes, the first random number value and the second random number value can be stably updated, making it possible to update the random number values appropriately.

(3-2) The updating means may start updating the random numbers in order from the random number for which the maximum random number value is set.
For example, it may be a part that uses the function setting register storage value table AKT01 to set maximum values for the 16-bit random number circuit channel RL0 with channel number "0", the 16-bit random number circuit channel RL2 with channel number "2", and the 8-bit random number circuit channels RS1 to RS3 with channel numbers "1" to "3".
In such a configuration, the uncertainty of the random number value is increased depending on the timing at which the update of the random number value is started, reducing the processing load and enabling appropriate updating of the random number value.

(3-3) A gaming machine capable of playing games,
An update means capable of updating the random value;
processing means for executing processing relating to game control using the random number value updated by the updating means;
a storage means including a storage area relating to the functions of the updating means and the processing means;
the processing means is capable of executing a maximum value setting process for setting a maximum value of the random numbers updated by the update means when a storage value is set in a storage area related to a function by a startup process executed based on the start of power supply;
The update method is
a first updating means capable of updating the first random number value and the second random number value by a random number clock signal;
a second updating means capable of updating the third random number value by a random number updating process;
the first updating means, in the maximum value setting process executed by the processing means, starts updating the first random number value when the maximum random number value of the first random number value is set, and then starts updating the second random number value when the maximum random number value of the second random number value is set;
The second updating means may start updating the third random number value after the processing means has executed the maximum value setting process.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The updating means may be, for example, a random number circuit 104 or a CPU 103 that executes random number update processing P_RANDOM. The processing means may be, for example, a CPU 103 that executes special symbol process processing P_TPROC or normal symbol process processing P_FPROC. The storage area related to the function may be, for example, a function setting register area of setting example AKA01 or a function control register area of setting example AKA02. The storage means may be, for example, an internal register of the gaming control microcomputer 100. The startup processing may be, for example, a main processing P_MAIN for gaming control. The maximum value setting processing may be, for example, steps AKS11 to AKS13 in the power supply start response processing P_POWER_ON. The first random number value may be, for example, random numbers MR1-1, MR3-2, etc. The second random number value may be, for example, random numbers MR3-3, MR3-4, etc. The first updating means may be, for example, a 16-bit random number circuit 104A or an 8-bit random number circuit 104B. The third random number value may be, for example, random numbers MR1-2 or MR2-1. The random number updating process may be, for example, the random number updating process P_RANDOM. The second updating means may be, for example, the CPU 103 that executes the random number updating process P_RANDOM in step S56. The updating of the first random number value may be initiated, for example, by setting maximum values for the 16-bit random number circuit channel RL0 with channel number "0" and the 16-bit random number circuit channel RL2 with channel number "2" using the function setting register stored value table AKT01. The updating of the second random number value may be initiated, for example, by setting maximum values for the 8-bit random number circuit channels RS1 to RS3 with channel numbers "1" to "3" using the function setting register stored value table AKT01. The updating of the third random number value may be started, for example, at the part where the random number update processing P_RANDOM of step S56 is executed in the timer interrupt processing P_PCT for game control after the power supply start response processing P_POWER_ON of step S1 is executed.
In such a configuration, by starting the update of random numbers such as MR1-1, which have a high correlation with the gaming value, first, uncertainty is increased, and appropriate random number values can be updated.

(4-1) a storage means capable of storing information related to game control;
a storage means including a storage area relating to the functions of the updating means and the processing means;
a specific storage area among the storage areas relating to the function can be set to a first storage value that prohibits access to the storage means in response to the start of power supply;
The processing means is
After setting a storage value in the storage area related to the function, a second storage value that allows access to the storage means can be set in the specific storage area;
As a next process after the second storage value is set in the specific storage area, a confirmation process may be executed to confirm whether or not the control state can be restored based on the stored contents of the storage means.
Here, the storage means may be, for example, RAM 102. The storage area related to the function may be, for example, the function setting register area of setting example AKA01 or the function control register area of setting example AKA02. The storage means may be, for example, an internal register of the game control microcomputer 100. The specific storage area may be, for example, an RWM access protection register. The first storage value may be, for example, 00 [H]. The second storage value may be, for example, 01 [H]. The second storage value may be set in the specific storage area by, for example, executing step AKS14 in the power supply start response processing P_POWER_ON. The confirmation processing may be, for example, the RWM check processing P_RWM_CHK of step S2.
In this configuration, the contents stored in the storage means are prevented from being changed unnecessarily, so that the confirmation process can be executed reliably and the random number value can be updated appropriately.

(4-2) The processing means is
In response to the power supply interruption, a stoppage storage process can be executed to store recovery information for restoring the control state in the storage means,
After the stop-time storage process is executed, a stop-time storage process can be executed to set the first storage value in the specific storage area,
After the stop storage process is executed, the machine may be shifted to a standby state in which game control is not executed, and in response to the power supply being restored while the machine is in the standby state, the start-up process based on the start-up of the game machine may be executed from the beginning.
The recovery information may be, for example, checksum data. The stop storage process may be, for example, the checksum calculation process of step AKS39 or step AKS40 in the power-off process P_POWER_OFF. The stop storage process may be, for example, steps AKS41 and AKS42 in the power-off process P_POWER_OFF. The transition to the standby state may be, for example, the execution of steps AKS48 and AKS49 in the power-off process P_POWER_OFF. The executable process from the beginning of the startup process may be, for example, the execution of step AKS50 in the power-off process P_POWER_OFF and then the execution of the RET command.
In such a configuration, when the power supply is restored, unstable operation can be prevented and the random number values can be updated appropriately.

(4-3) a storage means capable of storing information related to game control;
a storage means including a storage area relating to the functions of the updating means and the processing means;
The storage means includes, as a storage area relating to functions,
a first area for setting functions;
a second area for function control;
the second area includes a specific storage area in which a storage value indicating whether or not access to the storage means is permitted can be set;
The processing means performs a startup process based on the start of power supply,
A control storage process for setting a storage value in the second area can be executed;
After the control storage process is executed, a setting storage process can be executed to set a storage value in the first area,
After the setting storage process is executed, a storage value that allows access to the storage means may be set in the specific storage area.
Here, the storage means may be, for example, RAM 102. The storage area related to the function may be, for example, the function setting register area of setting example AKA01 or the function control register area of setting example AKA02. The storage means may be, for example, an internal register of the game control microcomputer 100. The first area may be, for example, the function setting register area of setting example AKA01. The second area may be, for example, the function control register area of setting example AKA02. The specific storage area may be, for example, an RWM access protection register. The startup processing may be, for example, the main processing P_MAIN for game control. The control storage processing may be, for example, steps AKS5 to AKS7 in the power supply start response processing P_POWER_ON. The setting storage processing may be, for example, steps AKS11 to AKS13 in the power supply start response processing P_POWER_ON. The storage value can be set in the specific storage area by, for example, executing step AKS14 in the power supply start response process P_POWER_ON.
In this configuration, it is possible to prevent the contents stored in the storage means from being changed unnecessarily and to update the random number values appropriately.

(Explanation of characteristic part 003AK)
FIG. 11-1 shows the memory area of addresses 0000 [H] to 3FFF [H] allocated to the ROM 101 for the feature section 003AK. The game program area included in the memory area of the ROM 101 is allocated addresses 0000 [H] to 0BD2 [H], with a total storage capacity of 3027 bytes. The game data area included in the memory area of the ROM 101 is allocated addresses 1200 [H] to 1D33 [H], with a total storage capacity of 2868 bytes. The non-game program area included in the memory area of the ROM 101 is allocated addresses 2000 [H] to 24DD [H]. The non-game data area included in the memory area of the ROM 101 is allocated addresses 24DE [H] to 2576 [H]. Addresses 2E00[H] to 2E3F[H] are assigned to the ROM comment area included in the memory area of the ROM 101. Addresses 3FC0[H] to 3FFF[H] are assigned to the program management area included in the memory area of the ROM 101.

The memory area of ROM 101 includes an unused area assigned addresses 0BD3 [H] to 11FF [H] between the game program area and the game data area. The unused area of addresses 0BD3 [H] to 11FF [H] has a total storage capacity of 1069 bytes. The memory area of ROM 101 includes an unused area assigned addresses 1D34 [H] to 1FFF [H] between the game data area and the non-game program area. The unused area of addresses 1D34 [H] to 1FFF [H] has a total storage capacity of 1228 bytes. The memory area of ROM 101 includes an unused area assigned addresses 2577 [H] to 2DFF [H] between the non-game data area and the ROM comment area. The memory area of ROM 101 includes an unused area assigned addresses 2E40[H] to 3FBF[H] between the ROM comment area and the program management area.

In all of these unused areas, zero data with a storage value of 00 [H] is stored as unused data. In this way, all unused areas store zero data with a storage value of 00 [H] as unused data indicating 0. The unused area may be any area to which access by the CPU 103 is prohibited. For example, it may be possible to prohibit access to all or part of the unused area using designated data for the program code end address or program code start address stored in the program management area.

In the game control microcomputer 100, the ROM 101 can store programs, and the CPU 103 can control the progress of the game using the programs stored in the ROM 101. Therefore, the ROM 101 can correspond to storage means capable of storing programs. The CPU 103 can correspond to control means capable of controlling the progress of the game using the programs stored in the storage means. Note that the storage means capable of storing programs may be configured using an external storage device different from the ROM 101, and the entire game control microcomputer 100 may be configured as control means capable of controlling the progress of the game using the programs stored in this storage device.

The game program area stores programs related to game control. The game data area stores data used to execute the programs stored in the game program area. A non-game program area and a non-game data area are provided as memory areas separate from the game program area and game data area. Therefore, the game program area may correspond to a first memory area in which programs related to game control are stored. The game data area may correspond to a second memory area in which data used to execute the programs stored in the first memory area is stored. The non-game program area and non-game data area may correspond to a third memory area separate from the first memory area and second memory area.

If the game program area is the first memory area and the game data area is the second memory area in the memory area of ROM 101, the unused area at addresses 0BD3 [H] to 11FF [H] becomes an unused memory area that can store unused data between the first memory area and the second memory area. Here, unused data indicating all 0s is stored in the unused area that becomes the unused memory area. In this case, the total memory capacity of the game program area that becomes the first memory area is 3027 bytes, which is larger than the total memory capacity of the unused area that becomes the unused memory area, which is 1069 bytes.

In the memory area of ROM 101, if the game program area is the first memory area, the game data area is the second memory area, and the non-game program area and non-game data area are the third memory area, the unused area from addresses 0BD3 [H] to 11FF [H] becomes an unused memory area between the first memory area and the second memory area where unused data can be stored, and the unused area from addresses 1D34 [H] to 1FFF [H] becomes an unused memory area between the second memory area and the third memory area where unused data can be stored. Here, unused data indicating all 0s is stored in the unused area that becomes the unused memory area. In this case, the total memory capacity of the game data area that becomes the second memory area is 2,868 bytes, which is larger than the total memory capacity of the unused area that becomes the unused memory area, which is 2,297 bytes.

In the memory area of ROM 101, the unused area corresponding to the unused memory area capable of storing unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area may be a single area to which consecutive addresses are assigned and in which unused data indicating 0 is stored. In the memory area of ROM 101, the unused area corresponding to the unused memory area capable of storing unused data between the game data area corresponding to the second memory area and the non-game program area and non-game data area corresponding to the third memory area may be a single area to which consecutive addresses are assigned and in which unused data indicating 0 is stored.

For example, in the address map of the game control microcomputer 100, the locations of memory areas, such as memory areas assigned addresses in ROM 101, are determined based on the magnitude of the address values, with smaller assigned addresses being in the front and larger assigned addresses being in the back. Therefore, a second area assigned a larger address value than a first area becomes the second area located behind the first area, and a third area assigned a smaller address value than the first area becomes the third area located ahead of the first area. The locations of the first, second, and third areas can be arbitrarily set based on the magnitude of the addresses assigned in accordance with the specifications of the pachinko gaming machine 1. The location of each area in the memory area of ROM 101, including the game program area, game data area, non-game program area, non-game data area, and other unused areas, can be arbitrarily set based on the addresses assigned in accordance with the specifications of the pachinko gaming machine 1.

Figure 11-2 shows setting example 003AKA01 of unused data in the game program area contained in the memory area of ROM 101. In setting example 003AKA01, the processing start address includes the start address of the program module and the start address of the table data. The processing end address includes the end address of the program module and the end address of the table data. The unused data amount is the number of bytes that constitutes the storage capacity of the area where zero data, with a storage value of 00 [H], is stored as unused data indicating 0. Therefore, the processing start address is the start address of the program or the start address of data usable for program execution, and the processing end address is the end address of the program or the end address of data usable for program execution. However, data usable for program execution may include data that is not used for program execution, depending on various instructions and settings in the implemented program.

In the game program area contained in the memory area of ROM 101, addresses 0008[H], 0010[H], 0018[H], 0020[H], 0028[H], 0030[H], 0038[H], and 0040[H] are predetermined as restart addresses where program modules can be allocated. Restart addresses are 8-byte addresses in the area allocated to addresses 0008[H] through 0040[H] in the game program area, where the lowest digit of the address is 0[H] or 8[H]. Therefore, restart addresses can correspond to multiple specific addresses allocated at predetermined intervals. The CPU 103 is provided with a RST command, which is a 1-byte restart command that can call and execute a program module whose starting address is a predetermined restart address.

Figure 11-3 shows an example of the structure of an RST instruction. As shown in Figure 11-3 (A), the RST instruction is constructed using an operation code from bit 0 to bit 7, and all bits other than bit 3 to bit 5 are constructed with an operation code indicating 1 [B]. As shown in Figure 11-3 (B), the operation code from bit 3 to bit 5 in the RST instruction is a parameter defined corresponding to the specified address, which is the call address of the program module. For example, parameter 001[B] corresponds to address 0008[H], parameter 010[B] corresponds to address 0010[H], parameter 011[B] corresponds to address 0018[H], parameter 100[B] corresponds to address 0020[H], parameter 101[B] corresponds to address 0028[H], parameter 110[B] corresponds to address 0030[H], parameter 111[B] corresponds to address 0038[H], and parameter 000[B] corresponds to address 0040[H]. Therefore, each three-digit binary parameter corresponds to a four-digit hexadecimal address.

When a program module is called using the RST instruction, which serves as a restart instruction, an operation code including parameters is used. The RST instruction specifies a parameter whose data volume is smaller than the address in the memory area of ROM 101, making it possible to call the program module stored at the address corresponding to the specified parameter. The operation code of the RST instruction includes a three-digit binary variable t, and multiple restart addresses can be specified using the operation code in which a parameter is substituted for this variable. In this way, the RST instruction is a call instruction that specifies a value corresponding to a predetermined restart address, thereby calling and making executable the program stored at the restart address corresponding to the specified value.

The CPU 103 is provided with a CALL instruction, which differs from the RST instruction, as a call instruction for calling and executing a program stored in the game program area. The CALL instruction is a call instruction that calls and makes executable a program stored at an address specified by an operand. When a program is called and executed using the CALL instruction, a total of two bytes, consisting of an upper byte and a lower byte, that make up the program's start address are specified by the operand of the CALL instruction. The CPU 103 identifies the program's start address using the operand of the CALL instruction. Therefore, the CALL instruction can correspond to a first call instruction that calls a program stored at a specified address by specifying an address. In contrast, the RST instruction can correspond to a second call instruction that calls a program stored at a specific address corresponding to the specified parameter from among multiple specific addresses assigned at predetermined intervals by specifying a parameter with a smaller data amount than the address.

Of the game programs that control the progress of the game, at least some of the frequently used program modules are stored in a restart area that uses the restart address as the starting address. In the setting example 003AKA01 shown in Figure 11-2, program modules corresponding to each of the following processes are stored in the restart area: special symbol process end check process P_TPRO_END, time-saving check process P_JTN_CHK, 2-byte/1-byte addition process P_ABX, output process P_OUT, 2-byte data selection process P_ABXEXC, second allocation judgment value comparison process P_HANTEI2, start port winning check process P_STR_CHK, allocation judgment value comparison process P_HANTEI, and command set process P_COM_SET. The power recovery vector table is also included in the data stored in the restart area.

The program module for special pattern process end check processing P_TPRO_END has a start address of address 0008 [H]. The program module for time-saving check processing P_JTN_CHK has a start address of address 0010 [H]. The program module for 2-byte 1-byte addition processing P_ABX has a start address of address 0018 [H]. The program module for 2-byte data selection processing P_ABXEXC has a start address of address 0020 [H]. The program module for second allocation judgment value comparison processing P_HANTEI2 has a start address of address 0028 [H]. The program module for start slot winning check processing P_STR_CHK has a start address of address 0030 [H]. The program module for allocation judgment value comparison processing P_HANTEI has a start address of address 0038 [H]. The program module for command set processing P_COM_SET has a start address of address 0040 [H].

In the restart area, the area from one restart address to just before the next restart address is 8 bytes, except when the first restart address is the final restart address at address 0040 [H]. When a program module of less than 8 bytes is stored with a restart address as its starting address, the area from after the end address of the program module that starts at the first restart address to just before the next restart address may be able to store other program modules or table data.

For example, the program module for the time-saving check process P_JTN_CHK has address 0010[H], which is included in multiple restart addresses, as its start address, and address 0014[H] as its end address. In this case, table data for the power interruption recovery vector table can be stored in the area from address 0010[H], which is one restart address, to just before address 0018[H], which is the next restart address. A power interruption recovery vector table such as configuration example AKT11 is composed of table data containing lower address specification data 00[H] stored at address 0016[H] and upper address specification data 00[H] stored at address 0017[H].

For example, a program module for a two-byte, one-byte addition process P_ABX has a start address of address 0018[H], which is included in multiple restart addresses, and an end address of address 001A[H]. In this case, a program module for output process P_OUT can be stored in the area from address 0018[H], which is one restart address, to just before address 0020[H], which is the next restart address. The program module for output process P_OUT simply needs to have a start address of address 001B[H], which is different from the multiple restart addresses, and an end address of address 001F[H]. Therefore, the restart area starting from address 0018[H], which is the restart address, can store program modules corresponding to multiple processes, such as the two-byte, one-byte addition process P_ABX and the output process P_OUT, with the process start address being address 0018[H] and the process end address being address 001F[H].

In this way, other program modules or table data may be stored in the area from the end address of a program module whose start address is the restart address to just before the next restart address. This allows multiple program modules, or combinations of program modules and table data, to be stored in the area from one restart address to just before the next restart address.

In the restart area, the area from one restart address to just before the next restart address is 8 bytes, except when the first restart address is the final restart address at address 0040 [H]. When a program module of less than 8 bytes is stored with a restart address as its starting address, the area from the end address of the program module starting at the first restart address to just before the next restart address may store zero data, with a storage value of 00 [H], as unused data indicating 0.

Figure 11-4 shows an example of the program modules stored in the restart area, corresponding to the start port winning check process P_STR_CHK and the allocation judgment value comparison process P_HANTEI. As shown in Figure 11-4 (A), the start port winning check process P_STR_CHK stores a program module in the restart area from address 0030 [H], which is the first restart address, to address 0038 [H], which is the next restart address, with address 0030 [H] being the start address and including the LDQ command, etc. The start port winning check process P_STR_CHK ends at address 0034 [H], and resumes processing by executing the RET command. As shown in Figure 11-4 (B), the allocation judgment value comparison process P_HANTEI stores program modules in the restart area from address 0038[H], which is one restart address, to address 0040[H], which is the next restart address, with address 0038[H] being the start address and including the LDIN instruction. The allocation judgment value comparison process P_HANTEI ends at address 003E[H], and processing resumes when the RET instruction is executed.

The area from addresses 0035[H] to 0037[H] shown in Figure 11-4(A) stores three bytes of zero data with a storage value of 00[H]. This area is after the end address 0034[H] of the program module where the start slot winning check process P_STR_CHK ends with the RET instruction and returns to the calling process, and before address 0038[H], which is the next restart address. Therefore, the area from addresses 0035[H] to 0037[H] is an area where unused data is stored, unlike an area where programs executed by the CPU 103 and data used to execute programs can be stored. Therefore, the area from addresses 0035[H] to 0037[H] is included in a special storage area where unused data indicating 0 is stored at a special address. In this way, the area assigned addresses 0035[H] to 0037[H] from address 0030[H], which is one restart address, to just before address 0038[H], which is the next restart address, is included in the special memory area to which special addresses are assigned.

The area at address 003F[H] shown in Figure 11-4 (B) stores one byte of zero data with a storage value of 00[H]. This area is after the end address 003E[H] of the program module where the allocation judgment value comparison process P_HANTEI ends with the RET instruction and returns to the caller's process, and before address 0040[H], which is the next restart address. Therefore, the area at address 003F[H] is an area where unused data is stored, unlike an area that can store programs executed by the CPU 103 or data used to execute programs. Therefore, the area at address 003F[H] is included in a special memory area where unused data indicating 0 is stored at special addresses. In this way, the area assigned to address 003F[H], from address 0038[H], which is one restart address, to just before address 0040[H], which is the next restart address, is included in a special memory area where special addresses are assigned.

In addition, as shown in Figure 11-2, from address 0014[H], the end address of the time-saving check process P_JTN_CHK, to address 0016[H], the start address of the power-off recovery vector table, the area at address 0015[H] stores one byte of zero data with a storage value of 00[H], and is included in a special memory area where unused data indicating 0 is stored at a special address. As a result, the area assigned to address 0015[H] from address 0010[H], which is the first restart address, to just before address 0018[H], which is the next restart address, is included in a special memory area where special addresses are assigned. The 2-byte data selection process P_ABXEXC has address 0020[H] as its start address and 0025[H] as its end address. In this case, the area from address 0020[H], which is the first restart address and the starting address of the 2-byte data selection process P_ABXEXC, to just before the next restart address, 0028[H], stores two bytes of zero data with a storage value of 00[H], and is included in a special memory area where unused data indicating 0 is stored at special addresses. As a result, the area assigned to addresses 0026[H] and 0027[H] from address 0020[H], which is the first restart address, to just before address 0028[H], which is the next restart address, is included in a special memory area to which special addresses are assigned.

In this way, the restart area from one restart address to the next restart address included in the multiple restart addresses stores zero data with a storage value of 00 [H], and may include an area in a special address where unused data indicating 0 is stored. Therefore, the special memory area includes an area in which unused data is stored from one specific address to the next specific address included in the multiple specific addresses.

In this case, the area from address 0010 [H], which is one restart address where the program module for the time-saving check processing P_JTN_CHK is stored, to address 0018 [H], which is the next restart address, contains a special memory area where 1 byte of unused data is stored. The area from address 0020 [H], which is one restart address where the program module for the 2-byte data selection processing P_ABXEXC is stored, to address 0028 [H], which is the next restart address, contains a special memory area where 2 bytes of unused data are stored. The area from address 0030 [H], which is one restart address where the program module for the start-port winning check processing P_STR_CHK is stored, to address 0038 [H], which is the next restart address, contains a special memory area where 3 bytes of unused data are stored. The area from address 0038[H], which is one restart address where the distribution judgment value comparison process P_HANTEI program module is stored, to address 0040[H], which is the next restart address, includes a special memory area where 1 byte of unused data is stored. Therefore, the total memory capacity of the special memory area in the restart area where special addresses are assigned and unused data indicating 0 is stored is 7 bytes.

Furthermore, multiple restart addresses are assigned every 8 bytes, and each restart address becomes the start address of a program module. Therefore, zero data with a storage value of 00 [H] is stored in the restart area, and the special memory area where unused data indicating 0 is stored at special addresses includes multiple areas assigned discontinuous addresses. Furthermore, zero data with a storage value of 00 [H] is stored in the restart area, and the special memory area where unused data indicating 0 is stored at special addresses is assigned special addresses so that there are no consecutive areas of more than a certain number of bytes, for example 16 bytes.

Figure 11-5 shows an example of how table data contained in the interrupt vector table XTBL_INTR is stored. In the game program area contained in the memory area of ROM 101, address 0060[H] is defined as the address where the interrupt vector table XTBL_INTR can be located. For example, the lower byte 60[H] of address 0060[H] can be set as a vector address corresponding to the interrupt cause using the interrupt initial setting data stored in the program management area. Furthermore, step AKS8 of the power supply start response processing sets the upper byte 00[H] of address 0060[H] as the upper address of the interrupt vector table, and step AKS9 sets this in the I register.

The interrupt initial setting data can set vector addresses corresponding to multiple interrupt sources. The interrupt mask register at address FE00[H] in the function setting register area can store setting values, including bit values indicating whether to use multiple maskable interrupts. In the power supply start response setting process, step AKS11 sets the function setting register storage value table address, step AKS12 loads the number of processes, and step AKS13 executes the function setting register store command, setting the value stored in the interrupt mask register to 7E[H]. The interrupt controller 135 enables maskable interrupts corresponding to multiple interrupt sources, such as seven maskable interrupts IR0 to IR6. When the value stored in the interrupt mask register is 7E[H], maskable interrupt IR0 is enabled and the other maskable interrupts IR1 to IR6 are disabled.

The interrupt vector table XTBL_INTR contains table data that can set the start address of interrupt processing corresponding to multiple maskable interrupts IR0 to IR6. The table data at addresses 0060 [H] and 0061 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR0. The table data at addresses 0062 [H] and 0063 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR1. The table data at addresses 0064 [H] and 0065 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR2. The table data at addresses 0066 [H] and 0067 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR3. The table data at addresses 0068 [H] and 0069 [H] specifies the start address of interrupt processing corresponding to maskable interrupt IR4. The table data at addresses 006A[H] and 006B[H] specifies the start address of the interrupt processing corresponding to maskable interrupt IR5. The table data at addresses 006C[H] and 006D[H] specifies the start address of the interrupt processing corresponding to maskable interrupt IR6. Therefore, the area at addresses 0060[H] to 006D[H] that stores the table data included in the interrupt vector table XTBL_INTR can correspond to an address storage area that can store the addresses of the interrupt processing program.

When the value stored in the interrupt mask register is 7E [H], only maskable interrupt IR0 is enabled, and the other maskable interrupts IR1 to IR6 are disabled. Therefore, in the interrupt vector table XTBL_INTR, the table data at addresses 0060 [H] and 0061 [H] is used data for specifying the start address of the interrupt process, while the table data at addresses 0062 [H] to 006D [H] is unused data. For example, the table data at address 0060 [H] indicates the lower address, which is the lower byte of the start address for the timer interrupt process P_PCT for game control. The table data at address 0061 [H] indicates the upper address, which is the upper byte of the start address for the timer interrupt process P_PCT for game control. As a result, the program that becomes the timer interrupt process P_PCT for game control is the interrupt process program whose address is stored in the interrupt vector table XTBL_INTR. In contrast, the table data at addresses 0062[H] to 006D[H] contains 12 bytes of zero data with a storage value of 00[H], which is unused interrupt vector data. Thus, the area from addresses 0062[H] to 006D[H] is an area where unused data is stored, unlike an area that can store programs executed by the CPU 103 or data used to execute programs. Therefore, the area from addresses 0062[H] to 006D[H] is included in a special storage area where unused data indicating 0 is stored at a special address.

When the area from addresses 0060[H] to 006D[H], which stores table data included in the interrupt vector table XTBL_INTR, serves as an address storage area, the area assigned to addresses 0062[H] to 006D[H] is included in the special storage area to which special addresses are assigned. In this case, the special storage area includes the area in the address storage area where unused data is stored. The area assigned to addresses 0062[H] to 006D[H] has a total storage capacity of 12 bytes. Therefore, when the area from addresses 0060[H] to 006D[H] serves as an address storage area, the total storage capacity of the special storage area in this address storage area, which is assigned a special address and stores unused data indicating 0, is 12 bytes.

Thus, the game program area includes an area where unused data indicating 0 is stored. In the game program area, an area where unused data indicating 0 is stored may correspond to a special memory area assigned a special address. Furthermore, the total memory capacity of the special memory area in the restart area where a special address is assigned and unused data indicating 0 is stored is 7 bytes. When the area from addresses 0060[H] to 006D[H], which stores table data included in the interrupt vector table XTBL_INTR, serves as an address memory area, the total memory capacity of the special memory area in this address memory area where a special address is assigned and unused data indicating 0 is stored is 12 bytes. Thus, the total memory capacity of the area that serves as a special memory area in the game program area is 19 bytes. The total memory capacity of the unused area corresponding to the unused memory area that can store unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area is 1,069 bytes. Therefore, the total memory capacity of the special memory area is 19 bytes, which is smaller than the total memory capacity of the unused area that serves as an unused memory area, 1,069 bytes.

The total storage capacity of the game program area corresponding to the first storage area is greater than the total storage capacity of the unused area between the first storage area and the second storage area, which is an unused storage area capable of storing unused data. When such a first storage area includes a special storage area, the total storage capacity of the special storage area is smaller than the total storage capacity of the unused area. This increases the likelihood of distinguishing between the unused area and the special storage area, enabling appropriate management of the storage area to prevent misidentification.

The special memory area assigned a special address in the restart area includes multiple areas assigned discontinuous addresses. For example, the area from addresses 0035[H] to 0037[H] shown in Figure 11-4(A) and the area at address 003F[H] shown in Figure 11-4(B) are both included in the special memory area and may correspond to multiple areas assigned discontinuous addresses. Additionally, in the area from address 0010[H], which is one restart address where the program module for the time-saving check process P_JTN_CHK is stored, to address 0018[H], which is the next restart address, the area where one byte of unused data is stored is included in the special memory area and may be included in multiple areas assigned discontinuous addresses from the special memory areas provided in other restart areas. In the area from address 0020 [H], which is one restart address where the program module for the 2-byte data selection process P_ABXEXC is stored, to address 0028 [H], which is the next restart address, the area where 2 bytes of unused data are stored is included in a special memory area, and can be included in multiple areas assigned discontinuous addresses from special memory areas provided in other restart areas. Therefore, the special memory area in the restart area where special addresses are assigned and unused data indicating 0 is stored includes multiple areas assigned discontinuous addresses as special addresses.

Special memory areas assigned special addresses in the restart area and special memory areas assigned special addresses in the area storing table data included in the interrupt vector table XTBL_INTR are assigned discontinuous addresses. The area storing table data included in the interrupt vector table XTBL_INTR is an area from addresses 0060[H] to 006D[H], with the program address for the game control timer interrupt process P_PCT stored in addresses 0060[H] and 0061[H], and unused data indicating 0 stored in addresses 0062[H] to 006D[H]. Therefore, the special memory areas assigned special addresses in the area storing table data included in the interrupt vector table XTBL_INTR are included in the special memory areas assigned special addresses in the restart area and multiple areas assigned discontinuous addresses.

In this way, the storage addresses of unused data in setting example 003AKA01 are assigned discontinuous addresses as special addresses in the special storage area, which makes it less likely that unused data indicating 0 will be stored in an area of the special storage area with consecutive special addresses, unlike unused areas where consecutive addresses are assigned and unused data indicating 0 is stored. This increases the likelihood of distinguishing between unused areas and special storage areas, enabling appropriate management of storage areas to prevent misidentification.

The total storage capacity of the special memory areas assigned special addresses in the restart area is smaller than the total storage capacity of the special memory areas assigned special addresses in the area storing table data included in the interrupt vector table XTBL_INTR. This allows the memory area that becomes the restart area to be used efficiently to store program modules, thereby preventing an increase in storage capacity in the game program area. Furthermore, the special memory areas assigned special addresses in the restart area include multiple areas assigned with discontinuous addresses, while the special memory areas assigned special addresses in the area storing table data included in the interrupt vector table XTBL_INTR include a single area assigned with a contiguous address. In this case, the possibility of distinguishing between unused areas and special memory areas in the restart area is higher than the possibility of distinguishing between unused areas and special memory areas in the address memory area, enabling appropriate memory area management to reliably prevent misidentification of special memory areas in the restart area.

Note that, depending on the configuration of the program modules and table data stored in the restart area, the restart area may not have a special memory area to which a special address is assigned and unused data indicating 0 is stored. Also, depending on the configuration of the interrupt program corresponding to multiple interrupt causes, the area that stores table data included in the interrupt vector table XTBL_INTR may not have a special memory area to which a special address is assigned and unused data indicating 0 is stored. Thus, depending on the specifications of the pachinko gaming machine 1, the special memory area may not include an area from one specific address to the next specific address included in multiple specific addresses where unused data is stored. Also, depending on the specifications of the pachinko gaming machine 1, the special memory area may not include an area in the address memory area where unused data is stored.

The zero data stored in the game program area as 00 [H] is not limited to unused data not used in program execution, but may also include data used in program execution. For example, when setting the interrupt vector table upper address in step AKS8 of the power supply start response processing P_POWER_ON, the upper byte of the interrupt vector table address is directly specified by the operand in the transfer instruction for setting the internal register of CPU 103. Since the upper byte of the interrupt vector table address is 00 [H], zero data stored in the game program area as 00 [H] is stored as data used to set the interrupt vector table upper address. Furthermore, for example, when storing an access permission output value in the RWM access protection register in step AKS14 of the power supply start response processing P_POWER_ON, the address of the RWM access protection register is directly specified by the operand in the transfer instruction for setting the internal register of CPU 103. The RWM access protection register is located at the beginning of the function control register area, such as setting example AKA02, and is assigned address FF00[H]. Therefore, zero data with a storage value of 00[H] is stored in the game program area as usage data used to specify the lower byte of the RWM access protection register's address.

For example, when backup monitoring timer clear data is stored by step AKS34 of the power-off processing P_POWER_OFF, zero data indicating 00 [H] is directly specified as the clear data by the operand in a transfer instruction that can update the stored data at the address pointed to by the pointer. Therefore, zero data with a storage value of 00 [H] is stored in the game program area as the data used to store clear data in the backup monitoring timer. For example, when clear data is stored in the RWM access protect register by step AKS42 of the power-off processing P_POWER_OFF, the address of the RWM access protect register is directly specified by the operand in the transfer instruction. Therefore, zero data with a storage value of 00 [H] is stored in the game program area as the data used to specify the lower byte of the address of the RWM access protect register. Furthermore, in the power interruption recovery vector table such as setting example AKT11, the table data at addresses 0016 [H] and 0017 [H] is used to specify address 0000 [H], which is the start address for the game control main processing P_MAIN. The power interruption recovery vector table is used to set the stored value of the program counter when an interrupt return command is executed after the address is set in the stack pointer by step AKS50 of the power interruption processing P_POWER_OFF. In this way, the table data contained in the power interruption recovery vector table is used as address specification data that enables the game control main processing P_MAIN, which is the startup processing based on the startup of the pachinko gaming machine 1, to be executed from the beginning. For this reason, zero data with a storage value of 00 [H] is stored in the game program area as address specification data that enables the startup processing to be executed from the beginning.

In this way, the game program area includes an area in which usage data indicating 0 is stored. In the game program area, the area in which usage data indicating 0 is stored may correspond to a predetermined memory area to which a predetermined address is assigned. In this case, the total memory capacity of the predetermined memory area only needs to be smaller than the total memory capacity of the unused area corresponding to the unused memory area capable of storing unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area. The total memory capacity of the special memory area and the predetermined memory area only needs to be smaller than the total memory capacity of the unused area corresponding to the unused memory area capable of storing unused data between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area.

The predetermined memory area in the gaming program area, to which a predetermined address is assigned, may include multiple areas to which discontinuous addresses are assigned. For example, addresses 0016[H] and 0017[H] of the table data included in the power-off recovery vector table such as setting example AKT11, the address storing the usage data used in step AKS34 of the power-off processing P_POWER_OFF, and the address storing the usage data used in address AKS42 of the power-off processing P_POWER_OFF may each be set to be discontinuous addresses. In this case, the usage data stored in the predetermined memory area includes address designation data that enables startup processing based on the startup of the gaming machine to be executed from the beginning, such as table data included in the power-off recovery vector table such as setting example AKT11.

The usage data stored in the specified memory area may include address designation data that can designate any address, such as the upper byte, lower byte, or both the upper and lower bytes of an address assigned to any memory area in ROM 101, RAM 102, or the built-in register of the game control microcomputer 100. The usage data stored in the specified memory area may also include stored value setting data that can be used when setting a stored value in any register, counter, timer, or other memory area. Usage data that indicates 0 that can be used when setting a stored value in a register is also called register initial setting data. Usage data that indicates 0 that can be used when setting a stored value in a counter is also called counter initial setting data. Usage data that indicates 0 that can be used when setting a stored value in a timer is also called timer initial setting data.

Depending on the configuration of the programs and table data stored in the game program area, the game program area may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. Furthermore, depending on the configuration of the programs and table data stored in the game program area, for example, the area in which table data for a power-off recovery vector table is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. Furthermore, the area in which arbitrary address designation data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. The area in which register initial setting data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. The area in which counter initial setting data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. The area in which timer initial setting data is stored may not have a predetermined memory area in which a predetermined address is assigned and usage data indicating 0 is stored. Thus, depending on the specifications of the pachinko gaming machine 1, the game program area corresponding to the first memory area may not include a normal memory area in which a predetermined address is assigned and usage data indicating 0 is stored. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the specified memory area may not include address designation data that enables startup processing based on the startup of the gaming machine to be executed from the beginning. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the specified memory area may not include address designation data that allows any address to be designated. Alternatively, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the specified memory area may not include setting data that allows a storage value to be set in any memory area.

Figure 11-6 shows setting example 003AKA11 of zero data, which becomes unused data or used data in the game data area contained in the memory area of ROM 101. Zero data, which has a storage value of 00 [H] in the game data area, can become used data used in program execution, or unused data not used in program execution. Data stored in the game data area can constitute table data contained in various tables. In setting example 003AKA11, the table data start address is the start address of the table data contained in the various tables. The table data end address is the end address of the table data contained in the various tables. The zero data amount is the number of bytes that is the storage capacity of the area where zero data, which becomes unused data or used data, is stored. Therefore, the table data start address is the start address of data usable for program execution, and the table data end address is the end address of data usable for program execution. However, data usable for program execution may include data not used for program execution, depending on various instructions and settings in the implemented program.

In the game data area contained in the memory area of ROM 101, the area from addresses 1200[H] to 121D[H] stores the table data contained in each of the following tables: display device control table XD_DG, first special symbol display control table XD_TOKUZU1, second special symbol display control table XD_TOKUZU2, first special symbol buffer shift control table XD_TBUFSHIFT1, second special symbol buffer shift control table XD_TBUFSHIFT2, and normal symbol stop display table XD_FZU_STOP. The area from addresses 121E[H] to 1227[H] stores the table data contained in the normal symbol reserved memory count display table XD_FMEM. The area from addresses 1228[H] to 1231[H] stores the table data contained in the first reserved memory count display table XD_TMEM1. The area from addresses 1232 [H] to 123B [H] stores table data contained in the second reserved memory count display table XD_TMEM2. The area from addresses 123C [H] to 1247 [H] stores table data contained in the variable pattern command allocation selection table XP_TPAT_TBL. The area from addresses 1248 [H] to 1250 [H] stores table data contained in the right-hit round count display table XD_TOKU1. The area from addresses 1251 [H] to 1258 [H] stores table data contained in the solenoid pattern allocation selection table XP_YSOL_SEL.

In the game data area, the area where table data included in various tables is stored may store zero data with a storage value of 00 [H] as used data indicating 0. Also, in the game data area, the area where table data included in various tables is stored may store zero data with a storage value of 00 [H] as unused data indicating 0.

Figure 11-7 shows an example of table data storage contained in various tables. The regular map reserved memory count display table XD_FMEM shown in Figure 11-7 (A) has a table data start address of 121E [H] and a table data end address of 1227 [H]. The regular map reserved memory count display table XD_FMEM is used to execute a program that controls the display of the regular map reserved memory count on the regular map reserved indicator 25C, and contains table data that serves as display data corresponding to regular map reserved memory counts of "0" to "4". The first reserved memory count display table XD_TMEM1 shown in Figure 11-7 (B) has a table data start address of 1228 [H] and a table data end address of 1231 [H]. The first reserved memory count display table XD_TMEM1 is used to execute a program that controls the display of the first reserved memory count on the first reserved indicator 25A, and contains table data that serves as display data corresponding to the first reserved memory counts of "0" to "4". The right-hit round count display table XD_TOKU1 shown in Figure 11-7 (C) has a table data start address of 1248 [H] and a table data end address of 1250 [H]. The right-hit round count display table XD_TOKU1 is used to execute programs that control the display by the light-emitting elements that serve as right-hit indicator lights and the light-emitting elements that serve as round count indicators, and contains table data that serves as display data corresponding to the jackpot game status and number of rounds.

The stored data at addresses 121E [H] and 121F [H] shown in Figure 11-7 (A) are the first and second bytes of the display data used in correspondence with a normal map reserved memory count of "0". All of these stored data are a total of two bytes of zero data with a stored value of 00 [H]. The stored data at addresses 1220 [H] and 1221 [H] are the first and second bytes of the display data used in correspondence with a normal map reserved memory count of "1". Of these, the stored data at address 1221 [H] is one byte of zero data with a stored value of 00 [H]. The stored data at addresses 1222 [H] and 1223 [H] are the first and second bytes of the display data used in correspondence with a normal map reserved memory count of "2". Of these, the stored data at address 1223 [H] is one byte of zero data with a stored value of 00 [H]. The data stored at addresses 1224 [H] and 1225 [H] are the first and second bytes of the display data used in accordance with the normal map reserve memory count of "3". All of this stored data is non-zero data with a stored value other than 00 [H]. The data stored at addresses 1226 [H] and 1227 [H] are the first and second bytes of the display data used in accordance with the normal map reserve memory count of "4". All of this stored data is non-zero data with a stored value other than 00 [H].

The regular map reserve indicator 25C may be constructed using light-emitting elements, such as two LEDs, and may include a first light-emitting element whose light-emitting state can be changed in response to the first byte of the display data read from the regular map reserve memory count display table XD_FMEM, and a second light-emitting element whose light-emitting state can be changed in response to the second byte of the display data read from the regular map reserve memory count display table XD_FMEM. The regular map reserve indicator 25C may be able to recognizably display the number of regular map reserve memories based on the light-emitting states of the first and second light-emitting elements. The first and second light-emitting elements of such a regular map reserve indicator 25C may correspond to light-emitting means. For example, the first light-emitting element of the regular map reserve indicator 25C may be turned off when the first byte corresponds to 00 [H], turned on when the first byte corresponds to 20 [H], and flashed when the first byte corresponds to 24 [H] in the display data read from the regular map reserve memory count display table XD_FMEM. Additionally, the second light-emitting element of the regular map reserve display 25C turns off when the second byte corresponds to 00 [H], turns on when the second byte corresponds to 20 [H], and blinks when the second byte corresponds to 24 [H] in the display data read from the regular map reserve memory count display table XD_FMEM. In the regular map reserve memory count display table XD_FMEM, the table data at addresses 121E [H], 121F [H], 1221 [H], and 1223 [H] is usage data used in program execution, but is zero data with a storage value of 00 [H]. Therefore, the areas at addresses 121E [H], 121F [H], 1221 [H], and 1223 [H] are included in the regular memory area, where usage data indicating 0 in regular addresses is stored. In this case, the usage data stored in the regular memory area includes extinguishing control data that can be used to extinguish the light-emitting means.

The stored data at addresses 1228[H] and 1229[H] shown in Figure 11-7 (B) are the first and second bytes of display data used in correspondence with the first pending memory number "0". All of these stored data are a total of two bytes of zero data with a stored value of 00[H]. The stored data at addresses 122A[H] and 122B[H] are the first and second bytes of display data used in correspondence with the first pending memory number "1". Of these, the stored data at address 122B[H] is one byte of zero data with a stored value of 00[H]. The stored data at addresses 122C[H] and 122D[H] are the first and second bytes of display data used in correspondence with the first pending memory number "2". Of these, the stored data at address 122D[H] is one byte of zero data with a stored value of 00[H]. The data stored at addresses 122E[H] and 122F[H] are the first and second bytes of the display data used in accordance with the first pending memory count of "3". All of this stored data is non-zero data with a stored value other than 00[H]. The data stored at addresses 1230[H] and 1231[H] are the first and second bytes of the display data used in accordance with the first pending memory count of "4". All of this stored data is non-zero data with a stored value other than 00[H].

The first hold indicator 25A may be configured using light-emitting elements, such as two LEDs, and may include a first light-emitting element whose light-emitting state can be changed in response to the first byte of the display data read from the first hold memory count display table XD_TMEM1, and a second light-emitting element whose light-emitting state can be changed in response to the second byte of the display data read from the first hold memory count display table XD_TMEM1. The first hold indicator 25A may be able to recognizably display the first hold memory count based on the light-emitting states of the first and second light-emitting elements. The first and second light-emitting elements of such a first hold indicator 25A may correspond to light-emitting means. For example, the first light-emitting element of the first hold indicator 25A may be turned off when the first byte corresponds to 00 [H], turned on when the first byte corresponds to 80 [H], and flashed when the first byte corresponds to 90 [H] in the display data read from the first hold memory count display table XD_TMEM1. Furthermore, the second light-emitting element of the first hold display 25A turns off when the second byte corresponds to 00 [H], turns on when the second byte corresponds to 80 [H], and blinks when the second byte corresponds to 90 [H] in the display data read from the first hold memory count display table XD_TMEM1. In the first hold memory count display table XD_TMEM1, the table data at addresses 1228 [H], 1229 [H], 122B [H], and 122D [H] is usage data used in program execution, but is zero data with a storage value of 00 [H]. Therefore, the areas at addresses 1228 [H], 1229 [H], 122B [H], and 122D [H] are included in the normal memory area, where usage data indicating 0 is stored in normal addresses. In this case, the usage data stored in the normal memory area includes extinguishing control data that can be used to extinguish the light-emitting means.

The stored data at address 1248 [H] shown in Figure 11-7 (C) is display data used for two rounds of round number "2" in the jackpot gaming state. The stored data at address 1249 [H] is display data used for three rounds of round number "3" in the jackpot gaming state. The stored data at address 124A [H] is display data used for four rounds of round number "4" in the jackpot gaming state. These stored data are non-zero data with stored values other than 00 [H]. The stored data at address 124B [H] is display data corresponding to five rounds of round number "5" in the jackpot gaming state. The stored data at address 124C [H] is display data corresponding to six rounds of round number "6" in the jackpot gaming state. Due to the specifications of the pachinko gaming machine 1, if the number of rounds in the jackpot gaming state is not set to "5" or "6," the table data at addresses 124B[H] and 124C[H] will be unused data. Thus, the areas at addresses 124B[H] and 124C[H] are areas where unused data is stored, unlike areas where data used by the CPU 103 to execute programs can be stored. The data stored at address 124D[H] is display data used for seven rounds in the jackpot gaming state, where the number of rounds is "7." The data stored at address 124E[H] is display data corresponding to eight rounds in the jackpot gaming state, where the number of rounds is "8." The data stored at address 124F[H] is display data corresponding to nine rounds in the jackpot gaming state, where the number of rounds is "9." Due to the specifications of the pachinko gaming machine 1, if the number of rounds in the jackpot gaming state is not set to "8" or "9", the table data at addresses 124E[H] and 124F[H] will be unused data. In this way, the areas at addresses 124E[H] and 124F[H] are areas where unused data is stored, and are different from areas where data used by the CPU 103 to execute programs can be stored. The data stored at address 1250[H] is display data used for 10 rounds when the number of rounds in the jackpot gaming state is "10".

The light-emitting element serving as the right-hit indicator or the round number indicator may include one or more light-emitting elements whose light-emitting state can be changed in response to the display data read from the right-hit round number display table XD_TOKU1. The light-emitting element serving as the right-hit indicator or the round number indicator may be capable of recognizably displaying the right-hit notification or round number corresponding to the jackpot game state based on the light-emitting state of the light-emitting element. Such light-emitting elements serving as the right-hit indicator or the round number indicator may correspond to a light-emitting means. In the right-hit round number display table XD_TOKU1, the table data at addresses 124B[H], 124C[H], 124E[H], and 124F[H] is unused data not used in program execution and is zero data with a storage value of 00[H]. Therefore, the areas at addresses 124B[H], 124C[H], 124E[H], and 124F[H] are included in a special memory area where unused data representing 0 is stored at special addresses. In this case, the unused data stored in the special memory area includes state-related data corresponding to a number of rounds that is different from the number of rounds that can be played in an advantageous state for the player, such as a jackpot game state.

Furthermore, as shown in Figure 11-6, the second reserved memory count display table XD_TMEM2 has address 1232[H] as the table data start address and address 123B[H] as the table data end address. The area from addresses 1232[H] to 123B[H] stores 4 bytes of zero data with a storage value of 00[H], and includes a normal storage area where usage data indicating 0 is stored at a normal address. The variable pattern command allocation selection table XP_TPAT_TBL has address 123C[H] as the table data start address and address 1247[H] as the table data end address. The area from addresses 123C[H] to 1247[H] stores 1 byte of zero data with a storage value of 00[H], and includes a normal storage area where usage data indicating 0 is stored at a normal address. In the solenoid pattern allocation selection table XP_YSOL_SEL, address 1251 [H] is the table data start address and address 1258 [H] is the table data end address. The area from addresses 1251 [H] to 1258 [H] stores two bytes of zero data with a storage value of 00 [H], and includes a normal storage area where use data indicating 0 is stored at a normal address.

In this way, the game data area includes a normal memory area in which zero data with a storage value of 00 [H] is stored and in which use data indicating 0 is stored at a normal address, and a special memory area in which unused data indicating 0 is stored at a special address. Furthermore, the use data stored in the normal memory area includes light-off control data that can be used to turn off the light-emitting means. The unused data stored in the special memory area includes state-related data corresponding to a number of rounds that is different from the number of rounds that can be executed in an advantageous state that is advantageous to the player.

In this case, the game data area includes a normal memory area in which 216 bytes of zero data are stored as use data, and a special memory area in which 19 bytes of zero data are stored as unused data. Furthermore, the normal memory area in which zero data with a storage value of 00 [H] is stored in the game data area and use data indicating 0 is stored at a normal address includes multiple areas to which discontinuous addresses are assigned. The special memory area in which zero data with a storage value of 00 [H] is stored in the game data area and unused data indicating 0 is stored at a special address includes multiple areas to which discontinuous addresses are assigned. Furthermore, the normal memory area in which zero data with a storage value of 00 [H] is stored in the game data area and use data indicating 0 is stored at a normal address is assigned a normal address so that there are no contiguous areas of more than a specific number of bytes, for example, 16 bytes. The special memory area in which zero data with a storage value of 00 [H] is stored in the game data area and unused data indicating 0 is stored at a special address is assigned a special address so that there are no contiguous areas of more than a specific number of bytes, for example, 16 bytes.

The usage data indicating 0 stored in the normal memory area may include table selection data that can be used as an offset value for setting a reference table address when selecting a table using various specified values or random number values. The usage data indicating 0 stored in the normal memory area may include fluctuation pattern determination data that can be used as an offset value for setting a reference fluctuation pattern when determining a fluctuation pattern using various specified values or random number values. Additionally, the usage data indicating 0 stored in the normal memory area may include determination value setting data that can be used to set a reference determination value when determining a control mode using various specified values or random number values.

Thus, the game data area includes an area in which use data indicating 0 is stored and an area in which unused data indicating 0 is stored. In the game data area, the area in which use data indicating 0 is stored may correspond to a normal memory area assigned a normal address. In the game data area, the area in which unused data indicating 0 is stored may correspond to a special memory area assigned a special address. The total memory capacity of the normal memory area in the game data area, in which use data indicating 0 is stored and assigned a normal address, is 216 bytes. The total memory capacity of the special memory area in the game data area, in which unused data indicating 0 is stored and assigned a special address, is 19 bytes. The total memory capacity of the unused area that becomes the unused memory area between the game program area corresponding to the first memory area and the game data area corresponding to the second memory area is 1069 bytes. The total memory capacity of the unused area that becomes the unused memory area between the game data area corresponding to the second memory area and the non-game program area and non-game data area corresponding to the third memory area is 1228 bytes. Therefore, the total storage capacity of the normal storage area, 216 bytes, is smaller than the total storage capacity of the unused storage area, 2297 bytes. Furthermore, the total storage capacity of the normal storage area and special storage area, 235 bytes, is smaller than the total storage capacity of the unused storage area, 2297 bytes. This increases the likelihood of distinguishing between unused areas and normal storage areas, enabling appropriate management of storage areas to prevent misidentification. Furthermore, this increases the likelihood of distinguishing between unused areas and normal storage areas and special storage areas, enabling appropriate management of storage areas to prevent misidentification.

The normal memory area in the game data area, which is assigned a normal address, includes multiple areas assigned discontinuous addresses. For example, the areas at addresses 121E[H], 121F[H], 1221[H], and 1223[H] shown in FIG. 11-7(A) and the areas at addresses 1228[H], 1229[H], 122B[H], and 122D[H] shown in FIG. 11-7(B) are all included in the normal memory area and may correspond to multiple areas assigned discontinuous addresses. In addition, in the area from address 1232[H], which is the table data start address and address 123B[H], which is the table data end address, where the table data of the second reserved memory count display table XD_TMEM2 is stored, the area where 4 bytes of zero data are stored as usage data is included in the normal memory area and may be included in multiple areas assigned addresses that are discontinuous with other normal memory areas in the game data area. In the area from address 123C [H], which is the table data start address and address 1247 [H], which is the table data end address, where the table data of the variable pattern command allocation selection table XP_TPAT_TBL is stored, the area where one byte of zero data is stored as use data is included in the normal memory area and can be included in multiple areas assigned addresses that are discontinuous with other normal memory areas provided in the game data area. In the area from address 1251 [H], which is the table data start address and address 1258 [H], which is the table data end address, where the table data of the solenoid pattern allocation selection table XP_YSOL_SEL is stored, the area where two bytes of zero data are stored as use data is included in the normal memory area and can be included in multiple areas assigned addresses that are discontinuous with other normal memory areas provided in the game data area. Therefore, the normal memory area in the game data area where normal addresses are assigned and use data indicating 0 is stored includes multiple areas assigned discontinuous addresses as normal addresses. This increases the likelihood of distinguishing between unused and regular storage areas, enabling appropriate storage area management to prevent misidentification.

A special memory area in the game data area that is assigned a special address includes multiple areas that are assigned discontinuous addresses. For example, the areas with addresses 124B[H], 124C[H], 124E[H], and 124F[H] shown in Figure 11-7(C) are all included in the special memory area and may correspond to multiple areas that are assigned discontinuous addresses. In addition, in an area where table data included in an arbitrary table is stored, an area where zero data is stored as unused data may be included in the special memory area and may be included in multiple areas that are assigned addresses that are discontinuous with other special memory areas in the game data area. Therefore, a special memory area in the game data area that is assigned a special address and stores unused data indicating 0 includes multiple areas that are assigned discontinuous addresses as special addresses. This increases the likelihood of distinguishing between unused areas, normal memory areas, and special memory areas, enabling appropriate memory area management to prevent misidentification.

Depending on the configuration of the table data stored in the game data area, the game data area may not have a normal memory area in which a normal address is assigned and usage data indicating 0 is stored. Also, depending on the configuration of the table data stored in the game data area, the game data area may not have a special memory area in which a special address is assigned and unused data indicating 0 is stored. In this way, depending on the specifications of the pachinko gaming machine 1, the game data area corresponding to the second memory area may not include a normal memory area in which a normal address is assigned and usage data indicating 0 is stored. Also, depending on the specifications of the pachinko gaming machine 1, the game data area corresponding to the second memory area may not include a special memory area in which a special address is assigned and unused data indicating 0 is stored.

Depending on the configuration of the table data stored in the game data area, for example, the area storing the table data for the normal reserved memory count display table XD_FMEM or the first reserved memory count display table XD_TMEM1 may not have a normal memory area to which a normal address is assigned and in which usage data indicating 0 is stored. Also, for example, the area storing the table data for the right-hit round count display table XD_TOKU1 may not have a special memory area to which a special address is assigned and in which unused data indicating 0 is stored. In this way, depending on the specifications of the pachinko gaming machine 1, the usage data stored in the normal memory area may not include light-off control data that can be used to turn off the light-emitting means. Also, depending on the specifications of the pachinko gaming machine 1, the unused data stored in the special memory area may not include state-related data corresponding to a number of rounds different from the number of rounds that can be executed in an advantageous state favorable to the player.

Figure 11-8 shows a dump list output example 003AKB01. The dump list outputs the storage contents of each area assigned an address in the address map, and can be displayed on any display device or printed on any printing device. The storage contents of memory areas such as ROM 101 are output in units of a specified data size, such as 16 bytes, using the dump list. In the dump list of output example 003AKB01, the multiple display lines representing the horizontal arrangement each correspond to different upper bytes of the address in the address map. In the dump list of output example 003AKB01, the multiple display columns representing the vertical arrangement each correspond to different lower bytes of the address in the address map. In this way, when the dump list is output corresponding to the upper and lower bytes of the address, the unit size of the program or data that can be displayed in one display line is 16 bytes.

In this case, unused areas capable of storing unused data, such as those between the game program area and the game data area, or between the game data area and the non-game program area or non-game data area, have a total storage capacity greater than a specific number of bytes, and all zero data with a storage value of 00 [H] is stored as unused data indicating 0. In a dump list such as output example 003AKB01, because the total storage capacity of the unused areas is greater than a specific number of bytes, zero data with a storage value of 00 [H] is displayed consecutively across multiple display lines, making it easy to identify unused areas. On the other hand, if consecutive addresses are assigned to areas in the game program area or game data area where zero data with a storage value of 00 [H] is stored, they may be displayed consecutively in the dump list, making it difficult to distinguish them from unused areas. Therefore, addresses are assigned to areas in the game program area or game data area where zero data with a storage value of 00 [H] is stored so that there are no consecutive areas with a storage value of more than a specific number of bytes.

The game program area includes a special memory area where unused data indicating 0 is stored at a special address. In this special memory area, the portion to which consecutive addresses are assigned is a maximum of 12 bytes from addresses 0062 [H] to 006D [H] in the area that stores table data contained in the interrupt vector table XTBL_INTR. In this way, special addresses are assigned to the special memory area so that no consecutive areas of 16 bytes or more (the specified number of bytes) are created. This makes it easy to distinguish between unused areas and special memory areas, and enables appropriate memory area management to prevent misidentification.

The game program area includes a predetermined memory area in which usage data indicating 0 is stored at a predetermined address. In this predetermined memory area, the portion to which consecutive addresses are assigned may be, for example, a two-byte area at addresses 0016[H] and 0017[H] that stores table data included in the power-off recovery vector table. In this way, the predetermined addresses are assigned so that there are no consecutive areas of 16 bytes or more, which is the specific number of bytes. This makes it easy to distinguish between unused area and predetermined memory area, and enables appropriate management of memory area to prevent misidentification.

The game data area includes a normal memory area in which usage data indicating 0 is stored at a normal address. In this normal memory area, the portion to which consecutive addresses are assigned may be, for example, the two-byte area at addresses 121E[H] and 121F[H] in the area storing table data included in the normal reserved memory count display table XD_FMEM, or the two-byte area at addresses 1228[H] and 1229[H] in the area storing table data included in the first reserved memory count display table XD_TMEM1. In this way, normal addresses are assigned to the normal memory area so that there are no consecutive areas of 16 bytes or more, which is the specific number of bytes. This makes it easy to distinguish between unused and normal memory areas, preventing misidentification and enabling appropriate memory area management.

The game data area includes a special memory area where unused data indicating 0 is stored at a special address. In this special memory area, the portion assigned consecutive addresses may be, for example, the two-byte area at addresses 124B[H] and 124C[H] or the two-byte area at addresses 124E[H] and 124F[H] in the area storing table data included in the right-hand hit round count display table XD_TOKU1. In this way, the special memory area is assigned specific addresses so that there are no consecutive areas of 16 bytes or more, which is the specific number of bytes. This makes it easy to distinguish between unused areas and special memory areas, and enables appropriate memory area management to prevent misidentification.

The game data area includes a normal memory area where used data indicating 0 is stored at a normal address, and a special memory area where unused data indicating 0 is stored at a special address. Therefore, depending on the layout of the normal memory area and special memory area, it may be difficult to distinguish between the game data area and adjacent unused areas. Therefore, the game data area stores data indicating values other than 0 at its start and end addresses. For example, since the game data area is the area from addresses 1200 [H] to 1D33 [H], non-zero data with a storage value other than 00 [H] is stored at the start address 1200 [H], and non-zero data with a storage value other than 00 [H] is stored at the end address 1D33 [H]. In a dump list such as output example 003AKB01, the storage value at address 1200 [H], which is the start address of the game data area, is set to 08 [H], which is not 00 [H], and the storage value at address 1D33 [H], which is the end address of the game data area, is set to 02 [H], which is not 00 [H], so that data other than 0 is stored. This makes it easy to distinguish between the unused areas located before and after the game data area and the game data area, and enables appropriate storage area management to prevent misidentification.

Furthermore, the game data area stores data other than 0 in the address following the start address and the address preceding the end address. For example, the start address of the game data area is 1200 [H], so the next address, 1201 [H], stores non-zero data with a value other than 00 [H]. The end address of the game data area is 1D33 [H], so the previous address, 1D32 [H], stores non-zero data with a value other than 00 [H]. In a dump list like output example 003AKB01, the start address of the game data area is 1200 [H], the next address, 1201 [H], stores a value of 10 [H] other than 00 [H], the end address of the game data area is 1D33 [H], and the previous address, 1D32 [H], stores a value of 2B [H] other than 00 [H], allowing data other than 0 to be stored. In this way, the game data area stores data other than 0 in a two-byte area that is consecutive from the start address up to and including the start address, and in a two-byte area that is consecutive from the end address up to and including the end address. This makes it easier to distinguish between the game data area and the unused areas located before and after the game data area, enabling appropriate management of memory areas to reliably prevent misidentification.

In addition, the area is not limited to a contiguous two-byte area, and data indicating a value other than 0 may be stored in an area to which multiple contiguous addresses are assigned after a start address (including the start address) of the game data area, and in an area to which multiple contiguous addresses are assigned before an end address (including the end address) of the game data area. For example, a non-zero range including multiple addresses may be set in advance, and data indicating a value other than 0 may be stored in an area to which the non-zero range is assigned after a start address (including the start address) of the game data area and in an area to which the non-zero range is assigned before an end address (including the end address) of the game data area. In this case, the non-zero range set in association with the start address of the game data area and the non-zero range set in association with the end address of the game data area may have address ranges of different sizes. For example, as a non-zero range including multiple addresses, a post-start non-zero range and a pre-end non-zero range, which has an address range of a different size from the post-start non-zero range, may be set in advance. Data indicating values other than 0 may be stored in a post-start non-zero range area after the start address including the start address of the game data area, and in a pre-end non-zero range area before the end address including the end address of the game data area. As with the game data area, program code and data indicating values other than 0 may be stored in non-zero range areas set up corresponding to the start address and end address of any memory area in the memory area of ROM 101 that is not an unused area, such as the game program area, non-game program area, and non-game data area. However, in accordance with settings based on the specifications of the pachinko gaming machine 1, there may be a memory area, such as the program management area, in which zero data with a storage value of 00 [H] is stored in a zero setting range area before the end address including the end address.

The total storage capacity of the first storage area, the total storage capacity of the second storage area, the total storage capacity of the unused storage area, the total storage capacity of the special storage area, the total storage capacity of the normal storage area, and the total storage capacity of the normal storage area and special storage area can be changed as desired to correspond to the specifications of the pachinko gaming machine 1. However, the total storage capacity of the first storage area only needs to be greater than the total storage capacity of the unused storage area between the first storage area and the second storage area that can store unused data. The total storage capacity of the special storage area only needs to be less than the total storage capacity of the unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area that can store unused data. The total storage capacity of the normal storage area only needs to be less than the total storage capacity of the unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area that can store unused data. The total storage capacity of the normal storage area and the special storage area must be smaller than the total storage capacity of the unused storage areas capable of storing unused data between the first storage area and the second storage area, and between the second storage area and the third storage area.

Special memory areas, predetermined memory areas, normal memory areas, and special memory areas may be assigned addresses so that there are no contiguous areas of any particular number of bytes or more, not limited to 16 bytes. For example, the particular number of bytes may be a number other than 16 bytes, such as 8 bytes, 32 bytes, or 64 bytes. Special memory areas, predetermined memory areas, normal memory areas, and special memory areas may be assigned addresses so that there are no contiguous areas of any particular number of bytes or more, which makes it easy to recognize that they are memory areas different from unused memory areas, for example, when displaying a dump list.

(Means for solving the problems and effects of characteristic part 003AK)
[1-1] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means for controlling the progress of the game by a program stored in the storage means;
The storage means is
a first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
an unused storage area between the first storage area and the second storage area, capable of storing unused data;
The unused storage area stores unused data that indicates all 0s.
The total storage capacity of the first storage area is greater than the total storage capacity of the unused storage area,
the first storage area includes a special storage area in which unused data indicating 0 is stored at a special address;
The total storage capacity of the special storage area is smaller than the total storage capacity of the unused storage area,
The special storage area includes a plurality of areas to which discontinuous addresses are assigned as special addresses.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a game program area. The second storage area may be, for example, a game data area. The unused storage area may be, for example, an unused area at addresses 0BD3 [H] to 11FF [H]. The total storage capacity of the first storage area may be, for example, 3027 bytes. The total storage capacity of the unused storage area may be, for example, 1069 bytes. The special storage area may be, for example, a storage area for unused data in setting example 003AKA01. The total storage capacity of the special storage area may be, for example, 19 bytes. The discontinuous addresses may be, for example, storage addresses of unused data in setting example 003AKA01.
According to this configuration, discontinuous addresses are assigned as special addresses in which unused data is stored in the special storage area, and since the special storage area has a smaller total storage capacity than the unused storage area, appropriate management of the storage area becomes possible so as to prevent the special storage area from being mistaken for an unused storage area.

[1-2] The special storage area may be assigned a special address so that no area of a specific number of bytes or more is consecutive.
Here, the specific number of bytes may be, for example, 16 bytes.
In this configuration, when the dump list is displayed, it is possible to appropriately manage the storage area so that the special storage area can be prevented from being mistaken for an unused storage area.

[1-3] The control means
a first call instruction for calling a program stored at a specified address by specifying the address;
a second call instruction that calls a program stored at a specific address corresponding to the specified parameter among a plurality of specific addresses allocated at predetermined intervals by specifying a parameter having a data amount smaller than that of the address;
The special storage area may include an area in which unused data is stored, from one specific address to the next specific address included in the plurality of specific addresses.
Here, the first call instruction may be, for example, a CALL instruction, the second call instruction may be, for example, a RST instruction, and the specific address may be, for example, a restart address.
In such a configuration, unused data is stored so as to prevent the special storage area from being mistaken for an unused storage area, thereby enabling appropriate management of storage areas.

[1-4] The storage means includes an address storage area capable of storing addresses of the interrupt processing program,
The special storage area may include an area in the address storage area where unused data is stored.
Here, the interrupt processing program may be, for example, a program that processes a timer interrupt P_PCT for game control. The address storage area may be, for example, an area from addresses 0060[H] to 006D[H] that stores table data included in the interrupt vector table XTBL_INTR. The area in the address storage area where unused data is stored may be, for example, an area from addresses 0062[H] to 006D[H].
In such a configuration, unused data is stored so as to prevent the special storage area from being mistaken for an unused storage area, thereby enabling appropriate management of storage areas.

[1-5] The first storage area includes a predetermined storage area in which usage data indicating 0 is stored at a predetermined address,
The predetermined storage area may include a plurality of areas to which discontinuous addresses are assigned as the predetermined addresses.
Here, the specified address may be, for example, addresses 0016 [H] and 0017 [H] of the table data included in the vector table at the time of power failure recovery, an address where the usage data used in step AKS34 of the power failure processing P_POWER_OFF is stored, or an address where the usage data used in step AKS42 of the power failure processing P_POWER_OFF is stored.
In such a configuration, usage data indicating 0 is stored so that a predetermined storage area can be prevented from being mistaken for an unused storage area, thereby enabling appropriate management of storage areas.

[1-6] The usage data stored in the predetermined storage area may include address designation data that enables startup processing based on startup of the gaming machine to be executed from the beginning.
Here, the startup process may be, for example, the main process P_MAIN for game control, etc. The address designation data may be, for example, zero data with a stored value of 00 [H] in the vector table when power is restored after a power outage.
In such a configuration, usage data indicating 0 is stored so that a predetermined storage area can be prevented from being mistaken for an unused storage area, thereby enabling appropriate management of storage areas.

[2-1] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means for controlling the progress of the game by a program stored in the storage means;
The storage means is
a first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, the unused storage area being capable of storing unused data;
The unused storage area stores unused data that indicates all 0s.
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
the second storage area includes a normal storage area in which use data indicating 0 is stored at a normal address;
The total storage capacity of the normal storage area is smaller than the total storage capacity of the unused storage area.
The normal storage area may include a plurality of areas to which discontinuous addresses are assigned as normal addresses.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a gaming program area. The second storage area may be, for example, a gaming data area. The third storage area may be, for example, a non-gaming program area and a non-gaming data area. The unused storage area may be, for example, an unused area from addresses 0BD3 [H] to 11FF [H] and an unused area from addresses 1D34 [H] to 1FFF [H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of the unused storage area may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area for zero data, which is used data in setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes. The non-consecutive addresses may be, for example, storage addresses of zero data that is used data in the setting example 003AKA01.
According to this configuration, discontinuous addresses are assigned as normal addresses where used data is stored in the normal storage area, and since the normal storage area has a smaller total storage capacity than the unused storage area, appropriate management of the storage area becomes possible so as to prevent the normal storage area from being mistaken for an unused storage area.

[2-2] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means for controlling the progress of the game by a program stored in the storage means;
The storage means is
a first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, the unused storage area being capable of storing unused data;
The unused storage area stores unused data that indicates all 0s.
The total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area,
The second storage area is
a normal storage area in which use data indicating 0 is stored at a normal address;
a special storage area in which unused data indicating 0 is stored at a special address;
The total storage capacity of the normal storage area and the special storage area is smaller than the total storage capacity of the unused storage area,
The normal storage area includes a plurality of areas to which discontinuous addresses are assigned as normal addresses,
The special storage area may include a plurality of areas to which discontinuous addresses are assigned as special addresses.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a gaming program area. The second storage area may be, for example, a gaming data area. The third storage area may be, for example, a non-gaming program area and a non-gaming data area. The unused storage area may be, for example, an unused area from addresses 0BD3 [H] to 11FF [H] and an unused area from addresses 1D34 [H] to 1FFF [H]. The total storage capacity of the second storage area may be, for example, 2868 bytes. The total storage capacity of the unused storage area may be, for example, 2297 bytes. The normal storage area may be, for example, a storage area for zero data, which is used data in setting example 003AKA11. The special storage area may be, for example, a storage area for zero data, which is unused data in setting example 003AKA11. The total storage capacity of the normal storage area may be, for example, 216 bytes. The total storage capacity of the special storage area may be, for example, 19 bytes. The discontinuous addresses as normal addresses may be, for example, storage addresses of zero data that become used data in setting example 003AKA11. The discontinuous addresses as special addresses may be, for example, storage addresses of zero data that become unused data in setting example 003AKA11.
According to this configuration, discontinuous addresses are assigned as normal addresses where used data is stored in the normal storage area, and discontinuous addresses are assigned as special addresses where unused data is stored in the special storage area.Furthermore, since the normal storage area and the special storage area have a smaller total storage capacity than the unused storage area, appropriate management of storage areas becomes possible so as to prevent the normal storage area and the special storage area from being mistaken for unused storage areas.

[2-3] The usage data stored in the normal storage area may include extinguishing control data that can be used to extinguish the light-emitting means.
Here, the light emitting means may be, for example, the first and second light emitting units in the normal symbol display device 20, the first and second light emitting units in the first special symbol display device 4A, etc. The light-off control data may be, for example, zero data that sets the storage value to 00 [H] in the normal symbol reserved memory number display table XD_FMEM, or zero data that sets the storage value to 00 [H] in the first reserved memory number display table XD_TMEM1.
In such a configuration, usage data indicating 0 is stored so that normal storage areas are prevented from being mistaken for unused storage areas, and appropriate management of storage areas becomes possible.

[2-4] The unused data stored in the special storage area may include state-related data corresponding to a number of rounds that is different from the number of rounds that can be executed in an advantageous state that is advantageous to the player.
Here, the advantageous state may be, for example, a jackpot game state, etc. The state-related data may be, for example, zero data in which the storage value is 00 [H] in the right-hit round number display table XD_TOKU1.

[2-5] Normal addresses are assigned to normal storage areas so that no areas of more than a specific number of bytes are consecutive.
The special storage area may be assigned a special address so that no area having a specific number of bytes or more is continuous.
Here, the specific number of bytes may be, for example, 16 bytes.
In such a configuration, when the dump list is displayed, it is possible to appropriately manage the storage areas so that the normal storage areas and special storage areas can be prevented from being mistaken for unused storage areas.

[3-1] A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means for controlling the progress of the game by a program stored in the storage means;
The storage means is
a first storage area in which a program related to game control is stored;
a second storage area in which data used for executing the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, the unused storage area being capable of storing unused data;
The unused storage area stores unused data that indicates all 0s.
The second storage area is
The usage data indicating 0 is stored at the normal address,
Data indicating a value other than 0 may be stored at the start address and end address.
Here, the gaming machine may be, for example, a pachinko gaming machine 1. The storage means may be, for example, a ROM 101. The control means may be, for example, a CPU 103. The first storage area may be, for example, a gaming program area. The second storage area may be, for example, a gaming data area. The third storage area may be, for example, a non-gaming program area and a non-gaming data area. The unused storage area may be, for example, an unused area from addresses 0BD3 [H] to 11FF [H] and an unused area from addresses 1D34 [H] to 1FFF [H]. The normal address may be, for example, a storage address of zero data that becomes the used data in setting example 003AKA11. The start address may be, for example, address 1200 [H]. The end address may be, for example, address 1D33 [H].
This configuration enables appropriate management of storage areas so that the second storage area can be prevented from being mistaken for an unused storage area.

[3-2] The second storage area may store data indicating a value other than 0 at the address next to the start address and the address before the end address.
Here, the address next to the start address may be, for example, address 1201 [H], and the address before the end address may be, for example, address 1D32 [H].
In this configuration, it is possible to appropriately manage storage areas so as to prevent the second storage area from being mistaken for an unused storage area.

1 ... Pachinko gaming machine 4A ... First special symbol display device 4B ... Second special symbol display device 11 ... Main board 12 ... Performance control board 100 ... Game control microcomputer 101 ... ROM
102...RAM
103...CPU
104, 104A, 104B ... random number circuit

Claims (1)

A gaming machine capable of playing games,
a storage means capable of storing a program;
a control means for controlling the progress of the game by the program stored in the storage means;
The storage means
a first storage area in which a program related to game control is stored;
a second storage area in which usage data used in the execution of the program is stored;
a third storage area different from the first storage area and the second storage area;
an unused storage area between the first storage area and the second storage area and between the second storage area and the third storage area, in which unused data can be stored;
the unused data stored in the unused storage area is zero data indicating all 0;
the total storage capacity of the second storage area is greater than the total storage capacity of the unused storage area;
The second storage area is
The use data includes a normal storage area in which the zero data is stored,
the total storage capacity of the normal storage areas is smaller than the total storage capacity of the unused storage areas,
the normal storage area includes an area in which a plurality of the zero data are stored and to which discontinuous addresses are assigned,
a second unused storage area between the second storage area and the third storage area has a storage capacity greater than a specific number of bytes ;
A gaming machine, wherein one of the areas in which the plurality of zero data are stored and to which discontinuous addresses are assigned, included in the second memory area , has a memory capacity smaller than the specific number of bytes .