JP7501438B2 - Method for manufacturing SOI wafer - Google Patents

Description

The present invention relates to a method for manufacturing an SOI wafer and an SOI wafer.

SOI wafers (Silicon on Insulator) are known as semiconductor wafers. SOI wafers have a structure in which an insulating film such as silicon oxide (SiO ₂ ) and a single crystal silicon layer used as a device active layer (sometimes called an "active layer" or an "SOI layer") are sequentially formed on a support substrate. SOI wafers are classified according to the thickness of their active layer, with those with an active layer thickness of 1 μm or more being called "thick film SOI" and those with an active layer thickness of less than 1 μm being called "thin film SOI". In general, thick film SOI is used in power devices, BiCMOS, etc., and thin film SOI is used in CMOS-LSI, etc.

Here, the SmartCut method (registered trademark) and the bonding method are known as typical manufacturing methods for SOI wafers. In the SmartCut method, hydrogen ions are implanted at a high concentration into a silicon substrate for the active layer to form an embrittled layer. Next, the silicon substrate is peeled off at the embrittled layer to form an active layer, and the peeled active layer is bonded to a support substrate via an oxide film to produce an SOI wafer (for example, Patent Document 1). The SmartCut method is a technology that can only be applied to thin-film SOI manufacturing because it is not possible to implant hydrogen ions from the wafer surface to a deep position inside the wafer and therefore is not possible to obtain a thick active layer. On the other hand, the bonding method forms an oxide film (also called a "BOX (Buried Oxide) layer") on at least one of the support substrate and the active layer substrate, and then these substrates are stacked together via the oxide film, and then a bonding heat treatment is performed at a high temperature of about 1200 ° C to produce an SOI wafer (for example, Patent Document 2). The bonding method involves bonding two silicon wafers together with an oxide film between them, so the thickness of the active layer produced can be adjusted as desired, and is therefore commonly used in the manufacture of thick-film SOI.

JP 5-211128 A JP 8-250688 A

By the way, the non-SOI region at the periphery of the SOI wafer, i.e., the part where the support substrate or oxide film is exposed outside the outer edge of the active layer, is called the "terrace portion." The width of the terrace portion is called the "terrace width" (JEITA EM-3604A).

Here, FIG. 1(A) is an optical microscope photograph of a thin-film SOI wafer produced by a general smart cut method before final polishing, and is an enlarged photograph of the peripheral portion including the boundary between the active layer and the terrace portion. The terrace width of a thin-film SOI wafer is generally more than 2 mm and less than 3 mm even before final polishing. Also, as shown in FIG. 1(A), the boundary between the active layer and the oxide film becomes a distorted line, and multiple dot-like protrusions (called SOI islands) are formed on the terrace portion. Such boundaries and SOI islands cause contamination during device formation. For this reason, the terrace portion is subjected to final polishing, but as shown in the photograph after final polishing shown in FIG. 1(B), the boundary does not become a circle, and undulations remain, and the final terrace width also increases to 3 mm or more (in FIG. 1(B), the terrace width after final polishing is about 4 to 5 mm).

In order to increase the effective area that can be used for device formation, the edge exclusion of semiconductor wafers has been increasing from 3 mm from the wafer edge to 2 mm, and there is also a demand to reduce it to 1 mm. It is expected that the edge exclusion will also be reduced in thin-film SOI, but to achieve this, the terrace width must be reduced. However, as mentioned above, the terrace width of thin-film SOI wafers produced by the Smart Cut method is wide, and the bonding strength at the outer periphery of the active layer is low, making it difficult to reduce the terrace width to 2 mm or less. In fact, even if additional terrace polishing is performed on the outer periphery to remove the SOI islands, the terrace width increases from 2 mm to 3 to 4 mm, and undulations are formed.

In order to achieve a narrower terrace width for thin-film SOI wafers, the inventor attempted to apply the bonding method applied to thick-film SOI wafers instead of the smart cut method conventionally used in the manufacture of thin-film SOI. Specifically, the inventor investigated whether it would be possible to manufacture thin-film SOI wafers with an active layer thickness of less than 1 μm using the bonding method.

The inventors attempted to thin the active layer by lamination when the terrace width was set to 2 mm, which is narrower than the lower limit of the terrace width in the Smart Cut method. However, the inventors newly confirmed that in this case, part of the active layer was completely removed in the thickness direction, exposing the oxide film.

The present invention aims to provide a method for manufacturing an SOI wafer that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method, and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method.

As a result of extensive investigations aimed at solving the above problems, the present inventors have obtained the following findings.
(A) First, in order to make the thickness of the active layer of the SOI wafer by the bonding method less than 1 μm so as not to expose the oxide film, it is necessary to grind the substrate for the active layer with high precision, so it is considered that the application of the dry chemical planarization (DCP) processing method using local plasma etching is suitable at least in the final stage of thinning. The DCP processing method uses local plasma etching, so the surface roughness is inferior to that of a normal polished surface. Therefore, after the DCP processing, the surface of the substrate for the active layer is subjected to finish polishing.

(B) However, it was experimentally confirmed that when the DCP processing and finish polishing were performed with a terrace width of 2 mm, the oxide film was exposed at the edge of the active layer in the area where the active layer was located before the finish polishing. Even when the terrace width was set to 3 mm, assuming the extension of the edge exclusion area to be false, the oxide film was similarly exposed. After detailed investigation of the cause of this, the inventor believed that the shape of the SOI wafer before the finish polishing caused the pressure from the pad to be greater at the edge of the active layer during the finish polishing compared to the center of the active layer, resulting in excessive removal of the edge of the active layer.

(C) Therefore, by optimizing the shape of the SOI wafer before the final polishing, the pressure from the pad at the end of the active layer can be suppressed, and as a result, the exposure of the oxide film can be prevented. As for the shape of the SOI wafer, the terrace width before the final polishing is a particularly important index.
The present invention is based on the above findings and studies, and has the following gist and configuration.

The method for producing an SOI wafer of the present invention includes an oxide film forming step of forming an oxide film on at least one surface of a substrate for active layer made of a silicon single crystal and a support substrate made of a silicon single crystal;
a bonding step of bonding the active layer substrate and the support substrate via the oxide film;
a thinning step of thinning the active layer substrate from a surface opposite to the support substrate after the bonding step,
the thinning step includes a first step of flattening the surface of the active layer substrate by dry chemical etching, and a second step of polishing the surface of the active layer substrate to form an active layer having a thickness of less than 1 μm;
Prior to the second step, the width of a region where the oxide film or the support substrate is exposed outward from the outer edge of the active layer substrate in a top view is set to 1.5 mm or less in a radial direction from the end face of the SOI wafer.

Here, it is preferable that the thickness of the active layer is 0.3 μm or more.

In addition, the method for producing an SOI wafer of the present invention further includes, between the bonding step and the thinning step, a chamfering step of chamfering an end face of the active layer substrate so that a peripheral portion on the support substrate side remains, a wet etching step following the chamfering step of wet-etching the remaining portion to expose a part of the oxide film, and a removal step following the wet etching step of removing the peripheral portion of the oxide film, wherein it is preferable that, in the removal step, the width is 1.5 mm or less, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (1):
Record
T≧0.36W+0.32 ... (1)

On the other hand, the method for producing an SOI wafer of the present invention further includes, between the bonding step and the thinning step, a surface grinding step of grinding the surface of the active layer substrate, and a peripheral portion polishing step of polishing a peripheral portion of the active layer substrate from an oblique direction relative to a main surface of the active layer substrate following the surface grinding step, and it is preferable that, in the peripheral portion polishing step, the width is 1.5 mm or less, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (2):
Record
T≧0.54W+0.24 ... (2)

In addition, the method for producing an SOI wafer of the present invention preferably further includes an edge grinding step between the bonding step and the thinning step, in which the edges of the bonded active layer substrate and support substrate are ground to form a continuous rounded or tapered surface via the oxide film.

The SOI wafer of the present invention has a support substrate made of single crystal silicon, an oxide film located on the support substrate, and an active layer made of single crystal silicon located on the oxide film, the active layer having a thickness of less than 1 μm, and the width of the region where the oxide film or the support substrate is exposed outward from the outer edge of the active layer in a top view is 1.5 mm or less in the radial direction from the end face of the SOI wafer.

Here, it is preferable that the thickness of the active layer is 0.3 μm or more.

In the SOI wafer of the present invention, it is preferable that the support substrate and the oxide film are arranged in a stepped manner at the peripheral portion of the SOI wafer, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (1):
Record
T≧0.36W+0.32 ... (1)

On the other hand, in the SOI wafer of the present invention, it is preferable that the support substrate is exposed at the peripheral portion of the SOI wafer, the ends of the oxide film and the active layer are continuous rounded or tapered surfaces, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (2):
Record
T≧0.54W+0.24 ... (2)

In addition, in the SOI wafer of the present invention, it is preferable that the ends of the active layer and the supporting substrate have continuous rounded or tapered surfaces through the oxide film.

The method for manufacturing an SOI wafer of the present invention can provide a method for manufacturing an SOI wafer that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method, and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method.

1A and 1B are photographs showing the vicinity of a terrace portion of an SOI wafer produced by the Smart Cut method according to the conventional technology, in which (A) is an optical microscope photograph of the vicinity of the terrace portion before finish polishing, and (B) is a photograph of the vicinity of the terrace portion after finish polishing. 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to an embodiment of the present invention. 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to a first preferred embodiment of the present invention. FIG. 2 is a schematic cross-sectional view illustrating a second step of finish polishing in the method for producing an SOI wafer according to the first preferred embodiment of the present invention. 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to a second preferred embodiment of the present invention. FIG. 11 is a schematic cross-sectional view illustrating a second step of finish polishing in a method for producing an SOI wafer according to a second preferred embodiment of the present invention. 11A to 11C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to a third preferred embodiment of the present invention. FIG. 13 is a schematic cross-sectional view illustrating a second step of finish polishing in a method for producing an SOI wafer according to a third preferred embodiment of the present invention. 1 is a graph showing the relationship between the terrace width and the thickness of the active layer in Experimental Examples 1 to 3. 6A and 6B are photographs of the vicinity of the terrace portion after finish polishing in Experimental Example 3, and 6C and 6D are photographs of the vicinity of the terrace portion after finish polishing in Experimental Example 2.

Embodiments of the present invention will be described below with reference to the drawings. Note that for ease of explanation, the thickness and width of each component are shown in Figs. 2 to 8 in an exaggerated manner, rather than in accordance with the actual thickness ratio.

(Method of Manufacturing SOI Wafer)
A method for manufacturing an SOI wafer according to one embodiment of the present invention will be described with reference to Fig. 2. The method for manufacturing an SOI wafer 100 according to one embodiment of the present invention includes an oxide film forming step (Figs. 2(A) and (B)) of forming an oxide film 11A on at least one surface of an active layer substrate 10A made of silicon single crystal and a support substrate 20 made of silicon single crystal, a bonding step (Fig. 2(C)) of bonding the active layer substrate 10A and the support substrate 20 via the oxide film 11A, and a thinning step (Figs. 2(D) and (E)) of thinning the active layer substrate 10A from the surface opposite to the support substrate 20 after the bonding step. For convenience of illustration, the oxide film 11A is formed on the active layer substrate 10A in Fig. 2, but an oxide film may be formed on the support substrate 20, or an oxide film may be formed on both the active layer substrate 10A and the support substrate 20.

Here, in this embodiment, the thinning process includes a first process of flattening the surface of the active layer substrate 10C by dry chemical etching, and a second process of polishing the surface of the active layer substrate 10C to form an active layer 10 having a thickness of less than 1 μm (FIGS. 2(D) and (E)). Prior to this second process, the width W of the region where the oxide film 11 or the support substrate 20 is exposed outward from the outer edge of the active layer substrate in a top view is set to 1.5 mm or less in the radial direction from the end face of the SOI wafer 100. FIG. 2(E) is a schematic cross-sectional view of the SOI wafer 100 obtained as a result of this manufacturing method. Hereinafter, the width of the region where the oxide film 11 or the support substrate 20 is exposed outward from the outer edge of the active layer substrate in a top view is referred to as the "terrace width". In addition, in this specification, the "end face of the SOI wafer" means the outermost circumference when the SOI wafer is viewed from the top. Below, the details of each process will be explained in order.

First, as shown in FIG. 2(A), an active layer substrate 10A is prepared. A single crystal silicon wafer made of a silicon single crystal is used as the active layer substrate 10A. The single crystal silicon wafer can be one obtained by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) with a wire saw or the like. In addition, any impurity dopant element may be added to make it n-type or p-type.

In addition, as shown in FIG. 2(A), a support substrate 20 is prepared separately from the active layer substrate 10A. The support substrate 20 is a wafer used as a support substrate for the SOI wafer 100, and may be a single crystal silicon wafer similar to the active layer substrate 10A. The active layer substrate 10A and the support substrate 20 may have different conditions such as oxide concentration and conductivity type, or may be the same.

Next, as shown in FIG. 2B, an oxide film 11A is formed on the active layer substrate 10A by, for example, heat treatment in an oxidizing atmosphere. In the figure, the oxide film 11A is formed on the entire surface of the active layer substrate 10A, but the oxide film may be formed only on one side of the active layer substrate 10A. As described above, the oxide film may be formed on the support substrate 20, or on both the active layer substrate 10A and the support substrate 20. The oxide film 11A is made of, for example, a silicon oxide film (SiO ₂ ), and can be formed using a commonly used thermal oxide film forming device. The thickness of the oxide film 11A can be appropriately set within a range that allows it to be used as an SOI. Although not intended to be limiting, the thickness of the oxide film 11A located between the active layer substrate 10A and the support substrate 20 can be, for example, 0.1 to 10 μm, or can be 10 to 30 μm.

Next, as shown in FIG. 2(C), the active layer substrate 10A and the support substrate 20 are bonded together via the oxide film 11A so that the oxide film 11A is located between the active layer substrate 10A and the support substrate 20. This bonding can be performed using a general wafer bonding device. After this bonding, it is also preferable to perform a heat treatment to strengthen the bonding strength of the bonded joint. The bonding strengthening heat treatment can be performed, for example, in an oxidizing gas or inert gas atmosphere at 800°C to 1200°C for 10 minutes to 6 hours.

Next, in order to form the final active layer 10 (see FIG. 2(E)), a thinning process is performed to thin the active layer substrate 10A from the side opposite the support substrate 20 (FIGS. 2(D) and (E)). This thinning process includes a first process of dry chemical etching the active layer substrate 10C to flatten the surface, and a second process of polishing the surface of the active layer substrate 10C to form an active layer 10 with a thickness T of less than 1 μm. Prior to this first process, the active substrate 10A may be subjected to a well-known surface grinding method or mirror polishing method.

Here, in the first step, DCP processing (dry chemical planarization) is performed. In DCP processing, etching gas is turned into plasma by microwaves to generate ions and reactive radicals, and localized plasma etching is performed using the radicals as the main etchant. Then, when scanning the injection nozzle during plasma etching, the thickness is measured and the stage speed is changed while injecting the etching gas, thereby performing localized processing with high precision. This type of DCP processing can be performed using a general DCP processing machine. This DCP processing can reduce the tolerance of the active layer thickness.

DCP processing in the first step uses local plasma etching, and therefore has inferior surface roughness compared to mechanical polishing, chemical mechanical polishing (CMP), and other polishing methods. Therefore, in the second step, the active layer substrate 10C is finish-polished to form the active layer 10. The thickness T of the active layer 10 after the finish polishing is set to less than 1 μm. The thickness of the active layer substrate may be set to less than 1 μm at the stage after the DCP processing. The polishing allowance by the finish polishing is usually about 0.05 μm to 0.30 μm, and the surface roughness can be improved by the finish polishing. Either double-sided polishing or single-sided polishing can be used for the finish polishing, but single-sided polishing is more preferable.

Here, it is essential that the terrace width W is 1.5 mm or less at least prior to the second step. The terrace width W may be set to the above range prior to the first step. This is because in the DCP processing in the first step, the thickness of the active layer substrate 10C is measured in advance, and the DCP processing is performed based on the measurement results, so there is almost no effect on the terrace width after processing. To make the terrace width T 1.5 mm or less, known chamfer etching methods, terrace polishing methods, and terrace-free wafer fabrication methods can be applied.

According to the inventor's study, it was experimentally confirmed that if the terrace width T is 1.5 mm or less when the second step is performed, even if the thickness T of the active layer 10 after the second step of finish polishing is less than 1 μm, the oxide film 11 will not be exposed. Note that "the oxide film is not exposed" does not mean that the oxide film was exposed before the finish polishing, but rather that the portion that was not exposed before the finish polishing was exposed after the finish polishing.

Contrary to the inventor's expectations, in the second step, by narrowing the terrace width T to 1.5 mm or less rather than widening it, thinning of the thin-film SOI by the lamination method was realized. The inventor believes that this is because, when the active layer is very thin, less than 1 μm, if the terrace width exceeds 1.5 mm just before the finish polishing, the polishing pad sinks into the periphery of the SOI wafer, and the pressure applied to the periphery increases, resulting in more of the active layer being ground away. On the other hand, the inventor believes that, when the terrace width is 1.5 mm or less just before the finish polishing, the active layer, oxide film, and support substrate have a relatively smooth shape when the periphery of the SOI wafer is viewed macroscopically, and the pressure applied to the edge of the active layer is reduced.

As described above, this embodiment can provide a method for manufacturing an SOI wafer that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method, and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method. Preferred embodiments of this embodiment will be described below in order.

(First Preferred Embodiment)
In the first preferred embodiment, in order to make the terrace width T 1.5 mm or less, a so-called "chamfering etching method" is performed prior to the thinning process. That is, as shown in FIG. 3, it is preferable to perform a chamfering process for chamfering the edge of the active layer substrate 10A so that the peripheral portion of the support substrate side 20 remains between the lamination process and the thinning process. After the active layer substrate 10A is chamfered, it becomes the active layer substrate _10B1 as shown in FIG. 3(B). With this chamfering, the oxide film 11A is removed and the active layer substrate _10B1 is separated into an oxide film 11C on the upper surface side and an oxide film 11B on the lower surface side.

Following this chamfering step, as shown in FIG. 3(C), it is preferable to carry out a wet etching step in which the remaining portion of the active layer substrate 10B ₁ on the support substrate side is wet etched to expose a part of the oxide film 11B. After the etching step, the active layer substrate 10B ₂ is formed. Following the wet etching step, a removal step is carried out to remove the peripheral portion of the oxide film 11B (FIG. 3(D)). A general polishing or grinding method can be applied to this removal step, and it is preferable to set the terrace width to 1.5 mm or less in this removal step. Finally, by carrying out the thinning step described above, a thin-film SOI wafer with an active layer thickness of less than 1 μm can be produced (FIG. 3(E)).

In this preferred embodiment, it is preferable to carry out the removal step so that W and T satisfy the following formula (1), where W (mm) is the terrace width and T (μm) is the active layer thickness.
T≧0.36W+0.32 ... (1)
By making the terrace width and the active layer thickness satisfy the formula (1), a thin-film SOI wafer in which the oxide film is not exposed can be realized more reliably.

In this preferred embodiment, as shown in Figures 4(A) to (C), the terrace width during finish polishing is 1.5 mm or less, so that the sinking of the polishing pad P at the periphery of the SOI wafer 200 during finish polishing can be suppressed, and even after forming an active layer 10 with a thickness of less than 1 μm, new exposure of the oxide film 11 can be prevented. However, depending on the polishing conditions, if the terrace width exceeds 1.5 mm or T and W do not satisfy the above formula (1), as shown in Figure 4(D), the terrace width of the SOI wafer 200' to be produced may be W' (W'>W), and the peripheral portion of the active layer 10 may be excessively removed, resulting in exposure of the oxide film 11.

(Second Preferred Embodiment)
In the second preferred embodiment, in order to make the terrace width 1.5 mm or less, a so-called "terrace polishing method" is performed prior to the thinning step. That is, as shown in Fig. 5, it is preferable to first perform a surface grinding step of grinding the surface of the active layer substrate 10A between the lamination step and the thinning step. After the surface grinding, the active layer substrate 10B is formed, and an oxide film 11B is formed accordingly (Fig. 5(B)). A known grinding method can be used for the surface grinding.

Following this surface grinding step, it is preferable to carry out a peripheral polishing step in which the peripheral portion of the active layer substrate 10B is polished from an oblique direction relative to the main surface of the active layer substrate 10B. After the peripheral polishing, the active layer 10C is formed, and the ends of the oxide film 11B and the support substrate 20 are also ground (FIG. 5(C)). This peripheral polishing can also be performed using a known polishing method in which only the outer periphery is polished while the support substrate 20 is held by a holding plate having an uneven shape. It is preferable to make the terrace width 1.5 mm or less by this peripheral polishing step. Finally, by carrying out the thinning step described above, a thin-film SOI wafer with an active layer thickness of less than 1 μm can be produced (FIG. 5(D)).

In this preferred embodiment, it is preferable to perform the peripheral portion polishing step so that W and T satisfy the following formula (2), where W (mm) is the terrace width and T (μm) is the active layer thickness.
T≧0.54W+0.24 ... (2)
By making the terrace width and the active layer thickness satisfy the formula (2), a thin-film SOI wafer in which the oxide film is not exposed can be realized more reliably.

In this preferred embodiment, as shown in Figures 6(A) to (C), the terrace width during finish polishing is 1.5 mm or less, so that the sinking of the polishing pad P at the peripheral portion of the SOI wafer 300 during finish polishing can be suppressed, and even after forming an active layer 10 of less than 1 μm, new exposure of the oxide film 11 can be prevented. However, depending on the polishing conditions, if the terrace width exceeds 1.5 mm or T and W do not satisfy the above formula (2), as shown in Figure 6(D), the terrace width of the SOI wafer 300' to be produced will be W' (W'>W), and the peripheral portion of the active layer 10 may be excessively removed, resulting in exposure of the oxide film 11.

Comparing the control of terrace width by the above-mentioned chamfer etching method with the control of terrace width by the terrace polishing method, in the terrace polishing method, the active layer substrate 10C tends to come into contact with the polishing pad P more easily, and the oxide film 11 tends to be exposed more easily when that portion is ground away. Therefore, it is more preferable to use the first embodiment for controlling the terrace width.

(Third Preferred Embodiment)
In the third preferred embodiment, in order to make the terrace width 1.5 mm or less, a so-called "terrace-free" SOI wafer is formed prior to the thinning step (sometimes called "round processing"). That is, as shown in FIG. 7, between the bonding step and the thinning step, it is preferable to perform an edge grinding step in which the edges of the bonded active layer substrate 10B and support substrate 20 are ground to make the edges into a continuous rounded or tapered surface via the oxide film 11B (FIGS. 7(A) to (C)). More specifically, it is preferable to perform peripheral grinding of the bonded active layer substrate 10B and support substrate 20 using a grindstone of a predetermined shape (FIG. 7(B)), and then perform surface grinding (FIG. 7(C)). After surface grinding, a continuous rounded or tapered surface is formed. It is also preferable to form an intermediate body of the same type of SOI wafer between the above peripheral grinding and surface grinding, stack them, and perform etching in a stacked and clamped state to improve the deterioration of the surface roughness caused by peripheral grinding. Finally, by carrying out the thinning process described above, a thin-film SOI wafer having an active layer thickness of less than 1 μm can be produced.

Even in SOI wafers that are called "terrace-free," there may be exposed regions of the oxide film 11 of about several nm to several tens of nm, as shown in FIG. 7(C). However, this exposure is not a flat surface exposure, and is not visible to the naked eye. Therefore, in cases where the edge of the SOI wafer is a continuous rounded or tapered surface through the oxide film, the terrace width is treated in this specification as being substantially 0 mm.

In this preferred embodiment, as shown in Figures 8(A) to (C), the terrace width is substantially 0 mm during finish polishing, and the pressure applied by the polishing pad P to the peripheral portion of the SOI wafer 400 during finish polishing is averaged. Therefore, even after forming an active layer 10 of less than 1 μm, new exposure of the oxide film 11 can be almost certainly prevented, which is particularly preferable. Furthermore, compared to the first and second preferred embodiments described above, this preferred embodiment is preferable because it best prevents exposure of the oxide film 11.

The thickness of the active layer of the so-called "thin film SOI" that can be produced by this manufacturing method is not particularly limited, but considering processing accuracy and productivity, it is preferable to set the lower limit of the thickness to 0.3 μm.

In addition, before or after the thinning process, the support substrate 20 may be thinned separately depending on the application, and during this thinning, the insulating film on the surfaces other than the bonding surface may be ground or polished.

(SOI wafer)
Next, the SOI wafer of this embodiment obtained by the above manufacturing method will be described. The same reference numerals are given to overlapping components, and overlapping descriptions will be omitted. As shown in FIG. 2(E), the SOI wafer 100 of this embodiment has a support substrate 20 made of silicon single crystal, an oxide film 11 located on the support substrate 20, and an active layer 10 made of silicon single crystal located on the oxide film 11, in which the thickness T of the active layer 10 is less than 1 μm, and the width of the region where the oxide film 11 or the support substrate 20 is exposed outward from the outer edge of the active layer 10 in a top view (i.e., terrace width) is 1.5 mm or less in the radial direction from the end face of the SOI wafer 100.

Here, the thickness T of the active layer 10 can be set to 0.3 μm or more.

As shown in FIG. 4C, in the SOI wafer 200 according to the preferred embodiment of the present invention, the support substrate 20 and the oxide film 11 are arranged in a stepped manner at the peripheral portion of the SOI wafer 200, and when the terrace width is W (mm) and the thickness of the active layer 10 is T (μm), it is preferable that W and T satisfy the above-mentioned formula (1).
T≧0.36W+0.32 ... (1)
This SOI wafer 200 is obtained by the above-mentioned first preferred embodiment (chamfer etching method).

In addition, as shown in FIG. 6(C), in an SOI wafer 300 according to a preferred embodiment of the present invention, the support substrate 20 is exposed at the peripheral portion of the SOI wafer 300, and the ends of the oxide film 11 and the active layer 10 are continuous rounded or tapered surfaces. When the terrace width is W (mm) and the thickness of the active layer 10 is T (μm), it is preferable that W and T satisfy the above-mentioned formula (2).
T≧0.54W+0.24 ... (2)
This SOI wafer 300 is obtained by the above-mentioned second preferred embodiment (terrace polishing method).

Furthermore, as shown in FIG. 8(C), in the SOI wafer 400 according to the preferred embodiment of the present invention, the ends of the active layer 10 and the support substrate 20 preferably have a continuous rounded or tapered surface via the oxide film 11. In this case, as already described, the terrace width can be treated as being substantially 0 mm. This SOI wafer 400 is obtained according to the third preferred embodiment (terrace-free) described above.

An n-type silicon wafer (diameter: 200 mm, thickness: 725 μm, oxygen concentration: 3.0×10 ¹⁷ atoms/cm ³ , dopant type: phosphorus) harvested from a single crystal silicon ingot obtained by the CZ method was prepared as an active layer substrate. Also, a p-type silicon wafer (diameter: 200 mm, thickness: 725 μm, oxygen concentration: 1.2×10 ¹⁸ atoms/cm ³ , dopant type: boron) harvested from a single crystal silicon ingot obtained by the CZ method was prepared as a support substrate.
Next, the silicon wafer for the active layer was introduced into a thermal oxide film preparation device, and an oxide film formation process was performed at 1050°C in a hydrogen and oxygen mixed gas atmosphere to form a silicon oxide film with a thickness of 2.5 μm, and the active layer substrate and the support substrate were bonded together. Next, the bonded wafer was transported into a vertical heat treatment device in an oxygen gas atmosphere, and the temperature in the device was raised to 800°C and held for 2 hours, and then raised to 1000°C and held for 1 hour, whereby a heat treatment was performed to strengthen the bonding.
Thereafter, the terrace width was adjusted as in the following Experimental Examples 1 to 3, and then thinning was performed by DCP processing and finish polishing.

(Experimental Example 1)
The substrate for the active layer was thinned to 3 μm by chamfer etching. At this time, the terrace width was set to 0.7 mm. Next, DCP processing was performed using a DCP processing machine, and finally, the polishing allowance was set to 0.20 μm using a single-sided polishing device, and thinning was repeated until the oxide film was exposed. After DCP processing, it was confirmed that the oxide film was not exposed until the thickness of the active layer was 0.50 μm, but it was confirmed that the oxide film was exposed when the thickness of the active layer was less than 0.50 μm.

The terrace width after chamfer etching was adjusted to the value shown in Table 1 below, and the conditions other than the terrace width were the same as above, and the lower limit of the thickness of the active layer after finish polishing where no exposure of the oxide film occurs was measured. The lower limit of the terrace width and the thickness of the active layer are shown below. The approximation line (corresponding to the above-mentioned formula (1)) obtained from these results using the least squares method is shown in Figure 9.

(Experimental Example 2)
The substrate for active layer was thinned to 3 μm by terrace polishing. At this time, the terrace width was set to 1.0 mm. Next, DCP processing was performed using a DCP processing machine, and finally, the polishing allowance by a single-sided polishing device was set to 0.20 μm, and thinning was repeated until the oxide film was exposed. After DCP processing, it was confirmed that the oxide film was not exposed until the thickness of the active layer was 0.8 μm, but it was confirmed that the oxide film was exposed when the thickness of the active layer was less than 0.8 μm.

The terrace width after terrace polishing was adjusted to the value shown in Table 2 below, and the conditions were the same as above except for the terrace width, and the lower limit of the thickness of the active layer after finish polishing at which the oxide film was not exposed was measured. The lower limit of the terrace width and the thickness of the active layer are shown below. The approximation line (corresponding to the above-mentioned formula (2)) obtained from these results using the least squares method is shown in Figure 9.

(Experimental Example 3)
A terrace-free SOI wafer was produced, and the active layer substrate was thinned to 3 μm. Then, DCP processing was performed using a DCP processing machine, and finally, the polishing allowance was set to 0.20 μm using a single-sided polishing device, and thinning was repeated until the oxide film was exposed. It was confirmed that the oxide film was not exposed at least until the active layer thickness reached 0.3 μm. No experiments were performed for active layer thicknesses of less than 0.3 μm. The results are shown in FIG. 9 together with the above-mentioned Experimental Examples 1 and 2. However, the terrace width is expressed as 0 mm.

Regarding the exposure of the oxide film, photographs of the active layer having a thickness of 0.30 μm in Experimental Example 3 are shown as representative examples in Figures 10(A) and (B). (A) is a photograph of the peripheral portion other than the notch portion, and (B) is a photograph of the notch portion. In both Figures 10(A) and (B), no exposure of the oxide film was observed. On the other hand, Figures 10(C) and (D) show the results of Experimental Example 2, where the terrace width is 2.0 mm and the active layer has a thickness of 0.90 μm. (C) is a photograph of the peripheral portion other than the notch portion, and (D) is a photograph of the notch portion. In both Figures 10(A) and (B), exposure of the oxide film was observed.

From the above results, it was confirmed that by making the terrace width 1.5 mm or less before finish polishing, it is possible to produce thin-film SOI wafers with active layer thicknesses of less than 1 μm by the bonding method. It was also confirmed that when making the terrace width 1.5 mm or less by the chamfer etching method, it is preferable to satisfy the above-mentioned formula (1), and when making the terrace width 1.5 mm or less by the terrace polishing method, it is preferable to satisfy the above-mentioned formula (2).

The present invention provides a method for manufacturing an SOI wafer that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method, and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method.

10 Active layer 10A Substrate for active layer 11 Oxide film 20 Support substrate T Thickness of active layer W Terrace width

Claims (5)

an oxide film forming step of forming an oxide film on at least one surface of the active layer substrate made of silicon single crystal and the support substrate made of silicon single crystal;
a bonding step of bonding the active layer substrate and the support substrate via the oxide film;
a thinning step of thinning the active layer substrate from a surface opposite to the support substrate after the bonding step,
the thinning step includes a first step of flattening the surface of the active layer substrate by dry chemical etching, and a second step of polishing the surface of the active layer substrate to form an active layer having a thickness of less than 1 μm;
A method for manufacturing an SOI wafer, characterized in that, prior to the second step, a width of a region where the oxide film or the support substrate is exposed outward from an outer edge of the active layer substrate in a top view is set to 1.5 mm or less in a radial direction from an end face of the SOI wafer. The method for manufacturing an SOI wafer according to claim 1, in which the thickness of the active layer is 0.3 μm or more. Between the lamination step and the thinning step, the method further includes a chamfering step of chamfering an end face of the active layer substrate so that a peripheral portion on the support substrate side remains, a wet etching step of wet-etching the remaining portion to expose a part of the oxide film, and a removal step of removing the peripheral portion of the oxide film, following the wet etching step.
In the removing step, the width is set to 1.5 mm or less,
3. The method for producing an SOI wafer according to claim 1, wherein, when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (1):
Record
T≧0.36W+0.32 ... (1) between the lamination step and the thinning step, a surface grinding step of grinding a surface of the active layer substrate, and a peripheral portion polishing step of polishing a peripheral portion of the active layer substrate from an oblique direction relative to a main surface of the active layer substrate following the surface grinding step,
In the peripheral portion polishing step, the width is set to 1.5 mm or less,
3. The method for producing an SOI wafer according to claim 1, wherein, when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (2):
Record
T≧0.54W+0.24 ... (2) The method for producing an SOI wafer according to claim 1 or 2, further comprising an edge grinding step between the bonding step and the thinning step, in which the edges of the bonded active layer substrate and support substrate are ground to form a continuous rounded or tapered surface through the oxide film.

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