JP7510596B2 - Light emitting device and method for manufacturing the same - Google Patents

Description

The embodiment relates to a light-emitting device and a method for manufacturing the same.

Patent Document 1 discloses a device in which multiple light-emitting elements and multiple switching elements are integrated on a substrate, and each light-emitting element can be controlled independently by each switching element. In such a device, it is desirable to arrange the light-emitting elements and the switching elements in close proximity.

JP 2019-192746 A

One embodiment of the present invention aims to provide a light-emitting device that allows light-emitting elements and switching elements to be arranged in close proximity to each other, and a method for manufacturing the same.

The light emitting device according to one embodiment of the present invention includes a first silicon substrate, a second silicon substrate, a switching element, a light emitting element, an insulating member, and a wiring electrode. The first silicon substrate includes a first surface and a second surface located on the opposite side to the first surface. The second silicon substrate is provided on the second surface side of the first silicon substrate. The second silicon substrate includes a third surface facing the second surface and a fourth surface located on the opposite side to the third surface. The switching element is formed on the first surface of the first silicon substrate. The light emitting element is provided on the fourth surface side of the second silicon substrate. The wiring electrode is provided in the insulating member and connects the switching element to the light emitting element. A first through hole is formed in the first silicon substrate and the second silicon substrate. The insulating member is provided on the side of the first through hole. A second through hole exposing the light emitting element is formed in the insulating member.

A method for manufacturing a light-emitting device according to one embodiment of the present invention includes a step of preparing a structure. The structure includes a first silicon substrate, an insulating film, a second silicon substrate, a light-emitting element, and a first wiring. The first silicon substrate includes a first surface and a second surface located on the opposite side to the first surface. At least a portion of the first surface is of a first conductivity type. The insulating film is provided on the first surface of the first silicon substrate. The second silicon substrate is provided on the second surface side of the first silicon substrate. The second silicon substrate includes a third surface facing the second surface and a fourth surface located on the opposite side to the third surface. The light-emitting element is provided on the fourth surface of the second silicon substrate. The first wiring has a conductive portion connected to the light-emitting element and located outside the region in which the light-emitting element is provided in a top view. The manufacturing method includes a step of forming a gate electrode on the insulating film. The manufacturing method includes a step of forming a first semiconductor region and a second semiconductor region of a second conductivity type on the first surface of the first silicon substrate by injecting impurities into the first surface of the first silicon substrate using the gate electrode as a mask. The manufacturing method includes a step of forming a first through hole that exposes the light emitting element by selectively removing the insulating film, the first silicon substrate, and the second silicon substrate from the insulating film side. The manufacturing method includes a step of forming a first hole that exposes the first semiconductor region from the insulating film and a second hole that exposes the second semiconductor region from the insulating film by removing the insulating film. The manufacturing method includes a step of forming a second wiring that connects the conductive portion and the first semiconductor region.

According to one embodiment of the present invention, it is possible to realize a light-emitting device and a manufacturing method thereof that allow the light-emitting element and the switching element to be arranged in close proximity.

1 is a schematic top view showing a light emitting device according to one embodiment of the present invention. 2 is a schematic cross-sectional view taken along line II-II shown in FIG. 1. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention. 5A to 5C are schematic cross-sectional views showing a method for manufacturing a light emitting device according to one embodiment of the present invention.

<Embodiment>
An embodiment of the present invention will now be described.
FIG. 1 is a schematic top view showing a light emitting device according to the present embodiment.
FIG. 2 is a schematic cross-sectional view taken along line II-II shown in FIG.
In FIG. 1, some components are omitted and the main components are shown in perspective.

As shown in FIG. 2, the light emitting device 1 according to this embodiment has a support substrate 10. As shown in FIGS. 1 and 2, a switching element 30 and a light emitting element 50 are provided on the support substrate 10. In the light emitting device 1, a switching region Rs in which the switching element 30 is formed, a light emitting region Rl in which the light emitting element 50 is formed, and a peripheral region Rp excluding the switching region Rs and the light emitting region Rl are set. When viewed from above, the light emitting region Rl is separated from the switching region Rs.

First, the configuration of the peripheral region Rp will be described.
In the peripheral region Rp, a bonding member 11, a first interlayer insulating film 12, a compound semiconductor layer 13, a second silicon substrate 14, an oxide film 15, a first silicon substrate 16, an insulating film 17, a first silicon oxide layer 18, a light reflecting member 19, a second interlayer insulating film 20, and a protective film 21 are stacked in this order on a supporting substrate 10.

Hereinafter, the laminate from the support substrate 10 to the protective film 21 is also referred to as the laminate 29. The direction from the support substrate 10 toward the protective film 21 is also referred to as the "upper" direction, and the opposite direction is also referred to as the "lower" direction, but these expressions are for convenience and have no relation to the direction of gravity. Also, a view from above is referred to as a "top view." In Figures 1 and 2, the upward direction is marked as "Z." Also, the direction from the light-emitting region Rl toward the switching region Rs is marked as "X," and the direction perpendicular to the Z direction and the X direction is marked as "Y."

The support substrate 10 is, for example, a silicon substrate. The bonding member 11 is, for example, made of a metal. The first interlayer insulating film 12 is, for example, made of silicon oxide and formed, for example, by a spin-on-glass (SOG) method. The support substrate 10 is bonded to the first interlayer insulating film 12 by the bonding member 11. The compound semiconductor layer 13 is, for example, a two-layer film in which an aluminum nitride layer (AlN layer) and a gallium nitride layer (GaN layer) are stacked.

The second silicon substrate 14 is made of silicon and is, for example, a Si substrate whose main surface is a (111) surface. The second silicon substrate 14 includes a third surface 14a and a fourth surface 14b located on the opposite side to the third surface 14a. The third surface 14a is the upper surface of the second silicon substrate 14, and the fourth surface 14b is the lower surface of the second silicon substrate 14. The fourth surface 14b is in contact with the compound semiconductor layer 13. The oxide film 15 is, for example, made of silicon oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ).

The first silicon substrate 16 is made of silicon and is, for example, a Si substrate whose main surface is a (100) surface. The first silicon substrate 16 includes a first surface 16a and a second surface 16b located on the opposite side to the first surface 16a. The first surface 16a is the upper surface of the first silicon substrate 16, and the second surface 16b is the lower surface of the first silicon substrate 16. The third surface 14a of the second silicon substrate 14 is provided on the second surface 16b side of the first silicon substrate 16 and faces the second surface 16b. The first silicon substrate 16 contains impurities, and at least a portion of the first surface 16a has a first conductivity type. In this embodiment, the first conductivity type is p-type. For example, the entire first silicon substrate 16 may be p-type.

The insulating film 17 is made of silicon oxide, and is formed, for example, by performing a thermal oxidation process on the surface of the first silicon substrate 16. The first silicon oxide layer 18 is made of silicon oxide. The light reflecting member 19 is, for example, a DBR (Distributed Bragg Reflector) or the like. The light reflecting member 19 may be a metal film. As the metal film used for the light reflecting member 19, a metal film having a reflectance of 70% or more, preferably 80%, with respect to the peak wavelength of the light emitted from the light emitting element 50 is used. The light reflecting member 19 is made of, for example, a metal material containing aluminum (Al) or silver (Ag). The light reflecting member 19 covers the first surface 16a of the first silicon substrate 16. The second interlayer insulating film 20 is made of, for example, silicon oxide, and is formed, for example, by the SOG method. The protective film 21 is made of, for example, silicon oxide.

Next, the configuration of the switching region Rs will be described.
In the switching region Rs, the switching element 30 is formed on the first surface 16a of the first silicon substrate 16. The switching element 30 has a first semiconductor region 31 and a second semiconductor region 32 of a second conductivity type formed on the first surface 16a of the first silicon substrate 16, an insulating film 17 in contact with the first surface 16a of the first silicon substrate 16 between the first semiconductor region 31 and the second semiconductor region 32, and a gate electrode 33 provided on the insulating film 17. In this embodiment, the second conductivity type is n-type.

In the first surface 16a of the first silicon substrate 16, at least the region between the first semiconductor region 31 and the second semiconductor region 32 has a first conductivity type (p type). On the other hand, the conductivity type of the first semiconductor region 31 and the second semiconductor region 32 is a second conductivity type (n type). The gate electrode 33 faces the region between the first semiconductor region 31 and the second semiconductor region 32 in the first silicon substrate 16 via the insulating film 17.

As a result, the first semiconductor region 31 and the second semiconductor region 32 function as a source or drain, the region between the first semiconductor region 31 and the second semiconductor region 32 in the first silicon substrate 16 functions as a channel, the gate electrode 33 functions as a gate, and the insulating film 17 functions as a gate insulating film. As a result, an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed. This MOSFET constitutes the switching element 30. When viewed from above, the distance between the light-emitting element 50 and the switching element 30 is preferably, for example, 100 nm or more and 10 μm or less, and more preferably 100 nm or more and 5 μm or less.

Next, the configuration of the light emitting region Rl will be described.
In the light emitting region Rl, a first through hole 51 is arranged continuously through the compound semiconductor layer 13, the second silicon substrate 14, the oxide film 15, the first silicon substrate 16, the insulating film 17, and the first silicon oxide layer 18.

In the region where the first through hole 51 is formed, the compound semiconductor layer 13, the second silicon substrate 14, the oxide film 15, the first silicon substrate 16, the insulating film 17, the first silicon oxide layer 18, the light reflecting member 19, and the second interlayer insulating film 20 are not provided. The first interlayer insulating film 12 is located on the bottom surface 51b of the first through hole 51.

In the light-emitting region Rl, the light-emitting element 50, the insulating member 52, a part of the wiring electrode 53, the third wiring 54, and the wavelength conversion member 55 are provided in the first through hole 51. A light reflecting member 19 is provided on the side surface 51a and the bottom surface 51b of the first through hole 51. The light reflecting member 19 provided in the light-emitting region Rl is continuous with the light reflecting member 19 provided in the peripheral region Rp. That is, the light reflecting member 19 covers the first surface 16a of the first silicon substrate 16 in the peripheral region Rp, and covers the side surface 51a and the bottom surface 51b of the first through hole 51 in the light-emitting region Rl. The insulating member 52 is provided on the side surface 51a and the bottom surface 51b of the first through hole 51 and covers the light reflecting member 19. The insulating member 52 is made of, for example, silicon oxide.

A second through hole 56 is formed in the insulating member 52. The second through hole 56 is smaller than the first through hole 51 and has, for example, a rectangular prism shape. Therefore, the insulating member 52 is disposed between the first through hole 51 and the second through hole 56 and has a box shape with an open top. A light-emitting element 50 is provided at the bottom of the second through hole 56. The light-emitting element 50 is also provided on the fourth surface 14b side of the second silicon substrate 14.

In the light-emitting element 50, a cover metal 61, a p-side electrode 62, a first semiconductor layer 63 of a first conductivity type (p-type), an active layer 64, and a second semiconductor layer 65 of a second conductivity type (n-type) are laminated in this order. The active layer 64 is provided between the first semiconductor layer 63 and the second semiconductor layer 65. The first semiconductor layer 63, the active layer 64, and the second semiconductor layer 65 contain gallium (Ga) and nitrogen (N). The first semiconductor layer 63, the active layer 64, and the second semiconductor layer 65 are made of nitride semiconductors, for example, gallium nitride (GaN) or indium gallium nitride (InGaN).

The p-side electrode 62 is in contact with substantially the entire lower surface of the first semiconductor layer 63. The cover metal 61 covers the lower surface and side surfaces of the p-side electrode 62. The cover metal 61 is connected to the third wiring 54. The third wiring 54 passes through the insulating member 52 and the second interlayer insulating film 20 and is drawn out to the upper surface of the stack 29. A hole 66 is formed in the cover metal 61, the p-side electrode 62, the first semiconductor layer 63, and the active layer 64, for example, in the center when viewed from above.

A wavelength conversion member 55 is provided on the light emitting element 50 in the second through hole 56. The height of the upper surface of the wavelength conversion member 55 is the same as the height of the upper surface of the protective film 21. The wavelength conversion member 55 absorbs a part of the light emitted from the light emitting element 50 and emits light of a wavelength different from the wavelength of the light emitted from the light emitting element 50. For example, the wavelength conversion member 55 includes a base material made of a translucent resin material and a phosphor contained in the base material. A reflective film 70 is provided on the side of the wavelength conversion member 55. The reflective film 70 is formed of, for example, a metal material or a DBR. The reflective film 70 does not have to be provided. By providing the reflective film 70, it is possible to reflect light from the wavelength conversion member 55 toward the insulating member 52 or the second interlayer insulating film 20.

A color filter 71 is provided on the wavelength conversion member 55 and the protective film 21, and a microlens 72 is provided on the color filter 71. The color filter 71 transmits light of a predetermined wavelength range from the light emitted from the light emitting element 50 and the light emitted from the wavelength conversion member 55. The microlens 72 is a plano-convex lens made of a light-transmitting material. In other words, the lower surface of the microlens 72 is flat and in contact with the color filter 71, and the upper surface of the microlens 72 is convex. Note that the color filter 71 and the microlens 72 do not necessarily have to be provided.

A part of the wiring electrode 53 is provided in the insulating member 52 and electrically connects the switching element 30 and the light-emitting element 50. The wiring electrode 53 has a first wiring 53a and a second wiring 53b. The first wiring 53a has a conductive portion 53c located outside the region in which the light-emitting element 50 is provided in a top view, a first conductive portion 53d located in the light-emitting region Rl and extending in the X direction, and a second conductive portion 53e extending upward from the first conductive portion 53d and connected to the second semiconductor layer 65 through a hole 66. The second wiring 53b has a third conductive portion 53f drawn upward from the conductive portion 53c, a fourth conductive portion 53g drawn in the X direction from the upper end of the third conductive portion 53f, and a fifth conductive portion 53h extending vertically from the fourth conductive portion 53g and connected to the first semiconductor region 31.

As described above, the upper end of the second conductive portion 53e is connected to the second semiconductor layer 65 of the light-emitting element 50. The lower end of the second conductive portion 53e is connected to the first conductive portion 53d, the first conductive portion 53d is connected to the conductive portion 53c, the conductive portion 53c is connected to the lower end of the third conductive portion 53f, the upper end of the third conductive portion 53f is connected to the fourth conductive portion 53g, the fourth conductive portion 53g is connected to the upper end of the fifth conductive portion 53h, and the lower end of the fifth conductive portion 53h is connected to the first semiconductor region 31 of the switching element 30. In this way, the second semiconductor layer 65 and the first semiconductor region 31 are electrically connected by the wiring electrode 53.

The third wiring 54 is electrically connected to the first semiconductor layer 63 of the light-emitting element 50 via the cover metal 61 and the p-side electrode 62. This electrically connects the light-emitting element 50 to the wiring electrode 53 and the third wiring 54. Note that the wiring electrode 53 may be electrically connected to the first semiconductor layer 63, and the third wiring 54 may be electrically connected to the second semiconductor layer 65.

The light emitting device 1 is also provided with a fourth wiring 57. One end of the fourth wiring 57 is connected to the second semiconductor region 32 of the switching element 30. The other end of the fourth wiring 57 is extended to the upper surface of the laminate 29. As a result, the switching element 30 is electrically connected to the wiring electrode 53 and the fourth wiring 57.

A first upper wiring 73 and a second upper wiring 74 are provided on the laminate 29. The first upper wiring 73 is connected to the upper end of the third wiring 54 and extends in the X direction. The second upper wiring 74 is connected to the upper end of the fourth wiring 57 and extends in the X direction.

Next, a method for manufacturing the light emitting device according to this embodiment will be described.
3 to 27 are cross-sectional views showing a method for manufacturing the light emitting device according to this embodiment.
The cross sections shown in FIGS. 3 to 27 correspond to the cross section shown in FIG.

(Step of Preparing Structure 105)
First, as shown in FIG. 3, an SOI (Silicon On Insulator) substrate 101 is prepared. In the SOI substrate 101, a silicon substrate 102 is provided, an insulating film 17 is provided on a lower surface 102a of the silicon substrate 102, and a first silicon substrate 16 is provided on the lower surface. The silicon substrate 102 is, for example, a Si (100) substrate. The insulating film 17 is, for example, a thermally oxidized silicon film. A first surface 16a of the first silicon substrate 16 is in contact with the insulating film 17, and a second surface 16b located on the opposite side of the first surface 16a constitutes the lower surface of the SOI substrate 101. Impurities are ion-implanted into the first silicon substrate 16, and at least a part of the first surface 16a is of the first conductivity type. In this embodiment, the first conductivity type is, for example, p-type.

On the other hand, a structure 103 is prepared. In the structure 103, a second silicon substrate 14 is provided. The second silicon substrate 14 is, for example, a Si (111) substrate. An oxide film 15 is provided on the third surface 14a of the second silicon substrate 14. The oxide film 15 is formed of, for example, silicon oxide or aluminum oxide. A second semiconductor layer 65 of a second conductivity type, an active layer 64, and a first semiconductor layer 63 of a first conductivity type are provided in this order on the fourth surface 14b of the second silicon substrate 14. In this embodiment, the second conductivity type is n-type. The second semiconductor layer 65, the active layer 64, and the first semiconductor layer 63 contain gallium and nitrogen. The second semiconductor layer 65, the active layer 64, and the first semiconductor layer 63 are formed, for example, by epitaxially growing nitride semiconductors such as gallium nitride (GaN) or indium gallium nitride (InGaN) on the fourth surface 14b of the second silicon substrate 14.

Next, as shown in FIG. 4, the second surface 16b of the first silicon substrate 16 of the SOI substrate 101 is bonded to the upper surface of the oxide film 15 of the structure 103. This bonding is performed by, for example, plasma bonding. As a result, the structure 104 is formed.

Next, an electrode material is deposited on the entire lower surface of the first semiconductor layer 63. The electrode material is, for example, silver (Ag) or a silver alloy. Next, the electrode material, the first semiconductor layer 63, and the active layer 64 are selectively removed by etching. As a result, as shown in FIG. 5, the electrode material, the first semiconductor layer 63, and the active layer 64 remain in the light-emitting region Rl, and a hole 66 is formed in the center of the light-emitting region Rl. In the hole 66, the second semiconductor layer 65 is exposed at the bottom surface. The remaining portion of the electrode material forms the p-side electrode 62.

Next, a cover metal 61 is formed on the lower surface of the first semiconductor layer 63 so as to cover the p-side electrode 62. Through these steps, a light-emitting element 50 is formed, which includes the cover metal 61, the p-side electrode 62, the first semiconductor layer 63, the active layer 64, and the second semiconductor layer 65. The second semiconductor layer 65 remaining in the region other than the light-emitting region Rl becomes the compound semiconductor layer 13.

Next, as shown in FIG. 6, a part of the first interlayer insulating film 12 is formed on the lower surface of the structure 104. The first interlayer insulating film 12 is formed, for example, by depositing silicon oxide. The first interlayer insulating film 12 covers the second semiconductor layer 65 and the cover metal 61. The first interlayer insulating film 12 is also disposed in the hole 66.

Next, holes are formed in the first interlayer insulating film 12 in the portion disposed within the hole 66 and in the portion disposed on the lower surface of the cover metal 61. Next, a conductive material, for example, a high melting point material, is deposited and patterned. As a result, the first wiring 53a and a part of the third wiring 54 are formed, as shown in FIG. 7. The first wiring 53a has a conductive portion 53c located outside the region in which the light emitting element 50 is provided in a top view, a first conductive portion 53d located in the light emitting region Rl and extending in the X direction, and a second conductive portion 53e extending upward from the first conductive portion 53d and connected to the second semiconductor layer 65 via the hole 66.

In this manner, the structure 105 is prepared. The structure 105 includes a first silicon substrate 16 including a first surface 16a and a second surface 16b located on the opposite side of the first surface 16a, with at least a portion of the first surface 16a being of a first conductivity type (p-type), an oxide film 15 provided on the second surface 16b of the first silicon substrate 16, a second silicon substrate 14 including a third surface 14a provided on the second surface 16b side of the first silicon substrate 16 and facing the second surface 16b, and a fourth surface 14b located on the opposite side of the third surface 14a, a light-emitting element 50 provided on the fourth surface 14b of the second silicon substrate 14, and a first wiring 53a having a conductive portion 53c connected to the light-emitting element 50 and located outside the region in which the light-emitting element 50 is provided in a top view. The structure 105 may be prepared by means of purchasing from another party, etc.

(Step of bonding the support substrate)
8, silicon oxide is deposited on the lower surface of the structure 105 by, for example, an SOG method. Next, the lower surface of the structure 105 is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. As a result, another part of the first interlayer insulating film 12 is formed on the part of the above-mentioned first interlayer insulating film 12, and the first interlayer insulating film 12 covering the first wiring 53a and the third wiring 54 is formed.

Next, as shown in FIG. 9, a metal such as gold (Au) or titanium (Ti) is deposited on the underside of the first interlayer insulating film 12 to form a bonding member 11. Then, the support substrate 10 is bonded to the bonding member 11. In this manner, the support substrate 10 is bonded to the first interlayer insulating film 12 side of the structure 105, i.e., the light-emitting element 50 side, by the bonding member 11.

(Step of forming gate electrode 33)
10, the silicon substrate 102 is removed, thereby exposing the insulating film 17 on the upper surface of the structure 105.

Next, as shown in FIG. 11, a gate electrode 33 is formed on the insulating film 17. The gate electrode 33 can be formed, for example, by forming polysilicon on the insulating film 17 and patterning it.

(Step of forming the first semiconductor region 31 and the second semiconductor region 32)
12, a resist pattern 106 is formed on a part of the upper surface of the insulating film 17. Next, using the gate electrode 33 and the resist pattern 106 as a mask, impurity ions are implanted into the upper layer portion of the first silicon substrate 16 through the insulating film 17. The impurity is, for example, a donor impurity, such as phosphorus (P) ions. Next, the resist pattern 106 is removed.

Next, an annealing process is performed to activate the ion-implanted impurities. The annealing process is performed, for example, by laser annealing or rapid thermal annealing (RTA), so that heat is not transferred to areas of the first silicon substrate 16 other than the area to be activated. In this way, the first semiconductor region 31 and the second semiconductor region 32 are formed in a self-aligned manner on the first surface 16a of the first silicon substrate 16. Through this process, the conductivity type of the first semiconductor region 31 and the second semiconductor region 32 becomes the second conductivity type. The second conductivity type is, for example, n-type. As a result, a switching element 30 is formed in the switching region Rs.

Next, as shown in FIG. 13, a first silicon oxide layer 18 is formed on the insulating film 17. The first silicon oxide layer 18 is formed, for example, by depositing silicon oxide. The first silicon oxide layer 18 covers the gate electrode 33.

Next, anisotropic etching is performed on the first silicon oxide layer 18 and the insulating film 17 using the resist pattern as a mask. As a result, as shown in FIG. 14, the first silicon oxide layer 18 and the insulating film 17 are removed in the areas directly above the first semiconductor region 31, the areas directly above the second semiconductor region 32, and the areas directly above the gate electrode 33. By partially removing the first silicon oxide layer 18 and the insulating film 17 in this manner, a hole 107 reaching the first semiconductor region 31 and a hole 108 reaching the second semiconductor region 32 are formed. In addition, a part of the gate electrode 33 is exposed from the insulating film 17, and a part of the insulating film 17 remains on the side of the gate electrode 33 to form a sidewall.

(Step of forming the first through hole 51)
15, the first silicon oxide layer 18, the insulating film 17, the first silicon substrate 16, the oxide film 15, and the second silicon substrate 14 are selectively removed using a resist pattern that exposes the light-emitting region R1 as a mask. The second semiconductor layer 65 preferably has high corrosion resistance against the etchant used in this removal process, and the second semiconductor layer 65 can function as a stopper member. For example, the etchant used in this removal process is preferably one that has a higher etching rate for the second silicon substrate 14 than for the second semiconductor layer 65. As a result, a first through hole 51 that exposes the light-emitting element 50 is formed in the light-emitting region R1.

(Step of forming light reflecting member)
Next, the second semiconductor layer 65 located around the first semiconductor layer 63 and the active layer 64 in top view and a part of the first interlayer insulating film 12 are removed by etching. As a result, as shown in Fig. 16, a recess 109 is formed in the first interlayer insulating film 12 located around the first semiconductor layer 63 and the active layer 64. In top view, the recess 109 is disposed to surround, for example, the light emitting element 50.

Next, as shown in FIG. 17, a light reflecting member 19 is formed to cover the side of the first through hole 51 and the first surface 16a of the first silicon substrate 16. The light reflecting member 19 is formed, for example, by atomic layer deposition (ALD). The light reflecting member 19 is made of, for example, a DBR. Next, a part of the light reflecting member 19 is removed to expose the light emitting element 50. A part of the light reflecting member 19 is also formed in the hole 107 and the hole 108.

(Step of forming insulating member 52)
18, an insulating member 52 that covers the light reflecting member 19 and the light emitting element 50 is formed in the first through hole 51. The insulating member 52 is formed, for example, by forming a silicon oxide film in the first through hole 51 and on the surface of the light reflecting member 19 by the SOG method, and then planarizing the film by the CMP method. The insulating member 52 is also formed in regions other than the light emitting region Rl.

(Step of forming the first hole 111 and the second hole 112)
19 , the insulating member 52 is selectively removed by, for example, photolithography. As a result, a first hole 111 that exposes the first semiconductor region 31 from the insulating member 52 and a second hole 112 that exposes the second semiconductor region 32 from the insulating member 52 are formed in the insulating member 52.

(Step of forming second wiring 53b)
Next, the insulating member 52 is selectively removed by, for example, photolithography. As a result, as shown in Fig. 20, a third hole 113 that exposes the conductive portion 53c of the first wiring 53a from the insulating member 52 and a fourth hole 114 that exposes a part of the portion of the third wiring 54 that is disposed outside the light-emitting element 50 in a top view from the insulating member 52 are formed.

21, the fifth conductive portion 53h is formed in the first hole 111, a part of the fourth wiring 57 is formed in the second hole 112, the third conductive portion 53f is formed in the third hole 113, and a part of the third wiring 54 is formed in the fourth hole 114. The fifth conductive portion 53h, a part of the fourth wiring 57, the third conductive portion 53f, and a part of the third wiring 54 are formed, for example, by the following process. First, a metal material is formed on the surface of the insulating member 52, in the first hole 111, in the second hole 112, in the third hole 113, and in the fourth hole 114. Next, the part of the metal material deposited on the upper surface of the insulating member 52 is removed, for example, by the CMP method. In this way, the fifth conductive portion 53h and the third conductive portion 53f, which are part of the second wiring 53b, a part of the third wiring 54, and a part of the fourth wiring 57 are formed in the insulating member 52.

22, a second silicon oxide layer 20b having a plurality of openings is formed on the insulating member 52. Next, a fourth conductive portion 53g, a portion of the fourth wiring 57, and a portion of the third wiring 54 are formed in the openings of the second silicon oxide layer 20b. The fourth conductive portion 53g is connected to the fifth conductive portion 53h and the third conductive portion 53f. The third conductive portion 53f, the fourth conductive portion 53g, and the fifth conductive portion 53h form the second wiring 53b. The second wiring 53b electrically connects the conductive portion 53c and the first semiconductor region 31. The second wiring 53b and the first wiring 53a form a wiring electrode 53 that electrically connects the second semiconductor layer 65 of the light-emitting element 50 to the first semiconductor region 31.

Next, a third silicon oxide layer 20c having a plurality of openings is formed on the second silicon oxide layer 20b. Next, a part of the fourth wiring 57 and a part of the third wiring 54 are formed in the openings of the third silicon oxide layer 20c.

23, a fourth silicon oxide layer 20d having a plurality of openings is formed on the third silicon oxide layer 20c. Next, a part of the fourth wiring 57 and a part of the third wiring 54 are formed in the openings of the fourth silicon oxide layer 20d. This forms the fourth wiring 57 and the third wiring 54.

(Step of forming second through hole 56)
24, in the light-emitting region Rl, a part of the fourth silicon oxide layer 20d, a part of the third silicon oxide layer 20c, a part of the second silicon oxide layer 20b, and a part of the insulating member 52 are selectively removed to form a second through-hole 56 exposing the light-emitting element 50. Hereinafter, in the region other than the light-emitting region Rl, the insulating member 52, the second silicon oxide layer 20b, the third silicon oxide layer 20c, and the fourth silicon oxide layer 20d are collectively referred to as the second interlayer insulating film 20.

25, a reflective film 70 is formed on the side surface of the second through hole 56. The reflective film 70 is made of, for example, a metal material or a DBR. Note that the formation of the reflective film 70 may be omitted.
Next, as shown in FIG. 26 , a protective film 21 is formed on the second interlayer insulating film 20 .

(Step of forming wavelength conversion member 55)
27 , a wavelength conversion member 55 is formed in the second through-hole 56. For example, a translucent resin material containing a phosphor is potted in the second through-hole 56, solidified, and the upper surface is ground to be flattened. As a result, the upper surface of the wavelength conversion member 55 is flush with the upper surface of the protective film 21. The wavelength conversion member 55 is in contact with the upper surface of the light-emitting element 50.

Next, as shown in FIG. 2, a color filter 71 is formed on the wavelength conversion member 55. The peripheral portion of the color filter 71 is formed on the protective film 21. Next, a microlens 72 is formed on the color filter 71.

1 , a first upper interconnection 73 and a second upper interconnection 74 are formed on the protective film 21. The first upper interconnection 73 is connected to an upper end of the third interconnection 54 exposed from the second interlayer insulating film 20. The second upper interconnection 74 is connected to an upper end of the fourth interconnection 57 exposed from the second interlayer insulating film 20.
In this manner, the light emitting device 1 according to this embodiment is manufactured.

According to this embodiment, the structure 105 is prepared by the steps shown in FIGS. 3 to 7. The structure 105 includes an insulating film 17, a first silicon substrate 16, a second silicon substrate 14, etc., and a light-emitting element 50 is provided on the fourth surface 14b of the second silicon substrate 14. Then, a gate electrode 33 is formed on the insulating film 17 by the steps shown in FIGS. 8 to 11, and a first semiconductor region 31 and a second semiconductor region 32 are formed in the upper layer portion of the first silicon substrate 16 by the step shown in FIG. 12. This forms the switching element 30. Next, a first through hole 51 that exposes the light-emitting element 50 is formed by the step shown in FIG. 15, a first hole 111 and a second hole 112 that expose the first semiconductor region 31 and the second semiconductor region 32, respectively, are formed by the step shown in FIG. 19, and a wiring electrode 53 is formed by the steps shown in FIGS. 20 to 22. The wiring electrode 53 connects the switching element 30 to the light-emitting element 50 via the first through hole 51, the first hole 111, and the second hole 112. In this way, the light emitting element 50 and the switching element 30 can be formed and connected to each other within one laminate 29 formed using a series of semiconductor processes, so that the light emitting element 50 and the switching element 30 can be arranged in close proximity. As a result, the light emitting device 1 can be miniaturized, and the light emitting device 1 can be highly integrated.

In addition, because a MOSFET is used as the switching element 30, the switching speed is higher than when a thin film transistor (TFT) is used as the switching element 30. This allows the light-emitting element 50 to be controlled at a higher speed. As a result, for example, when the light-emitting device 1 is used as a pixel of a display device, the quality of the moving image display is improved.

In addition, in this embodiment, after the first through hole 51 is formed, a light reflecting member 19 is formed to cover the side surface of the first through hole 51 and the first surface 16a of the first silicon substrate 16 by the process shown in FIG. 17. This allows the light reflecting member 19 to reflect the light emitted from the light emitting element 50 upward, improving the light extraction efficiency of the light emitting device 1.

In this embodiment, the insulating member 52 is formed in the first through hole 51 by the process shown in FIG. 18, the third hole 113 is formed in the insulating member 52 by the process shown in FIG. 20, and the third conductive portion 53f of the wiring electrode 53 is formed in the third hole 113 by the process shown in FIG. 21 and FIG. 22. This allows the light-emitting element 50 and the switching element 30, which are arranged at different positions in the height direction, to be connected inside the laminate 29. As a result, electrical resistance can be reduced and reliability is improved compared to when the light-emitting element 50 and the switching element 30 are connected via the outside of the laminate 29.

In addition, in this embodiment, a second through hole 56 is formed in the insulating member 52 by the process shown in FIG. 24, and a wavelength conversion member 55 is formed in the second through hole 56 by the process shown in FIG. 27. This allows the light emitted from the light-emitting element 50 to be converted into other light having a different peak wavelength by the wavelength conversion member 55, and allows the light-emitting device 1 to emit light of a wavelength different from the wavelength of the light emitted from the light-emitting element 50. Furthermore, by disposing the wavelength conversion member 55 in the second through hole 56, the light-emitting device 1 can be made thinner.

In addition, in this embodiment, the support substrate 10 is bonded to the underside of the structure 105 via the first interlayer insulating film 12 and the bonding member 11 by the process shown in FIG. 8. This improves the rigidity of the structure 105, making subsequent processes easier. In addition, by leaving the support substrate 10 on the completed light-emitting device 1, the strength of the light-emitting device 1 is improved.

The structure 104 shown in FIG. 4 may be formed by providing the oxide film 15 on the SOI substrate 101 instead of the structure 103, and bonding the third surface 14a of the second silicon substrate 14 of the structure 103 to the lower surface of the oxide film 15 of the SOI substrate 101. Also, a first structure having the structure 103, the silicon substrate 102, and the insulating film 17 provided on the lower surface 102a of the silicon substrate 102, and a second structure having the first silicon substrate 16 and the oxide film 15 provided on the second surface 16b of the first silicon substrate 16 are prepared. Then, the lower surface of the insulating film 17 of the first structure may be bonded to the first surface 16a of the first silicon substrate 16 of the second structure, and the lower surface of the oxide film 15 of the second structure may be bonded to the third surface 14a of the second silicon substrate 14 of the structure 103, to form the structure 104 shown in FIG. 4.

In the above embodiment, an n-channel MOSFET is used as the switching element 30, but this is not limiting. For example, a p-channel MOSFET may be used as the switching element 30, or both an n-channel MOSFET and a p-channel MOSFET may be used to configure a CMOS.

The above-described embodiments are examples of the present invention, and the present invention is not limited to these embodiments. For example, the present invention also includes the above-described embodiments in which some components or steps are added, deleted, or modified.

The present invention can be used, for example, in self-luminous elements of display devices.

1: Light emitting device 10: Support substrate 11: Bonding member 12: First interlayer insulating film 13: Compound semiconductor layer 14: Second silicon substrate 14a: Third surface 14b: Fourth surface 15: Oxide film 16: First silicon substrate 16a: First surface 16b: Second surface 17: Insulating film 18: First silicon oxide layer 19: Light reflecting member 20: Second interlayer insulating film 20b: Second silicon oxide layer 20c: Third silicon oxide layer 20d: Fourth silicon oxide layer 21: Protective film 29: Stacked body 30: Switching element 31: First semiconductor region 32: Second semiconductor region 33: Gate electrode 50: Light emitting element 51: First through hole 51a: Side surface 51b: Bottom surface 52: Insulating member 53: Wiring electrode 53a: First wiring 53b: Second wiring 53c: Conductive portion 53d: First conductive portion 53e: Second conductive portion 53f: Third conductive portion 53g: Fourth conductive portion 53h: Fifth conductive portion 54: Third wiring 55: Wavelength conversion member 56: Second through hole 57: Fourth wiring 61: Cover metal 62: p-side electrode 63: First semiconductor layer 64: Active layer 65: Second semiconductor layer 66: Hole 70: Reflective film 71: Color filter 72: Microlens 73: First upper wiring 74: Second upper wiring 101: SOI substrate 102: Silicon substrate 102a: Lower surface 103, 104, 105: Structure 106: Resist pattern 107, 108: Hole 109: Recess 111: First hole 112: Second hole 113: Third hole 114: Fourth hole Rl: Light emitting region Rp: Peripheral region Rs: Switching region

Claims (12)

a first silicon substrate including a first surface and a second surface opposite the first surface;
a second silicon substrate provided on the second surface side of the first silicon substrate, the second silicon substrate including a third surface facing the second surface and a fourth surface positioned on the opposite side to the third surface;
a switching element formed on the first surface of the first silicon substrate;
a light emitting element provided on the fourth surface side of the second silicon substrate;
An insulating member;
a wiring electrode provided in the insulating member and connecting the switching element to the light-emitting element;
Equipped with
a first through hole is formed in the first silicon substrate and the second silicon substrate;
the insulating member is provided on a side surface of the first through hole,
The insulating member has a second through hole through which the light emitting element is exposed. At least a portion of the first surface is of a first conductivity type;
The switching element is
a first semiconductor region and a second semiconductor region of a second conductivity type formed on the first surface;
an insulating film in contact with the first surface of the first silicon substrate between the first semiconductor region and the second semiconductor region;
a gate electrode provided on the insulating film;
having
The light-emitting element is
a first semiconductor layer of the first conductivity type;
A second semiconductor layer of the second conductivity type;
an active layer provided between the first semiconductor layer and the second semiconductor layer;
having
The light emitting device according to claim 1 , wherein the wiring electrode connects one of the first semiconductor layer and the second semiconductor layer to the first semiconductor region. The light-emitting device according to claim 2, wherein the first semiconductor layer, the active layer, and the second semiconductor layer contain gallium and nitrogen. The light emitting device according to any one of claims 1 to 3, further comprising a light reflecting member that covers the side surface of the first through hole and the first surface. The insulating member has a hole.
The wiring electrode is
a first wiring having a conductive portion located outside a region in which the light emitting element is provided when viewed from above and connected to the light emitting element;
a second wiring, at least a portion of which is provided within the hole and connected to the conductive portion and the switching element;
5. The light emitting device according to claim 1, further comprising: The light emitting device according to any one of claims 1 to 5, further comprising a wavelength conversion member provided in the second through hole. 7. The light emitting device according to claim 1, further comprising a support substrate bonded to the fourth surface of the second silicon substrate and to the light emitting element . a step of preparing a structure including: a first silicon substrate including a first surface and a second surface located opposite to the first surface, at least a portion of the first surface being of a first conductivity type; an insulating film provided on the first surface of the first silicon substrate; a second silicon substrate provided on the second surface side of the first silicon substrate, including a third surface facing the second surface and a fourth surface located opposite to the third surface; a light emitting element provided on the fourth surface of the second silicon substrate; and a first wiring connected to the light emitting element and having a conductive portion located outside a region in which the light emitting element is provided in a top view;
forming a gate electrode on the insulating film;
forming a first semiconductor region and a second semiconductor region of a second conductivity type on the first surface of the first silicon substrate by implanting impurities into the first surface of the first silicon substrate using the gate electrode as a mask;
forming a first through hole exposing the light emitting element by selectively removing the insulating film, the first silicon substrate, and the second silicon substrate from the insulating film side;
removing the insulating film to form a first hole exposing the first semiconductor region from the insulating film and a second hole exposing the second semiconductor region from the insulating film;
forming a second wiring that connects the conductive portion and the first semiconductor region;
A method for manufacturing a light emitting device comprising the steps of: The method for manufacturing a light-emitting device according to claim 8, further comprising the step of forming a light-reflecting member that covers the side surface of the first through-hole and the first surface of the first silicon substrate after the step of forming the first through-hole. forming an insulating member covering the light reflecting member and the light emitting element in the first through hole after the step of forming the light reflecting member;
forming a second through hole exposing the light emitting element by selectively removing the insulating member;
Further equipped with
The step of forming the second wiring includes :
forming a third hole in the insulating member to expose the conductive portion;
connecting the second wiring to the conductive portion through the third hole and to the first semiconductor region through the first hole;
The method for manufacturing a light emitting device according to claim 9 , comprising: The method for manufacturing a light emitting device according to claim 10, further comprising the step of forming a wavelength conversion member in the second through hole after the step of forming the second through hole in the insulating member. The method for manufacturing a light emitting device according to any one of claims 8 to 11, further comprising the step of bonding a support substrate to the fourth surface of the second silicon substrate and the light emitting element prior to the step of forming the gate electrode.

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