JP7516787B2 - Start-up control device, start-up control system, and start-up control method - Google Patents

Description

The present invention relates to a startup control device, a startup control system, and a startup control method.

Traditionally, PCI (Peripheral Component Interconnect) devices were installed in slots within information processing devices, so the number of PCI devices that could be installed was limited to the number of slots. In such cases, a configuration in which the PCI device is connected under the PCI port of the CPU (Central Processing Unit) is generally adopted. Meanwhile, in recent years, PCIE switches that connect CPUs and PCI devices in a many-to-many manner have been put into practical use as IO (Input Output) switches. PCIE switches allow logical division of connections between ports. Each logically divided section in a PCIE switch is sometimes called a partition.

When comparing connecting a PCI device under a PCI port with connecting a PCI device via a PCIE switch, various problems arise in connection control with the PCIE switch. When connecting a PCI device via a PCIE switch, for example, there are many errata for each manufacturer and model of the PCIE switch, as well as compatibility issues with transmission and usage with specific PCI devices connected under the PCIE switch.

When a system problem occurs in an information processing device, a workaround is implemented as a temporary measure to avoid the problem. However, in a configuration in which PCI devices are connected to a PCIE switch, multiple types of PCI devices are installed together, and it is difficult to provide a workaround that is suitable for the operation of each PCI device when such a variety of PCI devices are installed together.

Therefore, workarounds related to each PCI device are applied individually, but in that case, the following problems occur. For example, when a specific PCI device is hard reset, an unintended PCI link training process may be executed due to a bug caused by the hardware of the PCI device. This unintended link training process may cause the PCIE switch and PCI link to become unstable, causing a PCI error that is difficult to recover from just before the system starts at the end of the BIOS (Basic Input Output System) process, making it difficult to start the system normally. Therefore, it is possible to apply a workaround related to a PCI device having such a problem, but in that case, changes occur in each PCI device and bus control. As a result of the change, the PCI link with the PCIE switch of other PCI devices that were operating without problems may become unstable, and the PCI link may fail, making it difficult to properly recognize the PCI device that should have been operating without problems.

For this reason, it is preferable to selectively apply workarounds related to the PCI devices actually used, rather than unconditionally and uniformly applying workarounds related to the system configuration. Such recovery processing that takes PCI devices into consideration is generally performed by the BIOS or BMC (Baseboard Management Controller).

However, in large-scale systems, PCI switch partitions are often reconfigured. In large-scale systems where reconfiguration of PCI switch partitions changes the number of PCI devices and the processing units that manage the PCI devices, it is difficult to grasp management that involves changes to the partition configuration, including PCI switch settings. Therefore, in large-scale systems, it is preferable to manage the execution of workarounds using a system management unit that has the function of managing the entire system of the information processing device.

Here, we will explain a typical method of executing a conventional workaround using a system management unit. Here, we will explain an example in which there are multiple system units equipped with a CPU and memory and functioning as an information processing device, and multiple IO units equipped with PCIE switches and PCI devices and functioning as input/output devices.

After powering on each IO unit and each system unit, the system management firmware running on the system management unit controls the PCIE switch mounted on the IO unit and performs initial settings of the PCIE switch for system startup. Next, the system management firmware checks the mounting information of the PCI slots, as well as the link speed and number of lanes of the PCI bus. Next, the system management firmware implements a workaround that also serves as a retry process, and then passes processing to the BIOS running on the system unit.

The BIOS executes the system startup process, during which it performs a PCI bus scan. The BIOS then notifies the system management unit of the PCI bus tree information and PCI device information acquired in the PCI bus scan via the BMC on the system unit. This allows the system management firmware to recognize information on all installed PCI devices.

A conventional technique for managing PCI devices when using a PCIE switch is to obtain management information indicating the identifier and status of the PCI tree at startup, and to restart or cancel powering on the computer if the management information indicates that initialization is incomplete. There is also a conventional technique in which a management server receives information on the addition or change of a PCI device from a PCIE switch, determines the allocation status from the basic information of the PCI device, and has the PCIE switch perform the allocation. A further conventional technique using a system controller for system management is to initialize PCI devices connected to the bridge using initialization information stored in a shared memory in the bridge when initializing the host bus.

JP 2009-169842 A JP 2011-065551 A JP 2007-241526 A

However, in the conventional method of executing a workaround, the system management unit uses the link information notified from the PCIE switch as information about the PCI device until it obtains information about the PCI device from the BIOS via the BMC after the system is started. In other words, before obtaining information about the PCI device from the BIOS, it is difficult for the system management unit to recognize what PCI device is installed in each PCI slot. Therefore, it is difficult to identify the PCI device that is the target of the execution of a specific workaround and to limit the execution of the specific workaround to the identified PCI device. Therefore, the conventional system management unit uniformly executes the workaround for all installed PCI devices. In this case, it is difficult for the PCI device that is the target of the execution of the specific workaround and the PCI device that loses the normal link state and is no longer recognized by the BIOS as a result of the execution of the specific workaround to coexist in the same system. If the coexistence of PCI devices is restricted in this way, scalability is restricted and it becomes difficult to improve system performance.

Conventional technology that controls power-on based on the acquired PCI tree identifier and management information targets multi-root PCIE switches, and the PCI tree and PCI device information is set by the operator. As a result, it is difficult to automatically acquire PCI device information and control workarounds based on it, and there is a risk of restrictions on the coexistence of PCI devices. Furthermore, in conventional technology that uses a management server to assign PCI devices, it is possible to acquire detailed information about PCI devices, but it is difficult to control workarounds, and there is a risk of restrictions on the coexistence of PCI devices. Furthermore, in conventional technology in which a system controller initializes PCI devices connected to a bridge, a PCI driver running on the CPU acquires PCI device information after the system starts up, and it is difficult to identify the PCI device when a workaround is executed.

The disclosed technology has been developed in consideration of the above, and aims to provide a startup control device, startup control system, and startup control method that improve system performance.

In one aspect of the boot control device, boot control system, and boot control method disclosed in the present application, the device includes the following units. Before booting an information processing device to which multiple PCI slots are connected, the acquisition unit acquires PCI device information of each PCI device mounted in each of the PCI slots from a BIOS running on the information processing device. The determination unit identifies each of the PCI devices mounted in each of the PCI slots based on the PCI device information acquired by the acquisition unit. Furthermore, the determination unit selects a target PCI device on which a workaround is to be executed from among the PCI devices, and determines the type of workaround to be executed for each of the selected target PCI devices. The workaround execution unit executes the type of workaround determined by the determination unit on each of the target PCI devices, and causes the BIOS to execute the startup of the information processing device.

In one aspect, the present invention can improve system performance.

FIG. 1 is a diagram showing the hardware configuration of a server device. FIG. 2 is a block diagram of the server device according to the first embodiment. FIG. 3 is a diagram illustrating an example of a PCI physical information table. FIG. 4 is a diagram illustrating an example of a PCI bus tree table. FIG. 5 is a diagram illustrating an example of a PCI device table. FIG. 6 is a diagram illustrating an example of the workaround information table. FIG. 7 is a diagram illustrating an example of a PCI device determination table. FIG. 8 is a flowchart of a workaround execution process according to the first embodiment. FIG. 9 is a flowchart of a startup process according to the first embodiment. FIG. 10 is a block diagram of a server device according to the second embodiment. FIG. 11 is a diagram illustrating an example of a PCI device determination table according to the second embodiment. FIG. 12 is a flowchart of a workaround execution process according to the second embodiment. FIG. 13 is a flowchart of a startup process according to the second embodiment.

Below, examples of the start-up control device, start-up control system, and start-up control method disclosed in the present application are described in detail with reference to the drawings. Note that the start-up control device, start-up control system, and start-up control method disclosed in the present application are not limited to the following examples.

Figure 1 is a hardware configuration diagram of a server device. As shown in Figure 1, the server device 500 according to this embodiment has a system management unit 1, a system unit 2, and an IO unit 3. In this embodiment, the server device 500, which is an information processing system, has multiple system units 2 and IO units 3. The server device 500 also has two system management units 1. There is no particular limit to the number of system management units 1, system units 2, and IO units 3 mounted on the server device 500.

The system management unit 1 performs system management of the entire server device 500. For example, the system management unit 1 performs power-on and configuration management of the system unit 2 and IO unit 3. This system management unit 1 is an example of a "startup control device." The single system management unit 1 manages multiple system units 2 and IO units 3. The system management unit 1 has a microprocessor 11, memory 12, a CPLD (Complex Programmable Logic Device) 13, and a NIC (Network Interface Card) switch 14.

The microprocessor 11 is connected to the memory 12, the CPLD 13, and the NIC switch 14 via a bus. The microprocessor 11 realizes the various functions of the system management unit 1 by reading a program, expanding it in the memory 12, and executing it. For example, the microprocessor 11 expands the system management firmware 15 in the memory 12 and executes it. The microprocessor 11 also communicates with the IO unit 3 via the CPLD 13. The microprocessor 11 also communicates with the system unit 2 via the NIC switch 14.

The memory 12 is the main storage device in the system management unit 1. For example, a dynamic random access memory (DRAM) is used for the memory 12. For example, the system management firmware 15 is deployed and executed in the memory 12.

CPLD 13 is a communication module between IO unit 3. CPLD 13 communicates with PCIe switch 31 in IO unit 3 using I2C (Inter-Integrated Circuit).

The NIC switch 14 is a network interface with the system unit 2. The NIC switch 14 communicates with the BMC 24 of the system unit 2 in accordance with the IPMI (Intelligent Platform Management Interface) standard.

The system unit 2 is a device that executes specified arithmetic processing, and functions as an information processing device by itself. The system unit 2 has a CPU 21, memory 22, a PCH (Platform Controller Hub), a BMC 24, a BIOSROM (Read Only Memory) 25, and a BMCROM 26.

The CPU 21 is connected to the memory 22 via a memory bus. The CPU 21 is also connected to the PCH 23 via a PCIe (PCI express) bus. The CPU 21 executes arithmetic processing. The CPU 21 also implements various functions of the system unit 2 by expanding and executing various programs on the memory 22. For example, the CPU 21 reads a BIOS program from the BIOSROM 25 via the PCH 23, expands it on the memory 22 as a BIOS program 27, and executes it to perform hardware recognition processing at startup.

The memory 22 is the main storage device in the system unit 2. For example, a DRAM is used for the memory 22. The BIOS program 27 is expanded and executed in the memory 22.

The PCH 23 is connected to the CPU 21 and the BMC 24 via a PCIe bus. The PCH 23 is also connected to the BIOSROM 25 via a Serial Peripheral Interface (SPI). The PCH 23 relays communication between the CPU 21 and the BMC 24 and BIOSROM 25.

The BMC 24 is a management and monitoring microcomputer that operates independently of the OS (Operating System). The BMC 24, for example, monitors and diagnoses the CPU 21 and memory 22 of the system unit 2, and controls the power supply of the system unit 2.

The BIOSROM 25 is a ROM that stores the BIOS program. The BMCROM 26 stores the programs executed by the BMC 24.

The IO unit 3 functions as an input/output device that transmits and receives data and signals from an external interface to the system unit 2 and the like. The IO unit 3 has a PCIe switch 31 and a PCI slot 32.

The PCIe switch 31 has input/output ports between the PCI devices 4 and the CPU 21, and also has PCI slots 32 connected to each port. It relays communication between the CPU 21 of the system unit 2 and the PCI devices 4 implemented in the PCI slots 32. The PCIE switch 31 connects multiple CPUs 21 and multiple PCI devices 4 in a many-to-many manner. The PCIE switch 31 is capable of logically dividing the connections between the ports connected to the PCI slots 32, and each logically divided section is sometimes called a partition. The PCIE switch 31 connects each partition to the system unit 2 according to the settings. A PCI device 4 is connected to each of the PCI slots 32.

Figure 2 is a block diagram of a server device according to the first embodiment. In Figure 2, the functional units for system startup in the server device 500 are described, and other functions are not shown. Below, the operation of system startup in the server device 500, which is an information processing system, will be described with reference to Figure 2. Each system management unit 1 has the same function, each system unit 2 has the same function, and each IO unit 3 has the same function. Therefore, one each of the system management unit 1, system unit 2, and IO unit 3 is illustrated in Figure 2.

The system management unit 1 has a PCI physical information acquisition unit 101, a system startup control unit 102, a PCI device determination unit 103, a PCI device information acquisition unit 104, and a system power-on unit 105. The PCI physical information acquisition unit 101, the system startup control unit 102, the PCI device determination unit 103, the PCI device information acquisition unit 104, and the system power-on unit 105 are all realized by the microprocessor 11 and memory 12 in FIG. 1. More specifically, the PCI physical information acquisition unit 101, the system startup control unit 102, the PCI device determination unit 103, the PCI device information acquisition unit 104, and the system power-on unit 105 are functions of the system management firmware 15 executed by the microprocessor 11.

The system power-on unit 105 receives a partition startup command from the operator and powers on the system unit 2 and IO unit 3 that belong to that partition. The system power-on unit 105 then resets the system unit 2. The system power-on unit 105 then determines whether the power output of the system unit 2 is normal or not. If the power output of the system unit 2 is abnormal, the system power-on unit 105 displays an error log related to the power abnormality of the system unit 2 and then stops the startup of the device. On the other hand, if the power output of the system unit 2 is normal, the system power-on unit 105 releases the reset of the system unit 2.

When an operator inputs a start command for the system unit 2 and IO unit 3 belonging to a partition to the system management unit 1, the PCI physical information acquisition unit 101 accesses the PCIe switch 31 of each IO unit 3. Then, the PCI physical information acquisition unit 101 acquires PCI physical information indicating the mounting state of the PCI device 4 for each PCI slot 32 of each PCIe switch 31. Then, the PCI physical information acquisition unit 101 generates a PCI physical information table 121 shown in FIG. 3 in which the presence or absence of mounting of the PCI device 4 in each PCI slot 32 is registered. FIG. 3 is a diagram showing an example of a PCI physical information table.

As shown in FIG. 3, the PCI physical information table 121 registers the PCI slots 32 of each IO unit 3 for each IO unit 3. The PCI physical information table 121 also registers information indicating whether or not a PCI device 4 is mounted for each PCI slot 32 as the presence or absence of a card. Here, an example is described in which the PCI device 4 is a card-type device connected to the PCI slot 32. In the PCI physical information table 121, if the presence or absence of a card is "Yes", it indicates that a PCI device 4 is mounted in that PCI slot 32.

The PCI physical information acquisition unit 101 stores the generated PCI physical information table 121 in the memory unit 120.

When the system power-on unit 105 turns on the power and releases the reset of the system unit 2, the system startup control unit 102 initializes the PCIE switch 31. When the initialization of the PCIE switch 31 is completed successfully, the system startup control unit 102 starts the operation of the PCIE switch 31.

Then, the system startup control unit 102 instructs the PCI device determination unit 103 to execute a determination process for the PCI device 4. After that, if the PCI device information is not registered in the PCI device information table 124, the system startup control unit 102 receives a notification from the PCI device determination unit 013 that determination is not possible.

Here, the PCI device information table 124 will be described. In this embodiment, the PCI device information table 124 has a PCI bus tree table 124A shown in FIG. 4 and a PCI device table 124B shown in FIG. 5. FIG. 4 is a diagram showing an example of a PCI bus tree table. Also, FIG. 5 is a diagram showing an example of a PCI device table.

As shown in FIG. 4, the PCI slots 32 of each IO unit 3 are registered in the PCI bus tree table 124. The PCI bus range of each PCI slot 32 is registered in the PCI bus tree table 124 from the PCI bus tree information.

Each row of the PCI device table 124B corresponds to each row of the PCI bus tree table 124A. That is, each row of the PCI device table 124B represents information for each PCI slot 32. As shown in FIG. 5, the PCI device table 124B registers PCI device information, which is identification information for the PCI device 4 mounted in each PCI slot 32. In this embodiment, a set of a unique vendor ID, device ID, sub-vendor ID, and subsystem ID of the PCI device 4 operable in the server device 500 is defined as the PCI device information. If no PCI device is mounted in the PCI slot 32, it is not reflected in the PCI device table 124B. Furthermore, the PCI device table 124B registers the PCI bus number assigned to each PCI slot 32.

In this embodiment, all the information contained in the PCI bus tree table 124A and the PCI device table 124B is registered in the PCI device information table 124. However, it is sufficient that at least the information of each PCI slot 32 in which a PCI device 4 is mounted and the identification information of the corresponding PCI device 4 are registered in the PCI device information table 124.

On the other hand, if the PCI device information has already been registered in the PCI device information table 124, the system startup control unit 102 receives notification of the PCI slot 32 on which the workaround will be executed and information on the PCI device 4 mounted therein from the PCI device determination unit 103. Furthermore, the system startup control unit 102 receives input of identification information of the workaround to be executed for each PCI device 4 from the PCI device determination unit 103. Then, the system startup control unit 102 obtains the workaround number from the identification information of the workaround.

Then, the system startup control unit 102 selects one by one of the PCI slots 32 in which the PCI device 4 to be used for the workaround is mounted as a target PCI slot 32 for executing the workaround. Next, the system startup control unit 102 refers to the workaround information table 122 stored in the memory unit 120.

Figure 6 is a diagram showing an example of a workaround information table. In the workaround information table 122, details of the processing performed by each workaround to which a workaround number is assigned are registered in association with the workaround number. Processing performed by a workaround includes processing to perform a normal reset, processing to perform a hot reset that does not stop operation, processing to control and re-recognize the port of the PCIe switch 31, and processing to control and recover the PCIe link. In addition, the workaround information table 122 registers the number of times each workaround has been performed and the entity that performs each workaround.

Returning to FIG. 2, the explanation will be continued. The system startup control unit 102 obtains the contents of the process corresponding to the workaround number of the workaround to be performed on the PCI device 4 mounted in the target PCI slot 32 from the workaround information table 122. The system startup control unit 102 then executes each process included in the workaround to be performed on the PCI device 4 mounted in the target PCI slot 32.

The system startup control unit 102 establishes a link to the PCI slot 32 in which the PCI device 4 is mounted while executing a workaround for the PCI device 4 that is the target of the workaround. Furthermore, if a notification is received from the PCI device determination unit 103 that determination is impossible, the system startup control unit 102 establishes a link to the PCI slot 32 in which the PCI device 4 is mounted without executing a workaround.

Then, the system startup control unit 102 judges whether or not a link has been established normally for each PCI slot 32. For PCI slots 32 for which a link has not been established normally, the system startup control unit 102 performs a link retry process. Here, for PCI slots 32 for which a workaround has been executed, the system startup control unit 102 executes a similar workaround during the link retry process.

If a normal link is not established, the system startup control unit 102 repeats the link retry process up to three times. For a PCI slot 32 that does not implement a workaround, the system startup control unit 102 increments and stores the number of retries. In contrast, for a PCI slot 32 that has implemented a workaround, the system startup control unit 102 increments the number of WA retries in the workaround information table 122 and registers the number of retries. Then, if there is a PCI slot 32 for which a normal link is not established even after three link retries, the system startup control unit 102 gives up on establishing a link for that PCI slot 32 and instructs the BIOS startup processing unit 201 in the system unit 2 to execute BIOS processing.

Also, when the links of all PCI slots 32 are normally established, the system startup control unit 102 instructs the BIOS startup processing unit 201 of the system unit 2 to execute BIOS processing. This system startup control unit 102 is an example of a "workaround execution unit."

The PCI device determination unit 103 receives an instruction to execute a determination process for the PCI device 4 from the system startup control unit 102. The PCI device determination unit 103 then determines whether or not PCI device information for each PCI device 4 mounted on each IO unit 3 has already been registered in the PCI device information table 124 stored in the storage unit 120. The PCI device information is acquired by the BIOS startup processing unit 201 after the BIOS startup processing unit 201 of the system unit 2 completes a bus scan of the PCI device 4, and is registered in the PCI device information table 124 of the storage unit 120 by the PCI device information acquisition unit 104.

If the PCI device information is not registered in the PCI device information table 124, the PCI device determination unit 103 outputs a notification that determination is not possible to the system startup control unit 102. On the other hand, if the PCI device information is already registered in the PCI device information table 124, the PCI device determination unit 103 determines the workaround to be executed for the PCI device 4 mounted in each PCI slot 32.

Specifically, the PCI device determination unit 103 checks the PCI device information table 124 and identifies the PCI slot 32 in which the PCI device information is registered as the PCI slot 32 in which the PCI device 4 is mounted. Then, the PCI device determination unit 103 obtains the PCI device information of the PCI device 4 mounted in the identified PCI slot 32 from the PCI device information table 124.

Next, the PCI device determination unit 103 refers to the PCI device determination table 123 stored in the storage unit 120. FIG. 7 is a diagram showing an example of the PCI device determination table. As shown in FIG. 7, the PCI device determination table 123 registers PCI device information indicating the identification information of the PCI device 4 and whether or not a workaround (WA) is required, which indicates whether or not a workaround is required. In the WA required field in the PCI device determination table 123, information on the workaround to be executed for the PCI device 4 having each piece of PCI device information is registered. In FIG. 7, WA1 and WA2 are identification information indicating the type of workaround to be executed, and the number after WA indicates the workaround number.

Returning to FIG. 2, the explanation will be continued. The PCI device determination unit 103 checks the PCI device information of the PCI device 4 mounted in the PCI slot 32 to see whether WA is required in the PCI device determination table 123. Then, the PCI device determination unit 103 determines whether or not to perform a workaround for each PCI device 4.

Next, the PCI device determination unit 103 obtains, from the PCI device determination table 123, identification information of the workaround to be executed for the PCI device 4 mounted in each PCI slot 32. After that, the PCI device determination unit 103 notifies the system startup control unit 102 of the PCI slot 32 for executing the workaround and information of the PCI device 4 mounted therein. Furthermore, the PCI device determination unit 103 notifies the system startup control unit 102 of the identification information of the workaround to be executed for each PCI device 4.

After the BIOS startup processing unit 201 of the system unit 2 completes the PCI bus scan process, the PCI device information acquisition unit 104 receives input of PCI device-related information including PCI device information from the PCI device information transmission unit 212. The PCI device-related information includes the PCI device information, which is identification information of the PCI device 4 mounted in each PCI slot 32, as well as the PCI bus range, PCI bus number, etc. Then, the PCI device information acquisition unit 104 registers the acquired PCI device-related information in the PCI device information table 124 stored in the memory unit 120, thereby completing the PCI bus tree table 124A and the PCI device table 124B.

The system unit 2 has a BIOS startup processing unit 201 that executes the startup process of the system unit 2. The BIOS startup processing unit 201 is realized by the CPU 21 and memory 22 in FIG. 1. The BIOS startup processing unit 201 has a PCI bus scan processing unit 211, a PCI device information transmission unit 212, and a storage unit 213. The PCI bus scan processing unit 211 is realized by the BIOS that operates when the CPU 21 in FIG. 1 executes the BIOS program 27. In addition, the PCI device information transmission unit 212 is realized by the BMC 24 in FIG. 1.

The BIOS startup processing unit 201 receives a BIOS processing execution instruction from the system startup control unit 102. The BIOS startup processing unit 201 then causes the PCI bus scan processing unit 211 to execute a PCI bus scan process for the PCIe switches 31 of each system unit 2 and IO unit 3.

The PCI bus scan processing unit 211 executes a PCI bus scan process on the PCIe switches 31 of each system unit 2 and IO unit 3, and recognizes and initializes each PCI device 4. If the PCI bus scan is not completed within the timeout period, the PCI bus scan processing unit 211 displays an error log and then stops starting. On the other hand, if the PCI bus scan is completed, the PCI bus scan processing unit 211 acquires PCI-related information including PCI device information of the PCI devices 4 mounted in each PCI slot 32 of each PCIe switch 31.

Next, the PCI bus scan processing unit 211 determines whether or not a PCI device information table 221 already exists in the storage unit 213. If the PCI device information table 221 does not exist, the PCI bus scan processing unit 211 generates a PCI device information table 221 using the acquired PCI device-related information and stores it in the storage unit 213. This PCI device information table 221 may be the same as or different from the PCI device information table 124 possessed by the system management unit 1, as long as the PCI device-related information is registered. Then, the PCI bus scan processing unit 211 notifies the PCI device information transmission unit 212 of the creation of the PCI device information table 221.

In contrast, if a PCI device information table 221 exists, the PCI bus scan processing unit 211 determines whether the PCI device information acquired in the current bus scan process matches the PCI device information already registered in the PCI device information table 221. If the PCI device information does not match, the PCI bus scan processing unit 211 updates the PCI device information table 124. Then, the PCI bus scan processing unit 211 notifies the PCI device information transmission unit 212 to create the PCI device information table 221.

On the other hand, if the PCI device information matches, the PCI bus scan processing unit 211 notifies the BIOS startup processing unit 201 that the PCI bus scan is complete and starts the system.

The PCI device information transmission unit 212 receives notification of the creation of the PCI device information table 221 from the PCI bus scan processing unit 211. Next, the PCI device information transmission unit 212 acquires PCI device-related information including PCI device information from the PCI device information table 221 stored in the memory unit 213. Then, the PCI device information transmission unit 212 transmits the acquired PCI device-related information to the PCI device information acquisition unit 104 of the system management unit 1.

Next, the flow of the workaround execution process by the system management unit 1 according to the first embodiment will be described with reference to FIG. 8. FIG. 8 is a flowchart of the workaround execution process according to the first embodiment.

When a startup command is input from an operator to the system management unit 1, the PCI physical information acquisition unit 101 generates a PCI physical information table 121 (step S101). Then, the PCI physical information acquisition unit 101 stores the generated PCI physical information table 121 in the storage unit 120.

The system power-on unit 105 powers on the system unit 2 and the IO unit 3 in response to a startup command from the operator (step S102).

Next, the system power-on unit 105 determines whether the power output of the system unit 2 and the IO unit 3 is normal (step S103). If the power output is not normal (step S103: No), the system management unit 1 displays an error log and then stops startup (step S120).

In contrast, if the power output is normal (step S103: Yes), the system power-on unit 105 releases the system reset (step S104).

Next, the system startup control unit 102 initializes the PCIE switch 31 (step S105).

The system startup control unit 102 determines whether the initialization of the PCIE switch 31 has been completed successfully (step S106). If the initialization of the PCIE switch 31 has not been completed successfully (step S106: No), the system management unit 1 displays an error log and then stops startup (step S120).

On the other hand, if the initialization of the PCIE switch 31 is completed normally (step S106: Yes), the system startup control unit 102 starts the operation of the PCIE switch 31 (step S107). After that, the system startup control unit 102 requests the PCI device determination unit 103 to execute a workaround determination process.

The PCI device determination unit 103 receives a request to execute a workaround determination process from the system startup control unit 102. The PCI device determination unit 103 then determines whether or not PCI device information exists in the PCI device information table 124 (step S108). If no PCI device information exists (step S108: No), the workaround execution process proceeds to step S111.

On the other hand, if the PCI device information exists (step S108: Yes), the PCI device determination unit 103 acquires the PCI device information of the PCI device 4 mounted in each PCI slot 32 from the PCI device information table 124. Then, the PCI device determination unit 103 detects the PCI device information acquired from the PCI device determination table 123 and determines whether or not a PCI device 4 to be a workaround exists (step S109). If a PCI device 4 to be a workaround does not exist (step S109: No), the workaround execution process proceeds to step S111.

On the other hand, if there is a PCI device 4 to be a workaround target (step S109: Yes), the PCI device determination unit 103 obtains identification information of the workaround to be executed for each target PCI device 4 from the PCI device determination table 123. Then, the PCI device determination unit 103 notifies the system startup control unit 102 of the information of the PCI device 4 to be a workaround target and the PCI slot 32 in which it is mounted, as well as the identification information of the workaround to be executed. The system startup control unit 102 receives notification from the PCI device determination unit 103 of the information of the PCI device 4 to be a workaround target and the PCI slot 32 in which it is mounted, as well as the identification information of the workaround to be executed. Then, the system startup control unit 102 implements a workaround for the target PCI device 4 (step S110).

Then, the system startup control unit 102 establishes links for all PCI slots 32 in which PCI devices 4 are mounted. After that, the system startup control unit 102 determines whether link establishment has been completed normally for all PCI slots 32 (step S111).

If there is a PCI slot 32 for which link establishment has failed (step S111: No), the system startup control unit 102 performs a link retry process (step S112). At this time, the system startup control unit 102 similarly performs a workaround again for the PCI device 4 for which a workaround has been performed.

The system startup control unit 102 increments the number of times link retry processing is performed for each PCI slot 32 that failed to establish a link (step S113).

Then, the system startup control unit 102 determines whether the number of times the link retry process has been performed for each PCI slot 32 for which link establishment has failed is less than three (step S114). If the number of times the link retry process has been performed is less than three (step S114: Yes), the system startup control unit 102 returns to step S111.

On the other hand, if the link retry process has been performed three or more times (step S114: No), proceed to step S115.

On the other hand, if link establishment has been completed successfully for all PCI slots 32 (step S111: Yes), the system startup control unit 102 proceeds to step S115.

The system startup control unit 102 sends an instruction to execute BIOS processing to the BIOS startup processing unit 201 of the system unit 2 (step S115).

Then, the PCI device information acquisition unit 104 receives the PCI device information from the PCI device information transmission unit 212 of the system unit 2 (step S116).

Next, the PCI device information acquisition unit 104 registers the PCI device information in the PCI device information table 124 and stores it in the memory unit 120 (step S117).

Then, the PCI physical information acquisition unit 101 determines whether the PCI physical information table 121 has been sent to the PCI physical information acquisition unit 215 of the system unit 2 (step S118). If the PCI physical information table 121 has been sent to the PCI physical information acquisition unit 215 (step S118: Yes), the workaround execution process returns to step S108.

On the other hand, if the PCI physical information table 121 has not been sent to the PCI physical information acquisition unit 215 (step S118: No), the PCI physical information acquisition unit 101 sends the PCI physical information table 121 to the PCI physical information acquisition unit 215 of the system unit 2 (step S119). After that, the workaround execution process returns to step S108.

Next, the flow of the startup process by the system unit 2 according to the first embodiment will be described with reference to FIG. 9. FIG. 9 is a flowchart of the startup process according to the first embodiment.

The BIOS startup processing unit 201 receives a BIOS processing execution instruction from the system startup control unit 102 of the system management unit 1 (step S201).

The PCI bus scan processing unit 211 starts a PCI bus scan process for the PCIe switch 31 of each IO unit 3 (step S202).

Then, the PCI bus scan processing unit 211 determines whether the PCI bus scan for each PCIe switch 31 is completed within the timeout period (step S203).

If there is a PCIe switch 31 for which the PCI bus scan is not completed within the timeout period (step S203: No), the BIOS startup processing unit 201 notifies the system management unit 1 of the timeout. Upon receiving the timeout notification, the system startup control unit 102 of the system management unit 1 displays an error log and then stops the startup (step S204).

In contrast, if the PCI bus scan for each PCIe switch 31 is completed within the timeout period (step S203: Yes), the PCI bus scan processing unit 211 determines whether the memory unit 213 holds the PCI device information table 221 (step S205).

If the memory unit 213 holds the PCI device information table 221 (step S205: Yes), the PCI bus scan processing unit 211 compares the PCI device information obtained in this bus scan with the PCI device information registered in the PCI device information table 221. Then, the PCI bus scan processing unit 211 determines whether the respective PCI device information matches (step S206).

If the PCI device information table 221 does not exist (step S205: No) or the PCI device information does not match (step S206: No), the PCI bus scan processing unit 211 executes the following process. That is, the PCI bus scan processing unit 211 creates the PCI device information table 221 using the PCI-related information including the currently acquired PCI device information, and stores it in the storage unit 213 (step S207). After that, the PCI bus scan processing unit 211 notifies the PCI device information transmission unit 212 of the creation of the PCI device information table 221.

Upon receiving the notification from the PCI bus scan processing unit 211, the PCI device information transmission unit 212 acquires PCI-related information from the PCI device information table 221 and transmits it to the PCI device information acquisition unit 104 of the system management unit 1 (step S208). After that, the startup process proceeds to step S116 in FIG. 8.

On the other hand, if the PCI device information matches (step S206: Yes), the BIOS startup processing unit 201 starts the system (step S209).

As described above, the system management unit according to this embodiment identifies the PCI devices installed in each PCI slot using the PCI device information acquired by the BIOS through the PCI bus scan process. The system management unit then executes a workaround for each PCI device installed in each PCI slot. In this way, the system management firmware operating in the system management unit according to this embodiment and the BIOS operating in the system unit share PCI device information with each other before the system is started. This not only allows the display of PCI device information and the display of messages when errors occur, but also allows the implementation of workflows and BIOS retry processing for specific PCI devices. In other words, it is possible to suppress the execution of unnecessary workarounds for PCI devices, and to reduce adverse effects on PCI devices that operate normally. Therefore, the scalability is expanded by reducing the restrictions on the coexistence of PCI devices, and the system performance can be improved.

FIG. 10 is a block diagram of a server device according to the second embodiment. The system management unit 1 according to the second embodiment determines whether the PCI device 4 meets the mounting requirements of the server device 500. The system unit 2 according to the second embodiment executes a bus scan process according to the PCI physical information table 222. In the following description, the same operations as those of the components in the first embodiment may be omitted.

The system management unit 1 according to the present embodiment will be described. FIG. 11 is a diagram showing an example of a PCI device determination table according to the second embodiment. In the PCI device determination table 123 according to the present embodiment, in addition to whether WA is required, the mixing prohibition condition and the maximum number of mounted devices are registered. The mixing prohibition condition indicates information on PCI devices 4 that cannot be mixed and mounted in the same partition in which the ports of the PCIe switch 31 are logically divided. The maximum number of mounted devices indicates the upper limit of the number of PCI devices 4 that can be mounted per server device 500 and per partition. For example, in FIG. 11, the PCI device 4 with the maximum number of mounted devices described as 24/16 indicates that up to 24 PCI devices 4 can be mounted per server device 500 and up to 16 PCI devices can be mounted per partition.

In addition, if the PCI device information is not registered in the PCI device determination table 123, the PCI device 4 having that PCI device information is a PCI device 4 that is not supported by the server device 500. "Not supported" means, for example, that the operation has not been confirmed or is not guaranteed by the server device 500.

The PCI device determination unit 103 acquires PCI device information of the PCI devices 4 mounted in each PCI slot 32 from the PCI device information table 124. Next, the PCI device determination unit 103 determines whether or not there is any PCI device information that is not registered in the PCI device determination table 123 among the acquired PCI device information. If there is a PCI device 4 that is not supported by the server device 500, the PCI device determination unit 103 causes the system startup control unit 102 to display an error log and stop startup.

The PCI device determination unit 103 also refers to the PCI device determination table 123 to determine whether or not a pair of prohibited PCI devices 4 exists. If a pair of prohibited PCI devices 4 exists, the PCI device determination unit 103 causes the system startup control unit 102 to display an error log and stop startup.

The PCI device determination unit 103 also refers to the PCI device determination table 123 to determine whether or not there are any PCI devices 4 that are installed in a number greater than the maximum number that can be installed, i.e., the upper limit number that can be installed is exceeded. If there are any PCI devices 4 that exceed the upper limit number that can be installed, the PCI device determination unit 103 causes the system startup control unit 102 to display an error log and stop startup.

If there are no unsupported PCI devices 4, no PCI devices 4 that are prohibited from being mixed, or no PCI devices 4 that exceed the upper limit of the number that can be installed, the PCI device determination unit 103 identifies the PCI device 4 to be the target of the workaround. After that, the PCI device determination unit 103 notifies the system startup control unit 102 of information on the target PCI device 4 and the PCI slot 32 in which it is installed, as well as identification information for the workaround to be executed.

In addition, the PCI physical information acquisition unit 101 in this embodiment transmits the created PCI physical information table 121 to the PCI physical information acquisition unit 215 of the system unit 2.

Next, the system unit 2 according to this embodiment will be described. In addition to the units exemplified in the first embodiment, the system unit 2 according to this embodiment has a PCI physical information determination unit 214 and a PCI physical information acquisition unit 215.

The PCI physical information acquisition unit 215 receives the PCI physical information table 121 from the PCI physical information acquisition unit 101. Then, the PCI physical information acquisition unit 215 stores the acquired PCI physical information table 121 in the memory unit 213 as the PCI physical information table 222.

The PCI bus scan processing unit 211 starts executing a PCI bus scan for each PCIE switch 31. Then, after recognizing the PCI device 4 installed in each PCI slot 32, the PCI bus scan processing unit 211 outputs information about the PCI slot 32 in which it has been recognized that the PCI device 4 is installed to the PCI physical information determination unit 214.

Then, when the PCI bus scan processing unit 211 receives a notification from the PCI physical information determination unit 214 that an unrecognized PCI device 4 exists, it performs a link retry process. The PCI bus scan processing unit 211 repeats the recognition of the PCI device 4 and the notification of the information of the PCI slot 32 in which the PCI device 4 is recognized to be installed, until the number of link retry processes reaches three. When the link retry process reaches three, the PCI bus scan processing unit 211 ends the link retry process.

When a notification that recognition has been completed for all PCI devices 4 has been received from the PCI physical information determination unit 214, or when the link retry process has ended, the PCI bus scan processing unit 211 proceeds with the PCI bus scan process and performs initialization of each PCI device, etc.

After that, if the PCI bus scan process is completed within the timeout period, the PCI bus scan processing unit 211 determines whether or not a PCI device information table 221 exists and whether or not to create one based on the registered contents. If a PCI device information table 221 is to be created, the PCI bus scan processing unit 211 creates a new PCI device information table 221 and stores it in the memory unit 213. On the other hand, if a PCI device information table 221 is not to be created, the PCI bus scan processing unit 211 causes the BIOS startup processing unit 201 to start the system.

The PCI physical information determination unit 214 receives an input of information on the PCI slot 32 in which the PCI device 4 is recognized from the PCI bus scan processing unit 211. Then, the PCI physical information determination unit 214 acquires information on the PCI slot 32 in which the PCI device 4 is mounted from the PCI physical information table 222 stored in the storage unit 213. Then, the PCI physical information determination unit 214 compares the PCI slot 32 in which the PCI device 4 is recognized and the information on the PCI slot 32 in which the PCI device 4 is mounted acquired from the PCI physical information table 222. Then, the PCI physical information determination unit 214 determines whether all of the PCI devices 4 mounted in the PCI slot 32 in which the PCI device 4 is mounted acquired from the PCI physical information table 222 can be recognized. If there is a PCI device 4 that cannot be recognized, the PCI physical information determination unit 214 instructs the PCI bus scan processing unit 211 to perform a link retry process. If there is no PCI device 4 that has not been recognized, the PCI physical information determination unit 214 notifies the PCI bus scan processing unit 211 that recognition is complete.

Next, the flow of the workaround execution process by the system management unit 1 according to the second embodiment will be described with reference to FIG. 12. FIG. 8 is a flowchart of the workaround execution process according to the second embodiment.

When a startup command is input from an operator to the system management unit 1, the PCI physical information acquisition unit 101 generates a PCI physical information table 121 (step S301). Then, the PCI physical information acquisition unit 101 stores the generated PCI physical information table 121 in the storage unit 120.

The system power-on unit 105 powers on the system unit 2 and IO unit 3 that belong to the partition in response to a startup command from the operator (step S302).

Next, the system power-on unit 105 determines whether the power output of the system unit 2 and the IO unit 3 is normal (step S303). If the power output is not normal (step S303: No), the system startup control unit 102 displays an error log and then stops startup (step S323).

On the other hand, if the power output is normal (step S303: Yes), the system power-on unit 105 releases the system reset (step S304).

Next, the system startup control unit 102 initializes the PCIE switch 31 (step S305).

The system startup control unit 102 determines whether the initialization of the PCIE switch 31 has been completed successfully (step S306). If the initialization of the PCIE switch 31 has not been completed successfully (step S306: No), the system startup control unit 102 displays an error log and then stops the startup (step S323).

On the other hand, if the initialization of the PCIE switch 31 is completed normally (step S306: Yes), the system startup control unit 102 starts the operation of the PCIE switch 31 (step S307). After that, the system startup control unit 102 requests the PCI device determination unit 103 to execute a workaround determination process.

The PCI device determination unit 103 receives a request to execute a workaround determination process from the system startup control unit 102. The PCI device determination unit 103 then determines whether or not PCI device information exists in the PCI device information table 124 (step S308). If no PCI device information exists (step S308: No), the workaround execution process proceeds to step S314.

On the other hand, if PCI device information exists (step S308: Yes), the PCI device determination unit 103 acquires PCI device information of the PCI device 4 mounted in each PCI slot 32 from the PCI device information table 124. Next, the PCI device determination unit 103 checks whether or not there is PCI device information that is not registered in the PCI device determination table 123 among the acquired PCI device information. Then, the PCI device determination unit 103 judges whether or not there is an unsupported PCI device 4 in the server device 500 (step S309). If there is an unsupported PCI device 4 in the server device 500 (step S309: Yes), the system startup control unit 102 displays an error log and then stops startup (step S323).

If there is no unsupported PCI device 4 in the server device 500 (step S309: No), the PCI device determination unit 103 refers to the PCI device determination table 123 to determine whether there is a pair of PCI devices 4 that are prohibited from being mixed (step S310). If there is a pair of PCI devices 4 that are prohibited from being mixed (step S310: Yes), the system startup control unit 102 displays an error log and then stops the startup (step S323).

If there is no pair of prohibited PCI devices 4 (step S310: No), the PCI device determination unit 103 refers to the PCI device determination table 123 and determines whether there are any PCI devices 4 that exceed the upper limit of the number that can be mounted (step S311). If there are any PCI devices 4 that exceed the upper limit of the number that can be mounted (step S311: Yes), the system startup control unit 102 displays an error log and then stops the startup (step S323).

On the other hand, if there is no PCI device 4 that exceeds the upper limit (step S311: No), the PCI device determination unit 103 uses the PCI device determination table 123 to determine whether or not there is a PCI device 4 that is a workaround target (step S312). If there is no PCI device 4 that is a workaround target (step S312: No), the workaround execution process proceeds to step S314.

On the other hand, if there is a PCI device 4 to be a workaround target (step S312: Yes), the PCI device determination unit 103 obtains identification information of the workaround to be executed for each target PCI device 4 from the PCI device determination table 123. Then, the PCI device determination unit 103 notifies the system startup control unit 102 of the information of the PCI device 4 to be a workaround target and the PCI slot 32 in which it is mounted, as well as the identification information of the workaround to be executed. The system startup control unit 102 receives notification from the PCI device determination unit 103 of the information of the PCI device 4 to be a workaround target and the PCI slot 32 in which it is mounted, as well as the identification information of the workaround to be executed. Then, the system startup control unit 102 implements a workaround for the target PCI device 4 (step S313).

Then, the system startup control unit 102 establishes links for all PCI slots 32 in which PCI devices 4 are mounted. After that, the system startup control unit 102 determines whether link establishment has been completed normally for all PCI slots 32 (step S314).

If there is a PCI slot 32 for which link establishment has failed (step S314: No), the system startup control unit 102 performs a link retry process (step S315). At this time, the system startup control unit 102 similarly performs a workaround again for the PCI device 4 for which a workaround has been performed.

The system startup control unit 102 increments the number of times link retry processing is performed for each PCI slot 32 that failed to establish a link (step S316).

Then, the system startup control unit 102 determines whether the number of times the link retry process has been performed for each PCI slot 32 for which link establishment has failed is less than three (step S317). If the number of times the link retry process has been performed is less than three (step S317: Yes), the system startup control unit 102 returns to step S314.

On the other hand, if the link retry process has been performed three or more times (step S317: No), the system startup control unit 102 proceeds to step S318.

On the other hand, if link establishment is completed normally for all PCI slots 32 (step S314: Yes), the system startup control unit 102 proceeds to step S318.

The system startup control unit 102 sends an instruction to execute BIOS processing to the BIOS startup processing unit 201 of the system unit 2 (step S318).

Then, the PCI device information acquisition unit 104 receives the PCI device information from the PCI device information transmission unit 212 of the system unit 2 (step S319).

Next, the PCI device information acquisition unit 104 registers the PCI device information in the PCI device information table 124 and stores it in the memory unit 120 (step S320).

Then, the PCI physical information acquisition unit 101 determines whether the PCI physical information table 121 has been sent to the PCI physical information acquisition unit 215 of the system unit 2 (step S321). If the PCI physical information table 121 has been sent to the PCI physical information acquisition unit 215 (step S321: Yes), the workaround execution process returns to step S308.

On the other hand, if the PCI physical information table 121 has not been sent to the PCI physical information acquisition unit 215 (step S321: No), the PCI physical information acquisition unit 101 sends the PCI physical information table 121 to the PCI physical information acquisition unit 215 of the system unit 2 (step S322). After that, the workaround execution process returns to step S308.

Next, the flow of the startup process by the system unit 2 according to the second embodiment will be described with reference to FIG. 13. FIG. 13 is a flowchart of the startup process according to the second embodiment.

The BIOS startup processing unit 201 receives a BIOS processing execution instruction from the system startup control unit 102 of the system management unit 1 (step S401).

The PCI bus scan processing unit 211 starts a PCI bus scan process for the PCIe switch 31 of each IO unit 3 (step S402).

Then, the PCI bus scan processing unit 211 outputs information about the PCI slot 32 in which the PCI device 4 is recognized to the PCI physical information determination unit 214. The PCI physical information determination unit 214 determines whether the memory unit 213 holds the PCI physical information table 222 (step S403). If the memory unit 213 does not hold the PCI physical information table 222 (step S403: No), the startup process proceeds to step S408.

On the other hand, if the memory unit 213 holds the PCI physical information table 222 (step S403: Yes), the PCI physical information determination unit 214 identifies the PCI slots 32 for which mounting information is present in the PCI physical information table 222. Then, the PCI physical information determination unit 214 determines whether or not a PCI device 4 is present in the PCI slots 32 for which mounting information is present (step S404). If a PCI device 4 is present in all of the PCI slots 32 for which mounting information is present (step S404: Yes), the startup process proceeds to step S408.

On the other hand, if there is a PCI slot 32 in which a PCI device 4 does not exist among the PCI slots 32 with implementation information (step S404: No), the PCI physical information determination unit 214 notifies the PCI bus scan processing unit 211 of an instruction to perform a link retry process.

Then, the PCI bus scan processing unit 211 performs link retry processing (step S405).

After performing the link retry process, the PCI bus scan processing unit 211 increments the number of times the link retry process has been performed that is stored in itself (step S406).

Then, the PCI bus scan processing unit 211 determines whether the number of times the link retry process has been performed is less than three (step S407). If the number of times the link retry process has been performed is less than three (step S407: Yes), the startup process returns to step S404.

If the link retry process has been performed three or more times (step S407: No), the PCI bus scan processing unit 211 determines whether the PCI bus scan for each PCIe switch 31 has been completed within the timeout period (step S408).

If there is a PCIe switch 31 for which the PCI bus scan is not completed within the timeout period (step S408: No), the BIOS startup processing unit 201 notifies the system management unit 1 of the timeout. Upon receiving the timeout notification, the system startup control unit 102 of the system management unit 1 displays an error log and then stops the startup (step S409).

In contrast, if the PCI bus scan for each PCIe switch 31 is completed within the timeout period (step S408: Yes), the PCI bus scan processing unit 211 determines whether the memory unit 213 holds the PCI device information table 221 (step S410).

If the memory unit 213 holds the PCI device information table 221 (step S410: Yes), the PCI bus scan processing unit 211 compares the PCI device information obtained in this bus scan with the PCI device information registered in the PCI device information table 221. Then, the PCI bus scan processing unit 211 determines whether the respective pieces of PCI device information match (step S411).

If the PCI device information table 221 does not exist (step S410: No) or if the PCI device information does not match (step S411: No), the PCI bus scan processing unit 211 executes the following process. That is, the PCI bus scan processing unit 211 creates the PCI device information table 221 using the PCI-related information including the currently acquired PCI device information, and stores it in the storage unit 213 (step S412). After that, the PCI bus scan processing unit 211 notifies the PCI device information transmission unit of the creation of the PCI device information table 221.

Upon receiving the notification from the PCI bus scan processing unit 211, the PCI device information transmission unit 212 acquires PCI-related information from the PCI device information table 221 and transmits it to the PCI device information acquisition unit 104 of the system management unit 1 (step S413). After that, the startup process proceeds to step S319 in FIG. 12.

On the other hand, if the PCI device information matches (step S411: Yes), the BIOS startup processing unit 201 starts the system (step S414).

As described above, the system management unit of this embodiment uses PCI device information acquired by the BIOS through PCI bus scan processing to determine whether each PCI device meets the installation requirements of the server device. The system management firmware can check the presence or absence of unsupported PCI devices, check the maximum conditions per server device and partition, and check the mixed conditions within the partition before starting the system. If a PCI device that does not meet the installation requirements of the server device is present, an error log is created and startup is halted. This makes it possible to avoid startup failures and failures, improving system performance.

1 System management unit 2 System unit 3 IO unit 4 PCI device 11 Microprocessor 12 Memory 13 CPLD
14 NIC switch 15 System management firmware 21 CPU
22 Memory 23 PCH
24 BMC
25 BIOS ROM
26 BMC ROM
27 BIOS program 31 PCIe switch 32 PCI slot 101 PCI physical information acquisition unit 102 System startup control unit 103 PCI device determination unit 104 PCI device information acquisition unit 105 System power-on unit 120 Storage unit 121 PCI physical information table 122 Workaround information table 123 PCI device determination table 124 PCI device information table 201 BIOS startup processing unit 211 PCI bus scan processing unit 212 PCI device information transmission unit 213 Storage unit 214 PCI physical information determination unit 215 PCI physical information acquisition unit 221 PCI device information table 222 PCI physical information table 500 Server device (information processing system)

Claims (7)

a PCI device information acquisition unit that acquires, before booting of an information processing device to which a plurality of PCI slots are connected, PCI (Peripheral Component Interconnect) device information of each PCI device mounted in each of the PCI slots from a BIOS (Basic Input Output System) that operates on the information processing device;
a PCI device determination unit that identifies each of the PCI devices mounted in each of the PCI slots based on the PCI device information acquired by the PCI device information acquisition unit, selects a target PCI device on which a workaround is to be executed from each of the PCI devices, and determines a type of workaround to be executed for each of the selected target PCI devices;
a workaround execution unit that executes the workaround of the type determined by the PCI device determination unit on each of the target PCI devices and causes the BIOS to execute startup of the information processing device. The startup control device according to claim 1, characterized in that the PCI device determination unit identifies the PCI device installed in each of the PCI slots of the PCIe switch installed in the information processing device. The startup control device according to claim 1 or 2, further comprising a PCI physical information acquisition unit that acquires implementation information indicating whether or not the PCI device is installed in each of the PCI slots, transmits the acquired implementation information to the BIOS, and causes the BIOS to acquire the PCI device information based on the implementation information when the information processing device is started after the workaround execution unit executes the workaround. The start-up control device according to any one of claims 1 to 3, characterized in that the PCI device determination unit determines whether or not there is a non-permitted PCI device among the PCI devices that is not permitted to be installed in the PCI slot. The start-up control device according to claim 4, characterized in that the PCI device determination unit determines, as the unauthorized PCI devices, PCI devices whose operation is not guaranteed, PCI devices whose mixing is prohibited, and PIC devices whose number of mounted devices has exceeded the upper limit. An information processing system having a system unit, an IO (Input Output) unit, and a system management unit,
The IO unit includes:
a PCIe switch having a plurality of PCI slots;
a plurality of PCI devices mounted in any one of the PCI slots;
The system unit includes:
a BIOS startup processing unit that acquires PCI device information including identification information of each of the PCI devices mounted in each of the PCI slots and starts up the system unit to which the IO unit is connected;
The system management unit includes:
a PCI device information acquisition unit that acquires the PCI device information from the BIOS boot processing unit before booting of the system unit;
a PCI device determination unit that identifies each of the PCI devices mounted in each of the PCI slots based on the PCI device information acquired by the PCI device information acquisition unit, selects a target PCI device on which a workaround is to be executed from each of the PCI devices, and determines a type of workaround to be executed for each of the selected target PCI devices;
a workaround execution unit that executes the workaround of the type determined by the PCI device determination unit on each of the target PCI devices and causes the BIOS startup processing unit to execute startup of the system unit. Before booting an information processing device to which a plurality of PCI slots are connected, PCI device information of each PCI device mounted in each of the PCI slots is obtained from a BIOS operating in the information processing device;
Identifying each of the PCI devices mounted in each of the PCI slots based on the acquired PCI device information;
Based on the identification result, a target PCI device on which a workaround is to be executed is selected from among the PCI devices;
determining a type of workaround to implement for each selected target PCI device;
implementing the determined type of workaround for each of the target PCI devices;
A startup control method comprising: causing a processor mounted on the information processing device to execute a process of causing the BIOS to start up the information processing device.

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