JP7519072B2 - Semiconductor manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing semiconductors.

Patent Document 1 discloses a conventional method for forming a single crystal thin film. In this method, an amorphous thin film is first formed on a single crystal substrate. Then, a linear opening (channel portion) is formed in the amorphous thin film by etching, exposing the surface of the single crystal substrate. Then, under reduced pressure, a molecular beam is made incident on the opening at an incident angle of 40° or less with respect to the surface of the single crystal substrate, and a single crystal thin film is grown on the surface of the single crystal substrate where the opening is exposed. This method of growing a crystal in a limited area (opening) to obtain a crystal with reduced dislocation density is called a microchannel epitaxy method. In particular, a method of making a molecular beam incident on the surface of the single crystal substrate where the opening is exposed at an angle lower than a predetermined angle and growing a single crystal thin film on the surface of the single crystal substrate where the opening is exposed is called low incidence angle microchannel epitaxy (LAIMCE). Here, growing a crystal in a limited area (opening) is called selective growth.

JP 2000-247798 A

However, in the method of forming a single crystal thin film in Patent Document 1, if a dislocation occurs in the single crystal substrate located at the opening, the dislocation will propagate to the vertical single crystal thin film formed in the opening. Dislocations that propagate to the vertical single crystal thin film are called threading dislocations. By suppressing the propagation of dislocations in the single crystal substrate to the vertical single crystal thin film at the opening, it is expected that semiconductors of better quality can be manufactured.

The present invention was made in consideration of the above-mentioned conventional situation, and the problem to be solved is to provide a semiconductor manufacturing method capable of producing high-quality semiconductors.

The method for producing a semiconductor of the present invention comprises the steps of:
a mask layer forming step of forming a plurality of mask layers covering a substrate at different positions on the substrate;
a graphene layer lamination step of laminating a graphene layer on at least a surface of the substrate;
and a crystal growing step of growing a semiconductor crystal on the surface of the graphene layer laminated on the surface of the substrate.

This semiconductor manufacturing method allows crystals to grow on the surface of the graphene layer while preventing dislocations and defects in the substrate at the position where the graphene layer is stacked from propagating to the semiconductor crystals growing on the surface of the graphene layer.

1 is a schematic diagram showing a semiconductor manufacturing method according to a first embodiment. FIG. 2 is a schematic diagram showing how a growth nucleus grows in an opening. 5A to 5C are schematic diagrams illustrating a semiconductor manufacturing method according to a second embodiment. 11 is a schematic diagram showing a semiconductor manufacturing method according to a third embodiment. 11 is a schematic diagram showing a semiconductor manufacturing method according to a fourth embodiment. 11 is a schematic diagram showing a first and second semiconductor manufacturing method according to Example 5. FIG. 13 is a schematic diagram showing a third semiconductor manufacturing method according to Example 5.

A preferred embodiment of the present invention will be described.

In the semiconductor manufacturing method of the present invention, the graphene layer may be at least a single layer. With this configuration, since the graphene layer is a single layer, information on the atomic arrangement of the substrate is easily transmitted to the surface side of the graphene layer. Therefore, information such as the period of the crystal lattice of the substrate is easily transmitted to the semiconductor crystal growing on the surface of the graphene layer.

In the semiconductor manufacturing method of the present invention, the graphene layer lamination step is performed before the mask layer formation step, and the mask layer is formed on the surface of the graphene layer, and the mask layer may suppress the crystal growth of the semiconductor crystal on its own surface when the semiconductor crystal is grown on the surface of the graphene layer. In this way, when the semiconductor crystal is grown on the surface of the graphene layer, the region where the semiconductor crystal grows can be adjusted by the mask layer.

In the semiconductor manufacturing method of the present invention, the graphene layer lamination step may be performed after the mask layer formation step, and the graphene layer may be laminated on the surface of the mask layer and the surface of the substrate. This makes it easier to peel the mask layer from the semiconductor crystal when peeling the semiconductor crystal grown on the surface of the graphene layer from the substrate. In other words, it makes it easier to peel only the semiconductor crystal.

In the semiconductor manufacturing method of the present invention, the graphene layer may be laminated so as to cover the surface of the substrate between the multiple mask layers. This prevents direct crystal growth of the semiconductor crystal on the surface of the substrate, and reliably prevents dislocations and defects of the substrate from propagating to the semiconductor crystal.

In the semiconductor manufacturing method of the present invention, the mask layer may be a layer of graphene that is greater in number than the graphene layers between the multiple mask layers. With this configuration, the mask layer and the graphene layer are made of the same material, which makes it easier to simplify the procedure for forming the mask layer and the graphene layer on the substrate.

The semiconductor manufacturing method of Example 1 will be described with reference to Figures 1(a) to 1(f) and Figures 2(a) to 2(d).

Example 1
First, a graphene layer 31 is grown on the surface of a thin plate-like Cu (copper) (hereinafter also referred to as copper foil 50) as a catalytic metal by using a CVD (chemical vapor deposition) method (see FIG. 1(a)). Specifically, while a mixed gas of 50 sccm H ₂ (hydrogen) and 500 sccm N ₂ (nitrogen) is flowed as a carrier gas into a reaction tube, the temperature of the alcohol of the carbon raw material is kept at −1° C., and N ₂ (nitrogen) is bubbled and supplied at 10 sccm. In the reaction tube, the copper foil 50 is kept at 1000° C., and the graphene layer 31 is grown on the surface of the copper foil 50. The growth time is 30 minutes. The graphene layer 31 is a single layer of graphene.

Next, the graphene layer 31 formed on the surface of the copper foil 50 is transferred from the surface of the copper foil 50 to the surface of the substrate 30. The substrate 30 has a structure in which, for example, a GaN layer 30B made of GaN (gallium nitride) is crystal-grown to a thickness of 2 μm on a sapphire substrate 30A with the (0001) surface by MOCVD. First, a polymethyl methacrylate resin (hereinafter also referred to as PMMA) (not shown) is applied to the surface of the graphene layer 31 formed on the surface of the copper foil 50 by spin coating. Next, the copper foil 50 with PMMA applied to the surface of the graphene layer 31 is immersed in a ferric chloride solution. At this time, the copper foil 50 is immersed in the ferric chloride solution with the copper foil 50 facing down. In this way, the copper foil 50 dissolves in the ferric chloride solution, and the PMMA and graphene layer 31 do not dissolve in the etching solution and float on the surface of the ferric chloride solution.

Next, the PMMA and graphene layer 31 are floated in pure water for approximately 30 minutes, in dilute hydrochloric acid for approximately 30 minutes, and then in pure water for another 10 minutes. The PMMA and graphene layer 31 are lifted up using a slide glass or the like and transferred to the surface of the pure water or dilute hydrochloric acid. The graphene layer 31 is located below the PMMA. The ferric chloride adhering to the PMMA and graphene layer 31 is dissolved and removed by the dilute hydrochloric acid. The dilute hydrochloric acid adhering to the PMMA and graphene layer 31 is washed away with pure water.

[Graphene layer stacking process]
Next, a graphene layer lamination process is performed in which the graphene layer 31 is laminated on the surface of the substrate 30. Specifically, the PMMA and the graphene layer 31 are scooped up from the pure water using the substrate 30. Then, the PMMA and the graphene layer 31 are placed on the surface of the substrate 30. At this time, the lower surface of the graphene layer 31 abuts on the surface of the GaN layer 30B of the substrate 30. Then, the PMMA and the graphene layer 31 and the substrate 30 are subjected to a drying process at a predetermined temperature for a predetermined time. In this way, the adhesion between the graphene layer 31 and the substrate 30 is improved by evaporating the moisture and the like. Then, the PMMA and the graphene layer 31 and the substrate 30 are immersed in an acetone solution to remove the PMMA. Then, the graphene layer 31 and the substrate 30 are subjected to a drying process at a predetermined temperature for a predetermined time to remove the acetone. In this way, the graphene layer 31 is transferred to the surface of the substrate 30, and the graphene layer lamination process is completed (see FIG. 1(b)).

[Mask layer formation process]
Next, a mask layer forming process is performed in which a plurality of mask layers 32 are formed at different positions on the substrate 30. Specifically, a mask layer 32 made of SiO ₂ (silicon dioxide) is formed on the substrate 30 on which the graphene layer 31 has been transferred. Specifically, OCD (product name, manufactured by Tokyo Ohka Kogyo Co., Ltd.), which is a material for forming a coating, is spin-coated on the surface of the graphene layer 31 of the substrate 30. Then, the substrate is pre-baked at 100° C. for 10 minutes, and then heated in the air at 400° C. for 30 minutes to solidify the OCD. In this way, the mask layer 32 made of SiO ₂ (silicon dioxide) is formed on the surface of the graphene layer 31 by laminating it. That is, the graphene layer laminating process is performed before the mask layer forming process, so that the mask layer 32 is formed on the surface of the graphene layer 31.

Next, the mask layer 32 is formed into a predetermined shape. Specifically, a resist pattern (not shown) with a period of 500 μm and an opening width of 3 μm is formed on the surface of the mask layer 32 using photolithography or the like. Then, the mask layer 32 in the area where the resist pattern is not formed is removed using buffered hydrofluoric acid. This forms an opening 32A (channel portion) that opens in the mask layer 32. The opening 32A is linear in the front-to-back direction of the paper surface in FIG. 1(c). Then, the resist pattern is removed with a stripping solution or the like. In this way, the selective growth mask layer 32 is formed in a striped shape and has the opening 32A, and the mask layer formation process is completed. The surface of the graphene layer 31 is exposed in the opening 32A formed in the mask layer 32 (see FIG. 1(c)). Although only one opening 32A is shown in FIG. 1(c), in reality, multiple openings 32A are formed at intervals of 500 μm.

[Crystal growth process]
Next, a crystal growth step is performed to grow a GaN layer 33A on the surface of the graphene layer 31 laminated on the surface of the substrate 30. Specifically, a GaN layer 33 is laminated and grown on the surface of the graphene layer 31 transferred to the substrate 30 and the surface of the mask layer 32. The crystal growth of the GaN layer 33 is performed in two steps: vertical crystal growth of the GaN layer 33A in the opening 32A ( FIG. 1( d )), and lateral crystal growth of the GaN layer 33B from the GaN layer 33A crystal-grown in the opening 32A ( FIG. 1( f )).

[Vertical crystal growth in the opening]
1(e) is a plan view of the mask layer 32 with the opening 32A formed therein, seen from above. The vertical crystal growth of the GaN layer 33A in the opening 32A is performed by generating a growth nucleus 33C made of GaN at the end of the longitudinal direction of the opening 32A, and growing the growth nucleus 33C along the longitudinal direction (i.e., the lateral direction) of the opening 32A, as shown in FIG. 1(e), so that the GaN layer 33A is grown to cover the entire opening 32A. As a result, the entire GaN layer 33A is formed from one growth nucleus 33C in the opening 32A. In other words, no bonding occurs between the growth nucleus 33C and other adjacent growth nuclei during the growth process of the growth nucleus 33C.

If a bond occurs between adjacent growth nuclei, new dislocations and defects often occur at the bond interface between the growth nuclei. In addition, the graphene layer 31 is arranged in advance in the opening 32A so as to cover the surface of the GaN layer 30B. Therefore, even if dislocations or defects occur in the GaN layer 30B located in the opening 32A, the graphene layer 31 suppresses the propagation of dislocations and defects in the GaN layer 30B to the GaN layer 33A while the crystal growth of the GaN layer 33A proceeds (see FIG. 1(d)). As a result, the dislocation density of the GaN layer 33A growing in the opening 32A is greatly reduced compared to the crystal growth by the conventional microchannel epitaxy method. In this way, the method of growing crystals on the surface of the graphene layer 31 transferred to the surface of the substrate 30 is also referred to as remote epitaxy hereinafter.

[Growth of nuclei across defects in remote epitaxy]
In the growth process of one growth nucleus 33C in remote epitaxy, the occurrence of dislocations in the growth nucleus 33C can be suppressed. For example, as shown in FIG. 2A, the growth nucleus 33C is crystal-grown by remote epitaxy on the surface of the graphene layer 31 stacked on the substrate 30 in which the crystal lattice period is shifted in the lateral direction at the defect D. Here, the crystal lattice period being shifted in the lateral direction refers to the period of the crystal lattice on the left side of the defect D being shifted relatively in the lateral direction from the period of the crystal lattice on the right side of the defect D. In the growth process of the growth nucleus 33C, new atoms are bonded to the side of the growth nucleus 33C, so that the growth nucleus 33C grows larger by crystal growth along the surface of the graphene layer 31. As a method for bonding new atoms to the side of the growth nucleus 33C, it is considered to adopt low-angle incidence microchannel epitaxy (hereinafter, simply referred to as LAIMCE).

In conventional epitaxial growth (i.e., crystal growth without a graphene layer), the substrate 30 and the atoms of the growth nucleus 33C form bonds. For this reason, in conventional epitaxial growth, when the growth nucleus 33C continues to grow and straddles the defect D, the shift in the period of the crystal lattice of the substrate 30 is propagated to the growth nucleus 33C. However, in remote epitaxy, the growth nucleus 33C grows in a state where the bond between the substrate 30 and the growth nucleus 33C is blocked by the graphene layer 31. In remote epitaxy, the substrate 30 and the growth nucleus 33C do not form bonds. For this reason, the growth nucleus 33C can grow laterally without being affected by the defect D and without any problems, even in places where the defect D exists in the substrate 30. This allows one growth nucleus 33C to grow in a crystal without being affected by the dislocations and defects of the substrate 30 and without the occurrence of dislocations or defects.

Even though the bond between the substrate and the growth nuclei is interrupted by the graphene layer, the period of the crystal lattice of the substrate at the position where the growth nuclei are present can be transmitted to the growth nuclei via the graphene layer. For this reason, when one growth nucleus is generated on each side of defect D, the period of the crystal lattice of the substrate at the position where each growth nuclei was generated is transmitted to each growth nuclei via the graphene layer. For this reason, the phase consistency of the atomic arrangement of each growth nuclei differs from each other. As a result, when each growth nuclei grows into a crystal and bonds to each other, defects will occur at their interface.

Next, as shown in FIG. 2(c), a case will be considered in which a growth nucleus 33C grows by climbing over defect D in a substrate 30 in which the crystal lattice periods on the left and right sides of defect D are relatively shifted in the vertical direction. Even when growth nucleus 33C is formed on the surface of graphene layer 31 located on the substrate 30 to the left of defect D and growth nucleus 33C grows over defect D toward the right side of defect D, the crystal growth of growth nucleus 33C is lateral.

The crystal information of the substrate 30 (crystal lattice period, dislocations, and defects) transmitted from the substrate 30 through the graphene layer 31 is not strong enough to displace the positions of the atoms bonded to the side of the growth nucleus 33C. Therefore, the growth nucleus 33C continues its crystal growth in the lateral direction while inheriting the crystal lattice period of the growth nucleus 33C. As shown in FIG. 2(d), the thickness of the growth nucleus 33C changes on the left and right sides of the defect D, thereby absorbing the shift in the crystal lattice period that has shifted vertically across the defect D. As a result, defects and dislocations in the substrate 30 are not propagated to the growth nucleus 33C.

From the above considerations, it can be seen that in the opening 32A covered by the graphene layer 31, by growing a single growth nucleus 33C in the lateral direction to cover the entire opening 32A, it is possible to grow a GaN layer 33A in the opening 32A with almost no dislocations.

[Lateral crystal growth on the surface of the mask layer]
Next, the GaN layer 33B is grown laterally from the GaN layer 33A in the opening 32A. The GaN layer 33B is grown laterally by LAIMCE. The mask layer 32 has a function of suppressing the GaN layer 33A from growing on its own surface when the GaN layer 33A is grown on the surface of the graphene layer 31. Furthermore, the mask layer 32 has a function of suppressing the transmission of dislocations and defects of the substrate 30 to the GaN layer 33B. Therefore, in the lateral crystal growth on the surface of the mask layer 32, the GaN layer 33B grows without generating new dislocations or defects. Therefore, by combining the GaN layer 33A, which has almost no threading dislocations and which is grown on the opening 32A by remote epitaxy, and the GaN layer 33B, which is grown laterally from the GaN layer 33A, it is possible to obtain the GaN layer 33, which is a semiconductor crystal in which dislocations have been significantly reduced.

In LAIMCE, raw materials (TMG (trimethylgallium) and ammonia) are supplied to the substrate 30 at a low angle with the substrate 30 at a temperature of 860°C, and crystals are grown laterally from the GaN layer 33A in the opening 32A. The crystal growth time is 10 hours. This completes the crystal growth process.

The GaN layer 33B thus grown laterally was measured by cathode luminescence, and it was confirmed that the crystals were grown laterally with almost no dislocations. The results of the cathode luminescence measurement are not shown. It was also found that the dislocation density in the GaN layer 33A in the opening 32A was lower by one order of magnitude or more than the dislocation density (5×10 ⁸ cm ⁻² ) of the GaN layer 30B of the substrate 30. It was thus found that a good quality GaN layer 33 can be grown by performing remote epitaxy using a configuration in which the graphene layer 31 is laminated on the surface of the GaN layer 30B exposed in the opening 32A.

The above-described configuration of Example 1 provides the following advantages:

The semiconductor manufacturing method of Example 1 includes a mask layer forming process in which each of the multiple mask layers 32 is formed at a different position on the substrate 30, a graphene layer lamination process in which a graphene layer 31 is laminated on the surface of the substrate 30, and a crystal growth process in which a GaN layer 33A is crystal-grown on the surface of the graphene layer 31 laminated on the surface of the substrate 30. This semiconductor manufacturing method allows crystal growth on the surface of the graphene layer 31 while suppressing the propagation of dislocations and defects of the substrate 30 at the position where the graphene layer 31 is laminated to the GaN layer 33A grown on the surface of the graphene layer 31 by the graphene layer 31.

In the semiconductor manufacturing method of Example 1, the graphene layer 31 is a single layer. With this configuration, since the graphene layer 31 is a single layer, information on the atomic arrangement of the substrate 30 is easily transmitted to the surface side of the graphene layer 31. Therefore, information on the atomic arrangement of the substrate 30 is easily and effectively transmitted to the GaN layer 33A that grows as a crystal on the surface of the graphene layer 31.

In the semiconductor manufacturing method of Example 1, the graphene layer lamination process is performed before the mask layer formation process, and the mask layer 32 is formed on the surface of the graphene layer 31. The mask layer 32 suppresses the crystal growth of the GaN layer 33A on its own surface when the GaN layer 33A is grown on the surface of the graphene layer 31. This allows the mask layer 32 to adjust the region where the semiconductor crystal grows when the GaN layer 33A is grown on the surface of the graphene layer 31.

Example 2
Next, a semiconductor manufacturing method according to Example 2 will be described with reference to Fig. 3(a) to Fig. 3(d). The semiconductor manufacturing method according to Example 2 differs from Example 1 in that the graphene layer 131 is provided only in the opening 32A. The same components as those in Example 1 are denoted by the same reference numerals, and descriptions of the structures, functions, and effects will be omitted.

First, a mask layer formation step is performed to laminate a mask layer 32 having an opening 32A formed therein on the surface of the GaN layer 30B (see FIG. 3A). Specifically, OCD is applied to the surface of the substrate 30 by spin coating. The conditions for solidifying the OCD are the same as those in Example 1. In this way, a mask layer 32 made of _SiO2 (silicon dioxide) is laminated on the surface of the GaN layer 30B.

Next, a resist pattern with a period of 500 μm and an opening width of 3 μm is formed on the surface of the mask layer 32 using photolithography or the like. Then, the mask layer 32 in the areas where the resist pattern is not formed is removed using buffered hydrofluoric acid. This forms openings 32A in the mask layer 32. The resist pattern is then removed using a stripping solution or the like. In this way, a selective growth mask layer 32 is formed in a striped pattern with openings 32A, and the mask layer formation process is completed.

Next, a graphene layer lamination process is performed, and the graphene layer 131 is selectively grown and formed in the opening 32A. That is, the graphene layer lamination process is performed after the mask layer formation process. The graphene layer 131 is grown in the opening 32A of the mask layer 32 (i.e., the region where the surface of the GaN layer 30B is exposed) by using a low-pressure CVD apparatus. In the low-pressure CVD, a mixed gas of 100 sccm H ₂ (hydrogen) and 899 sccm N ₂ (nitrogen) is flowed into the reaction tube as a carrier gas, while 3-hexyne as a carbon raw material is kept at −12° C., and N ₂ (nitrogen) is bubbled at 1 sccm and supplied to the reaction tube. In the reaction tube, the substrate 30 is held at 900° C., and the graphene layer 131 is grown for 120 minutes. In this way, the graphene layer 131 made of a single layer of graphene is formed only in the opening 32A, and the graphene layer lamination process is completed (see FIG. 3B). The graphene layer 131 is laminated so as to cover the surface of the substrate 30 between the multiple mask layers 32 .

Next, a crystal growth process is performed, and remote epitaxy is performed to grow the GaN layer 33A in the opening 32A. Specifically, a growth nucleus 33C formed of GaN is generated at the end of the longitudinal direction of the opening 32A, and the growth nucleus 33C is grown along the longitudinal direction of the opening 32A (i.e., the lateral direction, the front-rear direction of the paper), thereby growing the GaN layer 33A so as to cover the entire opening 32A. As a result, the entire GaN layer 33A is formed from one growth nucleus 33C in the opening 32A. Since the graphene layer 131 is previously stacked in the opening 32A so as to cover the surface of the GaN layer 30B, the crystal growth proceeds by remote epitaxy. As a result, the dislocation density of the GaN layer 33A growing in the opening 32A is greatly reduced compared to the crystal growth by the conventional microchannel epitaxy method. This is because remote epitaxy suppresses bonding with other growth nuclei by growing one growth nucleus 33C in the lateral direction, and can also suppress the propagation of dislocations and defects in GaN layer 30B to GaN layer 33A. In other words, by growing one growth nucleus 33C and forming GaN layer 33A over the entire opening 32A, GaN layer 33A can be formed with almost no dislocations.

Next, lateral crystal growth is performed by LAIMCE (see FIG. 3(d)). The substrate temperature, growth source material, and crystal growth time in LAIMCE are the same as in Example 1. This completes the crystal growth process.

As a result of measuring the GaN layer 33B grown laterally from the GaN layer 33A by LAIMCE using cathodoluminescence, it was confirmed that a substantially dislocation-free lateral crystal growth region was obtained. It was also found that the dislocation density in the GaN layer 33A grown in the opening 32A was reduced by one order of magnitude or more compared to the dislocation density (5×10 ⁸ cm ⁻² ) of the GaN layer 30B of the substrate 30. Thus, it was found that the semiconductor manufacturing method of Example 2 can grow a high-quality GaN layer 33 by performing remote epitaxy using a configuration in which the graphene layer 31 is laminated on the surface of the GaN layer 30B exposed in the opening 32A.

The second embodiment configured as described above provides the following advantages:

In the semiconductor manufacturing method of Example 2, the graphene layer 131 is laminated so as to cover the surface of the substrate 30 between the multiple mask layers 32. This prevents the GaN layer 33A from growing crystals directly on the surface of the substrate 30, and reliably prevents dislocations and defects in the substrate 30 from propagating to the GaN layer 33A.

Example 3
Next, a semiconductor manufacturing method according to Example 3 will be described with reference to Fig. 4(a) to Fig. 4(f). The semiconductor manufacturing method according to Example 3 differs from Examples 1 and 2 in the method of forming a mask layer 232 having an opening 232A (channel portion) and the method of forming a graphene layer 231 in the opening 232A. The same components as those in Example 1 are denoted by the same reference numerals, and the description of the structure, action, and effect will be omitted.

First, the graphene layer lamination process is performed. Specifically, a graphene layer 231 is formed by laminating it on the surface of a substrate 230 made of Si (silicon) using either a transfer method or a direct growth method (precipitation growth) (see FIG. 4(a)). The graphene layer 231 is a single layer of graphene. This completes the graphene layer lamination process.

Next, a mask layer formation step is performed. First, a protective layer 70 is laminated on the surface of the graphene layer 231. Specifically, OCD is applied to the surface of the graphene layer 231 by spin coating. In this way, a protective layer 70 made of SiO ₂ (silicon dioxide) is laminated on the surface of the graphene layer 231. The protective layer 70 functions as a protective film that protects the graphene layer 231 during patterning of the graphene layer 231 and thermal oxidation.

Next, a resist pattern with a period of 200 μm and an opening width of 3 μm is formed on the surface of the protective layer 70 using photolithography or the like. The protective layer 70 is then patterned using buffered hydrofluoric acid to form a protective pattern layer 70A (see FIG. 4(b)). The protective pattern layer 70A is used to form a graphene layer 231 so as to cover the openings 232A described below.

Then, water vapor is supplied to the surface of the protective pattern layer 70A and the surface of the exposed graphene layer 231, and the surface of the substrate 230 is thermally oxidized. As a result, on both the left and right sides of the protective pattern layer 70A, Si (silicon) on the surface of the substrate 230 formed of Si (silicon) is oxidized and changed to SiO ₂ (silicon dioxide), forming a mask layer 232. In order to thermally oxidize the surface of the substrate 230, water is heated to 80° C., and water vapor generated from the water heated to 80° is supplied to the reaction tube while bubbling with N ₂ (nitrogen). The substrate 230 is heated at 1000° C. The thermal oxidation time is about 1 hour. The exposed graphene layer 231 located on both the left and right sides of the protective pattern layer 70A is etched and removed by water vapor at the initial stage of thermal oxidation (see FIG. 4(c)). Thereafter, the exposed surface of the substrate 230 located on both sides of the protection pattern layer 70A is thermally oxidized to be converted to _SiO2 (silicon dioxide), thereby forming mask layers 232 in the regions on both sides of the graphene layer 231 covered by the protection pattern layer 70A. The regions of the substrate 230 covered by the graphene layer 231 that are not etched by the water vapor are not thermally oxidized.

Next, only the protective pattern layer 70A is etched away using lithography to obtain a wafer that can be used for remote epitaxy and LAIMCE (see FIG. 4(e)). This completes the mask layer formation process.

The region of the substrate 230 below the graphene layer 231 is the substrate 230 that has not been thermally oxidized, and is the opening 232A. Therefore, if this wafer is used for epitaxy of Si (silicon), it is possible to perform remote epitaxy of homoepitaxy, in which the substrate 230 and the crystals that grow are of the same material, i.e., homo remote epitaxy. On the other hand, as in Examples 1 and 2, if this wafer is used for epitaxy (crystal growth) of a material such as GaN that is different from the substrate 230, it is possible to perform remote epitaxy of heteroepitaxy, in which the substrate and the crystals that grow are of different materials, i.e., hetero remote epitaxy.

Next, the case where this wafer is used for GaN hetero remote epitaxy (i.e., the crystal growth process) will be described. In remote epitaxy of the opening 232A, for example, growth nuclei are generated at the longitudinal ends of the opening 232A, and these growth nuclei are grown along the longitudinal direction of the opening 232A (i.e., the lateral direction, from the front to the back of the page), thereby performing crystal growth of the GaN layer 33A so as to cover the entire opening 232A. At this time, growth nuclei are less likely to be generated than when the substrate 230 is GaN. For this reason, the amount of Ga raw material supplied is increased slightly, the group V-group III ratio is increased, the growth temperature is lowered, or other conditions that make it easier for growth nuclei to be generated are selected, and crystal growth is started.

Once crystal growth begins, the growth conditions for remote epitaxy are not significantly different between homoepitaxy and heteroepitaxy. However, to maintain good crystal growth, the growth temperature is set slightly lower, and crystal growth is continued under conditions that make it easier to pick up crystal information from the substrate 230. This allows the entire GaN layer 33A to be formed from a single growth nucleus in the opening 232A. In other words, since adjacent growth nuclei do not bond during the growth process, there is no need to worry about new dislocations or defects being generated at the bonding interface between adjacent growth nuclei.

In addition, the graphene layer 231 is laminated in advance on the surface of the substrate 230 exposed to the opening 232A. Therefore, on the surface of the graphene layer 231, crystal growth proceeds by remote epitaxy. As a result, the dislocation density of the GaN layer 33A grown in the opening 232A is significantly reduced compared to crystal growth by conventional heteroepitaxial growth (i.e., heteroepitaxial growth without a graphene layer). In remote epitaxy, by growing one growth nucleus 33C in the lateral direction, it is possible to suppress bonding with other growth nuclei and suppress the propagation of dislocations and defects in the GaN layer 30B. Therefore, by growing one growth nucleus 33C in the lateral direction to form the GaN layer 33A over the entire opening 232A, the GaN layer 33A can be formed with almost no dislocations.

Next, lateral crystal growth is performed by LAIMCE (see FIG. 4(f)). The substrate temperature, growth source material, and crystal growth time in LAIMCE are the same as in Examples 1 and 2. This completes the crystal growth process.

The GaN layer 33B grown laterally from the GaN layer 33A by LAIMCE was measured by cathodoluminescence, and it was confirmed that a substantially dislocation-free lateral crystal growth region was obtained. The dislocation density in the GaN layer 33A in the opening 232A was 5×10 ⁸ cm ^-2 , which is a good value for heteroepitaxial growth. This result shows that the semiconductor manufacturing method of Example 3 (i.e., forming the opening 232A and the graphene layer 231 and performing remote epitaxy) allows the crystal growth of a good quality GaN layer 33.

Example 4
Next, a semiconductor manufacturing method according to Example 4 will be described with reference to Fig. 5(a) to Fig. 5(d) . The semiconductor manufacturing method according to Example 4 differs from Examples 1 to 3 in that a graphene layer 331 is laminated so as to cover the opening 32A and the mask layer 32.

First, a mask layer formation process is carried out to form a mask layer 32 having an opening 32A to be used as a channel on the substrate 230 by photolithography (see FIG. 5(a)). Specifically, the mask layer 32 is formed on the entire surface of the substrate 230 by using OCD or the like. Then, a resist pattern is formed on the surface of the mask layer 32 by photolithography, and the mask layer 32 in the area where the resist pattern is not formed is removed using buffered hydrofluoric acid to form the opening 32A. This completes the mask layer formation process.

Next, a graphene layer lamination process is performed in which the surfaces of the mask layer 32 and the opening 32A are covered with a graphene layer 331 using a technique such as transfer (see FIG. 5B). The graphene layer 331 is a single layer of graphene. That is, the graphene layer lamination process is performed after the mask layer formation process, and the graphene layer 331 is laminated on the surface of the mask layer 32 and the surface of the substrate 230. In this way, a wafer that can be used for remote epitaxy and LAIMCE can be obtained. The graphene layer 331 covers the mask layer 32 and the opening 32A. That is, the graphene layer 331 is present in the opening 32A. Therefore, remote epitaxy can be performed in the opening 32A.

Here, the mask layer 32 is amorphous. As a result, the mask layer 32 suppresses the transmission of crystal information of the substrate 230 located below it to the GaN layer 33B growing as crystals on its surface side, regardless of the presence or absence of the graphene layer 331. Therefore, remote epitaxy is not performed on the surface of the mask layer 32. Therefore, it is possible to practice the present invention using a wafer produced in this way, that is, to perform remote epitaxy in the opening 32A, and then to perform lateral crystal growth on the surface of the mask layer 32, thereby growing a GaN layer 33 with reduced dislocations and defects.

The fourth embodiment configured as described above has the following advantages:

In the semiconductor manufacturing method of Example 4, the graphene layer lamination process is performed after the mask layer formation process, and the graphene layer 331 is laminated on the surface of the mask layer 32 and the surface of the substrate 230. This makes it easier to peel the mask layer 32 from the GaN layer 33 when peeling the GaN layer 33 grown on the surface of the graphene layer 331 from the substrate 230. In other words, it makes it easier to peel off only the GaN layer 33.

Example 5
Next, a semiconductor manufacturing method according to Example 5 will be described with reference to Figures 6(a) to 6(f) and Figures 7(a) to 7(c). The semiconductor manufacturing method according to Example 5 differs from Examples 1 to 4 in that a multi-layer graphene layer 435 in which a plurality of graphenes are stacked is used as a mask layer 432. The same components as those in the above examples are denoted by the same reference numerals, and descriptions of the structures, functions, and effects will be omitted.

In Example 4, it was found that even if the graphene layer 331 is present on the surface of the mask layer 32, the crystal information of the substrate 230 (such as the period, dislocations, and defects of the crystal lattice) is not transmitted to the GaN layer 33B. This suggests that the graphene layer 331 itself can be used as the mask layer 32. It is therefore expected that a multi-layer graphene layer in which multiple graphene layers are stacked can be used as the mask layer.

As shown in FIG. 6A, a graphene layer 431 made of a single layer of graphene is used in the opening 432A (channel portion), and a multi-layer graphene layer 435 in which multiple layers of graphene are stacked is used in the mask layer 432. In other words, the mask layer 432 is a multi-layer of graphene. Here, the graphene layer 431 in the opening 432A is not limited to a single layer, and may be a two-layer or three-layer graphene layer depending on the material of the crystal to be subjected to remote epitaxy. As a result, in the opening 432A, crystal information such as the period of the crystal lattice of the GaN layer 30B is mainly transmitted to the GaN layer 33A through the graphene layer 431, and remote epitaxy can be performed.

On the other hand, the mask layer 432 formed by the multi-layer graphene layer 435 functions as a layer that suppresses the propagation of the crystal information of the GaN layer 30B without transmitting the crystal information of the GaN layer 30B to the GaN layer 33B. In this sample, a layer covering the surface of the GaN layer 30B is formed by two different numbers of graphene layers: the multi-layer graphene layer 435 that forms the mask layer 432, and a single graphene layer 431 (or two or three graphene layers) in the opening 432A. Hereinafter, a layer having such a structure will be referred to as a double graphene mask. There are several methods for producing a double graphene mask, as shown below.

[First method]
First, a multi-layer graphene layer 439 is formed on the surface of the GaN layer 30B by using a method such as transfer or precipitation growth, and then patterned (see FIG. 6B). Specifically, the multi-layer graphene layer 439 is laminated on the surface of the GaN layer 30B. Next, a resist pattern is formed on the surface of the multi-layer graphene layer 439, and the exposed multi-layer graphene layer 439 is etched and removed by oxygen plasma treatment. This forms an opening 437 in the multi-layer graphene layer 439. Then, the multi-layer graphene layer 439 and the opening 437 are covered with a single graphene layer 436 by using a method such as CVD or transfer. In this way, a double graphene mask M1 can be formed by using the first method (see FIG. 6C). In the double graphene mask M1, the portion where the graphene layer 436 is laminated on the multi-layer graphene layer 439 is the mask layer 432, and the graphene layer 436 covering the surface of the GaN layer 30B is the graphene layer 431. The opening 437 covered by the graphene layer 436 is the opening 432A.

[Second method]
First, a single graphene layer 231 is laminated on the surface of the GaN layer 30B using either a transfer method or a direct growth method (precipitation growth) (see FIG. 6(d)). Next, a multi-layer graphene layer 439 having an opening 437 formed on the surface of the graphene layer 231 is laminated using a method such as precipitation growth. In the precipitation growth, an amorphous carbon layer, a Ni (nickel) catalyst layer, and a W (tungsten) cap layer are vapor-deposited in this order on the surface of the graphene layer 231 using an electron beam vapor deposition device to form a laminated structure. The sample thus produced is heat-treated, for example, at 900° C. for 30 minutes using an infrared lamp annealing device. As a result, a multi-layer graphene layer 439 is generated on the surface of the graphene layer 231. Thereafter, the Ni (nickel) catalyst layer is etched away using dilute aqua regia, leaving the multi-layer graphene layer 439 on the graphene layer 231.

To form the opening 437, in the above process, before the deposition of the W (tungsten) cap layer, a pattern is formed with resist in the area where the opening 437 is to be formed on the Ni (nickel) catalyst layer. Then, using an electron beam deposition device, the W (tungsten) cap layer is deposited on the surface of the Ni (nickel) catalyst layer and the resist pattern. This makes it possible to perform lift-off. In lift-off, when the resist pattern is dissolved and removed with acetone or the like, the W (tungsten) cap layer deposited on the resist pattern is also removed together with the resist pattern. As a result, only the W (tungsten) cap layer (i.e., the W (tungsten) cap layer deposited directly on the Ni (nickel) catalyst layer) remains in the area where the resist pattern was not formed. In this case, by using lift-off, the W (tungsten) cap layer is left only in the area where the mask layer 432 is to be formed. When a heat treatment is performed using an infrared lamp annealing device on the sample on which the W (tungsten) cap layer pattern is thus formed, a multi-layer graphene layer 439 is generated at the interface between the Ni (nickel) catalyst layer and the graphene layer 231 in the region where the W (tungsten) cap layer is present. After that, when the Ni (nickel) catalyst layer and the like are etched away using dilute aqua regia, a double graphene mask M2 can be formed in which the single graphene layer 231 is present in the opening 437 and the multi-layer graphene layer 439 is present in the mask layer 432.

In this way, the double graphene mask M2 can be formed using the second method (see FIG. 6(e)). In the double graphene mask M2, the portion in which the multi-layer graphene layer 439 is laminated on the graphene layer 231 is the mask layer 432, and the graphene layer 231 with the exposed surface is the graphene layer 431. The opening 437 is the opening 432A. By forming the double graphene masks M1 and M2 on the surface of the substrate 30 in this way, as shown in FIG. 6(f), remote epitaxy of the opening 432A and lateral crystal growth of the GaN layer 33B from the GaN layer 33A crystal-grown in the opening 432A can be achieved.

[Third method]
As shown in FIG. 7A, a graphene layer 531 is grown by CVD on the surface of a substrate 92 having a structure in which a thin film 91 of either Au (gold) or Cu (copper) is deposited only on the surface of a Ni (nickel) foil 90 in an area corresponding to an opening (i.e., a linear area extending in the front-rear direction of the paper). Then, even under conditions in which a multi-layer graphene layer grows on the surface of the Ni (nickel) foil 90, the solubility of the carbon raw material is low on the surface of the thin film 91. For this reason, a single graphene layer (or two or three graphene layers) grows on the surface of the thin film 91. Therefore, by using a substrate 92 having such a structure, a double graphene mask M3 can be produced by one CVD growth, as shown in FIG. 7B. Then, the double graphene mask M3 thus produced is transferred to the surface of the substrate 30 (see FIG. 7C). In the double graphene mask M3, multiple graphene layers formed on the surface of the Ni (nickel) foil 90 are the mask layer 432, and a single graphene layer formed on the surface of the thin film 91 is the graphene layer 431. The opening 432A is a portion between the multiple graphene layers formed on the surface of the Ni (nickel) foil 90. This makes it possible to manufacture a wafer that can be used for remote epitaxy and LAIMCE.

The fifth embodiment configured as described above provides the following advantages:

In the semiconductor manufacturing method of Example 5, the mask layer 432 is made of graphene having a greater number of layers than the graphene layers 431 between the multiple mask layers 432. With this configuration, the mask layer 432 and the graphene layer 431 are made of the same material, which makes it easier to simplify the procedure for forming the mask layer 432 and the graphene layer 431 on the substrate 30.

The present invention is not limited to the first to fifth embodiments described above with reference to the drawings, and the following embodiments are also included within the technical scope of the present invention.
(1) In Examples 1 to 5, sapphire with the (0001) surface is used for the substrate body. However, the present invention is not limited to this. A sapphire substrate with another surface, SiC (silicon carbide), ZnO (zinc oxide), Si (silicon), GaN, etc. may also be used.
(2) Instead of laminating SiO ₂ (silicon dioxide) as a mask layer, a material that prevents remote epitaxy, such as AlO (aluminum oxide) or SiN (silicon nitride), may be laminated.
(3) In Examples 1 to 5, the graphene layer is a single layer of graphene. However, the number of graphene layers in the graphene layer may be changed as appropriate depending on the material from which the crystal is grown. In other words, the graphene layer may be at least a single layer.

30, 230... Substrate 31, 131, 231, 331, 431... Graphene layer 32, 232, 432... Mask layer 33A... GaN layer (semiconductor crystal)

Claims (5)

a mask layer forming step of forming a plurality of mask layers covering a substrate at different positions on the substrate;
a graphene layer lamination step of laminating a graphene layer on at least a surface of the substrate;
a crystal growth step of growing a semiconductor crystal on the surface of the graphene layer laminated on the surface of the substrate;
Equipped with
A method for manufacturing a semiconductor device , wherein a linear opening is formed between adjacent mask layers . a mask layer forming step of forming a plurality of mask layers covering a substrate at different positions on the substrate;
a graphene layer lamination step of laminating a graphene layer on at least a surface of the substrate;
a crystal growth step of growing a semiconductor crystal on the surface of the graphene layer laminated on the surface of the substrate;
Equipped with
The graphene layer laminating step is performed after the mask layer forming step, and the graphene layer is laminated on a surface of the mask layer and a surface of the substrate. a mask layer forming step of forming a plurality of mask layers covering a substrate at different positions on the substrate;
a graphene layer lamination step of laminating a graphene layer on at least a surface of the substrate;
a crystal growth step of growing a semiconductor crystal on the surface of the graphene layer laminated on the surface of the substrate;
Equipped with
The graphene layer is laminated so as to cover a surface of the substrate between a plurality of the mask layers;
The mask layer is a layer of graphene having a greater number of layers than the graphene layers between the multiple mask layers. The method for manufacturing a semiconductor according to any one of claims 1 to 3, wherein the graphene layer is at least a single layer of graphene. The graphene layer lamination step is performed before the mask layer formation step, and the mask layer is formed on a surface of the graphene layer;
The method for producing a semiconductor according to claim 1 or claim 4 , wherein the mask layer suppresses crystal growth of the semiconductor crystal on a surface of the mask layer when the semiconductor crystal is grown on a surface of the graphene layer.

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