JP7546783B2 - Semiconductor device, power conversion device, and method for manufacturing the semiconductor device - Google Patents

Description

The present disclosure relates to a semiconductor device, a power conversion device, and a method for manufacturing a semiconductor device having a configuration in which components are sealed with a sealing material.

Industrial equipment, home appliances, information terminals, etc. equipped with power semiconductor devices are becoming more common. There is a demand for miniaturization of power semiconductor devices as semiconductor modules mounted in home appliances.

Because power semiconductor devices handle high voltages and large currents, they generate a large amount of heat. Therefore, in order to pass a certain amount of current through a power semiconductor device, it is necessary to efficiently dissipate the heat generated in the power semiconductor device to the outside of the power semiconductor device while maintaining electrical insulation from the outside.

One known example of such a power semiconductor device structure is a sealing structure in which a lead frame and an electronic component mounted on one side of the lead frame are sealed with a molding resin as a sealing material. The electronic component is, for example, a power semiconductor element. The molding resin is, for example, an epoxy-based thermosetting resin.

Patent document 1 discloses the configuration of a power semiconductor device having a sealing structure in which a semiconductor element is sealed with a molded resin as a sealing material (hereinafter also referred to as "related configuration A").

Furthermore, power semiconductor devices are required to efficiently dissipate heat from the other surface of the lead frame opposite the one surface mentioned above. This one surface is the surface on which electronic components are mounted. Power semiconductor devices are also required to ensure electrical insulation between the other surface of the lead frame and the outside.

To meet these demands, there is a power semiconductor device that has an insulating layer on the other side of the lead frame, and that insulating layer is exposed from the molded resin. For example, a ceramic substrate or a thermosetting resin layer made of epoxy resin is used as the insulating layer.

In such power semiconductor devices, when a sealing material such as molding resin is injected into a mold die, the sealing material may flow into the gap between the lead frame on which the electronic components are mounted and the mold die, resulting in resin burrs. Such gaps may arise, for example, due to dimensional tolerances of the lead frame.

Therefore, for example, Patent Document 2 discloses a configuration (hereinafter also referred to as "related configuration B") that suppresses the occurrence of resin burrs. Related configuration B is a configuration in which a semiconductor chip, which serves as a semiconductor element, is sealed with molded resin, which serves as a sealing material. In related configuration B, the insulating layer provided on the other surface of the lead frame is made of thermoplastic resin. The thermoplastic resin is a material that chemically bonds with epoxy resin, which is the molded resin, which serves as a sealing material.

International Publication No. 2019/216160 JP 2013-258354 A

In configurations such as related configurations A and B, in which a semiconductor element is sealed with a sealing material, high heat dissipation is required. Related configuration B is a configuration in which an insulating layer, which is a member through which heat generated by a semiconductor chip serving as a semiconductor element is transmitted, is exposed from a molded resin serving as a sealing material. Therefore, the heat dissipation of a semiconductor device of related configuration B is higher than that of a semiconductor device of related configuration A.

However, the insulating layer of the semiconductor device of related configuration B is made of a thermoplastic resin with low thermal conductivity. Therefore, the heat dissipation properties of the semiconductor device of related configuration B cannot be said to be excellent.

The present disclosure has been made to solve such problems, and aims to provide a semiconductor device with high heat dissipation properties, a power conversion device to which the semiconductor device is applied, and a method for manufacturing the semiconductor device.

In order to achieve the above-mentioned object, the semiconductor device of the present disclosure comprises a die pad having a first surface which is one surface and a second surface which is the other surface, a semiconductor element mounted on the first surface of the die pad, a heat sink having a third surface which is one surface and a fourth surface which is the other surface, an insulating layer present between the die pad and the heat sink, and a sealing material that seals the semiconductor element, the die pad, the insulating layer and the heat sink, wherein the second surface of the die pad is the surface of the die pad opposite the first surface, the insulating layer is in contact with the second surface of the die pad and the third surface of the heat sink, the fourth surface of the heat sink is the surface of the heat sink opposite the third surface, and the fourth surface of the heat sink, having the third surface in contact with the insulating layer, is an exposed surface exposed from the sealing material. A recess and a protrusion are formed on the periphery of the exposed surface of the heat sink , the recess extends along the periphery of the exposed surface of the heat sink, the exposed surface is polygonal in shape, and the recess extends along only one of the multiple sides that make up the polygon .

The power conversion device of the present disclosure has the above-mentioned semiconductor device and is equipped with a main conversion circuit that converts and outputs the input power, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

The method for manufacturing a semiconductor device according to the present disclosure uses a mold die having a cavity and a bottom surface facing the cavity. The semiconductor device includes a die pad having a first surface as one surface and a second surface as the other surface, a semiconductor element, a heat sink having a third surface as one surface and a fourth surface as the other surface, and an insulating layer, the second surface of the die pad being the surface of the die pad opposite the first surface, and the fourth surface of the heat sink being the surface of the heat sink opposite the third surface. The manufacturing method includes the steps of (a) mounting the semiconductor element on the first surface of the die pad, (b) arranging the die pad, the insulating layer, and the heat sink in the cavity of the mold die so that the die pad, the insulating layer, and the heat sink are in a sealing compatible state, and (c) injecting an encapsulant into the cavity of the mold die. The sealing-compatible state is a state in which the insulating layer is present between the die pad and the heat sink, the sealing-compatible state is a state in which the insulating layer is in contact with the second surface of the die pad and the third surface of the heat sink, and the sealing-compatible state is a state in which the fourth surface of the heat sink is in contact with the bottom surface of the molding die, step (c) is performed after step (b), and in step (c), a sealing material is injected into the cavity of the molding die such that the fourth surface of the heat sink having a third surface in contact with the insulating layer is exposed from the sealing material , and a depression is formed in the exposed surface, which is the fourth surface of the heat sink, and in step (c), the sealing material is injected into the cavity of the molding die such that the sealing material flows in a specific direction, the depression extending along the periphery of the exposed surface of the heat sink, and when step (c) is performed, the heat sink is positioned such that the direction in which the depression extends intersects the specific direction, and the depression is formed only in a region of the periphery of the exposed surface of the heat sink positioned when step (c) is performed that intersects with the specific direction .

According to the semiconductor device of the present disclosure, a semiconductor element is mounted on a first surface of a die pad. An encapsulant encapsulates the semiconductor element, the die pad, the insulating layer, and the heat sink. The insulating layer is between the die pad and the heat sink. The insulating layer is in contact with a second surface of the die pad and a third surface of the heat sink. A fourth surface of the heat sink, the third surface of which is in contact with the insulating layer, is exposed from the encapsulant.

That is, the heat sink is in contact with the insulating layer that contacts the die pad on which the semiconductor element is mounted. Furthermore, the heat sink in contact with the insulating layer is exposed from the sealing material. Therefore, due to the action of the heat sink, the semiconductor device of the present disclosure has higher heat dissipation properties than the semiconductor device of related configuration B in which the insulating layer is exposed from the sealing material. Therefore, it is possible to provide a semiconductor device with high heat dissipation properties.

The power conversion device according to the present disclosure also includes the semiconductor device described above. This makes it possible to obtain a power conversion device with high heat dissipation properties.

According to the method for manufacturing a semiconductor device disclosed herein, a sealant is injected into a cavity of a mold die such that a fourth surface of a heat sink having a third surface in contact with an insulating layer is exposed from the sealant. This allows a semiconductor device with high heat dissipation properties to be manufactured.

The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is a plan view of a semiconductor device according to a first embodiment; 1 is a cross-sectional view of a semiconductor device according to a first embodiment; 1 is a diagram showing a configuration of a lead frame according to a first embodiment; FIG. 2 is a plan view showing the configuration of a recess. FIG. 4 is a cross-sectional view showing the configuration of a recess. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to a first embodiment. 1 is a cross-sectional view for explaining a manufacturing method of a semiconductor device according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment; FIG. 13 shows another configuration of the recess in cross section. FIG. 13 is a diagram showing another configuration of the recess in plan view. FIG. 13 is a diagram showing another configuration of the recess in plan view. FIG. 13 is a diagram for explaining a configuration of modified example 1. FIG. 13 is a diagram for explaining a configuration of modified example 2. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a second embodiment is applied. FIG. 11A and 11B are diagrams showing an example of resin burrs generated in a configuration of a comparative example.

The following describes the embodiments with reference to the drawings. In the following drawings, identical components are given the same reference numerals. Components with the same reference numerals have the same names and functions. Therefore, detailed descriptions of some of the components with the same reference numerals may be omitted.

The dimensions, materials, shapes, and relative positions of the components illustrated in the embodiments may be changed as appropriate depending on the configuration of the device, various conditions, etc. Also, the dimensions of the components in the figures may differ from the actual dimensions.

<First embodiment>
(Configuration of Semiconductor Device)
1 is a plan view of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 is, for example, a power semiconductor device that operates at a high voltage. The package structure of the semiconductor device 100 is, for example, a DIP (Dual In-line Package) structure.

In FIG. 1, the X direction, Y direction, and Z direction are mutually orthogonal. The X direction, Y direction, and Z direction shown in the following figures are also mutually orthogonal. In the following, the direction including the X direction and the opposite direction of the X direction (-X direction) is also referred to as the "X-axis direction". In the following, the direction including the Y direction and the opposite direction of the Y direction (-Y direction) is also referred to as the "Y-axis direction". In the following, the direction including the Z direction and the opposite direction of the Z direction (-Z direction) is also referred to as the "Z-axis direction".

In the following, the plane including the X-axis direction and the Y-axis direction is also referred to as the "XY plane." In the following, the plane including the X-axis direction and the Z-axis direction is also referred to as the "XZ plane." In the following, the plane including the Y-axis direction and the Z-axis direction is also referred to as the "YZ plane."

2 is a cross-sectional view of the semiconductor device 100 taken along the XZ plane of FIG. 1. In FIG. 2, in order to make it easier to understand the configuration of the semiconductor device 100, only the outline of the sealing material 11, which will be described later, is shown.

The semiconductor device 100 includes a lead frame 2 as shown in FIG. 3. FIG. 3 is a diagram showing the configuration of the lead frame 2 according to the first embodiment. As shown in FIG. 3, the lead frame 2 includes a die pad 2a, a hanging lead 2n, a lead 2c, and a control lead 2b. That is, as shown in FIG. 1 and FIG. 2, the semiconductor device 100 includes a die pad 2a, a hanging lead 2n, a lead 2c, and a control lead 2b. The lead 2c is, for example, a power lead serving as a lead terminal.

The shape of the die pad 2a is plate-like. In a plan view, the shape of the die pad 2a is rectangular. The die pad 2a has one surface, 2s, and the other surface, 2r. Surface 2s is the first surface. Surface 2r is the surface of the die pad 2a opposite surface 2s. Surface 2r is the second surface. Surfaces 2s and 2r are flat surfaces.

The die pad 2a is joined to the lead 2c by the suspension lead 2n.

The semiconductor device 100 further comprises a semiconductor element S3, a control semiconductor element S6, an insulating layer 9, a heat sink 10, and a sealing material 11.

The semiconductor element S3 is, for example, a power semiconductor element that operates at a high voltage. Note that the semiconductor element S3 is not limited to a power semiconductor element and may be, for example, a semiconductor element that operates at a low voltage.

A semiconductor element S3 is mounted on the surface 2s of the die pad 2a. Specifically, the semiconductor element S3 is bonded to the surface 2s of the die pad 2a by a bonding material 4. The bonding material 4 is, for example, solder. Furthermore, a control semiconductor element S6 is bonded to the surface of the control lead 2b by a bonding material 8. The bonding material 8 is, for example, solder.

Two wires W7 are connected to the control semiconductor element S6. Each wire W7 is a signal transmission wire. Hereinafter, the two wires W7 are also referred to as wire W7a and wire W7b, respectively.

The semiconductor element S3 and the control semiconductor element S6 are electrically connected by a wire W7a. The control semiconductor element S6 and the control lead 2b are electrically connected by a wire W7b. The semiconductor element S3 is electrically connected to the lead 2c by a wire W5.

The heat sink 10 has one surface, 10s, and the other surface, 10r. Surface 10s is the third surface. Surface 10r is the fourth surface. Surface 10r is the surface of the heat sink 10 opposite surface 10s.

An insulating layer 9 and a heat sink 10 are provided on the surface 2r of the die pad 2a in this order. The insulating layer 9 is between the die pad 2a and the heat sink 10. The insulating layer 9 is in contact with the surface 2r of the die pad 2a and the surface 10s of the heat sink 10.

The sealing material 11 is, for example, a molded resin. The sealing material 11 seals the semiconductor element S3, the control semiconductor element S6, the wires W5 and W7, the die pad 2a, the suspension lead 2n, the lead 2c, the insulating layer 9, and the heat sink 10.

Two screw holes H1 are formed in the sealing material 11. The two screw holes H1 will be described later. The sealing material 11 also has a surface 11s and a surface 11r. The surface 11r is the surface of the sealing material 11 opposite to the surface 11s.

The lead 2c protrudes in the X direction from one side of the sealing material 11. The lead 2c is bent so that the tip of the lead 2c that is outside the sealing material 11 is parallel to the Z direction.

The control lead 2b protrudes in the -X direction from the other side of the sealing material 11. In addition, the control lead 2b is bent so that the tip of the control lead 2b that is outside the sealing material 11 is parallel to the Z direction.

The surface 10r of the heat sink 10, which has the surface 10s in contact with the insulating layer 9, is exposed from the sealing material 11. Specifically, the surface 10r of the heat sink 10 is exposed from the surface 11r of the sealing material 11. Hereinafter, the surface 10r exposed from the sealing material 11 is also referred to as the "exposed surface." The shape of the exposed surface, surface 10r, is a polygonal rectangle.

Next, the configuration of each part will be specifically described. The material of the lead frame 2 is, for example, either copper (Cu) or aluminum (Al). Alternatively, the material of the lead frame 2 may be an alloy composed of copper (Cu) and aluminum (Al).

The surface of the lead frame 2 may be plated with nickel (Ni), silver (Ag) or gold (Au) to prevent oxidation. That is, a nickel plating film, a silver plating film or a gold plating film may be formed on the surface of the lead frame 2. The plating film may be formed partially on the lead frame 2.

Hereinafter, the area on which the plating film is formed is also referred to as the "area to be plated." The area to be plated is an area that is susceptible to the effects of surface oxidation. The area to be plated is, for example, the periphery of the area on the surface 2s of the die pad 2a where the semiconductor element S3 is bonded by the bonding material 4. The area to be plated is, for example, the periphery of the area on the surface of the control lead 2b where the control semiconductor element S6 is bonded by the bonding material 8.

The plating target area is, for example, the area on the surface of control lead 2b around the area to which wire W7 is connected. The plating target area is, for example, the area on the surface of lead 2c around the area to which wire W5 is connected.

The semiconductor element S3 is, for example, an element that functions as a switching element or a rectifying element. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), etc. The rectifying element is a diode element.

The material constituting the semiconductor element S3 is, for example, silicon (Si). The material constituting the semiconductor element S3 is not limited to silicon, and may be, for example, a wide band gap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), diamond (C), etc. A wide band gap semiconductor material is a material that has a band gap wider than that of silicon. The semiconductor element S3 made of a wide band gap semiconductor material is capable of operating using a large current, operating in a high temperature environment, etc. The material constituting the semiconductor element S3 in the semiconductor device 100 is preferably a wide band gap semiconductor material.

In addition, electronic components such as resistor elements and capacitor elements may be mounted on the surface of the control lead 2b instead of the control semiconductor element S6. The semiconductor device 100 on which such electronic components are mounted is known as an IPM (Intelligent Power Module).

The material constituting each of the wires W5 and W7 may be aluminum (Al), copper (Cu), gold (Au), silver (Ag), etc. The material constituting each of the wires W5 and W7 may be an alloy. The alloy is composed of two or more metals selected from the metals aluminum (Al), copper (Cu), gold (Au), and silver (Ag). The material constituting each of the wires W5 and W7 may be an alloy to which a metal element such as nickel (Ni) or iron (Fe) is added.

The shape of each of the wires W5 and W7 is, for example, a thin wire or a cylinder. The cross-sectional shape of each of the wires W5 and W7 is, for example, a circle. The diameter of the circle is, for example, 10 μm or more and 500 μm or less.

Wires W5 and W7 are bonded in a wire bonding process by existing methods such as ball bonding and wedge bonding. If the material constituting wire W5 is the same as the material constituting wire W7, wires W5 and W7 can be bonded in the same wire bonding process.

Of the wires W5 and W7, the wire W5 is the main wiring. Therefore, the wire W5 is thicker than the wire W7. The thickness of the wire W5 may be the same as that of the wire W7. The wire W5 may also be thinner than the wire W7.

For example, when the semiconductor device 100 is a discrete semiconductor device, the thickness of the wire W5 is the same as the thickness of the wire W7. When the semiconductor device 100 is equipped with a semiconductor element having a complex configuration such as an integrated circuit (IC) or a large scale insulator (LSI), the thickness of the wire W5 may be the same as the thickness of the wire W7.

The sealing material 11 may also be a composite material. The composite material is, for example, a material containing a filler or other filler and a resin as main components. The filler is used to adjust the thermal expansion coefficient or mechanical properties of the sealing material 11. The resin contained in the composite material is, for example, a thermosetting resin with high electrical resistivity. The resin is, for example, an epoxy resin. It is preferable that the sealing material 11 has high insulation properties, good moldability, and reliability.

The sealing material 11 is formed, for example, by a transfer molding method. The sealing material 11 seals a part of the lead frame 2 so that the tip of the lead 2c and the tip of the control lead 2b are exposed from the sealing material 11. The sealing material 11 also seals the semiconductor element S3, the control semiconductor element S6, the wires W5 and W7, the die pad 2a, the suspension lead 2n, the lead 2c, the insulating layer 9, and the heat sink 10. In the semiconductor device 100, the tip of the lead 2c and the tip of the control lead 2b exposed from the sealing material 11 are electrically connected to other devices, etc. (not shown).

Face 10r of heat sink 10 is exposed from sealing material 11. Surfaces of heat sink 10 other than face 10r are sealed by sealing material 11. In other words, surfaces of heat sink 10 other than face 10r are not exposed from sealing material 11.

The material constituting the insulating layer 9 is a material with high heat dissipation and insulation properties. The insulating layer 9 is, for example, a thermally conductive insulating resin sheet. The insulating layer 9 is also disposed on the surface 2r of the die pad 2a. The insulating layer 9 is, for example, a printed sheet, a transferred sheet, or a molded sheet. The shape of the insulating layer 9 in plan view is rectangular. The size of the insulating layer 9 in plan view is equal to or smaller than the size of the die pad 2a in plan view.

The thickness of the insulating layer 9 is set taking into consideration the heat dissipation properties of the insulating layer 9. The thickness of the insulating layer 9 is thinner than the thickness of the die pad 2a. For example, when the thickness of the die pad 2a is in the range of 200 μm to 500 μm, the thickness of the insulating layer 9 is preferably about 200 μm or less.

When high heat dissipation and high insulation are required for the insulating layer 9, the insulating layer 9 may be an insulating substrate consisting of a conductor layer and a ceramic plate. The material constituting the conductor layer is a metal such as copper (Cu), aluminum (Al), or nickel (Ni). The surface of the conductor layer may be plated with gold (Au), silver (Ag), or nickel (Ni). The material constituting the ceramic plate is, for example, a ceramic material or a glass ceramic material. The ceramic material is, for example, alumina, silicon nitride, or aluminum nitride.

In this embodiment, a heat sink 10 is in contact with the insulating layer 9 to enhance the heat dissipation properties of the insulating layer 9.

The material constituting the heat sink 10 is, for example, an alloy. The alloy is, for example, aluminum (Al) to which at least one of the metals magnesium (Mg) and manganese (Mn) is added.

The material constituting the heat sink 10 is not limited to an alloy, and may be a metal other than an alloy. The material constituting the heat sink 10 may be, for example, copper (Cu). The heat sink 10 may also be a plate made of aluminum (Al).

The material constituting the heat sink 10 may be a material other than a metal. The material constituting the heat sink 10 may be, for example, an inorganic or organic material with high thermal conductivity.

A recess V1 is formed on the surface 10r (i.e., the exposed surface) of the heat sink 10. Figures 4 and 5 are diagrams for explaining the configuration of the recess V1. Figure 4 is a plan view showing the configuration of the recess V1. Figure 5 is a cross-sectional view showing the configuration of the recess V1.

As shown in FIG. 4, a recess V1 is formed around the entire circumference of surface 10r, which is the exposed surface of the heat sink 10. In other words, recess V1 is formed around the periphery of surface 10r, which is the exposed surface of the heat sink 10. Recess V1 extends along the periphery of surface 10r (i.e., the exposed surface) of the heat sink 10. In other words, recess V1 is formed at the end of the heat sink 10. The shape of recess V1 in plan view is a closed loop. Furthermore, the shape of recess V1 in plan view is rectangular.

Hereinafter, the direction in which the recess V1 extends on the surface 10r of the heat sink 10 is also referred to as the "recess extension direction." The recess extension directions in FIG. 4 are the X-axis direction and the Y-axis direction.

The closed loop depression V1 includes depression V1a, depression V1b, depression V1c, and depression V1d. Each of depression V1a, depression V1b, depression V1c, and depression V1d is a part of depression V1. That is, each of depression V1a, depression V1b, depression V1c, and depression V1d is depression V1.

In Fig. 4, each of the recesses V1a and V1c extends in the Y-axis direction. Also, in Fig. 4, each of the recesses V1b and V1d extends in the X-axis direction.

As shown in Figure 5, the shape of the depression V1 in a cross-sectional view is a semicircle. Specifically, the shape of the cross section of the depression V1 along the depth direction of the depression V1 is a semicircle. In Figure 5, the depth direction of the depression V1 is the Z direction.

Hereinafter, the depth of the recess V1 is also referred to as "depth L1." Also, below, the width of the recess V1 on the surface 10r, which is the exposed surface, is also referred to as "width L2."

The heat sink 10 is connected to a heat dissipation member (not shown). The heat dissipation member is a member that has the function of dissipating heat. The heat dissipation member is, for example, a member that has heat dissipation fins. Surface 10r, which is the exposed surface of the heat sink 10, becomes the connection surface that is connected to the heat dissipation member. Hereinafter, the state in which surface 10r of the heat sink 10 is connected to the heat dissipation member is also referred to as the "heat dissipation member connection state."

In addition, surface 10r of heat sink 10 may be configured not to be connected to a heat dissipation member (hereinafter also referred to as a "heat dissipation member non-connected configuration").

Any method can be used to manufacture and process the heat sink 10. For example, the method for manufacturing the heat sink 10 is a forging process using a die. Also, for example, the method for manufacturing the heat sink 10 is a cutting process performed on the workpiece.

Any method can be used to form the recess V1. The recess V1 may be formed, for example, by a forging process using a die, during the manufacture of the heat sink 10. The recess V1 may also be formed on the surface 10r of the manufactured heat sink 10 by performing a cutting process on the surface 10r.

Hereinafter, the area of surface 10r, which is the exposed surface, other than the periphery of surface 10r is also referred to as the "exposed surface non-peripheral area." The exposed surface non-peripheral area is, for example, the area of surface 10r of heat sink 10 in FIG. 4 other than the periphery of surface 10r. The semiconductor element S3 shown in FIG. 2 is disposed above the exposed surface non-peripheral area of heat sink 10. In other words, the exposed surface non-peripheral area of heat sink 10 exists below semiconductor element S3.

The semiconductor device 100 of embodiment 1 is configured as described above.

(Production method)
Next, an example of a method for manufacturing the semiconductor device 100 will be described with reference to Figures 3, 6, 7, 8, 9, and 10. Figures 3, 7, 8, 9, and 10 are cross-sectional views for explaining the method for manufacturing the semiconductor device 100 according to the first embodiment.

Hereinafter, the manufacturing method of the semiconductor device 100 is also referred to as "manufacturing method Pr." Manufacturing method Pr uses a mold 51, which will be described later. Figure 6 is a flowchart of manufacturing method Pr according to embodiment 1. Figure 6 shows only the main steps included in the multiple steps of manufacturing method Pr.

In the manufacturing method Pr, an initial process is first performed (step S110). In the initial process, the lead frame 2 of FIG. 3 is prepared. The lead frame 2 includes a die pad 2a, a suspension lead 2n, a lead 2c, and a control lead 2b. Each of the lead 2c and the control lead 2b is bent.

Specifically, in the initial process, a plate-shaped member is processed by a known method to form the lead frame 2. The plate-shaped member is made of, for example, copper (Cu) or aluminum (Al).

The lead frame 2 is provided with a plurality of leads 2c and a plurality of control leads 2b. The plurality of leads 2c are connected to each other by tie bars (not shown). The plurality of control leads 2b are also connected to each other by tie bars (not shown).

Next, an element mounting process is performed (step S120). The element mounting process is a process of mounting a control semiconductor element S6 on the surface of a control lead 2b included in the lead frame 2. Specifically, in the element mounting process, as shown in Figure 7, the control semiconductor element S6 is bonded to the surface of the control lead 2b by a bonding material 8. As described above, the bonding material 8 is, for example, solder.

The bonding material 8 is not limited to solder. The bonding material 8 may be a conductive adhesive or a sintered body. The sintered body is made of, for example, metal particles of any one of silver (Ag), copper (Cu), gold (Au) and nickel (Ni). The bonding material 8 may also be a mixed material. The mixed material is a member in which two or more metal particles of silver (Ag), copper (Cu), gold (Au) and nickel (Ni) are mixed.

The bonding material 8 may further be composed of metal particles in which a core member is coated with a coating material. The core member is a metal particle selected from the group consisting of silver (Ag), copper (Cu), gold (Au) and nickel (Ni). The coating material is a metal particle different from the core member. The coating material is a metal particle selected from the group consisting of silver (Ag), copper (Cu), gold (Au) and nickel (Ni).

The bonding material 8 may also be a hybrid sintered body containing metal particles with a low stress effect and a resin. The hybrid sintered body can be obtained, for example, by incorporating an epoxy resin into the sintered body.

The material constituting the bonding material 8 is selected, for example, taking into consideration the material of the back surface of the control semiconductor element S6. The back surface of the control semiconductor element S6 is the surface that is bonded to the front surface of the control lead 2b by the bonding material 8. If plating is present on the back surface of the control semiconductor element S6, the material of the back surface is, for example, the type of plating.

In addition, the material constituting the bonding material 8 is selected, for example, taking into consideration the surface condition of the control lead 2b. The material constituting the bonding material 8 is selected, for example, based on whether plating is present on the surface of the control lead 2b.

The element mounting process is also a process of mounting a semiconductor element S3 on the surface 2s of the die pad 2a included in the lead frame 2. Specifically, in the element mounting process, as shown in Fig. 8, the semiconductor element S3 is bonded to the surface 2s of the die pad 2a by a bonding material 4. As described above, the bonding material 4 is, for example, solder.

The bonding material 4 is not limited to solder. The bonding material 8 may be a sintered body. The sintered body is made of, for example, metal particles of any of silver (Ag), copper (Cu), gold (Au) and nickel (Ni). The thermal conductivity of the sintered body is k times the thermal conductivity of the solder. "k" is a real number, for example, in the range of 3 to 5.

The bonding material 4 may also be a mixture. The mixture is a mixture of two or more metal particles selected from the group consisting of silver (Ag), copper (Cu), gold (Au) and nickel (Ni).

The bonding material 4 may further be composed of metal particles in which the core member is coated with a coating material. The core member is any one of metal particles of silver (Ag), copper (Cu), gold (Au) and nickel (Ni). The coating material is a metal particle different from the core member. The coating material is any one of metal particles of silver (Ag), copper (Cu), gold (Au) and nickel (Ni).

The bonding material 4 may also be a hybrid sintered body containing metal particles with a low stress effect and a resin. The hybrid sintered body can be obtained, for example, by incorporating an epoxy resin into the sintered body.

The material constituting the bonding material 4 is selected, for example, taking into consideration the material of the back surface of the semiconductor element S3. The back surface of the semiconductor element S3 is the surface that is bonded to the surface 2s of the die pad 2a by the bonding material 4. If plating is present on the back surface of the semiconductor element S3, the material of the back surface is, for example, the type of plating.

In addition, the material constituting the bonding material 4 is selected, for example, taking into consideration the surface condition of the lead 2c. The material constituting the bonding material 4 is selected, for example, based on whether or not plating is present on the surface of the lead 2c.

By the above-mentioned element mounting process, a semiconductor element S3 and a control semiconductor element S6 are mounted on a lead frame 2 including a die pad 2a and a control lead 2b.

Next, the wire bonding process is performed. In the wire bonding process, as shown in Figure 9, the semiconductor element S3 and the lead 2c are electrically connected by a wire W5. The semiconductor element S3 and the control semiconductor element S6 are also electrically connected by a wire W7a. The control semiconductor element S6 and the control lead 2b are also electrically connected by a wire W7b.

Specifically, in the wire bonding process, one end of wire W5 is bonded to, for example, an electrode (not shown) on semiconductor element S3. The electrode in question is an emitter electrode, a source electrode, an anode electrode, etc. The other end of wire W5 is bonded to lead 2c. One end of wire W7a is bonded to a gate pad (not shown) on semiconductor element S3. The other end of wire W7a is bonded to the control semiconductor element S6. One end of wire W7b is bonded to the control semiconductor element S6. The other end of wire W7b is bonded to control lead 2b. The method of bonding wires W5, W7a, W7b is, for example, ball bonding, wedge bonding, etc.

If wire W5 and wire W7 are the same type of wire, wire W5 and wire W7 can be joined in the same step in the wire bonding process.

It is preferable to use the optimal wire W5 and optimal wire W7 taking into consideration the size of the gate pad in the semiconductor element S3 and the current capacity to be passed through the semiconductor element S3. In addition, the order of bonding the wire W5 and the wire W7 is not particularly restricted.

Hereinafter, the state of the lead frame 2 after the wire bonding process is performed is also referred to as the "element connection state." The lead frame 2 in the element connection state is the lead frame 2 shown in Figure 9. The lead frame 2 in the element connection state includes a die pad 2a on which a semiconductor element S3 is mounted, and a control lead 2b on which a control semiconductor element S6 is mounted. That is, the lead frame 2 in the element connection state is mounted with the semiconductor element S3 and the control semiconductor element S6.

The lead frame 2 in the element-connected state is a lead frame 2 to which wires W5, W7a, and W7b are joined. In the lead frame 2 in the element-connected state, for example, wires W5 and W7a are joined to the semiconductor element S3, and wires W7a and W7b are joined to the control semiconductor element S6.

Here, we will explain the mold 51 used to seal the components with a sealant. Figure 10 shows the mold 51. The mold 51 is a mold for sealing the components by a transfer molding method. The mold 51 is a transfer molding mold. The mold 51 includes a lower mold 51a and an upper mold 51b.

There are two states of the mold 51: a sealable state and an unsealable state. The sealable state is a state in which the components can be sealed with a sealant. Figure 10 shows the mold 51 in a sealable state as an example. Figure 10 also shows the configuration in the YZ plane of the lead frame 2 in the element connection state of Figure 9.

In the mold 51 in a sealable state, the upper mold 51b faces the lower mold 51a. The mold 51 in a sealable state has a cavity Cv1 defined by the upper mold 51b and the lower mold 51a. The mold 51 in a sealable state also has a resin injection gate 55.

Hereinafter, the fluid sealing material is also referred to as "sealing material 11n." The sealing material 11 is hardened sealing material 11n. The resin injection gate 55 is a hole for injecting the sealing material 11n into the cavity Cv1.

The non-sealable state is a state in which the components cannot be sealed with the sealing material. In the non-sealable state of the mold 51, the upper mold 51b and the lower mold 51a are separated.

The lower mold 51a also has a bottom surface Sb1. The mold 51 in a sealable state has a bottom surface Sb1 facing the cavity Cv1.

Hereinafter, the state of the die pad 2a, the insulating layer 9, and the heat sink 10 in a state in which the components are sealed with the sealing material is also referred to as the "sealing-ready state." In addition, below, the direction in which the sealing material flows in a state in which the components are sealed with the sealing material is also referred to as the "direction Dr1."

Next, a placement process is performed (step S130). In summary, the placement process is a process of placing the die pad 2a, the insulating layer 9, and the heat sink 10 in the cavity Cv1 of the mold 51 in a sealable state so that the die pad 2a, the insulating layer 9, and the heat sink 10 are in a sealing-compatible state.

The sealing-compatible state is a state in which the insulating layer 9 is present between the die pad 2a and the heat sink 10. The sealing-compatible state is also a state in which the insulating layer 9 is in contact with the surface 2r of the die pad 2a and the surface 10s of the heat sink 10. The sealing-compatible state is also a state in which the surface 10r of the heat sink 10 is in contact with the bottom surface Sb1 of the mold 51.

As shown in Fig. 4, a recess V1 is formed on the surface 10r of the heat sink 10 used in the placement process. As described above, the direction in which the recess V1 extends on the surface 10r of the heat sink 10 is the recess extension direction. The recess extension directions in Fig. 4 are the X-axis direction and the Y-axis direction.

Specifically, in the placement process, first, a lower die 51a of a die 51 in an unsealable state is prepared. Next, the heat sink 10 is placed so that the surface 10r of the heat sink 10 contacts the bottom surface Sb1 of the lower die 51a. In addition, the heat sink 10 is placed so that the extension direction of the recess V1b, which is the recess V1 formed on the surface 10r of the heat sink 10, intersects with the direction Dr1.

Specifically, the heat sink 10 is positioned so that the extension direction of the recess V1b, which is recess V1, is perpendicular to the direction Dr1. The expression "the extension direction of the recess is perpendicular to the direction Dr1" also includes the meaning that "the extension direction of the recess is approximately perpendicular to the direction Dr1."

Next, an insulating layer 9 is placed on the surface 10s of the heat sink 10. The insulating layer 9 is, for example, a printed sheet, a transferred sheet, or a molded sheet. The position where the insulating layer 9 is placed is a position below the die pad 2a, assuming that the die pad 2a is placed.

The heat sink 10 and the insulating layer 9 are not limited to being individually arranged on the lower mold 51a. For example, the heat sink 10 and the insulating layer 9 may be arranged on the lower mold 51a in a state where the heat sink 10 and the insulating layer 9 are integrated.

Next, the lead frame 2 in the element-connected state of Fig. 9 is placed on the lower mold 51a so that the surface 2r of the die pad 2a included in the lead frame 2 in the element-connected state contacts the insulating layer 9. As described above, the lead frame 2 in the element-connected state includes the die pad 2a on which the semiconductor element S3 is mounted, and the control lead 2b on which the control semiconductor element S6 is mounted. In other words, the lead frame 2 in the element-connected state is mounted with the semiconductor element S3 and the control semiconductor element S6.

Next, the upper mold 51b is positioned so that the state of the mold 51 transitions from a non-sealable state to a sealable state. Specifically, the upper mold 51b is positioned so that it faces the lower mold 51a. As a result, the die pad 2a and control leads 2b included in the lead frame 2 are accommodated in the cavity Cv1 of the mold 51 in the sealable state. As a result, the die pad 2a, insulating layer 9 and heat sink 10 are in the above-mentioned sealing-compatible state. The placement process is performed as described above.

After the placement process, the sealing process is performed (step S140). That is, the sealing process is performed after the placement process. The sealing process is a process of injecting the sealing material 11n into the cavity Cv1 of the mold 51 in a sealable state.

Here, surface 10r of heat sink 10 is in contact with bottom surface Sb1 of mold 51. Therefore, in the sealing process, sealant 11n is injected into cavity Cv1 of mold 51 in a sealable state so that surface 10r of heat sink 10, which has surface 10s in contact with insulating layer 9, is exposed from sealant 11n.

Specifically, in the sealing process, the sealing material 11n flows from the resin injection gate 55 toward the cavity Cv1, and the sealing material 11n is injected into the resin injection gate 55 so that the sealing material 11n flows in a specific direction Dr1. That is, in the sealing process, the sealing material 11n is injected into the cavity Cv1 of the mold 51 so that the sealing material 11n flows in the direction Dr1. The direction Dr1 is the Y direction. As a result, the sealing material 11n flows in the direction Dr1 or approximately in the direction Dr1.

As described above, in the arrangement process, the heat sink 10 is arranged so that the extension direction of the recess V1b, which is the recess V1 formed on the surface 10r of the heat sink 10, intersects with the direction Dr1. Therefore, when the sealing process is performed, the heat sink 10 is arranged so that the extension direction of the recess V1b, which is the recess V1 formed on the surface 10r of the heat sink 10, intersects with the direction Dr1. "The recess extension direction intersects with the direction Dr1" specifically means that "the recess extension direction is perpendicular to the direction Dr1."

When the sealing material 11n reaches the die pad 2a, part of the flow force of the sealing material 11n flowing in the direction Dr1 is also applied in the direction Dr2. Therefore, the sealing material 11n biases the die pad 2a toward the bottom surface Sb1 of the lower mold 51a.

By biasing the die pad 2a toward the bottom surface Sb1 of the lower mold 51a, the insulating layer 9 and the heat sink 10 are biased toward the bottom surface Sb1. Therefore, the surface 10r of the heat sink 10 is in close contact with the bottom surface Sb1 of the lower mold 51a. Therefore, the sealing material 11n is less likely to flow between the surface 10r of the heat sink 10 and the bottom surface Sb1 of the lower mold 51a.

However, there is a small gap (hereinafter also referred to as "gap Gp") between the surface 10r of the heat sink 10 and the bottom surface Sb1 of the lower mold 51a. The gap Gp occurs, for example, due to the dimensional tolerance of the heat sink 10.

When the sealing material 11n is filled into the cavity Cv1, the semiconductor element S3 and the control semiconductor element S6 mounted on the lead frame 2 in the element-connected state are sealed by the sealing material 11n, and the insulating layer 9 and the heat sink 10 are also sealed by the sealing material 11n.

After the sealing material 11n is filled into the cavity Cv1, the sealing material 11n hardens. When the sealing material 11n hardens, it becomes the sealing material 11. For example, the temperature of the sealing material 11n is reduced, causing the sealing material 11n to harden. As a result, the lead frame 2 and the components mounted on the lead frame 2 are sealed with the sealing material 11, which is the hardened sealing material 11n. The components mounted on the lead frame 2 are, for example, the semiconductor element S3 and the control semiconductor element S6.

In addition, the hardened sealant 11 is in contact with the inner wall of the mold 51 in a sealable state. The inner wall of the mold 51 in a sealable state is the part of the mold 51 that faces the cavity Cv1. The sealing process is performed as described above.

Hereinafter, the state of the lead frame 2 when it is sealed with the sealing material 11 will be referred to as the "sealed state." Here, the configuration of the lead frame 2 in the sealed state will be described with reference to FIG.

Figure 11 is a diagram showing the configuration of a semiconductor device 100 according to embodiment 1. In Figure 11, in order to make the configuration of the semiconductor device 100 easier to understand, only the outline of the sealing material 11 is shown for the sealing material 11. The semiconductor device 100 in Figure 11 shows the configuration of the semiconductor device 100 in Figure 2 in the YZ plane.

The configuration of the lead frame 2 in the sealed state is the same as that of the semiconductor device 100 in Figure 11, except that an unnecessary part (not shown) is further added. The unnecessary part is, for example, a runner.

The sealed lead frame 2 is obtained by carrying out the above-mentioned sealing process. In the sealed lead frame 2, the semiconductor element S3, the control semiconductor element S6, the wires W5 and W7, the die pad 2a, the leads 2c, the insulating layer 9, the heat sink 10, etc. are sealed with the sealing material 11.

Next, a removal process is performed (step S150). In the removal process, the upper mold 51b is removed so that the state of the mold 51 transitions from a sealable state to a non-sealable state.

Next, the sealed lead frame 2 is removed from the lower mold 51a. The configuration of the removed sealed lead frame 2 is the same as that of the semiconductor device 100 in FIG. 11, with, for example, unnecessary parts (not shown) added. The unnecessary parts are, for example, runners. The runners are, for example, members generated from the sealing material that was present in the resin injection gate 55. The removal process is performed as described above.

Next, a finishing process is performed. In the finishing process, the sealed lead frame 2 is subjected to a finishing process. In the finishing process, a die press (not shown) is used to cut the tie bars (not shown) that connect the multiple leads 2c to each other. This forms each lead 2c as an independent lead 2c.

In the finishing process, a die press is used to cut the tie bars (not shown) that connect the multiple control leads 2b together. This forms each control lead 2b as an independent control lead 2b. In the finishing process, unnecessary parts such as runners are also removed.

In this way, the semiconductor device 100 is completed. The completed semiconductor device 100 is the semiconductor device 100 in FIG. 11. Gate marks M1 are present on the surface of the sealing material 11 of the completed semiconductor device 100. The gate marks M1 are caused by the removal of the above-mentioned runner. Therefore, the surface of the sealing material 11 on which the gate marks M1 are present is rougher than the surface of the sealing material 11 that was in contact with the inner wall of the mold 51 in a sealing state immediately before the above-mentioned removal process was performed.

Therefore, the position of the resin injection gate 55 used in the encapsulation process can be ascertained from the gate mark M1 present on the surface of the encapsulant 11 of the completed semiconductor device 100. In other words, the position of the resin injection gate 55 used in the encapsulation process can be ascertained from the appearance of the completed semiconductor device 100.

In the above-mentioned manufacturing method Pr, the process of manufacturing the semiconductor device 100 using the bent lead 2c and the bent control lead 2b has been described, but is not limited to this. In the manufacturing method Pr, after the semiconductor device 100 is manufactured using the unbent lead 2c and the unbent control lead 2b, each of the lead 2c and the control lead 2b may be bent.

The semiconductor device 100 may be a finished product in which the leads 2c and the control leads 2b included in the semiconductor device 100 are not bent. The package structure of the semiconductor device 100 is not limited to a DIP structure, and may be a SOP (Small Outline Package) structure.

In the semiconductor device 100 described above, the recess V1 formed on the surface 10r (i.e., the exposed surface) of the heat sink 10 can suppress the occurrence of resin burrs in the semiconductor device 100, as will be explained below.

Here, we will explain a comparative example to which the present embodiment is compared. Hereinafter, the semiconductor device according to the comparative example will also be referred to as "semiconductor device N1." Semiconductor device N1 differs from semiconductor device 100 in that it includes a heat sink 10n instead of heat sink 10. Other configurations of semiconductor device N1 are similar to those of semiconductor device 100.

Heat sink 10n differs from heat sink 10 in that no recess V1 is formed on surface 10r. The rest of the configuration of heat sink 10n is the same as that of heat sink 10.

Hereinafter, the manufacturing method of the semiconductor device N1 according to the comparative example will also be referred to as the "manufacturing method Prn." The manufacturing method Prn differs from the manufacturing method Pr described above only in that a heat sink 10n is used instead of the heat sink 10 in which the recess V1 is formed.

In the sealing process of the manufacturing method Prn according to the comparative example, the sealing material 11n is injected into the cavity Cv1. In this case, the sealing material 11n may flow into the gap Gp that exists between the surface 10r of the heat sink 10n and the bottom surface Sb1 of the lower mold 51a, causing resin burrs to occur. Hereinafter, the resin burrs are also referred to as "resin burrs B1." Figure 18 is a diagram showing an example of a resin burr B1 that occurs in the configuration of the comparative example.

As shown in Figure 4, a recess V1 is formed on surface 10r (i.e., the exposed surface) of heat sink 10 of semiconductor device 100 according to this embodiment. As described above, in manufacturing method Pr according to this embodiment, when the sealing process is performed, heat sink 10 is positioned so that the recess extension direction of recess V1b, which is recess V1 formed on surface 10r of heat sink 10, intersects with direction Dr1. "The recess extension direction intersects with direction Dr1" specifically means that "the recess extension direction is perpendicular to direction Dr1."

Now, assume that in the sealing process of manufacturing method Pr, sealing material 11n flowing in direction Dr1 shown in Figure 10 penetrates into gap Gp between surface 10r of heat sink 10 and bottom surface Sb1 of lower mold 51a, and enters recess V1b extending in the X-axis direction in Figure 4. Recess V1b is recess V1. The X-axis direction is the recess extension direction. The depth direction of recess V1b, which is recess V1, is the Z direction. Hereinafter, the direction in which sealing material 11n flows is also referred to as the "flow direction."

In this case, most of the sealing material 11n that has entered the recess V1b (representing the recess V1) flows along the X-axis direction, which is the recess extension direction of the recess V1b. Also, a portion of the sealing material 11n that has entered the recess V1b (representing the recess V1) flows in the Z direction, which is the depth direction of the recess V1b.

That is, due to the presence of the recess V1b, which is the recess V1, the flow direction of the sealing material 11n changes from the Y direction, which is the direction Dr1, to the X-axis direction, which is the recess extension direction, and to the Z direction, which is the depth direction. Therefore, the recess V1b, which is the recess V1, has the function of blocking the sealing material 11n that has entered the gap Gp.

Therefore, it is possible to prevent the formation of resin burrs B1 in the non-peripheral region of the exposed surface of the surface 10r of the heat sink 10, which is located below the semiconductor element S3. As a result, the heat dissipation properties of the semiconductor device 100 can be ensured.

Next, the configuration of the recess V1 will be described with reference to Figure 5. The larger the width L2 of the recess V1, the greater the change in the flow direction of the sealing material 11n that has entered the recess V1. Also, the deeper the depth L1 of the recess V1, the greater the change in the flow direction of the sealing material 11n that has entered the recess V1. The change in the flow direction is from the Y direction, which is direction Dr1, to the X-axis direction, which is the recess extension direction, or the Z direction, which is the depth direction of the recess V1, etc. Therefore, the greater the change in the flow direction of the sealing material 11n that has entered the recess V1b, which is the recess V1, the greater the effect of suppressing the formation of resin burrs B1.

On the other hand, if the depth L1 of the recess V1 is more than half the thickness of the heat sink 10, the rigidity of the end of the heat sink 10 where the recess V1 exists will be weakened.

Furthermore, the larger the width L2 of the recess V1, the closer the recess V1 is to the non-peripheral region of the exposed surface. The non-peripheral region of the exposed surface is the region that exists below the semiconductor element S3. In the above-mentioned heat dissipation member connection state in which the surface 10r of the heat sink 10 is connected to the heat dissipation member, the larger the width L2 of the recess V1, the smaller the area of contact between the surface 10r of the heat sink 10 (i.e., the exposed surface) and the heat dissipation member. Therefore, in the heat dissipation member connection state, the larger the width L2 of the recess V1, the lower the heat dissipation performance of the semiconductor device 100.

Therefore, it is preferable to set the depth L1 and width L2 of the recess V1 in consideration of the rigidity of the heat sink 10 and the heat dissipation path of the semiconductor element S3. As described above, the width L2 is the width of the recess V1 on the surface 10r, which is the exposed surface.

Incidentally, in the above-mentioned heat dissipation member unconnected configuration in which the surface 10r of the heat sink 10 is not connected to the heat dissipation member, the larger the width L2 of the recess V1, the larger the area of the heat sink 10 exposed to the air. Therefore, in the heat dissipation member unconnected configuration, the larger the width L2 of the recess V1, the more improved the heat dissipation performance of the semiconductor device 100.

The relationship between the depth L1 and the width L2 of the recess V1 is set, for example, according to the heat dissipation specifications of the semiconductor device 100. The relationship between the depth L1 and the width L2 that is set is either "L1 = L2", "L1 < L2", or "L1 > L2".

In the following, the configuration in which the relationship between depth L1 and width L2 in recess V1 is "L1 = L2" is also referred to as "configuration Cm1." In addition, in the following, the configuration in which the relationship between depth L1 and width L2 in recess V1 is "L1 < L2" is also referred to as "configuration Cm2." In addition, in the following, the configuration in which the relationship between depth L1 and width L2 in recess V1 is "L1 > L2" is also referred to as "configuration Cm3."

In configuration Cm1, where the relationship between depth L1 and width L2 is "L1 = L2", the length corresponding to the depth L1 of recess V1 is the same as the width L2 of the recess V1. In configuration Cm2, where the relationship between depth L1 and width L2 is "L1 < L2", the length corresponding to the depth L1 of recess V1 is shorter than the width L2 of the recess V1. In configuration Cm3, where the relationship between depth L1 and width L2 is "L1 > L2", the length corresponding to the depth L1 of recess V1 is longer than the width L2 of the recess V1.

As shown in Fig. 5, the cross-sectional shape of the recess V1 along the depth direction of the recess V1 is a semicircle (hereinafter, also referred to as "structure Cs1"). However, this is not limited to this. Fig. 12 is a diagram showing another configuration of the recess V1 in a cross-sectional view.

As shown in Fig. 12(a), the cross-sectional shape of the depression V1 along the depth direction of the depression V1 may be a triangular configuration (hereinafter also referred to as "configuration Cs2"). As shown in Fig. 12(b), the cross-sectional shape of the depression V1 along the depth direction of the depression V1 may be a quadrangular configuration (hereinafter also referred to as "configuration Cs3"). As shown in Fig. 12(c), the cross-sectional shape of the depression V1 along the depth direction of the depression V1 may be a rhombus configuration (hereinafter also referred to as "configuration Cs4").

In any of configurations Cs2, Cs3, and Cs4, the relationship between depth L1 and width L2 in recess V1 is set appropriately depending on the heat dissipation specifications of the semiconductor device 100.

In addition, any of the configurations Cs1, Cs2, Cs3, and Cs4 can suppress the occurrence of resin burrs B1. Therefore, any of the configurations Cs1, Cs2, Cs3, and Cs4 may be adopted in consideration of the productivity when forming the recess V1 in the heat sink 10.

In the present embodiment, as shown in Fig. 4, one recess V1 is formed around the entire circumference of the surface 10r, which is the exposed surface of the heat sink 10, but this is not limited to the above. As shown in Fig. 13, two or more recesses V1 may be formed around the entire circumference of the surface 10r, which is the exposed surface of the heat sink 10.

Figure 13 is a diagram showing another configuration of the recess V1 in a plan view. Figure 13 is a diagram showing, as an example, a state in which two recesses V1 are formed around the entire circumference of the surface 10r of the heat sink 10. In Figure 13, a plurality of recesses V1 are formed on the surface 10r (i.e., the exposed surface) of the heat sink 10, extending along the periphery of the surface 10r.

Hereinafter, a configuration in which multiple recesses V1 are formed on the surface 10r (i.e., the exposed surface) of the heat sink 10 is also referred to as a "multiple recess configuration." The configuration in Figure 13 is a multiple recess configuration.

The more recesses V1 formed on the periphery of the exposed surface 10r, the greater the effect of suppressing the occurrence of resin burrs B1.

On the other hand, the more recesses V1 formed on the periphery of the exposed surface, surface 10r, the closer the recesses V1 are to the non-peripheral region of the exposed surface. The non-peripheral region of the exposed surface is the region that exists below the semiconductor element S3. In the above-mentioned heat dissipation member connection state, the greater the number of recesses V1, the smaller the area of contact between surface 10r of heat sink 10 and the heat dissipation member. Therefore, in the heat dissipation member connection state, the greater the number of recesses V1, the lower the heat dissipation performance of semiconductor device 100.

Therefore, the number of recesses V1 to be formed on the periphery of the exposed surface, surface 10r, can be set taking into consideration the effect of suppressing the occurrence of resin burrs B1 and the heat dissipation path of the semiconductor element S3.

Incidentally, in the above-mentioned heat dissipation member unconnected configuration in which the surface 10r of the heat sink 10 is not connected to the heat dissipation member, the greater the number of recesses V1, the greater the area of the heat sink 10 exposed to air. Therefore, in the heat dissipation member unconnected configuration, the greater the number of recesses V1, the more improved the heat dissipation performance of the semiconductor device 100.

Note that the recess V1 does not have to be formed around the entire circumference of the surface 10r, which is the exposed surface of the heat sink 10. For example, the recess V1 may be formed so that the recess V1 is perpendicular to the direction Dr1 in which the sealing material 11n, which causes the generation of the resin burr B1, flows. Figure 14 is a diagram showing another configuration of the recess V1 in a plan view.

For example, the depression V1 formed on the surface 10r, which is the exposed surface, may be a U-shaped depression V1 as shown in Fig. 14(a). The depression V1 in Fig. 14(a) includes a depression V1a, a depression V1b, and a depression V1c.

In addition, the recess V1 formed on the surface 10r, which is the exposed surface, may be the recess V1 shown in Fig. 14(b). In the following, a configuration in which the recess V1 is formed only on a portion of the periphery of the surface 10r, which is the exposed surface of the heat sink 10, is also referred to as a "minimal recess configuration." The configuration of the recess V1 in Fig. 14(b) is a minimum recess configuration.

In the minimum recess configuration, recess V1 is configured, for example, as shown in FIG. 14(b). Here, the shape of surface 10r, which is the exposed surface, is a rectangle as a polygon. Recess V1 in FIG. 14(b) extends along only one of the four sides that constitute the rectangle, which is the shape of surface 10r.

In the arrangement step of the manufacturing method Pr with the minimum recess configuration, the heat sink 10 is arranged so that the recess extension direction of the recess V1 formed on the surface 10r of the heat sink 10 intersects with the direction Dr1, as shown in FIG. 14(b). Therefore, in the manufacturing method Pr with the minimum recess configuration, the recess V1 is formed only in the area of the periphery of the surface 10r (i.e., the exposed surface) of the heat sink 10 arranged when the sealing step of step S140 is performed, which intersects with the direction Dr1. "The area of the periphery of the surface 10r of the heat sink 10 that intersects with the direction Dr1" specifically means "the area of the periphery of the surface 10r of the heat sink 10 that is perpendicular to the direction Dr1". The expression "the periphery of the surface 10r that is perpendicular to the direction Dr1" also includes the meaning of "the periphery of the surface 10r that is almost perpendicular to the direction Dr1".

(summary)
As described above, according to this embodiment, the semiconductor element S3 is mounted on the surface 2s of the die pad 2a. The sealing material 11 seals the semiconductor element S3, the die pad 2a, the insulating layer 9, and the heat sink 10. The insulating layer 9 is present between the die pad 2a and the heat sink 10. The insulating layer 9 is in contact with the surface 2r of the die pad 2a and the surface 10s of the heat sink 10. The surface 10r of the heat sink 10, which has the surface 10s in contact with the insulating layer 9, is exposed from the sealing material 11.

That is, the heat sink 10 is in contact with the insulating layer 9 that is in contact with the die pad 2a on which the semiconductor element S3 is mounted. The heat sink 10 is also exposed from the sealing material 11. Therefore, due to the action of the heat sink 10, the semiconductor device of the present disclosure has higher heat dissipation properties than the semiconductor device of related configuration B in which the insulating layer is exposed from the sealing material. Therefore, it is possible to provide a semiconductor device with high heat dissipation properties.

Furthermore, according to this embodiment, when the sealing process of manufacturing method Pr is performed, the heat sink 10 is positioned such that the recess extension direction of recess V1b, which is recess V1 formed on surface 10r of the heat sink 10, intersects with direction Dr1. Specifically, "the recess extension direction intersects with direction Dr1" means that "the recess extension direction is perpendicular to direction Dr1."

When the sealing material 11n penetrates the gap Gp and enters the recess V1b, most of the sealing material 11n that has entered the recess V1b (representing the recess V1) flows along the X-axis direction, which is the recess extension direction of the recess V1b. Also, a portion of the sealing material 11n that has entered the recess V1b (representing the recess V1) flows in the Z direction, which is the depth direction of the recess V1b.

That is, due to the presence of recess V1b, which is recess V1, the flow direction of the sealing material 11n during the sealing process changes from the Y direction, which is direction Dr1, to the X-axis direction, which is the recess extension direction, and to the Z direction, which is the depth direction.

Therefore, the recess V1b, which is the recess V1, blocks the sealing material 11n that has entered the gap Gp. In other words, the recess V1b, which is the recess V1, controls the flow direction of the sealing material 11n. Therefore, it is possible to suppress the occurrence of resin burrs on the surface 10r of the heat sink 10. As a result, it is possible to obtain the effect of ensuring the heat dissipation properties of the semiconductor device 100.

<Modification 1>
In the configuration of this modification, protrusions are formed on the exposed surface of the heat sink 10. The configuration of this modification is applied to the first embodiment. Fig. 15 is a diagram for explaining the configuration of the first modification. The configuration of Fig. 15 is a configuration in which the configuration of the first modification is applied to the configuration of Fig. 5.

In the configuration of Modification 1, compared to the configuration of Embodiment 1, a protrusion X1 is further formed on surface 10r, which is the exposed surface of the heat sink 10. Hereinafter, the configuration in which protrusion X1 is formed on surface 10r, which is the exposed surface of the heat sink 10, is also referred to as a "protrusion formation configuration." The configuration of FIG. 15 is a protrusion formation configuration.

In the configuration of this modified example, a recess V1 and a protrusion X1 are formed on the periphery of face 10r (i.e., the exposed face) of heat sink 10. In addition, a protrusion X1 is formed in the area of face 10r, which is the exposed face, outside the position where recess V1 is present. Protrusion X1 is formed at the end of face 10r. Protrusion X1 extends along the periphery of face 10r, which is the exposed face.

The protrusion X1 protrudes in the -Z direction. Hereinafter, the direction in which the protrusion X1 protrudes is also referred to as the "protrusion direction". The protrusion X1 extends in the recess extension direction of the recess V1. Hereinafter, the direction in which the protrusion X1 extends on the surface 10r of the heat sink 10 is also referred to as the "protrusion extension direction". In FIG. 15, the protrusion extension direction of the protrusion X1 is the X-axis direction.

As described above, the configuration of this modified example is applied to embodiment 1. For example, in a configuration in which the configuration of this modified example is applied to the configuration of FIG. 4, the shape of the protrusion X1 in plan view is a closed loop. Also, for example, in a configuration in which the configuration of this modified example is applied to the configuration of FIG. 14(b), the protrusion X1 extends along only one of the four sides that constitute the rectangular shape of the exposed surface, surface 10r.

Next, the configuration of the protrusion X1 will be described with reference to FIG. 15. The configuration of the recess V1 has been described in embodiment 1, and therefore the description will not be repeated. The shape of the protrusion X1 in cross-sectional view is semicircular. In the following, the height of the protrusion X1 will also be referred to as "height L3". In addition, in the following, the width of the protrusion X1 on the surface 10r, which is the exposed surface, will also be referred to as "width L4".

Here, it is assumed that in the sealing process of manufacturing method Pr, sealing material 11n flowing in direction Dr1 shown in FIG. 10 comes into contact with protrusion X1 formed on surface 10r of heat sink 10.

In this case, most of the sealing material 11n flows along the X-axis direction, which is the extension direction of the protrusion X1. Also, part of the sealing material 11n flows along the Z-axis direction, which includes the -Z direction, which is the protrusion X1 protruding direction. That is, due to the presence of the protrusion X1, the flow direction of the sealing material 11n changes from the Y direction, which is direction Dr1, to the X-axis direction, which is the protrusion extension direction, and to the Z-axis direction, which includes the protrusion X1 protruding direction. Therefore, the protrusion X1 has the function of blocking the sealing material 11n that has entered the gap Gp. This makes it possible to suppress the formation of resin burrs B1.

Furthermore, the greater the height L3 of the protrusion X1, the greater the change in the flow direction of the sealing material 11n. The change in the flow direction is from the Y direction, which is direction Dr1, to the X-axis direction, which is the protrusion extension direction, to the -Z direction, which is the protrusion X1 protruding direction, etc. Therefore, the greater the change in the flow direction of the sealing material 11n, the greater the effect of suppressing the formation of resin burrs B1.

On the other hand, the higher the height L3 of the protrusion X1, the more difficult it is to form the protrusion X1 on the exposed surface of the heat sink 10. Also, the higher the height L3 of the protrusion X1, the more difficult it is to control the height of the protrusion X1. Therefore, it is preferable to set the height L3 of the protrusion X1 taking into consideration the productivity of the heat sink 10, the effect of suppressing the occurrence of resin burrs, etc.

The relationship between the height L3 and width L4 of the protrusion X1 is set, for example, according to the heat dissipation specifications of the semiconductor device 100. The relationship between the height L3 and width L4 that is set is either "L3 = L4", "L3 < L4", or "L3 > L4".

In addition, the shape of the protrusion X1 in cross-sectional view is semicircular, but is not limited to this. The shape of the protrusion X1 in cross-sectional view may be triangular, rectangular, diamond, etc. Regardless of whether the shape of the protrusion X1 is semicircular, triangular, rectangular, or diamond, the relationship between the height L3 and width L4 of the protrusion X1 is appropriately set according to, for example, the heat dissipation specifications of the semiconductor device 100.

The material constituting the protrusion X1 is the same as the material constituting the heat sink 10. The material constituting the protrusion X1 is, for example, a metal with high heat dissipation properties such as copper (Cu) or aluminum (Al). This allows the heat generated by the semiconductor element S3 to be dissipated via the die pad 2a, the insulating layer 9, and the heat sink 10, as well as the heat to be dissipated via the protrusion X1. This provides the effect of dispersing heat that tends to be concentrated in the semiconductor element S3.

Furthermore, the material constituting the protrusion X1 is not limited to the above-mentioned materials. The material constituting the protrusion X1 may be, for example, a ceramic material, a glass ceramic material, etc. The ceramic material is alumina, silicon nitride, aluminum nitride, etc. A configuration in which the material constituting the protrusion X1 is a ceramic material provides higher adhesion between the protrusion X1 and the sealing material 11 than a configuration in which the material constituting the protrusion X1 is a metal. This makes it possible to suppress peeling of the sealing material 11 by the anchor effect.

As mentioned above, the heat sink 10 is connected to a heat dissipation member (not shown). The heat dissipation member is, for example, a member having heat dissipation fins. The exposed surface of the heat sink 10, surface 10r, becomes the connection surface that is connected to the heat dissipation member.

The heat dissipation member is fixed to the heat sink 10 using two screw holes H1 in the sealing material 11 shown in Figure 1. Specifically, a fixing screw (not shown) is fixed into each of the two screw holes H1 in the sealing material 11, and the surface 10r (i.e., the exposed surface) of the heat sink 10 is fixed to the heat dissipation member. Grease is provided as an intermediate member between the surface 10r of the heat sink 10 and the heat dissipation member.

In order to efficiently dissipate heat generated by the semiconductor element S3 of the semiconductor device 100, the surface 10r of the heat sink 10 and the heat dissipation member are in close contact with each other via grease. Here, the surface 11r of the sealing material 11 may be configured to be a curved surface (hereinafter also referred to as a "close contact configuration"). The shape of the curved surface is a downward convex shape. A downward convex shape is a shape in which the surface 11r protrudes below the surface 11r of the sealing material 11.

In the tight contact configuration, when the two screw holes H1 of the sealing material 11 are used for screw tightening, the surface 10r of the heat sink 10 and the heat dissipation member can be tightly contacted with the grease without any gaps. In addition, in the tight contact configuration, when the screws are tightened, the curved surface of the surface 11r of the sealing material 11 is corrected to a flat surface. This applies stress to the insulating layer 9 and the heat sink 10, which may cause cracks.

In the configuration of this modified example, as shown in FIG. 15, the protrusion X1 is formed on the end of the surface 10r of the heat sink 10. Therefore, in a close contact configuration, when the screw is tightened, the protrusion X1 first comes into contact with the heat dissipation member. When the protrusion X1 comes into contact with the heat dissipation member, the protrusion X1 may be crushed. When the protrusion X1 is crushed, the stress applied to the insulating layer 9 is alleviated. As the stress applied to the insulating layer 9 is alleviated, the surface 10r of the heat sink 10 comes into close contact with the heat dissipation member. Therefore, the semiconductor device 100 of this modified example can ensure high insulation and high heat dissipation.

(summary)
As described above, according to this modification, in the sealing step of the manufacturing method Pr, the protrusion X1 blocks the sealing material 11n that has entered the gap Gp. That is, the protrusion X1 controls the flow direction of the sealing material 11n. This makes it possible to suppress the formation of resin burrs B1.

Furthermore, according to this modified example, when the screw is tightened in the aforementioned close contact configuration, the protrusion X1 may come into contact with the heat dissipation member and be crushed. If the protrusion X1 is crushed, the stress applied to the insulating layer 9 is alleviated. As a result, the semiconductor device 100 of this modified example can ensure high insulation and high heat dissipation.

<Modification 2>
In the configuration of this modification, the dimple V1 is configured to have a plurality of local dimples. Each local dimple is a part of the dimple V1. Hereinafter, the configuration in which the dimple V1 is configured to have a plurality of local dimples is also referred to as a "local dimple configuration." The local dimple configuration of this modification is applied to the first embodiment or the first modification.

Figure 16 is a diagram for explaining the configuration of variant example 2. Figure 16 is a diagram showing another configuration of recess V1 in a plan view.

The configuration in Fig. 16(a) is a configuration in which the local recess configuration of variant example 2 is applied to the configuration in Fig. 4. The configuration of recess V1 formed on surface 10r (i.e., the exposed surface) of heat sink 10 may be the configuration of recess V1 shown in Fig. 16(a). Hereinafter, the configuration of recess V1 shown in Fig. 16(a) is also referred to as "local recess configuration A".

In the local dent configuration A of FIG. 16(a), the shape of the dent V1 in a planar view is a dotted line. Specifically, the dent V1 is made up of multiple local dents V1s. Each local dent V1s is a part of the dent V1. The multiple local dents V1s are scattered along the periphery of the surface 10r (i.e., the exposed surface) of the heat sink 10. Moreover, the multiple local dents V1s are formed around the entire circumference of the surface 10r.

16(a) is subjected to the sealing process of manufacturing method Pr, the sealing material 11n is directed in the X-axis direction, which is the extension direction of the recess V1b, and in the Z direction, which is the depth direction of the recess V1b. Therefore, the recess V1b, which is the recess V1 of local recess configuration A, has the function of blocking the sealing material 11n that has entered the gap Gp.

In addition, in the local recess configuration A, the shape of the recess V1 in a planar view is a dotted line. Therefore, the sealing material 11n is guided more preferentially in the X-axis direction.

The configuration of the recess V1 formed on the surface 10r (i.e., the exposed surface) of the heat sink 10 may be the configuration of the recess V1 shown in FIG. 16(b). Hereinafter, the configuration of the recess V1 shown in FIG. 16(b) is also referred to as "local recess configuration B." The local recess configuration B in FIG. 16(b) is a configuration in which the shape of the local recess V1s in FIG. 16(a) is changed.

In the local dent configuration B of FIG. 16(b), the shape of the dent V1 in a planar view is a dotted line. Specifically, the dent V1 is made up of multiple local dents V1s. The multiple local dents V1s are scattered along the periphery of the surface 10r (i.e., the exposed surface) of the heat sink 10. In addition, the multiple local dents V1s are formed around the entire circumference of the surface 10r.

Moreover, each local depression V1s is formed by dots. That is, each local depression V1s is a dot depression. The shape of each local depression V1s in plan view is a circle.

16(b) is subjected to the sealing process of manufacturing method Pr, the sealing material 11n is directed in the X-axis direction, which is the extension direction of the recess V1b, and in the Z direction, which is the depth direction of the recess V1b. Therefore, the recess V1b, which is the recess V1 of local recess configuration B, has the function of blocking the sealing material 11n that has entered the gap Gp.

Each local depression V1s is formed with dots. This allows the depression to be easily formed. It also allows the size of the depression (e.g., diameter, depth) to be easily changed, the size of the depression to be easily adjusted, etc.

In addition, when the depression V1 of the local depression configuration B is formed by pressing or the like, the protrusion X1 can be formed at the same time. This makes it possible to improve the productivity of the heat sink 10 while ensuring high insulation and high heat dissipation properties of the semiconductor device 100.

<Embodiment 2>
Here, a power conversion device will be described that applies the semiconductor device 100 according to the above-mentioned first embodiment, modification 1, or modification 2. Although the present disclosure is not limited to a specific power conversion device, a case in which the semiconductor device 100 according to the first embodiment, modification 1, or modification 2 is applied to a three-phase inverter will be described below as the second embodiment.

Figure 17 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to embodiment 2 is applied. The power conversion system shown in Figure 17 includes a power source Pw1, a power conversion device 200, and a load 300. The power source Pw1 is a DC power source. The power source Pw1 supplies DC power to the power conversion device 200. The power source Pw1 is composed of various elements. The power source Pw1 can be composed of, for example, a DC system, a solar cell, a storage battery, etc.

The power supply Pw1 may also be configured with a rectifier circuit or an AC/DC converter connected to an AC system. The power supply Pw1 may also be configured with a DC/DC converter that converts DC power output from a DC system into a predetermined power.

The power conversion device 200 is a three-phase inverter connected between the power source Pw1 and the load 300. The power conversion device 200 converts DC power supplied from the power source Pw1 into AC power and supplies the AC power to the load 300. As shown in FIG. 17, the power conversion device 200 includes a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts and outputs the power input to the main conversion circuit 201. Specifically, the main conversion circuit 201 converts DC power into AC power and outputs the AC power.

The control circuit 203 outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific use, but is a motor mounted on various electrical devices. The load 300 is used, for example, as a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

The details of the power conversion device 200 will be described below. The main conversion circuit 201 includes a switching element (not shown) and a free wheel diode (not shown). The switching element switches to convert the DC power supplied from the power source Pw1 into AC power, and the AC power is supplied to the load 300. There are various specific circuit configurations for the main conversion circuit 201. The main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit. The main conversion circuit 201 is composed of, for example, six switching elements and six free wheel diodes. The six switching elements are connected in inverse parallel to the six free wheel diodes.

At least one of the switching elements and free wheel diodes of the main conversion circuit 201 is configured by a semiconductor module 202. The semiconductor module 202 corresponds to the semiconductor device 100 according to the above-mentioned embodiment 1, modification 1 or modification 2. That is, the main conversion circuit 201 has a semiconductor module 202 corresponding to the semiconductor device 100 according to the embodiment 1, modification 1 or modification 2.

The main conversion circuit 201 includes three upper and lower arms configured using six switching elements. Each of the three upper and lower arms is configured with two switching elements connected in series. The three upper and lower arms correspond to the U phase, V phase, and W phase of the full bridge circuit, respectively. The output terminals of the three upper and lower arms correspond to the three output terminals of the main conversion circuit 201. The three output terminals of the main conversion circuit 201 are connected to the load 300.

The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor module 202. The main conversion circuit 201 may also include a drive circuit separate from the semiconductor module 202.

The drive circuit generates a drive signal that drives the switching elements of the main conversion circuit 201, and supplies the drive signal to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit outputs a drive signal that switches the switching element to an on state and a drive signal that switches the switching element to an off state to the control electrodes of each switching element in accordance with a control signal from the control circuit 203 described below.

When the switching element is maintained in the on state, the drive signal is a voltage signal equal to or greater than the threshold voltage of the switching element (i.e., an on signal). When the switching element is maintained in the off state, the drive signal is a voltage signal less than the threshold voltage of the switching element (i.e., an off signal).

The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the on-time, which is the time that each switching element of the main conversion circuit 201 should be in the on-state, based on the power to be supplied to the load 300. The control circuit 203 can control the main conversion circuit 201, for example, by PWM control. The PWM control is a control that modulates the on-time of the switching elements according to the voltage to be output.

The control circuit 203 then outputs a control signal as a control command to the drive circuit provided in the main conversion circuit 201. This control signal is a signal for outputting an ON signal to a switching element that should be in an ON state at each point in time. This control signal is also a signal for outputting an OFF signal to a switching element that should be in an OFF state at each point in time. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

In the power conversion device according to the present embodiment, at least one of the switching elements and free wheel diodes of the main conversion circuit 201 is configured by a semiconductor module 202. The semiconductor module 202 corresponds to the semiconductor device 100 according to the above-mentioned embodiment 1, variant 1 or variant 2. Therefore, by ensuring the heat dissipation properties of the semiconductor device 100, the reliability of the power conversion device can be improved.

In this embodiment, an example of applying the semiconductor device 100 according to embodiment 1, variant 1 or variant 2 to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and the semiconductor device 100 according to embodiment 1, variant 1 or variant 2 can be applied to various power conversion devices.

In addition, in this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. When supplying power to a single-phase load, the semiconductor device 100 according to embodiment 1, modification 1, or modification 2 may be applied to a single-phase inverter. When supplying power to a DC load or the like, the semiconductor device 100 according to embodiment 1, modification 1, or modification 2 may also be applied to a DC/DC converter or an AC/DC converter.

Furthermore, the configuration of the power conversion device to which the semiconductor device 100 according to embodiment 1, modification 1, or modification 2 is applied is not limited to the configuration in which the load 300 described above is an electric motor. The load 300 may be, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a power supply device for a non-contact power supply system. Furthermore, the power conversion device to which the semiconductor device 100 according to embodiment 1, modification 1, or modification 2 is applied may be used as a power conditioner for a solar power generation system, a power storage system, or the like.

(Other Modifications)
It is possible to freely combine the embodiments and modifications, and to modify or omit the embodiments and modifications as appropriate.

For example, the semiconductor device 100 is not limited to a power semiconductor device. The semiconductor device 100 may be, for example, a semiconductor device that operates at a low voltage.

In addition, for example, the shape of the depression V1 in a cross-sectional view is not limited to a semicircle, a triangle, a rectangle, a rhombus, etc. The shape of the depression V1 in a cross-sectional view may be, for example, a trapezoid. In addition, the shape of the depression V1 in a cross-sectional view may be, for example, a polygon other than a trapezoid, a triangle, a rectangle, and a rhombus.

In addition, for example, the shape of the surface 10r, which is the exposed surface of the heat sink 10, is not limited to a rectangle. The shape of the surface 10r may be, for example, a polygon such as a trapezoid or a hexagon.

For example, the multiple recess configuration described above may be applied to all or part of the minimum recess configuration and the protrusion formation configuration. In the following, a configuration in which the multiple recess configuration is applied to the minimum recess configuration is also referred to as "deformed configuration A." In the following, a configuration in which the multiple recess configuration is applied to the protrusion formation configuration is also referred to as "deformed configuration B."

In modified configuration A, for example, a plurality of depressions V1 having the configuration of FIG. 14(b) are formed only on a portion of the periphery of face 10r. In modified configuration A, each of the plurality of depressions V1 extends along only one of the four sides constituting the rectangular shape of face 10r.

In modified configuration B, for example, the configuration in Fig. 13 is further provided with protrusion X1 in Fig. 15. In this configuration, for example, multiple recesses V1 and protrusion X1 are formed on surface 10r, which is the exposed surface.

The protrusion formation configuration may also be a configuration applied to the modified configuration A (hereinafter, also referred to as the "modified configuration Ax"). In the modified configuration Ax, a plurality of depressions V1 are formed only on a portion of the periphery of the surface 10r, and a protrusion X1 is further formed on the periphery of the surface 10r.

Furthermore, configuration Cm1 in which the relationship between depth L1 and width L2 is "L1 = L2" may be applied to all or part of the multiple recess configuration, minimal recess configuration, protrusion formation configuration, deformed configuration A, deformed configuration B, and deformed configuration Ax. Hereinafter, a configuration in which configuration Cm1 is applied to all or part of the multiple recess configuration, minimal recess configuration, protrusion formation configuration, deformed configuration A, deformed configuration B, and deformed configuration Ax is also referred to as "deformed configuration Cm1a."

Furthermore, configuration Cm2 in which the relationship between depth L1 and width L2 is "L1<L2" may be applied to all or part of the multiple recess configuration, minimal recess configuration, protrusion formation configuration, deformed configuration A, deformed configuration B, and deformed configuration Ax. Hereinafter, a configuration in which configuration Cm2 is applied to all or part of the multiple recess configuration, minimal recess configuration, protrusion formation configuration, deformed configuration A, deformed configuration B, and deformed configuration Ax is also referred to as "deformed configuration Cm2a."

Furthermore, configuration Cm3 in which the relationship between depth L1 and width L2 is "L1>L2" may be applied to all or part of the multiple recess configuration, minimal recess configuration, protrusion formation configuration, deformed configuration A, deformed configuration B, and deformed configuration Ax. Hereinafter, a configuration in which configuration Cm3 is applied to all or part of the multiple recess configuration, minimal recess configuration, protrusion formation configuration, deformed configuration A, deformed configuration B, and deformed configuration Ax is also referred to as "deformed configuration Cm3a."

Furthermore, the configuration Cs1 in which the cross-sectional shape of the depression V1 is semicircular may be applied to all or part of the multiple depression configuration, the minimum depression configuration, the protrusion formation configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a. Hereinafter, a configuration in which the configuration Cs1 is applied to all or part of the multiple depression configuration, the minimum depression configuration, the protrusion formation configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a is also referred to as "deformed configuration Cs1a."

Furthermore, the configuration Cs2 in which the cross-sectional shape of the depression V1 is triangular may be applied to all or part of the multiple depression configuration, the minimum depression configuration, the protrusion formation configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the configuration Cm1, the configuration Cm2, the configuration Cm3, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a. In the following, a configuration in which the configuration Cs2 is applied to all or part of the multiple depression configuration, the minimum depression configuration, the protrusion formation configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the configuration Cm1, the configuration Cm2, the configuration Cm3, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a is also referred to as "deformed configuration Cs2a".

Furthermore, the configuration Cs3 in which the cross-sectional shape of the dent V1 is a rectangle may be applied to all or part of the multiple dent configuration, the minimum dent configuration, the protrusion-forming configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the configuration Cm1, the configuration Cm2, the configuration Cm3, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a. Hereinafter, a configuration in which the configuration Cs3 is applied to all or part of the multiple dent configuration, the minimum dent configuration, the protrusion-forming configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the configuration Cm1, the configuration Cm2, the configuration Cm3, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a is also referred to as "deformed configuration Cs3a".

Furthermore, the configuration Cs4 in which the cross-sectional shape of the depression V1 is a rhombus may be applied to all or part of the multiple depression configuration, the minimum depression configuration, the protrusion formation configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the configuration Cm1, the configuration Cm2, the configuration Cm3, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a. In the following, a configuration in which the configuration Cs4 is applied to all or part of the multiple depression configuration, the minimum depression configuration, the protrusion formation configuration, the deformed configuration A, the deformed configuration B, the deformed configuration Ax, the configuration Cm1, the configuration Cm2, the configuration Cm3, the deformed configuration Cm1a, the deformed configuration Cm2a, and the deformed configuration Cm3a is also referred to as "deformed configuration Cs4a".

For example, the semiconductor device 100 corresponding to the semiconductor module 202 included in the power conversion system of the second embodiment may have all or some of the above-mentioned multiple configurations. The multiple configurations are the multiple recess configuration, the minimal recess configuration, the protrusion formation configuration, the modified configuration A, the modified configuration B, the modified configuration Ax, the modified configuration Cm1a, the modified configuration Cm2a, the modified configuration Cm3a, the modified configuration Cs1a, the modified configuration Cs2a, the modified configuration Cs3a, and the modified configuration Cs4a.

Although the present disclosure has been described in detail, the above description is illustrative in all respects and is not limiting. It is understood that countless variations not illustrated can be envisioned.

The present disclosure is effectively used in semiconductor devices having a die pad on which a semiconductor element or the like is mounted.

2a die pad, 9 insulating layer, 10, 10n heat sink, 11, 11n sealing material, 51 mold, 100, N1 semiconductor device, Cv1 cavity, S3 semiconductor element, V1, V1a, V1b, V1c, V1d depression, V1s local depression, X1 protrusion.

Claims (10)

A semiconductor device comprising:
a die pad having a first surface which is one surface and a second surface which is the other surface;
a semiconductor element mounted on the first surface of the die pad;
a heat sink having a third surface which is one surface and a fourth surface which is the other surface;
an insulating layer between the die pad and the heat sink;
a sealing material that seals the semiconductor element, the die pad, the insulating layer, and the heat sink;
the second surface of the die pad is a surface of the die pad opposite to the first surface,
the insulating layer is in contact with the second surface of the die pad and the third surface of the heat sink;
the fourth surface of the heat sink is a surface of the heat sink opposite to the third surface,
the fourth surface of the heat sink having the third surface in contact with the insulating layer is an exposed surface exposed from the sealing material;
A recess and a protrusion are formed on the periphery of the exposed surface of the heat sink,
the recess extends along a periphery of the exposed surface of the heat sink;
The exposed surface has a polygonal shape,
The depression extends along only one of a plurality of sides constituting the polygon.
Semiconductor device. The exposed surface of the heat sink has a plurality of recesses formed therein, the recesses extending along a periphery of the exposed surface.
The semiconductor device according to claim 1 . The length corresponding to the depth of the depression is the same as the width of the depression on the exposed surface.
The semiconductor device according to claim 1 . A length corresponding to the depth of the depression is shorter than a width of the depression on the exposed surface.
The semiconductor device according to claim 1 . A length corresponding to the depth of the depression is longer than a width of the depression on the exposed surface.
The semiconductor device according to claim 1 . The cross-sectional shape of the depression along the depth direction of the depression is a semicircle, a triangle, a rectangle, or a rhombus.
The semiconductor device according to claim 1 . The depression comprises a plurality of local depressions;
Each of the local depressions is a portion of the depression;
the plurality of localized depressions being interspersed along a periphery of the exposed surface of the heat sink;
The semiconductor device according to claim 1 . The shape of each of the local depressions in a plan view is a circle;
The semiconductor device according to claim 7 . a main conversion circuit having the semiconductor device according to claim 1 , which converts input power and outputs the converted power;
a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit;
Power conversion equipment. A method for manufacturing a semiconductor device using a molding die having a cavity and a bottom surface facing the cavity, comprising the steps of:
The semiconductor device includes:
a die pad having a first surface which is one surface and a second surface which is the other surface;
A semiconductor element;
a heat sink having a third surface which is one surface and a fourth surface which is the other surface;
an insulating layer;
the second surface of the die pad is a surface of the die pad opposite to the first surface,
the fourth surface of the heat sink is a surface of the heat sink opposite to the third surface,
The manufacturing method includes:
(a) mounting the semiconductor element on the first surface of the die pad;
(b) placing the die pad, the insulating layer, and the heat sink in the cavity of the molding tool such that the die pad, the insulating layer, and the heat sink are in a sealing-compatible state;
(c) injecting an encapsulant into the cavity of the molding die;
the sealable state is a state in which the insulating layer is present between the die pad and the heat sink;
the sealing-ready state is a state in which the insulating layer is in contact with the second surface of the die pad and the third surface of the heat sink;
the sealable state is a state in which the fourth surface of the heat sink is in contact with the bottom surface of the molding die;
The step (c) is carried out after the step (b),
In the step (c), a sealant is injected into the cavity of the molding die such that the fourth surface of the heat sink having the third surface in contact with the insulating layer is exposed from the sealant ;
a recess is formed in the fourth exposed surface of the heat sink;
In the step (c), the sealing material is injected into the cavity of the molding die so that the sealing material flows in a specific direction;
the recess extends along a periphery of the exposed surface of the heat sink;
When the step (c) is performed, the heat sink is disposed so that the direction in which the recess extends intersects with the specific direction;
The recess is formed only in a region of the periphery of the exposed surface of the heat sink that is placed when the step (c) is performed, the region intersecting with the specific direction.
A method for manufacturing a semiconductor device.

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