JP7576274B2 - Insulated gate semiconductor device and method for manufacturing the same - Google Patents

Description

The present invention relates to an insulated gate semiconductor device and a method for manufacturing an insulated gate semiconductor device, and in particular to an insulated gate semiconductor device using silicon carbide (SiC) and a method for manufacturing an insulated gate semiconductor device.

In a MOS field effect transistor (FET) using SiC, a high density interface state is formed when a gate insulating film is formed on a semiconductor layer. Therefore, there is a problem that the mobility of the channel is reduced, and the electrical characteristics such as the on-resistance of the MOSFET are deteriorated. It has been proposed to reduce the interface state density (Dit) at the gate insulating film interface and increase the mobility by performing a heat treatment in a gas containing nitrogen (N) after the gate insulating film is formed and forming a high concentration nitrided region at the interface between the silicon oxide (SiO ₂ ) film and the SiC. However, there is a problem that the operational reliability of the semiconductor device cannot be ensured depending on the driving conditions due to negative bias temperature instability (NBTI), which causes fluctuations in the gate threshold voltage, which is the on-off voltage of the device, in response to negative bias application stress. In Non-Patent Document 1, it is pointed out that the cause of the NBTI problem is the possibility of hole trap generation by nitrogen atoms that have entered the SiO ₂ film, which is the gate insulating film, due to the nitrided region formation process. In Non-Patent Document 2, the effect of heat treatment with various gases including CO ₂ on the electrical characteristics of the SiC/SiO ₂ interface is reported.

In Patent Document 1, a technique for defining the N concentration near the interface between the SiO ₂ film and the SiC film is disclosed in order to improve NBTI. Specifically, the interface is defined as the position where the oxygen (O) concentration is 90% of the O concentration in the SiO ₂ film, and the N concentration in the region of ±5 nm from the interface is defined as higher than 5×10 ¹³ cm ⁻² and less than 1.6×10 ¹⁴ cm ⁻² . However, in the technique of Patent Document 1, the amount of N atoms contributing to the passivation of the interface is reduced, so that the nitriding effect is insufficient and the channel mobility is reduced. In addition, the fluctuation of the gate threshold voltage due to positive bias temperature instability (PBTI) becomes a problem.

SiC-MOSFETs have been put to practical use as power semiconductor elements such as inverters. In inverters, MOSFETs function as switching elements and are driven by repeatedly turning on and off. For example, when positive and negative gate voltages are repeatedly applied to the gate electrode of an n-type MOSFET, the gate threshold voltage fluctuates due to an increase in the density of electrons trapped in the gate oxide film, resulting in a problem of reduced reliability.

JP 2011-82454 A

J. Rozen et al., “Increase in oxide hole trap density associated with nitrogen incorporation at the SiO2/SiC interface,” J. Appl. Phys., Vol. 103, 2008, p. 124513. W. Wang et al., "Interface Properties of 4H-SiC/SiO2 with MOS Capacitors and FETs annealed in O2, N2O, NO and CO2," Materials Science Forum, Vol. 457-460, 2004, pp. 1309-1312.

In view of the above problems, the present invention aims to provide an insulated gate semiconductor device and a method for manufacturing an insulated gate semiconductor device that can reduce fluctuations in the gate threshold voltage and suppress deterioration of the reliability of the semiconductor device.

In order to achieve the above object, one aspect of the present invention is a method for manufacturing an insulated gate semiconductor device, comprising: (a) forming a gate insulating film made of a silicon oxide film on the upper surface of a channel formation region made of silicon carbide; (b) heat-treating the gate insulating film with a gas containing nitrogen atoms to nitride the interface between the gate insulating film and the silicon carbide to form an intermediate nitride layer at the interface between the channel formation region and the gate insulating film; (c) heat-treating the gate insulating film with a gas containing carbon dioxide to remove some of the nitrogen atoms in the gate insulating film and form a nitride termination layer at the interface; (d) heat-treating the gate insulating film with an inert gas after forming the nitride termination layer; and (e) forming a gate electrode on the gate insulating film to control the surface potential of the channel formation region.

Another aspect of the present invention is an insulated gate semiconductor device comprising: (a) a gate insulating film made of a silicon oxide film provided on an upper surface of a channel formation region made of silicon carbide; (b) a nitride termination layer made of silicon nitride provided at an interface between the channel formation region and the gate insulating film; and (c) a gate electrode provided on the gate insulating film for controlling a surface potential of the channel formation region, wherein when electrons are injected into the gate insulating film by passing a current through the channel formation region and the gate insulating film at an injection charge amount of 5× ¹⁰ cm ⁻² or more and 1× ¹⁰ cm ⁻² or less, the average density of electrons captured in the gate insulating film is 2× ¹⁰ cm ⁻³ or less.

The present invention provides an insulated gate semiconductor device and a method for manufacturing an insulated gate semiconductor device that can reduce fluctuations in the gate threshold voltage and suppress deterioration of the reliability of the semiconductor device.

1 is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to an embodiment of the present invention. 5A to 5C are schematic cross-sectional views for explaining an example of a process for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. 3 is a schematic cross-sectional view for explaining an example of a step subsequent to that shown in FIG. 2 in a method for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. FIG. 4 is a schematic cross-sectional view for explaining an example of a step subsequent to that of FIG. 3 in a method for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. FIG. 5 is a schematic cross-sectional view for explaining an example of a step subsequent to that of FIG. 4 in a method for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. FIG. 1 is a schematic cross-sectional view showing an example of a MOS capacitor according to Comparative Example 1 or 2. FIG. FIG. 1 is a band diagram for explaining an outline of a current test of a gate insulating film of a MOS capacitor. 1A and 1B are diagrams for explaining a method of evaluating a gate insulating film of a MOS capacitor by a current test. 1 is a diagram showing an example of the relationship between the amount of injected electrons and the density of trapped electrons obtained in a current test of a gate insulating film according to an embodiment. 1 is a table showing an example of evaluation results of a current test of a gate insulating film according to an embodiment. 5A to 5C are schematic cross-sectional views for explaining an example of a process of a method for manufacturing an insulated gate semiconductor device according to an embodiment. 12 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 11 in the method for manufacturing an insulated gate semiconductor device according to the embodiment. FIG. 13 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 12 in the method for manufacturing an insulated gate semiconductor device according to the embodiment. FIG. 14 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 13 in the method for manufacturing an insulated gate semiconductor device according to the embodiment. FIG. 15 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 14 in the method for manufacturing an insulated gate semiconductor device according to the embodiment. FIG. 16 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 15 in the method for manufacturing an insulated gate semiconductor device according to the embodiment. FIG. FIG. 11 is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to Comparative Example 3 or 4. 1 is a diagram showing an example of the relationship between the shift amount of the gate threshold voltage and the gate voltage application time of the insulated gate semiconductor device according to the embodiment. FIG. 1 is a table showing an example of a result of evaluation of the amount of shift in gate threshold voltage of an insulated gate semiconductor device according to an embodiment.

Below, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are given the same or similar reference numerals, and duplicate explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. Furthermore, there may be parts with different dimensional relationships and ratios between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

In this specification, the source region of a MOS transistor is the "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), one main region can be selected as the cathode region. The drain region of a MOS transistor is the "other main region (second main region)" of the semiconductor device that can be selected as the collector region in an IGBT and as the anode region in a thyristor. In this specification, when the term "main region" is used simply, it means either the first main region or the second main region that is appropriate from the technical common sense of a person skilled in the art.

In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and of course if it is rotated 180 degrees and observed, up and down are read inverted. In the following description, the case where the first conductivity type is p-type and the opposite second conductivity type is n-type will be described as an example. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, + and - attached to n and p mean that the semiconductor region has a relatively high or low impurity density, respectively, compared to a semiconductor region without + and -. However, even if the same n and n are attached to semiconductor regions, it does not mean that the impurity density of each semiconductor region is strictly the same. In addition, in the notation of Miller indices in this specification, "-" means a bar attached to the index immediately after it, and adding "-" before the index represents a negative index.

The insulated gate semiconductor device according to the embodiment of the present invention is a lateral MOSFET using a silicon oxide (SiO ₂ ) film as a gate insulating film. As shown in FIG. 1, a channel formation region (base region) 3 of a first conductivity type (p type) is provided, and an inversion channel is formed on the surface of the channel formation region 3. A high impurity density second conductivity type (n ⁺ type) main region, for example, a source region (first main region) 4a and a drain region (second main region) 4b, are selectively provided on the upper part of the channel formation region 3. An insulated gate electrode structure (5, 7) is provided on the upper surface of the channel formation region 3 across the source region 4a and the drain region 4b via a nitride termination layer 6 terminated with nitrogen (N). The insulated gate electrode structure (5, 7) is composed of a gate insulating film 5 made of a SiO ₂ film and a gate electrode (control electrode) 7 on the gate insulating film 5. The gate electrode 7 electrostatically controls the surface potential of the channel formation region 3 via the gate insulating film 5 to form an inversion channel on the surface of the channel formation region 3.

The nitride termination layer 6 is a nitrogen termination layer provided by nitriding the interface between the gate insulating film 5 and the channel formation region 3 and then heat-treating it with carbon dioxide (CO ₂ ) gas. As the silicon oxide film (SiO ₂ film) which is the gate insulating film 5 of the MOSFET, a thermal oxide film such as an oxygen (O ₂ ) dry oxidation or wet oxidation, or a deposited oxide film such as a sputter, thermal chemical vapor deposition (CVD), or plasma CVD can be used. As the material of the gate electrode 7, a metal film such as aluminum (Al), a polysilicon layer (doped polysilicon layer) to which impurities such as phosphorus (P) and boron (B) are added at a high concentration, or the like can be used.

As shown in FIG. 1, the channel formation region 3 is epitaxially grown on a substrate 1 made of an n-type SiC semiconductor. A source electrode 8a and a drain electrode 8b are provided so as to be in physical contact with the source region 4a and the drain region 4b, respectively. The source electrode 8a and the drain electrode 8b are ohmically connected to the source region 4a and the drain region 4b, respectively. For the source electrode 8a and the drain electrode 8b, for example, a single layer film made of Al or a metal film laminated in the order of nickel silicide (NiSi _x ), titanium nitride (TiN), and Al can be used. Although not shown in the figure, a p ⁺ type contact region electrically connecting the source electrode 8a and the channel formation region 3 is separated from the source region 4a and disposed in the channel formation region 3.

There are crystal polymorphs in SiC crystals, the main ones being cubic 3C, and hexagonal 4H and 6H. The band gap at room temperature has been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. Insulated gate type semiconductor devices according to embodiments of the present invention will be described using 4H-SiC. In the insulated gate type semiconductor devices according to embodiments, a semiconductor substrate (SiC substrate) made of SiC is used as the substrate 1. When a SiC substrate is used, the channel formation region 3 is exemplified by a structure made of an epitaxial layer (SiC layer) made of SiC. The surface orientation of the SiC substrate will be described using the (0001) surface (Si surface), but the (11-20) surface (a surface), (1-100) surface (m surface), and (000-1) surface (C surface) may also be used.

As shown in FIG. 1, in the insulated gate semiconductor device according to the embodiment, a voltage is applied to the gate electrode 7 to form an inversion layer that becomes a channel at the interface between the gate insulating film 5 and the channel formation region 3. At this time, a voltage is applied between the source electrode 8a and the drain electrode 8b, so that carriers (electrons) are injected from the source region 4a into the channel. The injected carriers travel through the channel and flow into the drain region 4b.

Usually, when the _SiO2 film used for the gate insulating film 5 is formed by a thermal oxidation method or the like, C atoms remain at the interface between the _SiO2 film and the SiC semiconductor layer, forming a high density interface state. When electrons are captured at the interface state, the electron mobility decreases due to Coulomb scattering or the like. A method has been proposed in which the interface between the _SiO2 film and the SiC semiconductor layer is terminated with N atoms to reduce the interface state density. However, when a high concentration nitride region is formed at the interface between the _SiO2 film and the SiC semiconductor layer, the gate threshold voltage of the semiconductor device fluctuates in response to the gate negative voltage application stress.

In the insulated gate semiconductor device according to the embodiment, the intermediate nitride termination layer formed at the interface between the gate insulating film 5 and the channel formation region 3 by nitridation is heat-treated with carbon dioxide (CO ₂ ) gas to provide the nitride termination layer 6. The CO ₂ heat treatment breaks the Si-N bonds in the nitride termination layer 6 and the gate insulating film 5, and the excess N atoms can be eliminated, thereby removing the hole traps in the gate insulating film 5. Furthermore, after the CO ₂ heat treatment, the gate insulating film 5 is heat-treated with an inert gas such as nitrogen (N ₂ ) or argon (Ar) to reduce the electron trap level in the gate insulating film 5 that remains without being removed by the nitridation or CO ₂ heat treatment. As a result, it becomes possible to suppress the gate threshold voltage fluctuation of the semiconductor device.

The variation in the gate threshold voltage of a semiconductor device can be evaluated, for example, by a shift in the flat band voltage (V _FB ) of a MOS capacitor. Therefore, a MOS capacitor corresponding to the insulated gate structure according to the embodiment was fabricated and the interface characteristics of the MOS capacitor were evaluated. A manufacturing method of a MOS capacitor corresponding to the insulated gate structure according to the embodiment will be described with reference to the process diagrams shown in FIGS. 2 to 5. Note that the manufacturing method of a MOS capacitor described below is one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit of the claims.

First, an n-type SiC substrate (substrate) 2 doped with n-type impurities such as nitrogen (N) is prepared. The substrate 2 is a 4H-SiC substrate, and has a surface orientation of (0001) surface (Si surface). First, the substrate 2 is subjected to RCA cleaning, which involves adding an alkali or acid to hydrogen peroxide and heating to clean it, and then is treated with hydrogen fluoride (HF) and dried. As shown in FIG. 2, the top surface of the cleaned substrate 2 is heated in a 100% oxygen (O ₂ ) gas atmosphere at a temperature of 1100° C. to 1300° C., for example, at about 1200° C., for about 160 minutes to form an oxide film 5a made of SiO ₂ having a thickness of about 50 nm. Although a dry oxide film is exemplified as the oxide film 5a, a wet oxide film may be used, or a deposited oxide film by sputtering, thermal CVD, plasma CVD, or the like may be used. For example, the oxide film 5a may be deposited at a pressure of about 0.2 Pa and a temperature of about 600° C. using silane (SiH ₄ ) gas and O ₂ gas by low pressure thermal CVD.

Next, nitriding is performed by heating for about 60 minutes at a temperature of 1150° C. to 1300° C., for example, about 1250° C., in a gas atmosphere in which 10% _nitric oxide (NO) gas is added to nitrogen (N 2 ) gas. By this nitriding, an intermediate nitride layer 6a is formed at the interface between the oxide film 5a and the substrate 2, as shown in Fig. 3. Nitrous oxide (N ₂ O) gas may be used instead of NO for the nitriding.

Next, in a CO ₂ gas atmosphere, heat treatment (CO ₂ heat treatment) is performed at 900°C to 1400°C, preferably 950°C to 1300°C, for about 30 minutes. The temperature of the CO ₂ heat treatment is 950°C in Example 1, and 1100°C in Examples 2 and 3. Furthermore, in Example 3, heat treatment (N ₂ heat treatment) is performed at about 1100°C for about 30 minutes in an inert gas, for example, N ₂ gas atmosphere. By the three types of heat treatment in Examples 1 to 3, as shown in FIG. 4, the N atom concentration in the oxide film 5a near the interface between the oxide film 5a and the substrate 2 is reduced, and the nitride termination layer 6 in which some N atoms are removed from the intermediate nitride layer 6a is generated in three different modes. In the CO ₂ heat treatment, 100% CO ₂ gas is used, but a mixed gas of CO ₂ gas and an inert gas such as N ₂ or Ar may be used.

As shown in FIG. 5, a circular pattern of a metal film with a diameter of about 200 μm is formed on the upper surface of the oxide film 5a using lift-off or normal photolithography. The metal film that is the premise of the circular pattern can be a metal film of Al or the like with a thickness of about 100 μm deposited on the upper surface of the oxide film 5a by sputtering, vacuum deposition, or the like. Then, a metal film of Al or the like with a thickness of about 100 μm is deposited on the entire back surface of the substrate 2 by sputtering, vacuum deposition, or the like. In this way, the front surface electrode 10 and the back surface electrode 11 are formed.

The three types of Examples 1 to 3 thus fabricated were repeatedly subjected to electrical tests and CV measurements to evaluate the average density of electrons captured at the trap levels in the oxide film 5a (trapped electron density). In addition, in order to compare with Examples 1 to 3, Comparative Example 1 was fabricated and evaluated in which the front electrode 10 and the back electrode 11 were formed without performing the CO ₂ heat treatment after the formation of the intermediate nitride layer 6a in FIG. 3, as shown in FIG. 6. Comparative Example 2 was also fabricated and evaluated in which, after the formation of the intermediate nitride layer 6a, N ₂ heat treatment was performed for about 30 minutes at about 1100° C. instead of the CO ₂ heat treatment.

In the current test, as shown in FIG. 7, a positive voltage _V is applied to the Al metal film, which is the front electrode 10, and a small current _I flows from the n-type SiC semiconductor layer, which is the substrate 2, to the Al metal film for a certain current flow time. During the current flow, electrons accumulated at the semiconductor interface between the SiC semiconductor layer and the SiO ₂ oxide film corresponding to the oxide film 5a cross the barrier at the interface or tunnel into the oxide film. The current _I is a constant current in the range of 30 pA to 100 pA, for example, about 50 pA. The amount of electrons injected into the oxide film (amount of injected charge) can be calculated by dividing the product of the current _I and the current flow time by the elementary charge.

Using the change ΔV _FB in the flat band voltage V _FB obtained from the CV measurement of the MOS capacitor, the density of electrons trapped in the oxide film, n _T , can be calculated from formula (1). Note that the trapped electron density n _T is a value obtained on the assumption that the trapped electrons are uniformly distributed in the oxide film, but this does not indicate that the electron trap sites are actually uniformly distributed in the oxide film, and the value obtained on this assumption is used as an index of the magnitude of the number of electron traps present in the oxide film.
n _T =-(2Cox/d)ΔV _FB (1)
Here, Cox is the oxide film capacitance per unit area, and d is the thickness of the oxide film. Figure 8 is a linear graph showing an outline of the relationship between the amount of electrons injected into the oxide film and the change amount ΔV _FB of V _FB or the trapped electron density n _T. As shown in Figure 8, the change amount ΔV _FB or the trapped electron density n _T tends to saturate as the injected electron amount accumulates with an increase in the current application time. When the accumulated injected electron amount reaches a limit due to a long period of current application, a dielectric breakdown of the oxide film occurs.

9 is a double logarithmic graph showing the relationship between the trapped electron density n _{T in the oxide film 5a and the amount of injected electrons, which was obtained by repeatedly performing the current test and the CV measurement for Examples 1 to 3 and Comparative Examples 1 and 2. As shown in FIG. 9, the trapped electron density n T increases} with an increase in the amount of injected electrons. The trapped electron density n _T of Example 1 is similar to that of Comparative Example 1 when the amount of injected electrons is 10 ¹⁵ cm ^-2 or less, but is lower than that of Comparative Example 1 when the amount of injected electrons exceeds about 10 ¹⁵ cm ^-2 . Furthermore, the trapped electron density n _T of Example 2 is similar to that of Comparative Example 2 in which N ₂ heat treatment is performed instead of CO ₂ heat treatment when the amount of injected electrons is 10 ¹⁵ cm ^-2 or less, but is lower than that of Comparative Example 2 when the amount of injected electrons exceeds about 10 ¹⁵ cm ^-2 . Furthermore, when the amount of injected electrons is about 5×10 ¹⁵ cm ^-2 or more, the trapped electron density n _T of Example 1 is also lower than that of Comparative Example 2. Thus, it is seen that the effect of reducing the trapped electron density _nT by the _CO2 heat treatment becomes apparent when the amount of injected electrons is in the range of about 5× ¹⁰¹⁵ cm ^-2 or more and about 1× ¹⁰¹⁶ cm ^-2 or less. Moreover, in Example 3 in which the _N2 heat treatment was performed after the _CO2 heat treatment, the trapped electron density _nT is reduced over the entire range of injected electron amounts compared to Examples 1 and 2. From this, it is presumed that the trap level of electrons remaining in the oxide film 5a without being removed by the nitriding treatment and the _CO2 heat treatment is reduced by the _N2 heat treatment, thereby reducing the trapped electron density _nT .

FIG. 10 shows the trapped electron density n _T at a total injected electron amount of about 6×10 ¹⁵ cm ⁻² obtained by current tests and CV measurements for Examples 1 to 3 and Comparative Examples 1 and 2. As shown in the table of FIG. 10, in Comparative Examples 1 and 2 where no CO ₂ heat treatment was performed, the trapped electron density n _T is high at 3.5×10 ¹⁷ cm ⁻³ and 3.35×10 ¹⁷ cm ⁻³ , respectively. On the other hand, in Examples 1 and 2 where CO ₂ heat treatment was performed, the trapped electron density n _T is 1.95×10 ¹⁷ cm ⁻³ and 0.66×10 ¹⁷ cm ⁻³ , respectively, which is reduced to 2×10 ¹⁷ cm ⁻³ or less. Furthermore, in Example 3 where N ₂ heat treatment was performed after CO ₂ heat treatment, the trapped electron density n _T is further reduced to 0.26×10 ¹⁷ cm ⁻³ . Thus, performing the CO ₂ heat treatment at a high temperature is more effective in reducing the trapped electron density n _T. Furthermore, when the N ₂ heat treatment is performed after the CO ₂ heat treatment, the trapped electron density n _T can be reduced by one order of magnitude or more compared to Comparative Examples 1 and 2.

In the insulating gate structure according to the embodiment, after the nitridation of the oxide film 5a, a CO ₂ heat treatment is performed, and then a N ₂ heat treatment is performed. In the CO ₂ treatment, the Si-N bonds or Si-O-N bonds in the oxide film 5a introduced by the nitridation are broken. Although the heat treatment with O ₂ gas instead of CO ₂ gas has the effect of breaking the Si-N bonds and converting them to Si-O bonds, the SiC surface of the substrate 2 is also oxidized, and the N passivation at the interface formed by the nitridation is destroyed. On the other hand, at about 800°C to 1400°C, CO ₂ gas is decomposed into CO, a reducing gas, and O ₂ , an oxidizing gas. CO can break the Si-N bonds in the SiO ₂ film, but it is not as easy to destroy the N passivation at the interface as O _2. Therefore, the interface state density can be reduced. In addition, by performing an additional N ₂ heat treatment, the electron trap level in the oxide film 5a, which is difficult to repair by the nitridation or CO ₂ heat treatment, can be reduced. As a result, it is possible to suppress fluctuations in the gate threshold voltage of the semiconductor device.

In the above description, a SiC substrate with a (0001) plane (Si plane) orientation is used as the substrate 2. The Si plane has a faster oxidation rate than the (11-20) plane (a plane), the (1-100) plane (m plane), and the (000-1) plane (C plane). Therefore, for the Si plane, the CO ₂ heat treatment temperature is preferably in the range of 1000°C to 1400°C, and more preferably in the range of 1100°C to 1300°C. For the a-plane, m-plane, and C-plane, the CO ₂ heat treatment temperature is preferably in the range of 800°C to 1200°C, and more preferably in the range of 1000°C to 1200°C.

(Method of manufacturing an insulated gate semiconductor device)
Next, a method for manufacturing an insulated gate semiconductor device according to an embodiment will be described using a lateral MOSFET as an example, with reference to the process diagrams shown in Figures 11 to 16. Note that the method for manufacturing a MOSFET described below is only one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be used within the scope of the spirit of the claims.

First, an n-type SiC substrate (substrate) 1 doped with n-type impurities such as nitrogen (N) is prepared. The substrate 1 is a 4H-SiC substrate, and has a surface orientation of (0001) (Si surface). A p-type channel formation region (base region) 3 is epitaxially grown on the upper surface of the substrate 1. An n-type impurity such as N is selectively injected from the upper surface side of the channel formation region 3 by photolithography technology, ion injection technology, or the like. The injected n-type impurity ions are activated by heat treatment. As a result, as shown in FIG. 11, an n ⁺ -type source region (first main region) 4a and a drain region (second main region) 4b are selectively embedded in the upper part of the channel formation region 3.

12, an oxide film 5b made of _SiO2 having a thickness of about 50 nm is formed on the upper surface of the channel formation region 3 by heating in a 100% _O2 gas atmosphere at a temperature of about 1200°C for about 160 minutes. Although a dry oxide film is exemplified as the oxide film 5b, a wet oxide film or a deposited oxide film by thermal CVD, plasma CVD or the like may also be used. For example, the oxide film 5b may be deposited by reduced pressure thermal CVD using silane ( _SiH4 ) gas and oxygen ( _O2 ) gas at a pressure of about 0.2 Pa and a temperature of about 600°C.

Next, nitridation is performed by heating for about 60 minutes at a temperature of about 1250° C. in a gas atmosphere in which 10% nitric oxide (NO) gas is added to _N2 gas. By this nitridation, an intermediate nitride layer 6a is formed at the interfaces between the oxide film 5b and the channel formation region 3, the source region 4a, and the drain region 4b, as shown in Fig. 13. Note that _N2O gas may be used instead of NO for the nitridation.

After the nitridation process, a _CO2 heat treatment is performed in a _CO2 gas atmosphere at two different temperatures for about 30 minutes each. The two temperatures are about 950°C for Example 4 and about 1100°C for Examples 5 and 6. For Example 3, after the _CO2 heat treatment, a N2 heat treatment is performed in a _N2 gas atmosphere at about 1100°C for about 30 minutes. As shown in FIG. 14, the heat treatments in Examples 4 to 6 reduce the N _atom concentration in the oxide film 5b near the interface between the oxide film 5b and the channel formation region 3, the source region 4a, and the drain region 4b in each mode. In each mode, a nitride termination layer 6 is generated in which some N atoms have been removed from the intermediate nitride layer 6a. Although 100% _CO2 gas is used in the _CO2 heat treatment, a mixed gas of _CO2 gas and an inert gas such as _N2 or Ar may be used.

Source contact holes and drain contact holes are opened in the oxide film 5b by photolithography and dry etching. As a result, as shown in FIG. 15, the pattern of the gate insulating film 5 selectively remains on the upper surface of the channel formation region 3 so as to straddle the source region 4a and the drain region 4b.

A metal film such as Al having a thickness of about 100 μm is deposited on the upper surfaces of the gate insulating film 5, the source contact hole, and the drain contact hole by sputtering, vacuum deposition, or the like. The metal film is separated by photolithography, dry etching, or the like to form the patterns of the gate electrode 7, the source electrode 8a, and the drain electrode 8b. As a result, an insulated gate electrode structure (5, 7) is formed on the upper surface of the channel formation region 3 via the nitride termination layer 6 so as to straddle a part of the ends of the source region 4a and the drain region 4b. In this way, the insulated gate semiconductor device according to the embodiment shown in FIG. 16 is completed.

For the three types of lateral MOSFETs thus fabricated, Examples 4 to 6, a transistor drive test is carried out to measure the transistor characteristics, and the shift amount ΔV _TH of the gate threshold voltage (V _TH ) is evaluated. The transistor drive test is carried out by applying a square wave voltage of +20 V/−10 V as the gate voltage for 10,000 hours at room temperature and a switching frequency of 200 kHz. As shown in FIG. 17, in order to compare with Examples 4 to 6, Comparative Example 3 in which the gate insulating film 5, the gate electrode 7, the source electrode 8a, and the drain electrode 8b are formed without carrying out the CO 2 heat treatment after the formation of the intermediate nitride layer 6a in FIG. 13 is also evaluated. Comparative Example 4 in which, instead of the CO ₂ heat treatment, an N ₂ heat treatment at about 1100° C. for about 30 minutes is carried out after the formation of the intermediate nitride layer 6a is also produced and evaluated.

FIG. 18 is a graph showing the shift amount ΔV _TH of the gate threshold voltage with respect to the transistor drive time. As shown in FIG. 18, the shift amount ΔV _TH increases with an increase in drive time. The shift amount ΔV _TH of Example 4 is similar to that of Comparative Example 3 when the drive time is less than 1000 hours, but is smaller than that of Comparative Example 3 when the drive time is 1000 hours or more. The shift amount ΔV _TH of Example 5 is similar to that of Comparative Example 4 in which N ₂ heat treatment is performed instead of CO ₂ heat treatment when the drive time is 100 hours or less, but is smaller than that of Comparative Example 4 when the drive time exceeds 100 hours. Furthermore, the shift amount ΔV _TH of Example 5 is smaller than that of Comparative Example 4 when the drive time exceeds 1000 _hours . Moreover, in Example 6 in which N ₂ heat treatment is performed after CO ₂ heat treatment, the shift amount ΔV _TH is small over the entire drive time range. The relationship between the drive time and the shift amount ΔV _TH shown in FIG. 18 is similar to the relationship between the injected electron amount and the trapped electron density n _T shown in FIG. 9. In particular, when linear interpolation is performed between the measured values of the trapped electron density _nT in FIG. 9, it is found that the trapped electron density _nT when the amount of injected electrons is about 5× ¹⁰¹⁵ cm ^-2 corresponds to the magnitude relationship of the shift amount _ΔVTH when the drive time exceeds 1000 hours.

FIG. 19 shows the evaluation results of the shift amount ΔV _TH of the gate threshold voltage after 10,000 hours of operation. As shown in the table of FIG. 19, the shift amount ΔV _TH of Example 4 and Example 5, which were subjected to CO ₂ heat treatment at 950° C. and 1100° C., is 0.30 V and 0.10 V, respectively. The shift amount ΔV _T of Example 6, which was subjected to CO ₂ heat treatment and N ₂ heat treatment at 1100° C., is 0.06 V. On the other hand, the shift amount ΔV _T of Comparative Example 3, which was subjected to only the conventional nitriding treatment, is 0.94 V, and the shift amount ΔV _T of Comparative Example 4, which was subjected to N ₂ heat treatment instead of CO ₂ heat treatment, is 0.86 V. Thus, in Examples 4 to 6, a large improvement is observed in the shift amount ΔV _TH of the gate threshold voltage after 10,000 hours of operation. This 10,000 hours of operation at a switching frequency of 200 kHz corresponds to 100,000 hours of operation at a switching frequency of 20 kHz, and the shift amount ΔV _TH in Examples 4 to 6 is within a range that does not cause practical problems. In this way, in the insulated gate semiconductor device according to the embodiment, it is possible to suppress the gate threshold voltage shift, and to suppress deterioration of the reliability of the semiconductor device.

Other Embodiments
As described above, the insulated gate semiconductor device according to the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

As described above, in the insulated gate semiconductor device according to the embodiment, a lateral MOSFET using 4H-SiC is exemplified, but it is also possible to apply the present invention to semiconductor devices using 6H-SiC and 3C-SiC. Furthermore, it is also possible to apply the present invention to planar gate vertical MOSFETs and trench gate vertical MOSFETs.

As such, the present invention naturally includes various embodiments not described here, such as configurations that arbitrarily apply the configurations described in the above embodiments and each modified example. Therefore, the technical scope of the present invention is determined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description.

1, 2...Substrate (SiC substrate)
3...Channel forming region (base region)
4a...Source area (first main area)
4b...Drain region (second main region)
5: gate insulating film 5a, 5b: oxide film 6: nitride termination layer 6a: intermediate nitride layer 7: gate electrode (control electrode)
8a... source electrode, 8b... drain electrode, 10... front surface electrode, 11... rear surface electrode

Claims (7)

forming a gate insulating film made of a silicon oxide film on an upper surface of a channel formation region made of silicon carbide;
a step of nitriding an interface between the gate insulating film and silicon carbide by heat-treating the gate insulating film with a gas containing nitrogen atoms, thereby forming an intermediate nitride layer at the interface between the channel formation region and the gate insulating film;
a step of heat-treating the gate insulating film with a gas containing carbon dioxide to remove some of the nitrogen atoms in the gate insulating film and form a nitride termination layer at the interface;
after forming the nitride termination layer, heat treating the gate insulating film with an inert gas;
and forming a gate electrode on the gate insulating film to control a surface potential of the channel formation region. 2. The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein when electrons are injected into the gate insulating film with an injection charge amount of 5× ¹⁰¹⁵ cm ^-2 or more and 1× ¹⁰¹⁶ cm- ² or less by passing a current between the channel formation region and the gate electrode, an average density of the electrons captured in the gate insulating film is 2× ¹⁰¹⁷ cm ^-3 or less. The method for manufacturing an insulated gate semiconductor device according to claim 1 or 2, characterized in that the heat treatment after forming the nitride termination layer is carried out in the inert gas at a temperature in the range of 900°C or more and 1200°C or less for a time period of 30 minutes or more and 60 minutes or less. The method for manufacturing an insulated gate semiconductor device according to any one of claims 1 to 3, characterized in that the nitride termination layer is formed in the gas containing carbon dioxide at a heat treatment temperature in the range of 900°C or more and 1400°C or less for a period of 30 minutes or more and 120 minutes or less. The method for manufacturing an insulated gate semiconductor device according to any one of claims 1 to 4, characterized in that the surface orientation of the upper surface of the channel formation region is a (0001) surface, and the nitride termination layer is formed at a heat treatment temperature of 1100°C or higher and 1300°C or lower. The method for manufacturing an insulated gate semiconductor device according to any one of claims 1 to 4, characterized in that the surface orientation of the upper surface of the channel formation region is any one of the (000-1), (11-20), and (1-100) planes, and the nitride termination layer is formed at a heat treatment temperature of 1000°C or higher and 1200°C or lower. a gate insulating film made of a silicon oxide film provided on an upper surface of a channel formation region made of silicon carbide;
a nitride termination layer made of silicon nitride provided at an interface between the channel formation region and the gate insulating film;
a gate electrode provided on the gate insulating film for controlling a surface potential of the channel formation region;
Equipped with
an insulated gate semiconductor device, characterized in that when electrons are injected into the gate insulating film with an injection charge amount of 5× ¹⁰¹⁵ cm ^-2 or more and 1× ¹⁰¹⁶ cm ^-2 or less by passing a current between the channel formation region and the gate electrode, the average density of the electrons captured in the gate insulating film is 2× ¹⁰¹⁷ cm ^-3 or less.

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