JP7579367B2 - Error rate measurement device and error rate measurement method - Google Patents

Description

The present invention relates to an error rate measurement device and an error rate measurement method for measuring whether the device under test is capable of FEC (Forward Error Correction) operation when transmitting a known pattern (PAM4 signal) as a test signal to the device under test while the device under test is transitioned to a signal pattern return state and measuring the bit error rate of input data that is returned and received from the device under test in response to the transmission of this test signal.

Error rate measuring devices have traditionally been known as devices that measure the bit error rate (BER) by transmitting a test signal of a known pattern containing fixed data to the device under test, and comparing the signal under test received by the device under test in response to the transmission of the test signal with a reference signal on a bit-by-bit basis.

Also, as disclosed in the following Patent Document 1, an error rate measurement device is known that has an RS-FEC measurement function that complies with the IEEE 802.3 standard. This error rate measurement device tallies the number of FEC symbol errors for each codeword length in an area separated by the codeword length, and obtains and displays each error count number and error rate.

JP 2021-136651 A

The error rate measurement device in Patent Document 1 counts the number of codewords for each number of symbol errors per codeword, and displays whether or not there is a codeword in which multiple symbol errors have been corrected.

However, the error rate measuring device of Patent Document 1 above could not check the number of FEC symbol errors within one Flit in an area divided by Flit length defined in, for example, the PCI Express 6 standard as a high-speed serial bus standard, or the number of FEC symbol errors for each ECC Group. This caused a problem that it became difficult to proceed with debugging of a device under test developed in accordance with, for example, the PCI Express 6 standard.

The present invention has been made in consideration of the above problems, and aims to provide an error rate measurement device and an error rate measurement method that can efficiently debug a device under test developed according to the high-speed serial bus standard.

In order to achieve the above object, the error rate measurement device according to the present invention is an error rate measurement device 1 for measuring whether or not a forward error correction (FEC) operation of a device under test ( W) is possible, comprising:
an operation unit 4 for setting a threshold n for the number of FEC symbol errors occurring in one ECC Group in one Flit, a threshold m for the number of consecutive FEC symbol errors occurring, and a threshold k for the number of consecutive Flit errors occurring as thresholds for determining a Flit error in a Flit defined in a high-speed serial bus standard;
a pattern generator 2 for generating a PAM4 signal to be transmitted to the device under test;
a storage unit 5 for storing data of a PAM4 signal that is returned from the device under test in association with the transmission of a PAM4 signal generated by the pattern generator;
an error detection unit 3b that masks an area of the PAM4 signal from the device under test that is not defined as an FEC symbol, and compares the masked PAM4 signal with a reference pattern to detect an FEC symbol error, an FEC symbol error within one Flit, and an FEC symbol error for each ECC Group;
an error counting unit 7c for counting FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group based on the error detection result of the error detection unit ;
a display control means for displaying a count result by the error count means on a list display screen ,
The display control means displays, on the list display screen, an uncorrectable. Flit error rate, the number of Flits in which the number of FEC symbol errors within a Flit length allocated to one lane exceeds the threshold n, an FEC symbol error rate, and the number of FEC symbol errors per FEC symbol within a Flit range,
Also, the number of Flits for each number of FEC symbol errors in the Flit, the distribution of FEC symbol errors in ECC Group units in the Flit and an error rate based on the distribution, and the distribution of FEC symbol errors in the Flit and an error rate based on the distribution are displayed on the list display screen.
Furthermore, the number of consecutive occurrences of Flit errors exceeding the threshold k and the error rate are displayed on the list display screen,
Furthermore, the number of consecutive FEC symbol errors exceeding the threshold value m and the error rate are displayed on the list display screen .

The error rate measurement device according to claim 2 of the present invention is the error rate measurement device according to claim 1,
The display control means 7d displays the frequency of occurrence of the number of FEC symbol errors in one Flit or the frequency of occurrence of the number of FEC symbol errors for each ECC Group counted by the error counting means 7c ,
The frequency of occurrence of the number of FEC symbol errors in one Flit is displayed in the form of a bar graph or a pie chart, in which the number of Flits in which an FEC symbol error has occurred is counted for each number of FEC symbol errors .
The error rate measurement device according to claim 3 of the present invention is the error rate measurement device according to claim 1 or 2,
a reference pattern generating means (7a) for generating a reference pattern based on the data of the PAM4 signal from the object to be measured (W) stored in the storage unit (5);
When a pattern that is the basis of the PAM4 signal to be transmitted to the device under test is a Flit, a pattern head signal that is generated when a pattern identical to the head of the pattern of the Flit set by the operation unit 4 is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate a Flit that is a reference to be set by the operation unit, and the generated Flit is divided into a reference pattern of MSB and a reference pattern of LSB and outputted;
When the PAM4 signal generated by the pattern generator 2 is based on the bit string data of Flit, a pattern identical to the beginning of a Flit pattern based on a Flit length, an EIEOS insertion period, and an SKP interval corresponding to the number of lanes set by the operation unit is searched for from the input data, and the beginning of the PAM4 signal is detected;
When the pattern that is the basis of the PAM4 signal to be transmitted to the device under test is an MCP, a pattern head signal that is generated when a pattern identical to the head of the pattern of the MCP set by the operation unit is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate an MCP that is to be a reference that is set by the operation unit, and the generated MCP is divided into an MSB reference pattern and an LSB reference pattern and outputted;
When the PAM4 signal generated by the pattern generator is based on the bit string data of the MCP, a pattern identical to the head of the MCP based on the selection of SRIS or Not SRIS set by the operation unit and the length and number of virtual Flits is searched for from the input data, thereby detecting the head of the PAM4 signal;
When a pattern that is the basis of the PAM4 signal to be transmitted to the device under test is a CP, a pattern head signal that is generated when a pattern identical to the head of the pattern of the CP set by the operation unit is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate a CP that is to be a reference that is set by the operation unit, and the generated CP is divided into an MSB reference pattern and an LSB reference pattern and outputted;
When the PAM4 signal generated by the pattern generator is based on the bit string data of a CP, the input data is searched for a pattern identical to the beginning of a CP based on the length and number of virtual Flits set by the operation unit, and the beginning of the PAM4 signal is detected.

The error rate measurement method according to claim 4 of the present invention is a method for measuring whether or not a forward error correction (FEC) operation of a device under test (W) is possible, comprising the steps of:
a step of setting, by an operation unit 4, a threshold n of the number of FEC symbol errors occurring in one ECC Group in one Flit, a threshold m of the number of consecutive FEC symbol errors occurring, and a threshold k of the number of consecutive Flit errors occurring, as thresholds for determining a Flit error of a Flit defined in a high-speed serial bus standard;
generating a PAM4 signal to be transmitted to the device under test by a pattern generator;
storing data of a PAM4 signal that is returned from the device under test in association with the transmission of the PAM4 signal generated by the pattern generator in a storage unit;
a step of masking an area of the PAM4 signal from the device under test that is not defined as an FEC symbol, and detecting an FEC symbol error, an FEC symbol error within one Flit, and an FEC symbol error for each ECC Group by an error detection unit 3b by comparing the masked PAM4 signal with a reference pattern;
counting FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group by an error counting means 7c based on the error detection result of the error detection section ;
a step of displaying the count result by the error count means on a list display screen 15 by a display control means 7d ;
displaying, on the list display screen, an uncorrectable. Flit error rate, the number of Flits in which the number of FEC symbol errors in a Flit length allocated to one lane exceeds the threshold n, an FEC symbol error rate, and the number of FEC symbol errors in FEC symbol units within a Flit range, by the display control means;
displaying , on the list display screen by the display control means, the number of Flits for each number of FEC symbol errors in the Flits, a distribution of FEC symbol errors in units of ECC Groups in the Flits and an error rate based on the distribution , and a distribution of FEC symbol errors in the Flits and an error rate based on the distribution;
displaying, on the list display screen, the number of consecutive occurrences of Flit errors exceeding the threshold k and an error rate by the display control means;
and displaying, on the list display screen, the number of consecutive FEC symbol errors exceeding the threshold m and the error rate using the display control means .

The error rate measurement method according to claim 5 of the present invention is the error rate measurement method according to claim 4 ,
a step of displaying, by the display control means 7d , the frequency of occurrence of the number of FEC symbol errors in one Flit or the frequency of occurrence of the number of FEC symbol errors for each ECC Group counted by the error count means 7c ;
and displaying the frequency of occurrence of the number of FEC symbol errors in one Flit in a bar graph or a pie chart, the frequency of occurrence being calculated by counting the number of Flits in which an FEC symbol error occurred for each number of FEC symbol errors.
The error rate measurement method according to claim 6 of the present invention is the error rate measurement method according to claim 4 or 5,
generating a reference pattern by a reference pattern generating means 7a based on the data of the PAM4 signal from the object W stored in the storage unit 5;
When a pattern that is the basis of the PAM4 signal to be transmitted to the device under test is a Flit, a pattern head signal that is generated when a pattern identical to the head of the pattern of the Flit set by the operation unit 4 is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate a Flit that is a reference to be set by the operation unit, and the generated Flit is divided into a reference pattern of an MSB and a reference pattern of an LSB and outputted;
When the PAM4 signal generated by the pattern generator 2 is based on the bit string data of Flit, a step of searching the input data for a pattern identical to the head of a Flit pattern based on a Flit length, an EIEOS insertion period, and an SKP interval according to the number of lanes set by the operation unit, thereby detecting the head of the PAM4 signal;
a step of generating an MCP to be a reference set by the operation unit, using a pattern head signal generated when a pattern identical to the head of the pattern of the MCP set by the operation unit is searched for in the PAM4 signal stored in the storage unit as a trigger when the pattern is an MCP, and dividing the generated MCP into an MSB reference pattern and an LSB reference pattern and outputting the resulting MCP;
When the PAM4 signal generated by the pattern generator is based on the bit string data of the MCP, a step of searching the input data for a pattern identical to the head of the MCP based on the selection of SRIS or Not SRIS set by the operation unit and the length and number of virtual Flits, thereby detecting the head of the PAM4 signal;
a step of generating a CP to be set as a reference in the operation unit, using a pattern head signal generated when a pattern identical to the head of the pattern of the CP set in the operation unit is searched for in the PAM4 signal stored in the storage unit as a trigger when the pattern is a CP, and dividing the generated CP into an MSB reference pattern and an LSB reference pattern and outputting them;
When the PAM4 signal generated by the pattern generator is based on the bit string data of a CP, the method further includes a step of searching for a pattern identical to the beginning of a CP based on the length and number of virtual Flits set by the operation unit from among input data to detect the beginning of the PAM4 signal.

According to the present invention, it is possible to check the number of FEC symbol errors within one Flit in an area divided by the Flit length defined in the high-speed serial bus standard, and the number of FEC symbol errors for each ECC Group, and it is possible to efficiently debug a device under test developed in accordance with the high-speed serial bus standard.

1 is a block diagram showing a schematic configuration of an error rate measurement device according to the present invention; FIG. 2 is an explanatory diagram of Flit defined in the PCI Express 6 standard. 11 is a diagram illustrating an example of the number of errors for each ECC Group in a Flit, and the number of Flits for each number of FEC symbol errors in a Flit. FIG. 1 is a diagram showing an example of an FEC measurement screen of the PCI Express 6 standard in the error rate measurement device according to the present invention. FIG. 13 is a diagram showing an example of a list display screen of error count results in the error rate measurement device according to the present invention. FIG. 13 is a diagram showing an example of an FEC measurement screen in which the number of Flits in which an FEC symbol error occurred within one Flit is tallied by the number of FEC symbol errors and displayed in a bar graph in the error rate measurement device according to the present invention. FIG. 13 is a diagram showing an example of an FEC measurement screen when FEC symbol errors occurring within one Flit are recounted into the number of errors for each ECC Group and displayed in a bar graph in the error rate measurement device according to the present invention. 4 is a flowchart of a processing operation of the error rate measurement device according to the present invention.

The following describes in detail the embodiment of the present invention with reference to the attached drawings.

The error rate measurement device of the present invention transmits a test signal of a known pattern to the device under test while the device under test is transitioned to a signal pattern return state, and measures the error rate of the received signal that is returned from the device under test in response to the transmission of this test signal.

As shown in FIG. 1, the error rate measurement device 1 of this embodiment is roughly configured with a pattern generator 2, an error detector 3, an operation unit 4, a memory unit 5, a display unit 6, and a control unit 7. When measuring whether the FEC (Forward Error Correction) operation of the object to be measured W is possible, in addition to the symbol measurement results and bit measurement results of the PAM4 signal, it has the function of displaying a list of the number of FEC symbol errors in one Flit of an area divided by the Flit length defined in PCI Express 6 (hereinafter referred to as PCIe Gen6 standard) as a high-speed serial bus standard and/or the number of FEC symbol errors for each ECC Group, and displaying a bar graph (or pie chart) of the occurrence frequency of these.

The concept of Flit was defined in PCIe Gen6, but the present invention can also be applied to future PCI Express standards that use a similar concept of Flit. In this embodiment, PCIe Gen6 is used as an example, but the present invention can also be applied to other high-speed serial bus standards such as USB, for example, when checking the number of FEC symbol errors within one Flit in an area divided by Flit length or the number of FEC symbol errors for each ECC Group.

First, we will explain Flit, which is defined in the PCIe Gen6 standard that is used by the error rate measurement device 1 of this embodiment. In the PCIe Gen6 standard, Flit is a data format that is transmitted when the state of the LTSSM (Link Training and Status State Machine) is L0, and has an error correction function using FEC.

As shown in Figure 2, one Flit is interleaved with three ECC Groups (ECC Group 0, ECC Group 1, ECC Group 2). One ECC Group is separated by one FEC Symbol (4 PAM4 Symbols = 8 bits).

To summarize the conditions for a Flit to become uncorrectable, if an FEC Symbol Error occurs twice in the same ECC Group within one Flit, it becomes uncorrectable.

Further explanation will be given using Figure 3. Figure 3 shows an example of the number of errors for each ECC Group in a Flit, the number of uncorrectables (2 or more), and the number of Flits for each number of FEC symbol errors in a Flit (0 to 7, 8 or more). Note that in Figure 3, the parts indicated with diagonal lines slanting downwards to the right indicate parts that are uncorrectable, and the parts indicated with diagonal lines slanting upwards to the right indicate parts that may or may not be uncorrectable.

For example, the case where FEC Symbol Error Threshold in One ECC Group (threshold n described later) is ≧2 will be explained with reference to Figure 3. In A (number of Flits: 3) surrounded by dotted lines in Figure 3, two FEC symbol errors have occurred in the Flit, but since the number of errors in each of the separate ECC Groups (ECC Group 0 and ECC Group 1 in this case) is one each, it does not become Uncorrectable.

In contrast, in B (number of Flits: 5) enclosed by the dotted line in Figure 3, not only are there four FEC symbol errors in the Flit, but when looking at the number of errors per ECC Group, there are two errors in one of the ECC Groups (ECC Group 0 in this case), so it is uncorrectable.

Furthermore, in C (number of Flits: 9) surrounded by the dotted line in Figure 3, two FEC symbol errors occur within the Flit, and the number of errors in the same ECC Group (ECC Group 0 in this case) is two, so it becomes Uncorrectable.

In this embodiment, the threshold value for the number of FEC symbol errors that occur in one ECC Group in one Flit, n, is set in the operation unit 4 as a threshold value for determining Flit errors described later, and errors that exceed the threshold value n are counted. Specifically, errors that exceed the "FEC Symbol Error Threshold in One ECC Group" (threshold value n described later) setting item in FIG. 4 are counted as Uncorrectable. Flit, and errors below n are counted as the number of FEC symbol errors in one Flit and the number of FEC symbol errors for each ECC Group.

For example, if n ≥ 2, n = 0 and 1 count the number of FEC symbol errors for each ECC Group within 1 Flit, and n = 2 or more counts it as an Uncorrectable Flit.

As will be described later, in the setting items in FIG. 4, "Consecutive FEC Error Threshold" is the threshold for the number of consecutive FEC symbol errors: m, and "Consecutive Errored Flit Threshold" is the threshold for the number of consecutive Flit errors: k.

Next, the configuration of each part of the error rate measurement device 1 will be described. Based on the settings of the operation unit 4, the pattern generator 2 generates a PAM4 signal based on bit string data of PRBS, Flit defined in the PCIe Gen6 standard, MCP (Modified Compliance Pattern), or CP (Compliance Pattern). The PAM4 signal generated by this pattern generator 2 is transmitted to the device under test W as a test signal of a known pattern.

The error detector 3 receives the PAM4 signal that is returned from the object to be measured W in response to the transmission of the test signal (PAM4 signal based on any one of the patterns PRBS, Flit, MCP, or CP) generated by the pattern generator 2, and performs error detection. It includes a signal receiving unit 3a and an error detection unit 3b.

The signal receiving unit 3a includes a data dividing means 3aa, and receives the PAM4 signal returned from the object to be measured W when a test signal (PAM4 signal) is transmitted from the pattern generator 2 to the object to be measured W in a state in which the object to be measured W has transitioned to a signal return state due to link training.

The data splitting means 3aa splits the PAM4 signal received from the object to be measured W into a most significant bit string signal (hereinafter referred to as MSB data) and a least significant bit string signal (hereinafter referred to as LSB data) as necessary.

The error detection unit 3b masks the portion of the PAM4 signal from the object to be measured W stored in the memory unit 5 that corresponds to SKP and EIEOS (area outside the Flit that is not defined as an FEC Symbol) with a mask pattern, and detects various errors (bit errors, PAM4 symbol errors, FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group) by comparing the masked PAM4 signal with a reference pattern described later.

The operation unit 4 also functions as a setting means, and is composed of a user interface such as an operation knob, various keys, switches, buttons, and soft keys on the display screen of the display unit 6, which are provided on the main body of the error rate measurement device 1 in FIG. 1.

The operation unit 4 performs various settings and instructions related to the pattern generator 2 and error detector 3, such as setting the conditions for generating a PAM4 signal to be transmitted to the object under test W, setting the conditions for detecting various errors (bit errors, PAM4 symbol errors, FEC symbol errors, FEC symbol errors within one Flit, FEC symbol errors for each ECC Group within one Flit) based on the PAM4 signal returned from the object under test W, and settings and instructions related to the baud rate and various compliance tests.

For example, the condition settings for generating a PAM4 signal to be transmitted to the object W under test, and the condition settings for detecting various errors based on the PAM4 signal returned from the object W under test will be described. When transmitting a PAM4 signal based on PRBS bit string data to the object W under test to detect various errors, the PRBS number of stages, the Flit length according to the number of lanes, the mask pattern length and mask pattern period for masking the portion corresponding to the SKP (portion outside the Flit), the threshold for determining the Flit error, the PAM4 Graycoding setting, and the PAM4 Precoding setting are set.

When detecting various errors by transmitting a PAM4 signal based on the bit string data of the Flit to the object to be measured W, the following settings are made: one period of the Flit pattern (including EIEOS and SKP) according to the number of lanes, the Flit length according to the number of lanes, the mask pattern length and mask pattern period for masking the parts corresponding to EIEOS and SKP (parts outside the Flit), the threshold for determining the Flit error, the PAM4 Graycoding setting, the PAM4 Precoding setting, the EIEOS insertion period, and the pattern start.

Furthermore, when detecting various errors by transmitting a PAM4 signal based on the MCP bit string data to the object to be measured W, the following settings are made: one period of the MCP pattern (including EIEOS and SKP), the Flit length according to the number of lanes, the mask pattern length and mask pattern period for masking the parts corresponding to EIEOS and SKP (parts outside the Flit), the threshold for determining Flit errors, the PAM4 Graycoding setting, the PAM4 Precoding setting, the MCP pattern length, the pattern start, and the selection of SRIS or Not SRIS.

When detecting various errors by transmitting a PAM4 signal based on the CP bit string data to the object to be measured W, the following settings are made: one period of the CP pattern (including EIEOS), the Flit length according to the number of lanes, the mask pattern length and mask pattern period for masking the part corresponding to EIEOS (outside the Flit), the threshold for determining Flit errors, the PAM4 Graycoding setting, the PAM4 Precoding setting, the CP pattern length, and the pattern start.

The thresholds for determining the above-mentioned Flit errors are: n, the threshold for the number of FEC symbol errors that occur in one ECC Group in one Flit; m, the threshold for the number of consecutive FEC symbol errors; and k, the threshold for the number of consecutive Flit errors.

The memory unit 5 stores the data (including MSB data and LSB data) of the PAM4 signal received by the signal receiving unit 3a from the object to be measured W. The memory unit 5 also stores various setting information set by the operation unit 4, reference patterns generated by the reference pattern generating means 7a described below, information on mask patterns generated by the mask pattern generating means 7b, and counting results by the error counting means 7c.

The display unit 6 is comprised of, for example, a liquid crystal display provided on the main body of the error rate measurement device 1 in FIG. 1, and displays, under the control of the display control means 7d described later, a setting screen for various compliance tests (tests to see whether the object W complies with a communication standard) including a measurement of whether the object W can perform FEC operation, a capture screen, an FEC measurement screen 11 (FIGS. 4, 6, and 7) described later, and a list display screen 15 (FIG. 5). The display unit 6 also has the operating functions of the operation unit 4, such as soft keys on the display screen.

The control unit 7 includes, for example, a central processing unit (CPU), ROM, RAM, etc., and controls the pattern generator 2, error detector 3, operation unit 4, memory unit 5, and display unit 6 when performing various compliance tests, including measuring whether FEC operation is possible for the object to be measured W, and includes a reference pattern generating means 7a, a mask pattern generating means 7b, an error counting means 7c, and a display control means 7d.

The reference pattern generating means 7a generates a reference pattern based on the PAM4 signal data from the object to be measured W stored in the memory unit 5.

To explain further, when the pattern that is the basis of the PAM4 signal to be transmitted to the object to be measured W is a PRBS, a PRBS that will be the MSB reference pattern is generated using the MSB data of the PAM4 signal stored in the memory unit 5 as a seed, with the PRBS number of stages set by the operation unit 4. A seed is also generated for generating the LSB reference pattern. Furthermore, a PRBS that will be the LSB reference pattern is generated using the MSB reference pattern as a seed, with the PRBS number of stages set by the operation unit 4.

When the pattern that is the basis of the PAM4 signal to be transmitted to the object to be measured W is a Flit, the pattern start signal that is generated when a pattern identical to the start of the pattern of the Flit set in the operation unit 4 is searched for among the PAM4 signals stored in the memory unit 5 is used as a trigger to generate a Flit that is the reference set in the operation unit 4, and the generated Flit is divided into an MSB reference pattern and an LSB reference pattern and output.

When the pattern that is the basis of the PAM4 signal to be transmitted to the object to be measured W is an MCP, the pattern start signal that is generated when a pattern identical to the start of the pattern of the MCP set in the operation unit 4 is searched for among the PAM4 signals stored in the memory unit 5 is used as a trigger to generate an MCP that is the reference set in the operation unit 4, and the generated MCP is divided into an MSB reference pattern and an LSB reference pattern and output.

When the pattern that is the basis of the PAM4 signal to be transmitted to the object to be measured W is a CP, the pattern start signal that is generated when a pattern identical to the start of the CP pattern set in the operation unit 4 is searched for among the PAM4 signals stored in the memory unit 5 is used as a trigger to generate a CP that is the reference set in the operation unit 4, and the generated CP is divided into an MSB reference pattern and an LSB reference pattern and output.

The mask pattern generating means 7b generates a mask pattern based on the mask pattern length and mask pattern period set in the operation unit 4.

The error counting means 7c counts bit errors, PAM4 symbol errors, FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group based on the error detection results of the error detection unit 3b.

The display control means 7d controls the display of a setting screen for various compliance tests, a capture screen using data (including MSB data and LSB data) of the PAM4 signal from the object to be measured W stored in the memory unit 5, an FEC measurement screen 11 including various error results based on the count results of the error count means 7c, a list display screen 15 of various error results, etc., on the display screen of the display unit 6.

Here, we will explain the FEC measurement screen 11 and list display screen 15, which are displayed and controlled by the display control means 7d. Figure 4 shows an example of the FEC measurement screen 11 when the PCIe6 FEC Symbol shortcut is selected, in which FEC symbol errors within one Flit in an area divided by the Flit length defined in the PCIe Gen6 standard and FEC symbol errors for each ECC Group are counted and displayed in a list.

In the FEC measurement screen 11 in FIG. 4, "FEC Symbol Error Threshold in One ECC Group (Uncorrectable Flit Threshold): n" is the threshold for FEC symbol errors that occur in one ECC Group in one Flit. The threshold n is set by selecting "Equal sign with equal sign" from the pull-down menu box 12 and entering a number in the number input box 13. In the example in FIG. 4, the threshold n is set to n≧2.

"Consecutive FEC Symbol Error Threshold: m" is the threshold for consecutive FEC symbol errors. As with threshold n, threshold m is set by selecting "equal inequality" from pull-down menu box 12 and entering a number in number input box 13. In the example of FIG. 4, threshold m is set to m≧4.

"Consecutive Errored Flit Threshold: k" is the threshold for consecutive uncorrectable flit errors. Like threshold n and threshold m, threshold k is set by selecting the equal sign with inequality from the pull-down menu box 12 and entering a number in the number input box 13. In the example in Figure 4, threshold k is set to k ≥ 1.

At the bottom of the setting area for the thresholds n, m, and k mentioned above, there are a tab "Result PAM4" that can be selected to display the PAM4 results, a tab "Result FEC" that can be selected to display the FEC results, and a tab "FEC Error Distribution" that can be selected to display a graph of the FEC symbol error count against the total count number of Flit or ECC Group.

The FEC measurement screen 11 in Figure 4 shows the tab "Result FEC" selected, and below it, the Flit results 14 from the PCIe6 FEC measurement are displayed.

In "Uncorr. Flit" of the Flit result 14, "ER" displays the Error Rate calculated by Flit error count/total Flit count. "EC" in "Uncorr. Flit" counts and displays the number of Flits that became Uncorrectable (the number of Flits in which the FEC symbol error in one Flit exceeded the threshold n). "%EFI" in "Uncorr. Flit" displays the error-free period in percentage relative to the measurement time. For example, if the EI/EFI setting is 100 ms, the measurement time is 10 s, and EC is performed once, it will display 99%. "EI" in "Uncorr. Flit" displays the 1 ms/10 ms EI count for the 100 ms period. Note that the EI period is preset, and the Uncorr. When a flight occurs, the count increases by one.

In addition, "ER" of "FEC Symbol" in Flit result 14 displays the Error Rate calculated by FEC Symbol Error Count / (Total Bit Count / FEC Symbol Length). "EC" of "FEC Symbol" synchronizes at the PCIe Gen6 1b/1b boundary and counts and displays the number of FEC Symbol Errors in FEC Symbol units within the Flit range. "%EFI" of "FEC Symbol" displays the percentage of the error-free period relative to the measurement time. "EI" of "FEC Symbol" displays the 1ms/10ms EI count for a 100ms period. The EI period is preset and counts up by one when an FEC Symbol Error occurs.

In addition, the "ER" of "Bit" in the Flit result 14 displays the Total Bit Error Rate based on the number of bits in the Flit and the number of Bit Errors. The "EC" of "Bit" displays the Total Bit Error Count based on the number of bits in the Flit.

Next, FIG. 5 shows an example of a list display screen 15 of error count results. The list display screen 15 displays a list of Uncorrectable. Flit, FEC Symbol, and Bit results within Flit.

Specifically, in the list display screen 15 of FIG. 5, the "MSB+LSB:ER" of "Uncorr. Flit" in the upper display area 15a displays the Uncorrectable. Flit Error Rate calculated by Errored Flit Count/Number of Flits Count (only the results within a Flit based on the Flit error count in the Scramble area). The "MSB+LSB:EC" of "Uncorr. Flit" counts and displays the number of Flits in which the number of FEC Symbol Errors exceeded the threshold n within the Flit length assigned to one lane.

In addition, "MSB+LSB:ER" of "FEC Symbol" displays the FEC Symbol Error Rate calculated by FEC Symbol Error Count/(Bit Count in Flit/FEC Symbol Length) (only the results within Flit based on Flit error count in the scramble area). "MSB+LSB:EC" of "FEC Symbol" synchronizes with the PCIe Gen6 1b/1b boundary and displays the number of FEC Symbol Errors in FEC Symbol units within the Flit range.

In addition, in "Bit," the error rate and error count value of "MSB," the error rate and error count value of "LSB," and the error rate and error count value of "MSB + LSB" are displayed for each of "Total," "INS," and "OMI," based on the results in Flit.

In the list display screen 15 of FIG. 5, the middle display area 15b counts and displays the number of Flits in which the number of FEC Symbol Errors is N (0, 1, 2, 3, 4, 5, 6, 7, Over 8).

"ECC Group Count" counts and displays the FEC Symbol Error distribution by ECC Group within the Flit.

"ECC Group Rate" displays the Error Rate count from the FEC Symbol Error distribution for each ECC Group in a Flit. The ER for each distribution = FEC Symbol EC for each distribution / Flit count.

"Flit Count" counts and displays the distribution of FEC Symbol Errors within a Flit.

"Flit Rate" counts and displays the Error Rate from the FEC Symbol Error distribution within a Flit. ER for each distribution = FEC Symbol EC for each distribution / Flit count.

In the list display screen 15 of FIG. 5, in the "Consecutive Error" in the lower display area 15c, the number of consecutive occurrences of Errored Flits exceeding the threshold k is displayed as the Consecutive Flit Error Count in the "EC" of "Flit".

In addition, the Consecutive Flit Error Rate calculated by the Consecutive Flit Error Count/flight count is displayed in the "ER" field under "Flit."

In addition, the number of consecutive FEC Symbol Errors in Flit that exceed the threshold m is counted and displayed in the "EC" of "FEC Symbol" as the Consecutive FEC Symbol Error Count.

The Consecutive FEC Symbol Error Rate calculated by Consecutive FEC Symbol Error Count / (Bit Count in Flit / FEC Symbol Length) is displayed in "ER" of "FEC Symbol".

Next, FIG. 6 shows an example of the FEC measurement screen 11 when the number of Flits in which an FEC symbol error occurred within one Flit is tallied by the number of FEC symbol errors and displayed in a bar graph.

The FEC measurement screen 11 in Figure 6 shows the tab "FEC Error Distribution" selected. When "Flit" is selected from the pull-down menu box 16 in the upper right corner, the number of FEC Symbol Errors that occurred in the flit is counted and the frequency of occurrence is displayed in a bar graph.

To explain further, on the FEC measurement screen 11 in Figure 6, the vertical axis of the bar graph indicates the frequency of occurrence of the corresponding FEC symbol error count, and the number of Flits in which an FEC symbol error occurred is tallied by the number of FEC symbol errors and the frequency of occurrence is displayed in a bar graph.

In this case, the setting item FEC Symbol Error Threshold in One ECC Group: counts up to threshold n, and anything exceeding threshold n is counted as Uncorr. Flit. For example, if threshold n is 4 or greater, counts are made up to 0-3, and anything above 4 is counted as Uncorr. Flit.

Then, the color of the bar graph is changed according to the threshold value n to distinguish between them. Specifically, green: when it is not Uncorrectable: green, orange: when it is sometimes not Uncorrectable: orange, when it is always Uncorrectable: red, and Uncorrectable graph: dark red. In the example of Figure 6, 0 and 1 shown with an upward slanting line on the horizontal axis are displayed in green, 2 and 3 shown with a downward slanting line are displayed in orange, 4, 5, 6, 7, and Over 8 shown with a mesh are displayed in red, and Uncorr. shown with black fill is displayed in dark red.

Next, Figure 7 shows an example of the FEC measurement screen 11 when the FEC symbol errors that occur within one flight are recounted into the number of errors for each ECC Group and displayed in a bar graph.

When "ECC Group" is selected from the pull-down menu box 16 in the upper right corner of the "FEC Error Distribution" tab on the FEC measurement screen 11 in Figure 7, the FEC symbol errors that occurred in the Flit are counted again as the number of FEC symbol errors for each ECC Group, and the occurrence frequency is displayed in a bar graph.

To explain further, on the FEC measurement screen 11 in Figure 7, the vertical axis of the bar graph indicates the frequency of occurrence of the corresponding FEC symbol error count, and the number of Flits in which an FEC symbol error occurred is tallied by the number of FEC symbol errors and the frequency of occurrence is displayed in a bar graph.

In this case, the setting item FEC Symbol Error Threshold in One ECC Group: counts up to threshold n, and anything that exceeds threshold n is counted as Uncorr. Flit. For example, if threshold n is 2 or greater, counts are made up to 0-1, and anything above 2 is counted as Uncorr. Flit.

Then, the color of the bar graph is changed according to the threshold value n to distinguish between them. Specifically, green: if it is not Uncorrectable, green; if it is always Uncorrectable, red; Uncorrectable graph: dark red. In the example of Figure 7, 0 and 1, indicated by diagonal lines slanting upwards to the right on the horizontal axis, are displayed in green; 2, 3, 4, 5, 6, 7, and Over 8, indicated by a crosshatch, are displayed in red; and Uncorr., indicated by black, is displayed in dark red.

In the FEC measurement screen 11 in Figures 6 and 7, "0" on the horizontal axis indicates the number of flits with no FEC symbol error, "1" indicates the number of flits with 1 FEC symbol error, "2" indicates the number of flits with 2 FEC symbol errors, "3" indicates the number of flits with 3 FEC symbol errors, "4" indicates the number of flits with 4 FEC symbol errors, "5" indicates the number of flits with 5 FEC symbol errors, "6" indicates the number of flits with 6 FEC symbol errors, "7" indicates the number of flits with 7 FEC symbol errors, "Uncorr." indicates the number of flits that cannot be corrected, and "Over8" indicates the number of flits with 8 or more FEC symbol errors.

In addition, on the FEC measurement screen 11 in FIG. 6 and FIG. 7, "Save" in the upper left corner of "FEC Error Distribution" is a button for saving the measured FEC Error Distribution results in a specified file format (for example, csv file format). Note that on the FEC measurement screen 11 in FIG. 6 and FIG. 7, a pie chart can also be displayed instead of a bar graph.

Next, the error count processing operation of the error rate measurement device 1 configured as above will be described with reference to the flowchart in FIG. 8. Note that in this error count processing operation, it is assumed that the device under test W has transitioned to a signal return state due to link training. It is also assumed that the operation unit 4 has set conditions for generating a PAM4 signal to be transmitted to the device under test W, a threshold for determining a Flit error, and various settings required for the error count operation.

First, a PAM4 signal based on any one of the bit string data of PRBS, Flit, MCP, or CP is generated from the pattern generator 2 and transmitted to the object to be measured W (ST1).

Then, the PAM4 signal that is returned from the object to be measured W in association with the transmission of the PAM4 signal from the pattern generator 2 to the object to be measured W is received by the signal receiving unit 3a of the error detector 3, and the data of the PAM4 signal (including the MSB data and the LSB data) is stored in the memory unit 5 (ST2). This PAM4 signal data is divided into the MSB data and the LSB data by the data dividing means 3aa as necessary.

Next, a reference pattern is generated by the reference pattern generating means 7a based on the PAM4 signal data from the object to be measured W stored in the memory unit 5 (ST3).

The mask pattern generating means 7b generates a mask pattern based on the mask length and mask pattern period set in the operation unit 4 (ST4).

Then, the error detection unit 3b detects the beginning of the PAM4 signal from the object W stored in the memory unit 5 (the beginning of the data within the Flit), masks the portion of the PAM4 signal from the object W corresponding to SKP and EIEOS (area outside the Flit that is not defined as an FEC Symbol) with a mask pattern, and compares the masked PAM4 signal with a reference pattern to detect various errors (bit errors, PAM4 symbol errors, FEC symbol errors, FEC symbol errors within one Flit, FEC symbol errors for each ECC Group) (ST5).

When detecting the beginning of the PAM4 signal, if the PAM4 signal generated by the pattern generator 2 is based on the bit string data of the PRBS, the beginning of one period of the PRBS pattern based on the setting of the operation unit 4 (PRBS stage number) is detected. Also, if the PAM4 signal generated by the pattern generator 2 is based on the bit string data of the Flit, the same pattern as the beginning of the Flit pattern based on the setting of the operation unit 4 (Flit length according to the number of lanes, EIEOS insertion period, SKP interval) is searched and detected from the input data. Furthermore, if the PAM4 signal generated by the pattern generator 2 is based on the bit string data of the MCP, the same pattern as the beginning of the MCP based on the setting of the operation unit 4 (selection of SRIS or Not SRIS, length and number of virtual Flits) is searched and detected from the input data. Also, if the PAM4 signal generated by the pattern generator 2 is based on the bit string data of the CP, the same pattern as the beginning of the CP based on the setting of the operation unit 4 (length and number of virtual Flits) is searched and detected from the input data.

Next, based on the error detection result of the error detection unit 3b, the error counting means 7c counts bit errors, PAM4 symbol errors, FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group (ST6).

Then, based on the counting result of the error counting means 7c, the display control means 7d displays a list (display format of Figures 4 and 5) or a bar graph (display format of Figures 5 and 6) of various errors (bit errors, PAM4 symbol errors, FEC symbol errors, FEC symbol errors within 1 Flit, FEC symbol errors for each ECC Group) (ST7).

In the above embodiment, the test signal (PAM4 signal) generated by the pattern generator 2 is transmitted to the object to be measured W when the object to be measured W is transitioned to the signal pattern return state by link training. However, the object to be measured W itself may have a function of transitioning to the signal return state without link training. Also, the pattern generator 2 may be omitted. In this case, the object to be measured W itself generates the test signal (PAM4 signal). Then, the test signal (PAM4 signal) generated by the object to be measured W is stored in the memory unit 5 of the error detector 3 as a reference pattern, and the error detector 3 compares the test signal (PAM4 signal) received from the object to be measured W with the reference pattern to execute the above-mentioned error count processing operation.

As described above, according to this embodiment, not only can the number of FEC symbol errors in one Flit and the number of FEC symbol errors for each ECC Group be shown to the user numerically, but the user can also easily recognize the frequency of occurrence, such as the ratio, in a diagram using a bar graph (histogram) or a pie chart. As a result, the distribution of FEC symbols that have caused errors and the number of errors within a PCIe Gen6 standard Flit can be easily confirmed, and the device under test developed for the PCIe Gen6 standard can be efficiently debugged.

The above describes the best mode for the error rate measurement device and error rate measurement method according to the present invention, but the present invention is not limited to the description and drawings of this mode. In other words, it goes without saying that all other modes, examples, and operational techniques that are made by those skilled in the art based on this mode are included in the scope of the present invention.

REFERENCE SIGNS LIST 1 Error rate measuring device 2 Pattern generator 3 Error detector 3a Signal receiving section 3aa Data dividing means 3b Error detecting section 4 Operation section 5 Memory section 6 Display section 7 Control section 7a Reference pattern generating means 7b Mask pattern generating means 7c Error counting means 7d Display control means 7e Error search means 11 FEC measurement screen 12 Pull-down menu box 13 Numerical value input box 14 In-flit results 15 List display screen 15a Upper display area 15b Middle display area 15c Lower display area 16 Pull-down menu box W Object to be measured

Claims (6)

An error rate measurement device (1) for measuring whether a device under test (W) is capable of performing a forward error correction (FEC) operation,
an operation unit (4) for setting a threshold n for the number of FEC symbol errors occurring in one ECC Group in one Flit, a threshold m for the number of consecutive FEC symbol errors occurring, and a threshold k for the number of consecutive Flit errors occurring, as thresholds for determining a Flit error in a Flit defined in a high-speed serial bus standard;
A pattern generator (2) for generating a PAM4 signal to be transmitted to the device under test;
a memory unit (5) for storing data of a PAM4 signal that is returned from the device under test in association with the transmission of a PAM4 signal generated by the pattern generator;
an error detection unit (3b) that masks an area of the PAM4 signal from the device under test that is not defined as an FEC symbol, and compares the masked PAM4 signal with a reference pattern to detect an FEC symbol error, an FEC symbol error within one Flit, and an FEC symbol error for each ECC Group;
an error counting means (7c) for counting FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group based on an error detection result from the error detection means ;
a display control means (7d) for displaying the count result by the error count means on a list display screen (15) ;
The display control means displays, on the list display screen, an uncorrectable. Flit error rate, the number of Flits in which the number of FEC symbol errors within a Flit length allocated to one lane exceeds the threshold n, an FEC symbol error rate, and the number of FEC symbol errors per FEC symbol within a Flit range,
Also, the number of Flits for each number of FEC symbol errors in the Flit, the distribution of FEC symbol errors in ECC Group units in the Flit and an error rate based on the distribution, and the distribution of FEC symbol errors in the Flit and an error rate based on the distribution are displayed on the list display screen.
Furthermore, the number of consecutive occurrences of Flit errors exceeding the threshold k and the error rate are displayed on the list display screen ,
Furthermore, the error rate measuring device is characterized in that the number of consecutive FEC symbol errors exceeding the threshold value m and the error rate are displayed on the list display screen . The display control means (7d) displays the frequency of occurrence of the number of FEC symbol errors in one Flit or the frequency of occurrence of the number of FEC symbol errors for each ECC Group counted by the error counting means (7c) ,
2. The error rate measuring device according to claim 1, wherein the frequency of occurrence of FEC symbol errors in one Flit is calculated by counting the number of Flits in which an FEC symbol error occurs for each FEC symbol error, and the frequency of occurrence is displayed in the form of a bar graph or a pie chart . a reference pattern generating means (7a) for generating a reference pattern based on data of a PAM4 signal from the object to be measured (W) stored in the storage unit (5);
When the pattern that is the basis of the PAM4 signal to be transmitted to the device under test is a Flit, a pattern head signal that is generated when a pattern identical to the head of the pattern of the Flit set in the operation unit (4) is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate a Flit that is a reference to be set in the operation unit, and the generated Flit is divided into a reference pattern of MSB and a reference pattern of LSB and outputted;
When the PAM4 signal generated by the pattern generator (2) is based on Flit bit string data, a pattern identical to the beginning of a Flit pattern based on a Flit length, an EIEOS insertion period, and an SKP interval corresponding to the number of lanes set by the operation unit is searched for from the input data, and the beginning of the PAM4 signal is detected;
When the pattern that is the basis of the PAM4 signal to be transmitted to the device under test is an MCP, a pattern head signal that is generated when a pattern identical to the head of the pattern of the MCP set by the operation unit is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate an MCP that is to be a reference that is set by the operation unit, and the generated MCP is divided into an MSB reference pattern and an LSB reference pattern and outputted;
When the PAM4 signal generated by the pattern generator is based on the bit string data of the MCP, a pattern identical to the head of the MCP based on the selection of SRIS or Not SRIS set by the operation unit and the length and number of virtual Flits is searched for from the input data, thereby detecting the head of the PAM4 signal;
When a pattern that is the basis of the PAM4 signal to be transmitted to the device under test is a CP, a pattern head signal that is generated when a pattern identical to the head of the pattern of the CP set by the operation unit is searched for from the PAM4 signal stored in the storage unit is used as a trigger to generate a CP that is to be a reference that is set by the operation unit, and the generated CP is divided into an MSB reference pattern and an LSB reference pattern and outputted;
3. The error rate measuring device according to claim 1, wherein when the PAM4 signal generated by the pattern generator is based on the bit string data of the CP, the device detects the beginning of the PAM4 signal by searching the input data for a pattern identical to the beginning of the CP based on the length and number of virtual Flits set by the operation unit. An error rate measurement method for measuring whether a device under test (W) is capable of performing a forward error correction (FEC) operation, comprising:
a step of setting, by an operation unit (4), a threshold n for the number of FEC symbol errors occurring in one ECC Group in one Flit, a threshold m for the number of consecutive FEC symbol errors occurring, and a threshold k for the number of consecutive Flit errors occurring, as thresholds for determining a Flit error in a Flit defined in a high-speed serial bus standard;
A step of generating a PAM4 signal to be transmitted to the device under test by a pattern generator (2);
storing data of a PAM4 signal that is returned from the device under test in association with the transmission of the PAM4 signal generated by the pattern generator in a storage unit (5);
a step of masking an area of the PAM4 signal from the device under test that is not defined as an FEC symbol, and detecting an FEC symbol error, an FEC symbol error within one Flit, and an FEC symbol error for each ECC Group by an error detection unit (3b) by comparing the masked PAM4 signal with a reference pattern;
counting FEC symbol errors, FEC symbol errors within one Flit, and FEC symbol errors for each ECC Group by an error counting means (7c) based on the error detection result of the error detection section ;
a step of displaying the count result by the error count means on a list display screen (15) by a display control means (7d) ;
displaying, on the list display screen, an uncorrectable. Flit error rate, the number of Flits in which the number of FEC symbol errors in a Flit length allocated to one lane exceeds the threshold n, an FEC symbol error rate, and the number of FEC symbol errors in FEC symbol units within a Flit range, by the display control means;
displaying , on the list display screen by the display control means, the number of Flits for each number of FEC symbol errors in the Flits, a distribution of FEC symbol errors in units of ECC Groups in the Flits and an error rate based on the distribution , and a distribution of FEC symbol errors in the Flits and an error rate based on the distribution;
displaying, on the list display screen, the number of consecutive occurrences of Flit errors exceeding the threshold k and an error rate by the display control means;
and displaying, on the list display screen, the number of consecutive FEC symbol errors exceeding the threshold m and the error rate using the display control means . displaying, by the display control means (7d) , the frequency of occurrence of the number of FEC symbol errors in one Flit or the frequency of occurrence of the number of FEC symbol errors for each ECC Group counted by the error count means (7c) ;
and displaying the frequency of occurrence of the number of FEC symbol errors in one Flit in a bar graph or a pie chart by tallying the number of Flits in which an FEC symbol error occurred for each number of FEC symbol errors as the frequency of occurrence of the number of FEC symbol errors in one Flit . generating a reference pattern by a reference pattern generating means (7a) based on the data of the PAM4 signal from the object to be measured (W) stored in the storage unit (5);
When a pattern that is the basis of the PAM4 signal to be transmitted to the device under test is a Flit, a pattern head signal generated when a pattern identical to the head of the pattern of the Flit set by the operation unit (4) is searched from the PAM4 signal stored in the storage unit is used as a trigger to generate a Flit that is a reference to be set by the operation unit, and the generated Flit is divided into a reference pattern of an MSB and a reference pattern of an LSB and outputted;
When the PAM4 signal generated by the pattern generator (2) is based on the bit string data of Flit, a step of searching the input data for a pattern identical to the beginning of a Flit pattern based on a Flit length, an EIEOS insertion period, and an SKP interval according to the number of lanes set by the operation unit, thereby detecting the beginning of the PAM4 signal;
a step of generating an MCP to be a reference set by the operation unit, using a pattern head signal generated when a pattern identical to the head of the pattern of the MCP set by the operation unit is searched for in the PAM4 signal stored in the storage unit as a trigger when the pattern is an MCP, and dividing the generated MCP into an MSB reference pattern and an LSB reference pattern and outputting the resulting MCP;
When the PAM4 signal generated by the pattern generator is based on the bit string data of the MCP, a step of searching the input data for a pattern identical to the head of the MCP based on the selection of SRIS or Not SRIS set by the operation unit and the length and number of virtual Flits, thereby detecting the head of the PAM4 signal;
a step of generating a CP to be set as a reference in the operation unit, using a pattern head signal generated when a pattern identical to the head of the pattern of the CP set in the operation unit is searched for in the PAM4 signal stored in the storage unit as a trigger when the pattern is a CP, and dividing the generated CP into an MSB reference pattern and an LSB reference pattern and outputting them;
The error rate measuring method according to claim 4 or 5, further comprising: a step of: searching for a pattern identical to the beginning of a CP based on the length and number of virtual Flits set by the operation unit from among input data, when the PAM4 signal generated by the pattern generator is based on bit string data of a CP, thereby detecting the beginning of the PAM4 signal.

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