JP7579377B2 - Error rate measurement device and error rate measurement method - Google Patents

Description

The present invention relates to an error rate measurement device and an error rate measurement method that measure errors in a PAM4 signal based on MCP bit string data transmitted by a device under test that transitions to a loopback state during link training and is looped back from the device under test in the loopback state.

Error rate measuring devices have been known for some time as devices that measure the bit error rate (BER) by transmitting a test signal of a known pattern containing fixed data to the device under test, and comparing the signal under test received by the device under test in response to the transmission of the test signal with a reference signal on a bit-by-bit basis.

Also, as disclosed in the following Patent Document 1, an error rate measurement device is known that has an RS-FEC measurement function that complies with the IEEE 802.3 standard. This error rate measurement device tallies the number of FEC symbol errors for each codeword length in an area separated by the codeword length, and obtains and displays each error count number and error rate.

Incidentally, physical layer evaluation of PCI Express 5.0 has been performed by performing link training with the LTSSM (Link Training and Status State Machine) of the DUT to put the DUT in a loopback state (signal loopback state) and using the MCP (Modified Compliance Pattern). The performance index at this time is BER< ^10-12 .

JP 2021-136651 A

FEC was introduced in PCI Express 6.0. However, although MCP is also defined in PCI Express 6.0, it is not subject to FEC guard. The MCP prepared for performance indicators is a different pattern from FEC-guarded Flit, and does not have error correction by FEC. For this reason, there was a problem that it was difficult to grasp the Flit error situation when the Flit pattern was actually transmitted by simply evaluating the bit error situation using an MCP with a pattern length and SKP OS (SKP Ordered Sets) interval different from Flit.

Therefore, the present invention has been made in consideration of the above problems, and aims to provide an error rate measurement device and an error rate measurement method that use an MCP to simultaneously measure not only bit errors but also Flit errors.

In order to achieve the above object, the error rate measuring device according to the present invention includes an operation unit 2 for setting an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length corresponding to the number of lanes defined in the high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS;
a pattern generator 3 for generating a PAM4 signal based on the bit string data of the MCP and transmitting the PAM4 signal to a device under test W in a loopback state;
an error detector 4 including: an error detection unit 44 that receives a PAM4 signal based on the bit string data of the MCP that is looped back and transmitted from the device under test in the loopback state, divides an MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit length, and detects and counts errors in the part corresponding to the Flit with the part corresponding to the EIEOS and the SKP OS excluded from measurement; a Flit error detection unit 45 that detects FEC symbol errors for each ECC Group in the part corresponding to the Flit, counts the number of FEC symbol errors, and determines that an error in which the number of FEC symbol errors exceeds the threshold is a Flit error; and a synchronization state management unit 46 that instructs reacquisition of the pattern head of the MCP when the amount of errors in the part corresponding to the Flit detected by the error detection unit exceeds a synchronization condition threshold;
The present invention is characterized by comprising:

The error rate measurement device according to claim 2 of the present invention is the error rate measurement device according to claim 1,
When the portion corresponding to the SKP OS is excluded from the measurement target, the operation unit is used to select and set whether to mask bit errors in the corresponding portion or to filter out and remove the SKP OS itself.

The error rate measurement device according to claim 3 of the present invention is the error rate measurement device according to claim 1,
The present invention is characterized in that, for the portion corresponding to the Flit, the operation unit is used to selectively set whether coding of the high-speed bus standard is not cancelled or coding of the high-speed bus standard is cancelled.

The error rate measurement device according to claim 4 of the present invention is any one of the error rate measurement devices according to claims 1 to 3,
The present invention is characterized in that link training is performed with the device under test, and the LTSSM of the device under test is transitioned to a loopback state.

The error rate measuring device according to claim 5 of the present invention comprises an operation unit 2 for setting an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length corresponding to the number of lanes defined in the high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS;
a pattern generator 3 for generating a PAM4 signal based on the bit string data of the MCP and transmitting the PAM4 signal to a device under test W in a loopback state;
an error detector 4 including: an error detection unit 44 that receives a PAM4 signal based on the bit string data of the MCP that is looped back and transmitted from the device under test in the loopback state, divides an MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit length, and detects and counts errors in the part corresponding to the Flit with the part corresponding to the EIEOS and the SKP OS excluded from measurement; a Flit error detection unit 45 that detects FEC symbol errors for each ECC Group in the part corresponding to the Flit, counts the number of FEC symbol errors, and determines that an error in which the number of FEC symbol errors exceeds the threshold is a Flit error; and a synchronization state management unit 46 that instructs reacquisition of the pattern head of the MCP when the amount of errors in the part corresponding to the Flit detected by the error detection unit exceeds a synchronization condition threshold;
Equipped with
When the portion corresponding to the SKP OS is excluded from the measurement target, the operation unit is used to select and set whether to mask the bit error in the corresponding portion or to filter and remove the SKP OS itself;
Selecting and setting, by the operation unit, whether the portion corresponding to the Flit is coded without de-coding the high-speed bus standard or coded with de-coding the high-speed bus standard;
The present invention is characterized in that link training is performed with the device under test, and the LTSSM of the device under test is transitioned to a loopback state.

The error rate measurement method according to claim 6 of the present invention includes the steps of: setting, by an operation unit 2, an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length corresponding to the number of lanes defined in the high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS;
generating a PAM4 signal based on the bit string data of the MCP using a pattern generator 3 and transmitting the signal to the device under test W in a loopback state;
receiving a PAM4 signal based on the bit string data of the MCP transmitted by the DUT in the loopback state by an error detection unit 44 of the error detector 4, dividing the MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit length, detecting and counting errors in the part corresponding to the Flit while excluding the part corresponding to the EIEOS and the SKP OS from the measurement target;
a step of detecting an FEC symbol error for each ECC Group in the portion corresponding to the Flit by a Flit error detection unit 45 of the error detector, counting the number of FEC symbol errors, and determining that an FEC symbol error count that exceeds the threshold is a Flit error;
The method is characterized in that it includes a step of instructing a synchronization state management unit 46 of the error detector to re-acquire the head of the pattern of the MCP when the amount of errors in the part corresponding to the Flit detected by the error detection unit exceeds a synchronization condition threshold value.

The error rate measurement method according to claim 7 of the present invention is the error rate measurement method according to claim 6,
The method further includes a step of selecting and setting, in the operation unit, whether to mask bit errors in the corresponding portion or to filter and remove the SKP OS itself when the portion corresponding to the SKP OS is excluded from the measurement target.

The error rate measurement method according to claim 8 of the present invention is the error rate measurement method according to claim 6,
The method includes a step of selecting and setting, by the operation unit, whether the portion corresponding to the Flit is to be coded without de-coding the high-speed bus standard or coded with de-coding the high-speed bus standard.

The error rate measurement method according to claim 9 of the present invention is the error rate measurement method according to any one of claims 6 to 8,
The method further comprises the step of performing link training with the device under test and transitioning the LTSSM of the device under test to a loopback state.

The error rate measurement method according to claim 10 of the present invention includes the steps of: setting, by an operation unit 2, an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length corresponding to the number of lanes defined in the high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS;
generating a PAM4 signal based on the bit string data of the MCP using a pattern generator 3 and transmitting the signal to the device under test W in a loopback state;
receiving a PAM4 signal based on the bit string data of the MCP transmitted by the DUT in the loopback state by an error detection unit 44 of the error detector 4, dividing the MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit length, detecting and counting errors in the part corresponding to the Flit while excluding the part corresponding to the EIEOS and the SKP OS from the measurement target;
a step of detecting an FEC symbol error for each ECC Group in the portion corresponding to the Flit by a Flit error detection unit 45 of the error detector, counting the number of FEC symbol errors, and determining that an FEC symbol error count that exceeds the threshold is a Flit error;
When an amount of errors in the portion corresponding to the Flit detected by the error detector exceeds a synchronization condition threshold, instructing the MCP to reacquire a pattern head;
A step of selecting and setting, in the operation unit, whether to mask bit errors in the corresponding portion or to filter and remove the SKP OS itself when the portion corresponding to the SKP OS is excluded from the measurement target;
a step of selecting and setting, by the operation unit, whether the portion corresponding to the Flit is coded without de-coding the high-speed bus standard or coded with de-coding the high-speed bus standard;
and performing link training with the device under test and transitioning the LTSSM of the device under test to a loopback state.

According to the present invention, after the DUT is transitioned to a loopback state by link training, it is possible to distinguish between Flit and other conditions in a pseudo manner using the MCP (Modified Compliance Pattern) used in the physical layer evaluation of PCIe Gen6, and to estimate whether a Flit error will occur from the FEC symbol error status in the Flit area. In addition, even in an environment where patterns guarded by FEC and patterns not guarded by FEC are mixed, it is possible to identify patterns guarded by FEC and determine whether they will become uncorrectable.

1 is a block diagram showing a schematic configuration of an error rate measurement device according to the present invention; FIG. 2 is a block diagram showing the internal configuration of an error detector appearing in FIG. 1 . FIG. 2 is an explanatory diagram of Flit defined in the PCI Express 6.0 standard. 11 is a diagram illustrating an example of the number of errors for each ECC Group in a Flit, and the number of Flits for each number of FEC symbol errors in a Flit. FIG. 11 is a schematic explanatory diagram of an error measurement method using the error rate measurement device according to the present invention when a Not SRIS pattern is used. FIG. 1 is a schematic diagram illustrating an error measurement method using an error rate measurement device according to the present invention when an SRIS pattern is used. FIG. 4 is a diagram showing an example of a timing chart for detecting various errors in the error rate measurement device according to the present invention. 3 is a block diagram showing an internal configuration of a Flit error detection unit in FIG. 2 . FIG. 13 is a diagram showing an example of a timing chart of FEC symbol error detection for each ECC Group in the error rate measurement device according to the present invention. 4 is a flowchart of a processing operation of the error rate measurement device according to the present invention.

The following describes in detail the embodiment of the present invention with reference to the attached drawings.

As shown in FIG. 1, the error rate measurement device 1 of this embodiment has a function of simultaneously measuring not only bit errors but also Flit errors (whether the FEC of Flit becomes uncorrectable) using an MCP in measuring physical layer errors of the PCI Express 6.0 (hereinafter referred to as PCIe Gen6) standard, which is a high-speed bus standard, with a device under test (DUT) W that transitions to a loopback state during link training, and is roughly configured with an operation unit 2, a pattern generator 3, and an error detector 4.

In the PCIe Gen6 standard that is the subject of this embodiment, the signal handled is a PAM4 signal. Also, although the concept of Flit was defined in PCIe Gen6, the present invention can also be applied to future PCI Express standards that use a similar concept of Flit. Furthermore, although this embodiment will be described using PCIe Gen6 as an example, the present invention can also be applied when measuring Flit errors in other high-speed bus standards such as USB.

[About Flit]
First, Flit defined in the PCIe Gen6 standard handled by the error rate measurement device 1 of this embodiment will be described with reference to Figures 3 and 4. Flit is a data format that is transmitted when the state of the LTSSM (Link Training and Status State Machine) is L0 in the PCIe Gen6 standard, and has an error correction function by FEC.

As shown in Figure 3, one Flit is interleaved with three ECC Groups (ECC Group 0, ECC Group 1, ECC Group 2). One ECC Group is separated by one FEC symbol (4 PAM 4 symbols = 8 bits).

The conditions for a Flit to become uncorrectable can be summarized as follows: if two FEC symbol errors occur in the same ECC Group within one Flit, the Flit becomes uncorrectable.

Further explanation will be given using Figure 4. Figure 4 shows an example of the number of errors for each ECC Group in a Flit, the number of uncorrectables (2 or more), and the number of Flits for each number of FEC symbol errors in a Flit (0 to 7, 8 or more). Note that in Figure 4, the parts indicated with diagonal lines slanting downwards to the right indicate parts that are uncorrectable, and the parts indicated with diagonal lines slanting upwards to the right indicate parts that may or may not be uncorrectable.

For example, the case where the FEC symbol error threshold is n≧2 will be explained with reference to Figure 4. In A (number of Flits: 3) surrounded by the dotted line in Figure 4, two FEC symbol errors have occurred within the Flit, but since the number of errors in each of the different ECC Groups (in this case, ECC Group 0 and ECC Group 1) is one each, it does not become Uncorrectable.

In contrast, in B (number of Flits: 5) enclosed by the dotted line in Figure 4, not only are there four FEC symbol errors in the Flit, but when looking at the number of errors per ECC Group, there are two errors in one of the ECC Groups (ECC Group 0 in this case), so it is uncorrectable.

Furthermore, in C (number of Flits: 9) surrounded by the dotted line in Figure 4, two FEC symbol errors occur within the Flit, and the number of errors in the same ECC Group (ECC Group 0 in this case) is two, so it becomes Uncorrectable.

As such, PCIe Gen6 introduces a new Flit mode, which has a length of 256 FEC symbols (1 FEC symbol = 8 bits) and has an error correction function using FEC. In addition, since Gen6 Flit is 1b/1b encoded, 1 FEC symbol = 1b/1b symbol. Flit's FEC is 3-way interleaved ECC, and each ECC Group can correct a single byte error (error in 1 FEC symbol).

In one Flit, errors in up to three FEC symbols can be corrected, and if errors cannot be corrected, it becomes a Flit error (ECC is uncorrectable). However, even if there are three FEC symbol errors, they may be uncorrectable depending on the error location. For example, if there are errors in symbol 0 of ECC Group 0, symbol 1 of ECC Group 1, and symbol 2 of ECC Group 2, they can be corrected, but if there are errors in symbols 0, 3, and 6 of the same ECC Group 0, they cannot be corrected. This means that even with the same bit error rate, the number of Flit errors will differ depending on the location where the bit errors occur.

[Overview of the present invention]
5 and 6, the error rate measurement device 1 puts the device under test W into a loopback state by link training, and then transmits an MCP to the device under test W. At this time, the scrambled area (16 1b/1b symbols×256 blocks=32768 bits) of the received MCP is divided at regular intervals (pseudo-divided into Flit lengths (256 FEC symbols=2048 bits)), and errors (bit errors, PAM4 symbol errors, FEC symbol errors) in the parts corresponding to Flits and Flit errors are measured simultaneously. At this time, the pattern at the SKP OS (SKP Ordered Sets, hereinafter abbreviated as SKP: shown as "SKP" in the drawings) position is masked, and the pattern at the EIEOS (Electrical Idle Exit Ordered Set) position is further masked to exclude it from the measurement target, and errors (bit errors, PAM4 symbol errors, FEC symbol errors) are counted only in the portion corresponding to Flit. Furthermore, for the Flit portion, FEC symbol errors are counted for each ECC group, and an error in which the number of FEC symbol errors exceeds an FEC symbol error threshold is determined to be a Flit error.

When performing the above error measurement, there are two methods for excluding the part corresponding to SKP from the measurement target, which can be selected on the operation unit 2: a method for masking the bit errors in the relevant part, and a method for filtering out and removing the SKP itself. In addition, for the part corresponding to Flit, it is possible to select on the operation unit 2 whether to decode PCIe Gen6 without decoding PCIe Gen6 or to decode PCIe Gen6 with decoding, making it possible to check the occurrence of errors depending on whether coding is decoded or not. There are two types of MCP, the Not SRIS pattern and the SRIS pattern, but as shown in Figures 5 and 6, measurements can be performed with either pattern.

[Configuration of each part of the error rate measurement device]
The operation unit 2, which also functions as a setting means and a display means, is composed of a user interface such as an operation knob, various keys, switches, buttons, and soft keys on the display screen of the display means, which are provided on the main body of the error rate measurement device 1 in FIG. 1, and performs various settings, gives instructions, and displays measurement results in response to user operations.

The settings made by the operation unit 2 include MCP (including EIEOS, SKP), MCP pattern length, Flit length according to the number of lanes, mask pattern length for masking the part corresponding to SKP, mask pattern period corresponding to the SKP repetition period, threshold for determining Flit errors, mask pattern length for masking the part corresponding to EIEOS, EIEOS insertion period, MCP pattern start, and selection of SRIS or Not SRIS. In addition, the operation unit 2 allows the selection of either a method of masking bit errors in the relevant part or a method of filtering and removing the SKP itself as a method of excluding SKP from the measurement target, and allows the selection of either no PCIe Gen6 coding release or PCIe Gen6 coding release for the Flit part.

The pattern generator 3 generates an MCP error measurement pattern according to instructions from the operation unit 2, and as shown in FIG. 1, is configured with a first selection unit 11, a first sequence generation unit 12, a second sequence generation unit 13, a measurement pattern generation unit 14, a first encoder 15, a second encoder 16, a second selection unit 17, a bit division unit 18, and a PAM4 encoder 19.

The first selection unit 11 selects one of the transmission completion signals from the first sequence generation unit 12, the second sequence generation unit 13, or the measurement pattern generation unit 14 depending on the link speed, and outputs it to the LTSSM 36.

The first sequence generating unit 12 selectively generates training sequences (TSx OS) such as TS1, TS2, EIEOS, SKP used in PCIe Gen1-2 and training sequences (TSx OS) such as TS1, TS2, EIEOS, SKP used in PCIe Gen3-5.

The second sequence generator 13 generates training sequences (TSx OS) such as TS0, TS1, TS2, EIEOS, and SKP used in PCIe Gen6.

The measurement pattern generating unit 14 generates an MCP with one period of the MCP (including EIEOS and SKP) set in the operation unit 2 and a Flit length according to the number of lanes as the pattern that is the basis of the MCP error measurement pattern to be transmitted to the object to be measured W.

The first encoder 15 is composed of an 8b/10b encoder and a 128b/130b encoder. The 8b/10b encoder performs 8b/10b encoding, which is used in PCIe Gen1-2, on the training sequence generated by the first sequence generator 12. The 128b/130b encoder performs 128b/130b encoding, which is used in PCIe Gen3-5, on the training sequence generated by the first sequence generator 12.

The second encoder 16 performs 1b/1b encoding, which is used in PCIe Gen6, on the training sequence generated by the first sequence generator 12.

The second selection unit 17 selects the output data of one of the measurement pattern generation unit 14, the first encoder 15, or the second encoder 16 depending on the LTSSM state and Link Speed from the LTSSM 36.

The bit division unit 18 divides the input signal into most significant bit string data (hereinafter referred to as MSB data) and least significant bit string data (hereinafter referred to as LSB data) according to the link speed instructed by the LTSSM 36. Note that in PCIe Gen1-5, the same signal is output to the MSB data and LSB data so as to be NRZ, and in PCIe Gen6, the input signal is bit-interleaved and output into the MSB data and LSB data so as to be a PAM4 signal.

The PAM4 encoder 19 PAM4 encodes the MSB data and LSB data split by the bit splitter 18, and outputs the PAM4 encoded PAM4 signal as a Flit error measurement pattern.

When the MCP error measurement pattern (PAM4 signal) is transmitted from the pattern generator 3 to the object to be measured W, the error detector 4 detects an error by receiving the MCP error measurement pattern (PAM4 signal) that is looped back from the object to be measured W that has transitioned to a loopback state by link training. As shown in FIG. 2, the error detector 4 includes a PAM4 decoder 21, a bit synthesis unit 22, a first synchronization unit 23, a first SKP filter unit 24, a processing circuit 25, a first scramble analysis unit 26, a second synchronization unit 27, a second S It is configured with a KP filter unit 28, a precoding decoder 29, a first delay unit 30, a first selection unit 31, a Graycoding decoder 32, a second delay unit 33, a second selection unit 34, a second scramble analysis unit 35, an LTSSM 36, a third selection unit 37, a bit division unit 38, a synchronization pattern detection unit 39, a reference pattern generation unit 40, a symbol mask generation unit 41, a third delay unit 42, a fourth delay unit 43, an error detection unit 44, a Flit error detection unit 45, and a synchronization state management unit 46.

The PAM4 decoder 21 decodes and separates the PAM4 symbols of the MCP error measurement pattern (PAM4 signal) received from the object to be measured W into MSB data and LSB data.

The bit synthesis unit 22 synthesizes the MSB data and LSB data decoded by the PAM4 decoder 21 using a bit MUX and outputs the result to the first synchronization unit 23 and the second synchronization unit 27.

The first synchronization unit 23, the first SKP filter unit 24, the decoder 25, and the first scramble analysis unit 26 are circuits compatible with PCIe Gen1-5.

The first synchronization unit 23 is composed of an 8b/10b synchronization unit and a 128b/130b synchronization unit. The 8b/10b synchronization unit finds the EIEOS pattern of PCIe Gen1-2 from the data combined by the bit combination unit 22, achieves symbol synchronization at 10-bit intervals, and aligns the input data at symbol boundaries before outputting it. The 128b/130b synchronization unit finds the EIEOS pattern of PCIe Gen3-5 from the data combined by the bit combination unit 22, achieves symbol synchronization at 130-bit intervals, and aligns the input data at symbol boundaries before outputting it.

The first SKP filter unit 24 identifies the SKPs of PCIe Gen1-5 from the input bit string from the first synchronization unit 23 and removes the SKPs from the input bit string.

The processing circuit 25 is configured with an 8b/10b decoder, a 128b/130b decoder, a precoding decoder, a delay circuit, and a selection circuit. The 8b/10b decoder is a decoder that performs 8b/10b code conversion used in PCIe Gen1-2, and converts an input bit string of 10-bit symbols from which SKP has been removed by the first SKP filter unit 24 into 8-bit symbols. The 128b/130b decoder is a decoder that performs 128b/130b code conversion used in PCIe Gen3-5, and converts an input bit string of 130-bit symbols from which SKP has been removed by the first SKP filter unit 24 into 128-bit symbols. The precoding decoder is a decoder for removing the PCIe Gen5 precoding in the data decoded by the 128b/130b decoder. The delay circuit has the same delay as the processing time of the precoding decoder, and outputs data from the 128b/130b decoder in phase with the precoding decoder. The selection circuit selects the output of either the precoding decoder or the delay circuit according to instructions from the LTSSM36.

The first scramble analysis unit 26 is composed of a descrambler for removing the scrambling applied to the data from the processing circuit 25 in PCIe Gen1-2, and a descrambler for removing the scrambling applied to PCIe Gen3-5.

When the second synchronization unit 27 finds the PCIe Gen6 EIEOS pattern in the data combined by the bit combination unit 22, it performs symbol synchronization at 8-bit intervals and aligns the input data at the symbol boundary before outputting it.

The second SKP filter unit 28 identifies the PCIe Gen6 SKP from the input bit string from the second synchronization unit 27 and removes the SKP from the input bit string.

The precoding decoder 29 is a decoder for removing the PCIe Gen6 precoding from the input bit string from which the SKP has been removed by the second SKP filter unit 28.

The first delay unit 30 has a delay amount equal to the processing time of the precoding decoder 29, and outputs data from the second SKP filter unit 28 in phase with the precoding decoder 29.

The first selection unit 31 selects either the output of the precoding decoder 29 or the output of the first delay unit 30 according to instructions from the LTSSM 36.

The graycoding decoder 32 is a decoder for removing the PCIe Gen6 graycoding from the input bit string selected by the first selection unit 31.

The second delay unit 33 has a delay amount equal to the processing time of the Graycoding decoder 32, and outputs the input bit sequence selected by the first selection unit 31 in phase with the Graycoding decoder 32.

The second selection unit 34 selects either the output of the Graycoding decoder 32 or the second delay unit 33 according to instructions from the LTSSM 36.

The second scramble analysis unit 35 is a descrambler that removes the scrambling applied by PCIe Gen6 to the data selected by the second selection unit 34.

The LTSSM 36 is a state machine that analyzes T0 (output only from the second scramble analyzer 35), TS1 and TS2 training sequences, idle symbols, and idle Flit from the first scramble analyzer 26 and the second scramble analyzer 35, and advances the LTSSM value (internal state value) and Link Speed. The LTSSM 36 also generates a transmission REQ to the pattern generator and manages the transmission pattern by receiving a transmission ACK from the pattern transmitter.

The third selection unit 37 is a selector that selects the input raw data from the second synchronization unit 27, the data after SKP removal from the second SKP filter unit 28, and the data after decryption from the second scrambling analysis unit 35 after SKP removal, i.e., precoding, graycoding, or descrambled data, and is selected according to an instruction from the operation unit 2.

The bit division unit 38 divides the data selected and output by the third selection unit 37 into MSB data and LSB data using bit DMUX and outputs the data to the third delay unit 43.

The synchronization pattern detection unit 39 searches the data output by the third selection unit 37 for a pattern identical to the start of the MCP pattern set by the operation unit 2, and outputs a pattern start signal.

The reference pattern generation unit 40 uses the pattern start signal from the synchronization pattern detection unit 39 as a trigger to generate an MSB reference pattern and an LSB reference pattern as a reference MCP with one period of MCP (including EIEOS and SKP) according to the number of lanes set in the operation unit 2 and a Flit length according to the number of lanes.

The symbol mask generation unit 41 uses the pattern start signal from the synchronization pattern detection unit 39 as a trigger to generate a mask pattern in 1b/1b symbol units, which determines whether the input pattern, MSB data and LSB data, are to be distinguished from the Flit region or the SKP region and EIEOS region, based on the mask pattern length and mask pattern period set by the operation unit 2. The symbol mask generation unit 41 also outputs the mask pattern start signal to the error detection unit 44.

Note that the MCP of PCIe Gen6 is 1 FEC symbol = 8 bits, and since 1 FEC symbol is bit interleaved into MSB data and LSB data, it becomes a mask of 4PAM 4 symbol units. In this embodiment, 0: Flit area, 1: EIEOS area, SKP area. Mask patterns corresponding to Figures 5 and 6 are calculated in advance by the setting operation of the operation unit 2, and set in the internal memory of the symbol mask generation unit 41. Note that, if the third selection unit 37 selects data after SKP removal from the second SKP filter unit 28, or data after SKP removal from the second scramble analysis unit 35 and decoded PCIe Gen6, the data input to the error detection unit 44 has SKP removed, so a pattern without a mask for the SKP area is set (a mask pattern that distinguishes the EIEOS area is set).

The third delay unit 42 delays the MSB data and LSB data by a predetermined time and inputs them to the error detection unit 44 so that the MSB data, LSB data, pattern start signal, MSB reference pattern, LSB reference pattern, mask pattern, and mask pattern start signal input to the error detection unit 44 are in phase.

The fourth delay unit 43 delays the pattern start signal by a predetermined time and inputs it to the error detection unit 44 so that the MSB data, LSB data, pattern start signal, MSB reference pattern, LSB reference pattern, mask pattern, and mask pattern start signal input to the error detection unit 44 are in phase.

The error detection unit 44 uses the MSB data and LSB data from the MCP, the pattern start signal, the MSB reference pattern, the LSB reference pattern, the mask pattern, and the mask pattern start signal to detect and count bit errors (MSB bit errors, LSB bit errors), detect and count PAM4 symbol errors, and detect and count FEC symbol errors, and outputs the count results to the operation unit 2.

Here, FIG. 7 shows an example of a timing chart of various error detections by the error detection unit 44 of the error rate measurement device 1. FIG. 7 shows an example of a timing chart when a PAM4 signal based on the bit string data of the MCP is transmitted to the device under test W.

The following describes an example focusing on CLK positions 1 to 36 after input of the mask pattern start signal in Figure 7. In this case, each bit of the MSB (corresponding to MSB data by MCP) of the input MCP is compared with each corresponding bit of the MSB (corresponding to MSB reference pattern) of the reference MCP, and each bit of the LSB (corresponding to LSB data by MCP) of the input MCP is compared with each corresponding bit of the LSB (corresponding to LSB reference pattern) of the reference MCP.

As a result, the error results in the Flit area (mask signal is 0) are as follows: MSB bit error is "0", "1", "0", "1", "0", "1", "0", "1", "0", "0", "0", "1", "0", "1", "0", "1", "1", "1", "1", "1", "1", "1", LSB bit error is "1", "0", "0", "0", "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", PAM4 symbol error is "1", "1", "0", "1", "0", "1", "0", "1", "0", "1", "0", "0", "0", "0", "1", "0", "1", "0", "1", "1", "1", "1", "1", and FEC symbol error is "1", "1", "0", "1", "1".

In contrast, the error results for the EIEOS and SKP areas (mask signal is 0) are as follows: MSB bit error: "0", "1", "0", "1", "0", "1", "0", "1", "0", "0", "0", "0", "1", "1", "0", "0", LSB bit error: "1", "0", "1", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", "0", PAM4 symbol error: "1", "1", "1", "1", "0", "1", "0", "1", "0", "1", "0", "0", "0", "0", "1", "1", "0", "0", and FEC symbol error: "1", "1", "0", "1".

The error detection unit 44 aligns the mask pattern and mask pattern head signal input from the symbol mask generation unit 41 with the phase of the symbol-based error detection result, and outputs them to the Flit error detection unit 45 together with the symbol-based error detection result. Here, the pattern head signal from the fourth delay unit 43 may be used instead of the mask pattern head from the symbol mask generation unit 41.

The Flit error detection unit 45 uses a mask pattern to detect and count FEC symbol errors, dividing the area into the Flit region (mask signal is 0) and the EIEOS and SKP regions (mask signal is 1).

The Flit error detection unit 45 also detects and counts whether the number of FEC symbol errors in any ECC Group in one Flit length exceeds the FEC symbol error threshold set in the operation unit 2, and outputs the count result to the operation unit 2.

The detection results of the Flit error detection unit 45 can also be used to perform capture, etc.

The synchronization status management unit 46 notifies the operation unit 2 that synchronization has been established when the amount of errors in the portion corresponding to Flit falls below the synchronization condition threshold based on the error count information based on the error detection result of the error detection unit 44. Furthermore, the synchronization status management unit 46 notifies the operation unit 2 that synchronization has not been established when the amount of errors in the portion corresponding to Flit exceeds the synchronization condition threshold based on the error count information based on the error detection result of the error detection unit 44, and instructs the synchronization pattern detection unit 39 to reacquire the pattern head of the MCP (re-search for the pattern head). Note that the destination of the notification of synchronization establishment or synchronization not being established is not limited to the operation unit 2. For example, it may be an external terminal device, and the user can be notified by a message display or voice, etc.

Next, the internal configuration of the Flit error detection unit 45 in FIG. 2 will be explained with reference to FIG. 8.

As shown in FIG. 8, the Flit error detection unit 45 includes a Flit length timing counter 45a, an ECC Group timing counter 45b, a first ECC Group error detection unit 45c, a second ECC Group error detection unit 45d, a third ECC Group error detection unit 45e, a first ECC Group error count unit 45f, a second ECC Group error count unit 45g, a third ECC Group error count unit 45h, a comparison unit 45i, and a Flit error count unit 45j.

The Flit length timing counter 45a is triggered by the mask pattern start signal and counts the Flit length set by the operation unit 2. The counter counts up when the mask pattern is in the Flit area (mask signal is 0), and when it reaches the Flit length, it starts counting from 0 again.

The ECC Group timing counter 45b is a counter used to distinguish ECC Groups, and outputs the remainder when the Flit length timing counter value is divided by 3.

The first ECC Group error detection unit 45c detects an FEC symbol error when the counter value of the ECC Group timing counter 45b is 0 and the mask pattern is a Flit area (mask signal is 0).

The first ECC group error counting unit 45f counts the number of FEC symbol errors in one Flit-length interval detected by the first ECC group error detection unit 45c for each Flit-length interval.

The second ECC Group error detection unit 45d detects an FEC symbol error when the counter value of the ECC Group timing counter 45b is 1 and the mask pattern is a Flit area (mask signal is 0).

The second ECC group error counting unit 45g counts the number of FEC symbol errors in one Flit-length interval detected by the second ECC group error detection unit 45d for each Flit-length interval.

The third ECC group error detection unit 45e detects an FEC symbol error when the counter value of the ECC group timing counter 45b is 2 and the mask pattern is a Flit area (mask signal is 0).

The third ECC group error counting unit 45h counts the number of FEC symbol errors in one Flit-length interval detected by the third ECC group error detection unit 45e for each Flit-length interval.

The comparison unit 45i compares the number of FEC symbol errors in a 1 Flit-length section with the FEC symbol error threshold: n set in the operation unit 2, and outputs a Flit error detection signal to the Flit error count unit 45j when there is an ECC Group in which the number of FEC symbol errors in a 1 Flit-length section exceeds the FEC symbol error threshold: n.

The flip error count unit 45j counts the flip error detection signals from the comparison unit 45i and outputs the count result (flit error count value) to the operation unit 2.

Here, FIG. 9 shows an example of a timing chart of FEC symbol error detection for each ECC Group by the Flit error detection unit 45 of the error rate measurement device 1. In this example, it is assumed that the Flit length is set to 8 symbols, and the FEC symbol error threshold n is set to 3 symbols.

Focusing on the Flit area of CLK positions 0 to 15 in FIG. 9, the FEC symbol errors are "1", "1", "1", "1", "0", "0", "0", "1", "1", "1", "1", "0", "0", "1", and "0". The number of FEC symbol errors in ECC Group 0 for every 4 PAM4 symbols = 8 bits in the Flit area is "2", "3", the number of FEC symbol errors in ECC Group 1 is "1", "1", and the number of FEC symbol errors in ECC Group 2 is "1", "1". And the number of FEC symbol errors in ECC Group 0 in the Flit area of CLK positions 8 to 15 is "3", which is equal to or greater than the FEC symbol error threshold: n = "3", so Flit error 1 is output as the error result.

Note that CLK positions 16 to 20 and 37 to 41 in the SKP area in Figure 9 are masked by a mask pattern, so errors are not detected or counted.

Next, the processing operation when measuring errors in the PCIe Gen6 physical layer by the error rate measurement device 1 configured as above will be described with reference to the flowchart in FIG. 10. Note that when measuring errors in the PCIe Gen6 physical layer, it is assumed that the error rate measurement device 1 is operating normally up to PCIe Gen1-5, and that the device under test W has transitioned to a loopback state due to link training.

First, a PAM4 signal based on the MCP bit string data is generated from the pattern generator 3 and transmitted to the device under test W in the loopback state (ST1).

Then, the error detector 4 receives the PAM4 signal that is returned from the object to be measured W in association with the transmission of the PAM4 signal from the pattern generator 3 to the object to be measured W, and divides the received PAM4 signal into MSB data and LSB data by the PAM4 decoder 21 (ST2). The MSB data and LSB data divided by the PAM4 decoder 21 are bit-multiplexed by the bit synthesis unit 22 and output to the second synchronization unit 27.

Then, when the second synchronization unit 27 finds the EIEOS pattern of PCIe Gen6 from the data combined by the bit combination unit 22, it performs symbol synchronization at 8-bit intervals, aligns the input data at the symbol boundary, and outputs the data to the second SKP filter unit 28 and the third selection unit 37 (ST3).

Then, the synchronization pattern detection unit 39 searches for a pattern identical to the beginning of the MCP pattern set by the operation unit 2 from the data selected by the third selection unit 37 (either the data from the second synchronization unit 27, the data from the second SKP filter unit 28, or the data from the second scramble analysis unit 35) and outputs a pattern beginning signal (ST4).

Here, when the above-mentioned third selection unit 37 selects data, the following process is executed. First, the second SKP filter unit 28 removes the SKP from the input bit string from the second synchronization unit 27 and outputs it to the precoding decoder 29, the first delay unit 30, and the third selection unit 37. Next, the precoding decoder 29 cancels the PCIe Gen6 precoding from the input bit string from which the SKP has been removed and outputs it to the first selection unit 31. In addition, the first delay unit 30 outputs the input bit string from the second SKP filter unit 28 to the first selection unit 31 in phase with the precoding decoder 29. Then, in the first selection unit 31, the output of either the precoding decoder 29 or the first delay unit 30 is selected according to the instructions of the LTSSM 36, and is input to the Graycoding decoder 32 and the second delay unit 33.

Then, the Graycoding decoder 32 cancels the Graycoding of PCIe Gen6 for the input bit string selected by the first selection unit 31 and outputs it to the second selection unit 34. The second delay unit 33 also outputs the input bit string from the first selection unit 31 to the second selection unit 34 in phase with the Graycoding decoder 32. Then, in the second selection unit 34, the output of either the Graycoding decoder 32 or the second delay unit 33 is selected by the instruction of the LTSSM 36 and input to the second scrambling analysis unit 35. Furthermore, the second scrambling analysis unit 35 cancels the scrambling applied in PCIe Gen6 from the data selected by the second selection unit 34 and outputs it to the LTSSM 36 and the third selection unit 37.

Then, the reference pattern generation unit 40 generates an MSB reference pattern and an LSB reference pattern using the pattern start signal from the synchronization pattern detection unit 39 as a trigger (ST5).

The symbol mask generation unit 41 also generates an FEC symbol mask pattern based on the mask pattern length and mask pattern period set in the operation unit 2, using the pattern start signal from the synchronization pattern detection unit 39 as a trigger (ST6).

Then, the error detection unit 44 detects and counts bit errors, PAM4 symbol errors, and FEC symbol errors using the MSB data and LSB data from the MCP, the pattern start signal, the MSB reference pattern, the LSB reference pattern, the mask pattern, and the mask pattern start signal (ST7). The count result at this time is output to the operation unit 2. At that time, when the amount of errors in the part corresponding to the Flit detected by the error detection unit 44 falls below the synchronization condition threshold, the synchronization state management unit 46 notifies the operation unit 2 that synchronization has been established. On the other hand, when the amount of errors in the part corresponding to the Flit detected by the error detection unit 44 exceeds the synchronization condition threshold, the synchronization state management unit 46 notifies the operation unit 2 that synchronization has not been established, and instructs the synchronization pattern detection unit 39 to reacquire the pattern start of the MCP (re-search for the pattern start).

Furthermore, the Flit error detection unit 45 detects and counts whether the number of FEC symbol errors in any ECC Group in one Flit length exceeds the FEC symbol error threshold set in the operation unit 2 (ST8). The count result at this time is output to the operation unit 2.

In this way, according to this embodiment, after the DUT is transitioned to a loopback state by link training, a pseudo distinction is made between Flit and other conditions using the MCP (Modified Compliance Pattern) used in the physical layer evaluation of PCIe Gen6, and it becomes possible to estimate whether a Flit error will occur from the FEC symbol error situation in the Flit area. Moreover, since no error correction is performed, the circuit scale can be reduced.

In addition, even in an environment where patterns guarded by FEC and patterns not guarded by FEC are mixed, it is possible to identify patterns guarded by FEC and determine whether they are uncorrectable.

In addition, the data for error measurement can be selected from raw input data, data after SKP removal, and data after SKP removal and PCIe Gen6 code removal, making it possible to accurately grasp the occurrence of bit errors and Flit errors due to PCIe Gen6 coding.

In addition, even if the error rate is high and it is difficult to remove SKP, it is possible to exclude SKP from measurement by selecting a method to mask bit errors in the SKP portion.

The above describes the best mode for the error rate measurement device and error rate measurement method according to the present invention, but the present invention is not limited to the description and drawings of this mode. In other words, it goes without saying that all other modes, examples, and operational techniques that are made by those skilled in the art based on this mode are included in the scope of the present invention.

REFERENCE SIGNS LIST 1 Error rate measurement device 2 Operation unit 3 Pattern generator 4 Error detector 11 First selection unit 12 First sequence generation unit 13 Second sequence generation unit 14 Measurement pattern generation unit 15 First encoder 16 Second encoder 17 Second selection unit 18 Bit division unit 19 PAM4 encoder 21 PAM4 decoder 22 Bit synthesis unit 23 First synchronization unit 24 First SKP filter unit 25 Processing circuit 26 First scrambling analysis unit 27 Second synchronization unit 28 Second SKP filter unit 29 Precoding decoder 30 First delay unit 31 First selection unit 32 Graycoding decoder 33 Second delay unit 34 Second selection unit 35 Second scrambling analysis unit 36 LTSSM
37 Third selection section 38 Bit division section 39 Synchronization pattern detection section 40 Reference pattern generation section 41 Symbol mask generation section 42 Third delay section 43 Fourth delay section 44 Error detection section 45 Flit error detection section 45a Flit length timing counter 45b ECC Group timing counter 45c First ECC Group error detection section 45d Second ECC Group error detection section 45e Third ECC Group error detection section 45f First ECC Group error count section 45g Second ECC Group error count section 45h Third ECC Group error count section 45i Comparison section 45j Flit error count section 46 Synchronization state management section W Device under test

Claims (10)

An operation unit (2) for setting an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length according to the number of lanes defined in a high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS;
a pattern generator (3) that generates a PAM4 signal based on the bit string data of the MCP and transmits the PAM4 signal to a device under test (W) in a loopback state;
an error detector (4) including: an error detection unit (44) that receives a PAM4 signal based on the bit string data of the MCP that is looped back and transmitted from the device under test in the loopback state, artificially divides an MCP scrambled area of the received PAM4 signal into the length of the Flit length, and detects and counts errors in the part corresponding to the Flit while excluding the part corresponding to the EIEOS and the SKP OS from the measurement target; a Flit error detection unit (45) that detects FEC symbol errors for each ECC Group in the part corresponding to the Flit, counts the number of FEC symbol errors, and determines that an error in which the number of FEC symbol errors exceeds the threshold is a Flit error; and a synchronization state management unit (46) that instructs reacquisition of the pattern head of the MCP when the amount of errors in the part corresponding to the Flit detected by the error detection unit exceeds a synchronization condition threshold;
An error rate measuring device comprising: The error rate measurement device according to claim 1, characterized in that when the portion corresponding to the SKP OS is excluded from the measurement target, the operation unit is used to select whether to mask bit errors in the corresponding portion or to filter and remove the SKP OS itself. 2. The error rate measuring device according to claim 1, wherein the operation unit is used to selectively set whether the portion corresponding to the Flit is coded without decoding of the high-speed bus standard or coded with decoding of the high-speed bus standard. An error rate measurement device according to any one of claims 1 to 3, characterized in that link training is performed with the device under test, and the LTSSM of the device under test is transitioned to a loopback state. An operation unit (2) for setting an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length according to the number of lanes defined in a high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS;
a pattern generator (3) that generates a PAM4 signal based on the bit string data of the MCP and transmits the PAM4 signal to a device under test (W) in a loopback state;
an error detector (4) including: an error detection unit (44) that receives a PAM4 signal based on the bit string data of the MCP that is looped back and transmitted from the device under test in the loopback state, divides an MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit length, and detects and counts errors in the part corresponding to the Flit with the part corresponding to the EIEOS and the SKP OS excluded from measurement; a Flit error detection unit (45) that detects FEC symbol errors for each ECC Group in the part corresponding to the Flit, counts the number of FEC symbol errors, and determines that an error in which the number of FEC symbol errors exceeds the threshold is a Flit error; and a synchronization state management unit (46) that instructs reacquisition of the pattern head of the MCP when the amount of errors in the part corresponding to the Flit detected by the error detection unit exceeds a synchronization condition threshold;
Equipped with
When the portion corresponding to the SKP OS is excluded from the measurement target, the operation unit is used to select and set whether to mask the bit error in the corresponding portion or to filter and remove the SKP OS itself;
Selecting and setting, by the operation unit, whether the portion corresponding to the Flit is coded without de-coding the high-speed bus standard or coded with de-coding the high-speed bus standard;
2. An error rate measuring apparatus comprising: a device under test (DUT) for performing link training with the device under test; and causing an LTSSM of the device under test to transition to a loopback state. A step of setting an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length according to the number of lanes defined in a high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS on an operation unit (2);
a step of generating a PAM4 signal based on the bit string data of the MCP by a pattern generator (3) and transmitting the signal to a device under test (W) in a loopback state;
receiving a PAM4 signal based on the bit string data of the MCP transmitted by the device under test in the loopback state by an error detection unit (44) of an error detector (4), dividing the MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit, and detecting and counting errors in the part corresponding to the Flit while excluding the part corresponding to the EIEOS and the SKP OS from the measurement target;
a step of detecting an FEC symbol error for each ECC Group in the portion corresponding to the Flit by a Flit error detection unit (45) of the error detector, counting the number of FEC symbol errors, and determining that an FEC symbol error number that exceeds the threshold is a Flit error;
and when the amount of errors in the portion corresponding to the Flit detected by the error detector exceeds a synchronization condition threshold, instructing reacquisition of the beginning of the MCP pattern. The error rate measurement method according to claim 6, further comprising a step of selecting and setting in the operation unit whether to mask bit errors in the corresponding part or to filter and remove the SKP OS itself when the part corresponding to the SKP OS is excluded from the measurement target. 7. The error rate measuring method according to claim 6, further comprising a step of selecting and setting, by the operation unit, whether the portion corresponding to the Flit is coded without decoded according to the high-speed bus standard or coded with decoded according to the high-speed bus standard. The error rate measurement method according to any one of claims 6 to 8, characterized in that it includes a step of performing link training with the device under test and transitioning the LTSSM of the device under test to a loopback state. A step of setting an MCP including EIEOS and SKP OS, a pattern length of the MCP, a Flit length according to the number of lanes defined in a high-speed bus standard, a threshold value for determining a Flit error, a pattern head of the MCP, and a selection of SRIS or Not SRIS on an operation unit (2);
a step of generating a PAM4 signal based on the bit string data of the MCP by a pattern generator (3) and transmitting the signal to a device under test (W) in a loopback state;
receiving a PAM4 signal based on the bit string data of the MCP transmitted by the device under test in the loopback state by an error detection unit (44) of an error detector (4), dividing the MCP scrambled area of the received PAM4 signal into pseudo-partitions of the length of the Flit, and detecting and counting errors in the part corresponding to the Flit while excluding the part corresponding to the EIEOS and the SKP OS from the measurement target;
a step of detecting an FEC symbol error for each ECC Group in the portion corresponding to the Flit by a Flit error detection unit (45) of the error detector, counting the number of FEC symbol errors, and determining that an FEC symbol error number that exceeds the threshold is a Flit error;
When an amount of errors in the portion corresponding to the Flit detected by the error detector exceeds a synchronization condition threshold, instructing the MCP to reacquire a pattern head;
A step of selecting and setting, in the operation unit, whether to mask bit errors in the corresponding portion or to filter and remove the SKP OS itself when the portion corresponding to the SKP OS is excluded from the measurement target;
a step of selecting and setting, by the operation unit, whether the portion corresponding to the Flit is coded without de-coding the high-speed bus standard or coded with de-coding the high-speed bus standard;
performing link training with the device under test and transitioning an LTSSM of the device under test to a loopback state.

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