JP7591346B2 - Voltage Controlled Oscillator - Google Patents

Description

The present invention relates to a voltage-controlled oscillator circuit, and in particular to a voltage-controlled oscillator circuit that uses a transistor as a variable capacitance.

Voltage-controlled oscillator circuits that can vary the frequency of a local oscillation signal by voltage are widely used as a means for generating a local oscillation signal for wireless communication devices. In these voltage-controlled oscillator circuits, it is required to widen the range of variation of the output signal relative to the amount of variation in the control voltage. Therefore, technologies related to voltage-controlled oscillator circuits are disclosed in Patent Documents 1 and 2.

The voltage-controlled oscillator described in Patent Document 1 has a pair of variable capacitors whose capacitances are controlled by the same control voltage, a pair of inductors connected to the pair of variable capacitors, a constant current source that supplies current to the pair of inductors, and a switching means that switches the length of the portions through which the current flows in the pair of inductors.

Patent document 2 discloses an example of a variable capacitor used in a voltage-controlled oscillator, in which a MOS transistor is used as the variable capacitor.

JP 2003-229718 A JP 2004-56818 A

However, the variable capacitors described in Patent Documents 1 and 2 have a problem in that the range of capacitance change of the MOS transistor is limited, and the variable range of the oscillation frequency of the output signal is also limited.

One aspect of the voltage controlled oscillator circuit of the present invention includes a first transistor having a source connected to a first power supply, a second transistor having a source supplied with the first power supply, a drain connected to the gate of the first transistor, and a gate connected to the drain of the first transistor, an inductive impedance element having one terminal connected to the drain of the first transistor and the other terminal connected to the drain of the second transistor, and a common connection terminal supplied with a second power supply, a first variable capacitive impedance element having one terminal connected to the drain of the first transistor and the other terminal to which a frequency control voltage is applied, and a second variable capacitance impedance element having a first terminal connected to the drain of the first transistor and the other terminal to which a frequency control voltage is applied. and a second variable capacitive impedance element having one terminal connected to the drain of a capacitance transistor and the other terminal to which a frequency control voltage is applied, and the first variable capacitive impedance element and the second variable capacitive impedance element each have a capacitance transistor having a source connected to the second power supply, a resistor having one terminal connected to the gate of the capacitance transistor and the other terminal to which the frequency control voltage is applied, a first capacitor having one terminal which serves as the one terminal of the element and the other terminal which is connected to the gate of the capacitance transistor, and a second capacitor connected between the gate and drain of the capacitance transistor.

As a result, in one aspect of the voltage-controlled oscillator circuit of the present invention, the variable range of the capacitance value is determined based on the capacitance value of the second capacitor added to the parasitic capacitance of the capacitance transistor.

The voltage controlled oscillator circuit of the present invention can expand the frequency variable range.

1 is a circuit diagram of a voltage controlled oscillator circuit according to a first embodiment; 1 is a circuit diagram of a voltage controlled oscillator circuit illustrating a detailed circuit diagram of a variable capacitive impedance element according to a first embodiment. FIG. 1 is an equivalent circuit diagram of a variable capacitive impedance element according to a first embodiment; 4 is a graph illustrating a capacitance variable range of the variable capacitive impedance element according to the first embodiment; 4 is a graph illustrating a frequency variable range of the voltage controlled oscillator circuit according to the first embodiment; FIG. 11 is a circuit diagram of a voltage controlled oscillator circuit illustrating a detailed circuit diagram of a variable capacitive impedance element according to a second embodiment.

First embodiment
Hereinafter, the embodiments of the present invention will be described with reference to the drawings. First, FIG. 1 shows a block diagram of a voltage controlled oscillator circuit 1 according to the first embodiment. As shown in FIG. 1, the voltage controlled oscillator circuit 1 according to the first embodiment has a first transistor (e.g., transistor Tr1), a second transistor (e.g., transistor Tr2), resistors R1 and R2, a first variable capacitive impedance element (e.g., variable capacitive impedance element Cv1), a second variable capacitive impedance element (e.g., variable capacitive impedance element Cv2), and an inductive impedance element L1. In addition, the voltage controlled oscillator circuit 1 according to the first embodiment has buffer circuits BUF1 and BUF2 and a load resistor RL as circuits associated with the voltage controlled oscillator circuit 1. In addition, in the voltage controlled oscillator circuit 1, a power supply voltage VDD is supplied as a first power supply, and a ground voltage is supplied as a second power supply. In addition, a frequency control voltage VCTRL is provided to control the frequency of the output signal Vout of the voltage controlled oscillator circuit 1.

The source of the transistor Tr1 is supplied with the power supply voltage VDD, the gate is connected to the drain of the transistor Tr2, and the drain is connected to the gate of the transistor Tr2. The source of the transistor Tr2 is supplied with the power supply voltage VDD, the gate is connected to the drain of the transistor Tr2, and the drain is connected to the gate of the transistor Tr2. In the example shown in FIG. 1, one terminal of the resistor R1 is connected to the drain of the transistor Tr1, and one terminal of the resistor R2 is connected to the drain of the transistor Tr2. The gate of the transistor Tr1 is connected to the other terminal of the resistor R2, and the gate of the transistor Tr2 is connected to the other terminal of the resistor R1. The resistors R1 and R2 are load resistors for the transistors Tr1 and Tr2, and a circuit configuration that does not use the resistors R1 and R2 is also possible.

One terminal of the inductive impedance element L1 is connected to the drain of the transistor Tr1 via a resistor R1. Here, the node connecting one terminal of the inductive impedance element L1 and the other terminal of the resistor R1 is hereinafter referred to as the first output node N1. The other terminal of the inductive impedance element L1 is connected to the drain of the transistor Tr2 via a resistor R2. Here, the node connecting the other terminal of the inductive impedance element L1 and the other terminal of the resistor R2 is hereinafter referred to as the second output node N2.

One terminal of the variable capacitive impedance element Cv1 is connected to the drain of the transistor Tr1 (e.g., the first output node N1) via a resistor R1, and the other terminal is supplied with a frequency control voltage VCTRL. One terminal of the variable capacitive impedance element Cv2 is connected to the drain of the transistor Tr2 (e.g., the first output node N1) via a resistor R2, and the other terminal is supplied with a frequency control voltage VCTRL.

In the voltage controlled oscillator circuit 1, an output signal Vout is output from a second output node N2 that connects the other terminal of the resistor R2 and the other terminal of the inductive impedance element L1 via a buffer circuit BUF2. The buffer circuit BUF2 amplifies the oscillation signal generated in the voltage controlled oscillator circuit 1. In addition, in the voltage controlled oscillator circuit 1, the load resistor RL is driven by a buffer circuit BUF1 that is connected to a first output node N1 that connects the other terminal of the resistor R1 and one terminal of the inductive impedance element L1. The buffer circuit BUF1 amplifies the oscillation signal generated in the voltage controlled oscillator circuit 1 and aligns the impedance of the first output node N1 and the second output node N2.

Here, one of the features of the voltage controlled oscillator circuit 1 according to the first embodiment is the configuration of the variable capacitive impedance elements Cv1 and Cv2. The configuration of the variable capacitive impedance elements Cv1 and Cv2 will now be described in detail. Figure 2 shows a circuit diagram of the voltage controlled oscillator circuit 1 illustrating the detailed circuit diagram of the variable capacitive impedance elements Cv1 and Cv2 according to the first embodiment.

As shown in FIG. 2, the variable capacitive impedance element Cv1 and the variable capacitive impedance element Cv2 have the same configuration. Specifically, the variable capacitive impedance element Cv1 has a capacitor C11, a capacitor C12, a capacitance transistor Tr11, and a resistor R11. One terminal of the capacitor C11 becomes one terminal of the variable capacitive impedance element Cv1, and the other terminal is connected to the gate of the capacitance transistor Tr11. One terminal of the resistor R11 is supplied with a frequency control voltage VCTRL, and the other terminal is connected to the gate of the capacitance transistor Tr11. The source of the capacitance transistor Tr11 is supplied with a ground voltage, and the capacitor C12 is connected between the drain and gate of the capacitance transistor Tr11.

The variable capacitive impedance element Cv2 also has a capacitor C21, a capacitor C22, a capacitance transistor Tr21, and a resistor R21. One terminal of the capacitor C21 becomes one terminal of the variable capacitive impedance element Cv2, and the other terminal is connected to the gate of the capacitance transistor Tr21. One terminal of the resistor R21 is supplied with a frequency control voltage VCTRL, and the other terminal is connected to the gate of the capacitance transistor Tr21. A ground voltage is supplied to the source of the capacitance transistor Tr21, and the capacitor C22 is connected between the drain and gate of the capacitance transistor Tr21.

Capacitors C11, C12, C21, and C22 are formed as interlayer capacitances using an interlayer insulating film formed between wiring layers and metal wiring that sandwiches the interlayer insulating film.

Here, the variable capacitive impedance elements Cv1 and Cv2 have a variable capacitance value determined by a capacitance transistor and a capacitor connected between the drain and gate of the capacitance transistor. Therefore, the capacitance value of the variable capacitive impedance element Cv1 will be explained using the equivalent circuit of the capacitance transistor Tr12 and capacitor C12 of the variable capacitive impedance element Cv1 as an example.

Therefore, FIG. 3 shows an equivalent circuit diagram of the variable capacitive impedance element Cv1 according to the first embodiment. In the equivalent circuit diagram shown in FIG. 3, the gate of the capacitance transistor Tr11 is shown as terminal G, the drain of the capacitance transistor Tr11 is shown as terminal D, and the source of the capacitance transistor Tr11 is shown as terminal S. In the equivalent circuit diagram of the variable capacitive impedance element Cv1, a gate-source capacitance Cgs whose capacitance value changes depending on the frequency control voltage VCTRL is provided between terminals G and S, and a source-drain resistance Rds whose resistance value changes depending on the frequency control voltage VCTRL is provided between terminals S and D. In addition, a capacitor C12 is connected between terminals G and D.

（１）式において、周波数制御電圧ＶＣＴＲＬの電圧が０Ｖであった場合、ソース・ドレイン間抵抗Ｒｄｓが十分大きくなり、１＜＜ω^２Ｃ１２^２Ｒｄｓ^２になるため、アドミッタンスＹは、（２）式で表される。なお、（２）式において、Ｃｇｓ０は、周波数制御電圧ＶＣＴＲＬが０Ｖの時のゲート・ドレイン間容量である。

したがって、周波数制御電圧ＶＣＴＲＬの電圧が０Ｖであった場合、コンデンサＣ１２の影響は見えなくなり、コンデンサＣ１２が無い場合の容量値と同じとなる。 3, the admittance Y of the variable capacitive impedance element Cv1 is expressed by the following formula (1): In the following formula, the capacitor C11 is considered to have a capacitance value of about 500 fF.

In equation (1), when the frequency control voltage VCTRL is 0 V, the source-drain resistance Rds becomes sufficiently large, and 1<<ω ² C12 ² Rds ² , so that the admittance Y is expressed by equation (2). In equation (2), Cgs0 is the gate-drain capacitance when the frequency control voltage VCTRL is 0 V.

Therefore, when the voltage of the frequency control voltage VCTRL is 0 V, the effect of the capacitor C12 becomes invisible, and the capacitance value becomes the same as when the capacitor C12 is not present.

従って、可変容量性インピーダンス素子Ｃｖ１の容量値としてコンデンサＣ１２が並列成分として加算されることになり、可変容量性インピーダンス素子Ｃｖ１はコンデンサＣ１２分増加する。 On the other hand, when the frequency control voltage VCTRL is 1V, the source-drain resistance Rds becomes zero and 1>>ω ² C12 ² Rds ² holds, so the admittance Y can be expressed as in equation (3). In equation (3), Cgs1 is the gate-drain capacitance when the frequency control voltage VCTRL is 1V.

Therefore, the capacitor C12 is added as a parallel component to the capacitance of the variable capacitive impedance element Cv1, and the capacitance of the variable capacitive impedance element Cv1 increases by the amount of the capacitor C12.

In other words, the variable capacitive impedance element of embodiment 1 has a capacitance value equivalent to that of a circuit without capacitor C12 when the frequency control voltage VCTRL is 0 V, and has a capacitance value obtained by adding the capacitance of capacitor C12 to the gate-source capacitance Cgs when the frequency control voltage VCTRL is 1 V. Therefore, the variable capacitive impedance element of embodiment 1 has a wider variable range of capacitance value than a circuit without capacitor C12. Also, the voltage controlled oscillator circuit 1 having variable capacitive impedance elements Cv1 and Cv2 has a wider variable range of oscillation frequency.

The characteristics of the variable capacitive impedance elements Cv1 and Cv2 according to the first embodiment and the characteristics of a voltage-controlled oscillator circuit 1 having the variable capacitive impedance elements Cv1 and Cv2 will be described below. In the following description, a variable capacitive impedance element in which the capacitor provided between the gate and drain of the capacitance transistor of the variable capacitive impedance element has been removed and a voltage-controlled oscillator circuit including the variable capacitive impedance element will be referred to as a comparative example.

Figure 4 shows a graph explaining the variable capacitance range of the variable capacitive impedance element according to the first embodiment. In Figure 4, the upper figure shows a graph explaining the variable range of the capacitance value of the variable capacitive impedance element according to the comparative example, and the lower figure shows a graph explaining the variable range of the capacitance value of the variable capacitive impedance element according to the first embodiment. The graph shown in Figure 4 also shows the change in capacitance value when the frequency control voltage VCTRL is changed from 0V to 1V.

As shown in FIG. 4, in the variable capacitive impedance element of the comparative example, the variable range of the capacitance value is variable from about 50 fF to about 100 fF. On the other hand, the variable capacitive impedance element of the first embodiment can vary the capacitance value from about 50 fF to a capacitance value of 600 fF or more. In other words, the variable capacitive impedance element of the first embodiment has a wider variable range of the capacitance value than the variable capacitive impedance element of the comparative example, which does not have a capacitor connected between the gate and drain of the capacitance transistor.

Figure 5 shows a graph illustrating the frequency variable range of the voltage controlled oscillator circuit 1 according to the first embodiment. In Figure 5, the upper figure shows a graph illustrating the frequency variable range of the voltage controlled oscillator circuit according to the comparative example, and the lower figure shows a graph illustrating the frequency variable range of the voltage controlled oscillator circuit according to the first embodiment. The graph shown in Figure 5 also shows the change in the oscillation frequency when the frequency control voltage VCTRL is changed from 0V to 1V.

As shown in FIG. 5, in the voltage controlled oscillator circuit of the comparative example, the variable frequency range is approximately 6.5 GHz to 7.1 GHz. On the other hand, in the voltage controlled oscillator circuit 1 of the first embodiment, the variable frequency range is approximately 4.0 GHz to 6.7 GHz. In other words, in the voltage controlled oscillator circuit 1 of the first embodiment, the variable frequency range is clearly wider than that of the voltage controlled oscillator circuit of the comparative example.

As explained above, in the voltage-controlled oscillator circuit 1 according to the first embodiment, the variable range of the capacitance value of the variable capacitive impedance element can be expanded by providing a capacitor between the gate and drain of the capacitance transistor that constitutes the variable capacitive impedance element. In addition, the voltage-controlled oscillator circuit 1 having the variable capacitive impedance element according to the first embodiment can significantly widen the frequency variable range of the output signal compared to a voltage-controlled oscillator circuit having a variable capacitive impedance element that does not have a capacitor between the gate and drain of the capacitance transistor.

Embodiment 2
In the second embodiment, a description will be given of variable capacitive impedance elements Cv1a and Cv2a which are different forms of the variable capacitive impedance elements Cv1 and Cv2 according to the first embodiment. In the description of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof will be omitted.

Figure 6 shows a circuit diagram of a voltage controlled oscillator circuit that explains the detailed circuit diagram of the variable capacitive impedance elements Cv1a and Cv2a according to the second embodiment. As shown in Figure 6, the variable capacitive impedance element Cv1a is obtained by adding a bias circuit composed of a first mirror transistor (e.g., mirror transistor Tr31), a second mirror transistor (e.g., mirror transistor Tr32), and a mirror resistor R31 to the variable capacitive impedance element Cv1. The bias circuit supplies a bias current to the drain of the capacitive transistor Tr11.

The mirror transistor Tr31 has a source supplied with a bias voltage Vd, and a gate and drain connected in common. The mirror transistor Tr32 has a source supplied with a bias voltage Vd, a gate connected in common to the gate of the mirror transistor Tr31, and a drain connected to the drain of the capacitance transistor Tr11. The mirror resistor R31 is connected between the drain of the mirror transistor Tr31 and a ground terminal that supplies a ground voltage.

The variable capacitive impedance element Cv2a has substantially the same configuration as the variable capacitive impedance element Cv1a. In other words, the variable capacitive impedance element Cv2a is obtained by adding a bias circuit consisting of a first mirror transistor (e.g., mirror transistor Tr41), a second mirror transistor (e.g., mirror transistor Tr42), and a mirror resistor R41 to the variable capacitive impedance element Cv2. The bias circuit supplies a bias current to the drain of the capacitive transistor Tr21.

The mirror transistor Tr41 has a source supplied with a bias voltage Vd, and a gate and drain connected in common. The mirror transistor Tr42 has a source supplied with a bias voltage Vd, a gate connected in common to the gate of the mirror transistor Tr41, and a drain connected to the drain of the capacitance transistor Tr21. The mirror resistor R41 is connected between the drain of the mirror transistor Tr41 and a ground terminal that supplies a ground voltage.

In the variable capacitive impedance elements Cv1a and Cv2a according to the second embodiment, by appropriately setting the values of the mirror resistors R31 and R41, a circuit can be achieved in which the fluctuation in the value of the current flowing through the capacitive transistor is very small in response to fluctuations in the value of the bias voltage Vd.

The present invention is not limited to the above embodiment, and can be modified as appropriate without departing from the spirit and scope of the invention.

1, 2 Voltage controlled oscillator circuit Tr1, Tr2 Transistor Tr11, Tr21 Capacitive transistor Tr31, Tr32, Tr41, Tr42 Mirror transistor R1, R2, R11, R21 Resistor R31, R41 Mirror resistor L1 Inductive impedance element Cv1, Cv2, Cv1a, Cv2a Variable capacitive impedance element C11, C12, C21, C22 Capacitor BUF1, BUF2 Buffer circuit RL Load resistor Vout Output signal VCTRL Frequency control voltage

Claims (5)

a first transistor having a source connected to a first power supply;
a second transistor having a source supplied with the first power supply, a drain connected to the gate of the first transistor, and a gate connected to the drain of the first transistor;
an inductive impedance element having one terminal connected to the drain of the first transistor, the other terminal connected to the drain of the second transistor, and a common connection terminal to which a second power source is supplied;
a first variable capacitive impedance element having one terminal connected to the drain of the first transistor and having the other terminal to which a frequency control voltage is applied;
a second variable capacitive impedance element having one terminal connected to the drain of the second transistor and having the other terminal to which a frequency control voltage is applied;
The first variable capacitive impedance element and the second variable capacitive impedance element each have
a capacitance transistor having a source connected to the second power supply;
a resistor having one terminal connected to the gate of the capacitance transistor and having the other terminal to which the frequency control voltage is applied;
a first capacitor, one terminal of which serves as one terminal of a corresponding one of the first variable capacitive impedance element and the second variable capacitive impedance element, and the other terminal of which is connected to a gate of the capacitance transistor;
a second capacitor connected between the gate and drain of the capacitance transistor. The voltage controlled oscillator circuit of claim 1 further comprising a bias circuit that supplies a bias current to the drain of the capacitance transistor. The bias circuit includes:
a first mirror transistor having a source to which a bias voltage is applied and a gate and a drain connected in common;
a second mirror transistor, the source of which is supplied with the bias voltage, the gate of which is commonly connected to the gate of the first mirror transistor, and the drain of which is connected to the drain of the capacitance transistor;
a mirror resistor connected between the drain of the first mirror transistor and the second power supply;
3. The voltage controlled oscillator circuit of claim 2, comprising: A voltage controlled oscillator circuit according to any one of claims 1 to 3, wherein the capacitance transistor is a MOS transistor. The voltage controlled oscillator circuit according to any one of claims 1 to 4, wherein the first and second capacitors are formed using capacitance between wiring lines.

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