JP7599348B2 - Printed wiring board and its manufacturing method - Google Patents

Description

The present invention relates to a printed wiring board having multiple plated bumps and a method for manufacturing the same.

Patent document 1 discloses an example of a printed wiring board having multiple plated bumps.

JP 2010-129996 A

Figure 5 is a diagram showing an example of a plated bump of a conventional printed wiring board having multiple plated bumps. In Figure 5, the printed wiring board 51 has a solder resist layer 62 formed on a base insulating layer 61, a base plating layer 64 formed on a conductor pad 63 in an opening 62a formed in the solder resist layer 62, a top plating layer 65 formed on the base plating layer 64, and a plated bump 71 formed by reflowing the top plating layer 65.

In this case, as shown in FIG. 6, during heat treatment such as reflow of the top plating layer 65 made of Sn, molten Sn may drip down the side of the base plating layer 64, reducing the amount of Sn in the top plating layer 65 and decreasing the height of the bumps 71. As a result, the height of the bumps 71 may differ in some areas, causing poor contact between the terminals of the mounted components and the bumps 71 when the components are mounted by the customer.

The printed wiring board according to the present invention is a printed wiring board having a plurality of plating bumps, the plating bumps including a base insulating layer, a conductor layer formed on the base insulating layer, a solder resist layer formed on the base insulating layer and on the conductor layer and having an opening that exposes a part of the conductor layer as a conductor pad, a base plating layer formed in the opening of the solder resist layer, and a top plating layer formed in a hemispherical shape on the base plating layer, the plating bumps having at least a first bump and a second bump, the first bump having a convex curved surface at the center of the upper surface of the base plating layer, the second bump having a concave curved surface at the center of the upper surface of the base plating layer, the top plating layer of the first bump covering the upper surface and part of the side surface of the base plating layer, and the top plating layer of the second bump covering only the upper surface of the base plating layer.

A method for manufacturing a printed wiring board according to the present invention includes forming a base insulating layer, forming a conductor layer on the base insulating layer, forming a solder resist layer on the base insulating layer and on the conductor layer, forming an opening in the solder resist layer that exposes a portion of the conductor layer as a conductor pad, and forming a base plating layer in the opening.
A method for manufacturing a printed wiring board having a plurality of plating bumps, comprising: forming a top plating layer on the base plating layer; and forming a plating bump by reflowing the top plating layer, the method comprising: forming a first bump and a second bump as the plating bump; when forming the base plating, forming a convex curved surface at the center of the upper surface of the base plating layer in the first bump and forming a concave curved surface at the center of the upper surface of the base plating layer in the second bump; and when reflowing the top plating layer, the top plating layer covers the upper surface and part of the side surface of the base plating layer in the first bump, and the top plating layer covers only the upper surface of the base plating layer in the second bump.

1 is a cross-sectional view for explaining a configuration of a plating bump in a printed wiring board according to an embodiment of the present invention. 1 is a cross-sectional view illustrating an embodiment of a printed wiring board according to the present invention. FIG. 2 is a diagram for explaining areas in one embodiment of a printed wiring board according to the present invention. 1A to 1D are diagrams illustrating steps in one embodiment of a method for producing a printed wiring board according to the present invention. FIG. 1 is a diagram showing an example of a conventional printed wiring board having a plurality of plated bumps. 1A and 1B are diagrams for explaining a problem in an example of a conventional printed wiring board having a plurality of plated bumps.

<About the printed wiring board of the present invention>
An embodiment of a printed wiring board of the present invention will be described with reference to the drawings. In the example shown in Figures 1 and 2, the dimensions of each component, particularly the height dimension, are shown as different from the actual dimensions in order to make the features of the present invention easier to understand.

Figure 1 is a cross-sectional view for explaining the configuration of a plated bump in a printed wiring board according to one embodiment of the present invention. In Figure 1, a part of the printed wiring board 10 of the embodiment is shown enlarged. The printed wiring board 10 may be a cored board formed by alternately laminating conductor layers having a predetermined circuit pattern and resin insulating layers on one or both sides of a core board (not shown). When conductor layers are formed on both sides of the core board, the conductor layers facing each other via the core board may be connected via through-hole conductors (not shown). Alternatively, the printed wiring board 10 may be a coreless board formed by alternately laminating conductor layers and resin insulating layers on a support board (not shown) instead of a core board, and then removing the support board.

In any case, as shown in FIG. 1, the printed wiring board 10 includes a base insulating layer 12 that is the outermost of at least one resin insulating layer, a conductor layer 14 having a predetermined circuit pattern formed on the base insulating layer 12, and a solder resist layer 16 formed on the base insulating layer 12 and the conductor layer 14. In many cases, multiple other conductor layers and resin insulating layers are alternately provided below the base insulating layer 12, but these are omitted in the figure. However, the printed wiring board 10 may also be composed of one base insulating layer 12 and one conductor layer 14.

The base insulating layer 12 may be made of a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. The conductor layer 14 is made of a conductive metal, for example a metal mainly composed of copper. The solder resist layer 16 has an opening 16a that exposes a part of the conductor layer 14 as a conductor pad 14a. The aspect ratio of the opening 16a, that is, the ratio of the depth to the bottom diameter, may be 0.5 or less. An underlayer (not shown) may be formed on the conductor pad 14a. Examples of the underlayer include a nickel layer formed on the surface of the conductor pad 14a, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. Other examples include a nickel layer and a gold layer formed on the nickel layer.

The printed wiring board 10 further includes a plated bump 20 formed on the conductor pad 14a. The plated bump 20 can be used for connecting to a power source or ground line, or for connecting to a signal line. The plated bump 20 includes a base plating layer 24 formed in the opening 16a, and a top plating layer 28 formed on the base plating layer 24, the upper surface of which is a concave or convex curved surface with a curvature C. An intermediate layer (not shown), for example, mainly composed of nickel, can also be formed on the base plating layer 24. The thickness of the intermediate layer is preferably 7 μm or less.

The base plating layer 24 is formed of a conductive metal, preferably a metal mainly composed of copper. The base plating layer 24 is formed to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). This allows the plating bump 20 to be stably held within the opening 16a. The thickness of the base plating layer 24 from the surface of the solder resist layer 16 is preferably within the range of 3 μm to 20 μm. The top plating layer 28 is made of a metal, such as a metal mainly composed of tin, that has a lower melting point than the base plating layer 24 and is melted by reflow processing and shaped into an approximately hemispherical shape as shown in FIG. 1. The thickness of the top plating layer 28 (the vertical distance from the lower end of the top plating layer 28 to the top of the top plating layer 28 on the outer peripheral surface of the plating bump 20) is preferably within the range of 5 μm to 45 μm. By setting the thickness of the top plating layer 28 within this range, good connection reliability can be obtained between the plating bumps 20 and the connection pads (not shown) of electronic components such as semiconductor chips and memories mounted on the printed wiring board 10.

Figure 2 is a cross-sectional view for explaining one embodiment of a printed wiring board having the plated bumps of the above-mentioned configuration. The features of one embodiment of the printed wiring board of the present invention are that, as shown in Figure 2, the plated bump 20 has a first bump 20-1 and a second bump 20-2, the first bump 20-1 has a convex curved surface with a curvature C1 at the center of the upper surface of the base plating layer 24, the second bump 20-2 has a concave curved surface with a curvature C2 at the center of the upper surface of the base plating layer 24, the top plating layer 28 covers the upper surface and part of the side surface of the base plating layer 24 in the first bump 20-1, and the top plating layer 28 covers only the upper surface of the base plating layer 24 in the second bump 20-2, and the height of the first bump 20-1 is approximately the same as the height of the second bump 20-2. In addition, in one embodiment of the printed wiring board shown in Figure 2, the diameter of the first bump 20-1 and the diameter of the second bump 20-2 are approximately the same.

In one embodiment of the printed wiring board according to the present invention shown in FIG. 2, in the first bump 20-1, the center of the upper surface of the base plating layer 24 is a convex curved surface, and the top plating layer 28 is formed so as to cover the upper surface and part of the side surface of the base plating layer 24. On the other hand, in the second bump 20-2, the center of the upper surface of the base plating layer 24 is a concave curved surface, and the top plating layer 28 is formed so as to cover only the upper surface of the base plating layer 24. In this way, the height of the first bump 20-1 and the height of the second bump 20-2 can be made approximately the same. As a result, the problem of the bumps having different heights, which was a problem in the conventional printed wiring board, can be solved, which is that a contact failure occurs between the terminal of the mounted component and the bump during mounting by the customer. In addition, in one embodiment of the printed wiring board according to the present invention shown in FIG. 2, the height of the first bump 20-1 and the height of the second bump 20-2 are approximately the same, so that it can be used preferably when the connection pads (not shown) of electronic components such as semiconductor chips and memories mounted on the printed wiring board 10 are the same height.

Figure 3 is a diagram for explaining areas in one embodiment of a printed wiring board according to the present invention. In the printed wiring board 10 (all of which are component mounting surfaces) shown in Figure 3, at least the bumps included in the first area 10-1 of the component mounting surface are all first bumps 20-1, and the bumps included in the second area 10-2 are all second bumps 20-2. Note that, although an example has been described here in which the area is composed of two areas, the first area 10-1 and the second area 10-2, the number of areas is not limited to this.

<Regarding the method for producing a printed wiring board according to the present invention>
A method for manufacturing the printed wiring board 10 shown in FIGS. 1 and 2 according to the present invention will now be described with reference to FIGS.

Figure 4(a) shows an intermediate body in which a conductor layer 14 having a predetermined circuit pattern, a solder resist layer 16, and a plating resist 31 are formed on the base insulating layer 12 for each of the first bump 20-1 and the second bump 20-2 by a known method, and a base plating layer 24 is formed in the opening of the plating resist 31. In many cases, multiple other conductor layers and resin insulating layers are alternately formed under the base insulating layer 12, but these are omitted in the figure. Multiple conductor layers and resin insulating layers can be stacked on a core substrate or a support plate that can be removed later. However, the printed wiring board 10 may also be composed of one resin insulating layer as the base insulating layer 12 and one conductor layer 14, in which case the resin insulating layer corresponds to the base insulating layer 12.

The base insulating layer 12 may be a build-up insulating resin film containing inorganic fillers such as silica or alumina and epoxy resin. The solder resist layer 16 is formed with an opening 16a by, for example, a carbon dioxide gas laser or a UV-YAG laser, which exposes a part of the conductor layer 14 as a conductor pad 14a. The aspect ratio of the opening 16a is preferably 0.5 or less. A base layer (not shown) may be formed on the conductor pad 14a by plating, for example, a nickel layer, a palladium layer, and a gold layer stacked in this order. The base plating layer 24 is formed, for example, by electrolytic plating through a plating resist 31 of a predetermined pattern formed on the solder resist layer 16 and having an opening at the intended location for forming the plating bump 20.

Next, as shown in FIG. 4(b), a convex curved surface with a curvature C1 is formed at the center of the upper surface of the base plating layer 24 of the first bump 20-1, and a concave curved surface with a curvature C2 is formed at the center of the upper surface of the base plating layer 24 of the second bump 20-2. The convex curved surface and the concave curved surface can be formed by using a method of performing strong stirring plating on the upper surface of the base plating layer 24 in the plating resist 31 to form a concave curved surface by the leveling action of additives, a method of forming a concave curved surface by the action of stirring the etching liquid, etc., and by changing the conditions of use of strong stirring plating and etching. Note that, at the stage of FIG. 4(b), the upper surface of the base plating layer 24 of the first bump 20-1 is formed higher than the upper surface of the base plating layer 24 of the second bump 20-2.

Specific examples of forming convex and concave curved surfaces include a method of performing electrolytic plating using a plating solution containing an inhibitor and an accelerator while stirring the plating solution. Alternatively, a method may be used that includes performing electrolytic plating through a plating resist of a predetermined pattern having openings at the intended locations for forming plated bumps 20 formed on the solder resist layer 16, and, after the electrolytic plating, performing an etching process through the plating resist while stirring the etching solution.

Next, as shown in FIG. 4(c), in the first bump 20-1 and the second bump 20-2, electroplating is performed using, for example, tin in the plating resist 31, and then the plating resist 31 is removed to form a top plating layer 28 made of tin on the base plating layer 24. Note that, at the stage of FIG. 4(c), the upper surface of the top plating layer 28 of the first bump 20-1 is formed higher than the upper surface of the top plating layer 28 of the second bump 20-2. Then, as shown in FIG. 4(d), by reflowing the top plating layer 28, the first bump 20-1 covers the upper surface and part of the side surface of the base plating layer 24, and the second bump 20-2 covers only the upper surface of the base plating layer 24, and the height of the first bump 20-1 is approximately the same as the height of the second bump 20-2.

REFERENCE SIGNS LIST 10 Printed wiring board 10-1 First area 10-2 Second area 12 Base insulating layer 14 Conductive layer 14a Conductive pad 16 Solder resist layer 16a Opening 20 Plated bump 20-1 First bump 20-2 Second bump 24 Base plating layer 28 Top plating layer 31 Plating resist

Claims (5)

A printed wiring board having a plurality of plating bumps,
A base insulating layer;
a conductor layer formed on the base insulating layer;
a solder resist layer formed on the base insulating layer and the conductor layer, the solder resist layer having an opening for exposing a part of the conductor layer as a conductor pad;
a base plating layer formed in the opening of the solder resist layer;
a top plating layer formed in a hemispherical shape on the base plating layer; and
the plated bumps include at least a first bump and a second bump;
the first bump has a convex curved surface at the center of the upper surface of the base plating layer, and the second bump has a concave curved surface at the center of the upper surface of the base plating layer;
In the first bump, the top plating layer covers an upper surface and a part of a side surface of the base plating layer, and in the second bump, the top plating layer covers only an upper surface of the base plating layer ;
The diameter of the first bump is approximately the same as the diameter of the second bump . In the printed wiring board according to claim 1, at least all of the bumps in the first area of the component mounting surface are made of the first bumps, and all of the bumps in the second area are made of the second bumps. forming a base insulating layer;
forming a conductor layer on the base insulating layer;
forming a solder resist layer on the base insulating layer and on the conductor layer;
forming an opening in the solder resist layer to expose a portion of the conductor layer as a conductor pad;
forming a base plating layer in the opening;
forming a top plating layer on the base plating layer;
and forming a plating bump by reflowing the top plating layer,
forming a first bump and a second bump as the plating bump;
When forming the base plating, a convex curved surface is formed at the center of the upper surface of the base plating layer in the first bump, and a concave curved surface is formed at the center of the upper surface of the base plating layer in the second bump;
When the top plating layer is reflowed, the top plating layer is caused to cover the upper surface and a part of the side surface of the base plating layer in the first bump, and the top plating layer is caused to cover only the upper surface of the base plating layer in the second bump.
forming the first bump so that the diameter thereof is substantially the same as the diameter of the second bump;
Includes. In the method for manufacturing a printed wiring board described in claim 3 , the formation of a convex curved surface at the center of the upper surface of the base plating layer in the first bump and/or a concave curved surface at the center of the upper surface of the base plating layer in the second bump includes performing an electrolytic plating process using a plating solution containing an inhibitor and an accelerator while stirring the plating solution. In the method for manufacturing a printed wiring board described in claim 3 , the formation of a convex curved surface at the center of the upper surface of the base plating layer in the first bump and/or a concave curved surface at the center of the upper surface of the base plating layer in the second bump includes performing an electrolytic plating process through a plating resist of a predetermined pattern formed on the solder resist layer and having an opening at a location where the plating bump is to be formed, and after the electrolytic plating process, performing an etching process through the plating resist while stirring an etching solution.

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