JP7600862B2 - Comparator circuit and driver circuit - Google Patents

Description

This disclosure relates to a comparator circuit and a drive circuit.

Patent document 1 discloses a horizontal drive circuit for a liquid crystal display device. In FIG. 2 of patent document 1, a comparator compares the counter output with the pixel value of digital image data. The comparator outputs a match pulse indicating that the two match to a D-type flip-flop circuit. Then, a positive polarity switch and a negative polarity switch are switched in conjunction with the output of the D-type flip-flop.

Furthermore, the horizontal drive circuit of Patent Document 1 includes a comparator clock/counter clock generation circuit section. The comparator clock/counter clock generation circuit section generates a comparator clock and a counter clock based on an external clock.

JP 2013-105166 A

In Patent Document 1, the comparator clock is generated based on an external clock signal. Therefore, many large buffers are required to transmit the clock signal from the outside, making it difficult to reduce power consumption.

The present disclosure has been made in consideration of the above points, and aims to provide a comparator circuit and a drive circuit that consumes low power.

The comparator circuit according to this embodiment includes a comparator element that outputs a match signal indicating whether the value of a first input signal and the value of a second input signal match, a data input terminal and a clock input terminal to which a constant potential is supplied, a flip-flop circuit that holds the value of the data input terminal in response to a self-clocking signal to the clock input terminal, and a clock generation circuit that generates the self-clocking signal based on the output signal from the flip-flop circuit and the match signal.

This disclosure provides a low power consumption comparator circuit and drive circuit.

FIG. 1 is a circuit diagram showing a configuration of a drive circuit using a comparator circuit. 4 is a timing chart showing an operation of the comparator circuit. FIG. 1 is a circuit diagram showing a drive circuit including a comparator circuit according to a comparative example. FIG. 1 is a diagram showing a configuration of a liquid crystal display device using a driving circuit.

Specific embodiments to which the present invention is applied will be described in detail below with reference to the drawings. However, this disclosure is not limited to the following embodiments. In addition, the following description and drawings have been simplified as appropriate for clarity of explanation.

The following describes the comparator circuit according to this embodiment and the drive circuit using the same. Fig. 1 is a circuit diagram showing a drive circuit 100 equipped with a comparator circuit 30. Specifically, the drive circuit shown in Fig. 1 is a horizontal drive circuit for one column of pixels of a liquid crystal display device. Fig. 2 is a timing chart showing the operation of the comparator circuit 30.

The drive circuit 100 includes a latch circuit 10, a counter 20, and a comparator circuit 30. Here, 10-bit image data DATA is input to the drive circuit 100. In other words, one pixel is expressed in 1024 gradations (=10 bits). Of course, the number of bits of the image data is not particularly limited.

The latch circuit 10 receives a latch signal LATCH and image data DATA. The latch circuit 10 latches the 10-bit image data DATA in response to the latch signal LATCH. The latch circuit 10 outputs the latched image data DATA in parallel to the comparator circuit 30. The image data DATA output from the latch circuit 10 is referred to as latch output A. The latch output A is 10-bit parallel data. In FIG. 2, the value of the latch output A is α.

The counter 20 receives a counter clock signal CNT_CLOCK and a counter reset signal CNT_RST. The counter 20 performs a counting operation in synchronization with the counter clock signal CNT_CLOCK. For example, the counter 20 counts up a count value at the clock frequency of the counter clock signal CNT_CLOCK. The counter 20 outputs the count value resulting from the counting operation to the comparator circuit 30.

The counter 20 also resets the count value to an initial value in response to a counter reset signal CNT_RST. The counter reset signal CNT_RST corresponds to the horizontal scanning frequency. The output of the counter 20 is 10 bits. Therefore, the counter 20 counts up the count value from 0 to 1023. The counter 20 outputs the 10-bit count value to the comparator circuit 30. The count value output from the counter 20 is called counter output B. The counter output B is 10-bit parallel data. As shown in FIG. 2, the counter output B counts up in the order of α-1, α, and α+1.

The comparator circuit 30 includes a comparator element 31, a clock generation circuit 32, and an FF (flip-flop) circuit 33. The comparator circuit 30 is a self-clocking comparator circuit that generates a self-clock signal based on its own output. Therefore, no clock signal is input to the comparator circuit 30 from the outside.

The comparator element 31 compares the latch output A with the counter output B. The comparator element 31 generates a match signal Z indicating that the latch output A and the counter output B match. The comparator element 31 outputs the match signal Z to the clock generation circuit 32. The latch output A and the counter output B are each 10-bit parallel data. The comparator element 31 compares each bit of the latch output A and the counter output B. The comparator element 31 determines that the latch output A and the counter output B match when all bits of the latch output A and the counter output B match.

When latch output A and counter output B match, comparator element 31 asserts match signal Z. When latch output A and counter output B differ, comparator element 31 deasserts match signal Z. Therefore, match signal Z becomes a positive pulse signal as shown in FIG. 2. When the value of counter output B is α, match signal Z becomes high level. When the value of counter output B is not α, match signal Z becomes low level.

The clock generation circuit 32 generates a self-clock signal based on the match signal Z from the comparator circuit 30 and the output signal of the clock generation circuit 32. The clock generation circuit 32 outputs the self-clock signal to the FF circuit 33.

For example, the clock generation circuit 32 includes a NAND circuit. Specifically, the output terminal of the comparator element 31 and the inverted output terminal QB of the FF circuit 33 are connected to the clock generation circuit 32. Therefore, the coincidence signal Z from the comparator element 31 and the inverted output signal of the FF circuit 33 are input to the clock generation circuit 32. The clock generation circuit 32 outputs the NAND (negative logical product) of the coincidence signal Z and the inverted output signal. The output signal from the clock generation circuit 32 is the internal signal Z1. The clock generation circuit 32 outputs the internal signal Z1 to the FF circuit 33.

FF circuit 33 is a D-type flip-flop circuit. FF circuit 33 has a data input terminal D, a clock input terminal CK, a non-inverting output terminal Q, and an inverting output terminal QB. The output of the clock generation circuit 32 is connected to the clock input terminal CK. An internal signal Z1 is input to the clock input terminal CK. FF circuit 33 samples and holds the data value of data input terminal D in response to the internal signal Z1. FF circuit 33 holds a 1-bit value.

The FF circuit 33 outputs a non-inverted output signal corresponding to the data value held from the non-inverted output terminal Q. The FF circuit 33 outputs an inverted output signal obtained by inverting the non-inverted output signal from the inverted output terminal QB. The inverted output signal becomes the output signal OUT from the comparator circuit 30. When the value of the input data held by the FF circuit 33 is 1, the non-inverted output signal becomes high level and the inverted output signal becomes low level. When the value of the input data held by the FF circuit 33 is 0, the non-inverted output signal becomes low level and the inverted output signal becomes high level.

The comparator reset signal CMP_RST is input to the FF circuit 33. The FF circuit 33 resets the data it holds in response to the comparator reset signal CMP_RST. As a result, the data value held in the FF circuit 33 becomes 0. When the FF circuit 33 is reset by the comparator reset signal CMP_RST, the inverted output signal becomes high level and the non-inverted output signal becomes low level.

A constant power supply voltage VDD is input to the data input terminal D as input data. Therefore, a constant potential is always supplied to the data input terminal D. The clock input terminal CK is connected to the output of the clock generation circuit 32. Therefore, the internal signal Z1 from the clock generation circuit 32 is input to the clock input terminal CK of the FF circuit 33.

After being reset by the comparator reset signal CMP_RST, the FF circuit 33 samples a constant power supply voltage VDD in response to the internal signal Z1. The FF circuit 33 detects the edge of the internal signal Z1 and holds the input data to the data input terminal D. Therefore, at the edge of the internal signal Z1, the non-inverted output signal becomes high level and the inverted output signal becomes low level.

Therefore, as shown in FIG. 2, the inverted output signal is a negative step signal. The output signal OUT of the comparator circuit 30 is at a high level before the falling edge of the match signal Z, and changes to a low level at the falling edge of the match signal Z. In this way, a negative step signal is output from the inverted output terminal QB of the FF circuit 33. The level of the output signal OUT changes according to the falling edge of the match signal Z.

The comparator circuit 30 is equipped with a clock generation circuit 32 that generates a self-clocked signal. The clock generation circuit 32 generates an internal signal Z1 that is a self-clocked signal based on the match signal Z and the output signal OUT. In other words, the comparator circuit 30 is a self-clocked comparator that operates with a self-clocked signal generated by the comparator circuit 30 itself. The FF circuit 33 holds data according to the internal signal Z1, which is a self-clocked signal. Therefore, a buffer for an external clock is not required, and power consumption can be reduced.

Figure 3 shows a drive circuit having a comparator circuit 30 according to a comparative example. The basic operations of the latch circuit 10, counter 20, and comparator element 31 are the same as those in Figure 1, so detailed explanations will be omitted. For example, the comparator element 31 outputs a match signal Z indicating that the latch output A and the counter output B match. The match signal Z is a positive pulse.

In the comparator circuit 30 shown in FIG. 3, an external comparator clock signal CMP_CLOCK is input to the clock input terminal CK of the FF circuit 33. The comparator circuit 30 is a clock comparator that operates in response to the comparator clock signal CMP_CLOCK.

The inverted output signal of the FF circuit 33 is input to the OR circuit 35 via the inverter 34. In addition, the match signal Z from the comparator element 31 is input to the OR circuit 35. The internal signal Z1 output from the OR circuit 35 is input to the data input terminal D of the FF circuit 33. In other words, the internal signal Z1 becomes the input data input to the FF circuit 33. The FF circuit 33 is reset by the comparator reset signal CMP_RST. After the reset, the FF circuit 33 holds the value of the input data according to the comparator clock signal CMP_CLOCK.

Ideally, the FF circuit 33 samples the input data at a central point in response to the comparator clock signal CMP_CLOCK. For example, if the comparator clock signal CMP_CLOCK contains jitter, a timing error may occur between the comparator clock signal CMP_CLOCK and the input data in the comparator circuit 30 shown in FIG. 3.

In contrast, in the comparator circuit 30 according to the present embodiment, a constant potential is always supplied to the data input terminal D. In other words, the power supply voltage VDD is supplied to the data input terminal D. Therefore, in the FF circuit 33 of FIG. 1, it is possible to prevent timing errors from occurring between the internal signal Z1, which is a self-clock signal, and the input data. This improves reliability.

Furthermore, by providing the drive circuit with multiple comparator circuits 30 of FIG. 1, multiple buffers can be omitted, making it possible to reduce power consumption. For example, assume that the drive circuit 100 is applied to a WUXGA LCOS (Liquid Crystal On-Silicon) device with a frame rate of 120 Hz. In this case, the power consumption of the device can be reduced from 1188 mW to 1087 mW. In other words, it is possible to reduce power consumption by 8.5% (= 101 mW).

The configuration of a liquid crystal display device 200 in which a comparator circuit 30 is applied to a drive circuit will be described with reference to FIG. 4. The liquid crystal display device 200 is an LCOS display. FIG. 4 is a block diagram showing the backplane of an LCOS display.

The liquid crystal display device 200 includes a pixel display section 50, a vertical drive circuit 2, and a horizontal drive circuit 3. The horizontal drive circuit 3 includes the drive circuit 100 shown in FIG. 1. Specifically, the horizontal drive circuit 3 includes m drive circuits 100 (m is an integer equal to or greater than 2) corresponding to the number of pixels in one line.

The pixel display section 50 is provided with a plurality of data lines 6, a plurality of gate lines 8, and a plurality of pixels 42. The plurality of data lines 6 are arranged parallel to one another. The plurality of gate lines 8 are arranged parallel to one another. The plurality of data lines 6 and the plurality of gate lines 8 are arranged so as to intersect with one another. The gate lines 8 serve as row scanning lines.

The liquid crystal display device 200 has multiple sets of data lines 6, two in a set. The liquid crystal display device 200 inverts and drives the pixels 42 using one set of data lines 6. Hereinafter, the positive data line 6 in one set of data lines 6 will be referred to as data line 6a, and the negative data line 6 will be referred to as data line 6b. Similarly, the polarity of the switch 1 and the video signal line 5 will be identified as switch 1a, switch 1b, and video signal lines 5a, 5b. Two systems of data lines 6, switches 1, and video signal lines 5 are provided to invert the polarity.

Pixels 42 are arranged at the intersections of data lines 6 and gate lines 8. The pixels 42 are arranged in a matrix. Each pixel 42 is driven by one set of data lines 6 and one gate line 8. For example, if there are n gate lines 8 and 2m data lines 6, the pixels 42 are arranged in a matrix of n rows and m columns. Note that m and n are each integers equal to or greater than 2. The pixels 42 are equipped with a pixel driving circuit for driving the liquid crystal, pixel electrodes, and the like.

The vertical drive circuit 2 performs vertical drive by selecting multiple gate lines 8 for each horizontal scanning period. The vertical drive circuit 2 supplies scanning signals to the multiple gate lines 8. In other words, the vertical drive circuit 2 supplies scanning signals to sequentially select the gate lines 8 from the first row to the nth row. This causes the pixels 42 to be selected row by row. All gate lines 8 are selected within one vertical scanning period. Video signals can be written to the pixels 42 in the selected row.

The horizontal drive circuit 3 performs horizontal drive by driving a plurality of switches 1 within a horizontal scanning period. This causes a video signal to be supplied to a plurality of data lines 6. As described above, two data lines 6a, 6b are connected to a pixel 42 as a set. Therefore, two data lines 6a, 6b are commonly connected to one row of pixels 42.

The data line 6a is connected to the video signal line 5a via the switch 1a. The data line 6b is connected to the video signal line 5b via the switch 1b. The video signal line 5a is supplied with the positive video signal RAMP+. The video signal line 5b is supplied with the negative video signal RAMP-. The horizontal drive circuit 3 controls the switches 1a and 1b.

Therefore, a positive video signal RAMP+ is supplied to one data line 6a of a pair of data lines 6a, 6b, and a negative video signal RAMP- is supplied to the other data line 6b. The positive video signal RAMP+ is a positive voltage with respect to the common potential of the common electrode line, and the negative video signal RAMP- is a negative voltage with respect to the common potential of the common electrode line. The horizontal drive circuit 3 can supply a positive video signal RAMP+ and a negative video signal RAMP- to a selected row of pixels 42. The horizontal drive circuit 3 turns each switch 1 on and off multiple times within a horizontal scanning period. Therefore, the positive video signal RAMP+ and the negative video signal RAMP- are alternately supplied to the pixels 42.

Specifically, the horizontal drive circuit 3 includes a latch circuit 310, a counter 320, a comparator circuit 330, a shift register 360, and a buffer 370. The latch circuit 310 corresponds to the latch circuit 10 in FIG. 1. That is, the latch circuit 310 includes latch circuits 10 for m columns. The latch circuit 310 holds image data DATA of the pixels 42 in the 1st to mth columns.

The comparator circuit 330 corresponds to the comparator circuit 30 in FIG. 1. That is, the comparator circuit 330 has m columns of comparator circuits 30. The output signal OUT from the comparator circuit 30 shown in FIG. 1 controls the switch 1. The counter 320 corresponds to the counter 20 in FIG. 1. Therefore, the counter 320 performs a counting operation according to the counter clock signal CNT_CLOCK.

The shift register 360 sequentially transmits m columns of image data DATA in response to the horizontal clock HCLOCK. After the shift register 360 has held m columns of image data DATA, it outputs it to the latch circuit 310. The latch circuit 310 holds the image data DATA for each column in response to the latch signal LATCH.

As shown in FIG. 1, the comparator circuit 330 compares the latch output A with the counter output B. The comparator circuit 330 controls the pair of switches 1a and 1b. The pair of switches 1a and 1b opens and closes depending on the output signal of the comparator circuit 330. Initially, all switch 1 pairs are closed, so that no video signal is supplied to the pixel 42. When the output signal of the comparator circuit 330 is asserted, the corresponding switch 1 opens. This causes a positive video signal RAMP+ and a negative video signal RAMP- to be applied alternately to the pixel 42. The liquid crystal display device 200 can perform gradation display according to the image data DATA.

The buffer 370 buffers various signals output from an external controller. Because the pixel display unit 50 has a large number of columns, the buffer 370 is used to drive a heavy load. For example, the horizontal clock signal HCLOCK is input to the shift register 360 via the buffer 370. Similarly, the latch signal LATCH is input to the latch circuit 310 via the buffer 370. The counter output from the counter 320 is input to the comparator circuit 330 via the buffer 370.

In this embodiment, the comparator circuit 330 includes the comparator circuit 30 shown in FIG. 1. Therefore, it is possible to omit a buffer for the comparator clock signal input to the comparator circuit 330. In other words, the number of buffers can be reduced according to the number of columns, thereby reducing power consumption. Furthermore, it is possible to suppress timing errors, thereby improving reliability.

The invention made by the inventor has been specifically described above based on the embodiment, but it goes without saying that the invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

REFERENCE SIGNS LIST 1 Switch 2 Vertical drive circuit 3 Horizontal drive circuit 6 Data line 8 Gate line 42 Pixel 50 Pixel display section 100 Drive circuit 10 Latch circuit 20 Counter 30 Comparator circuit 31 Comparator element 32 Clock generation circuit 33 FF circuit 200 Liquid crystal display device 310 Latch circuit 320 Counter 330 Comparator circuit 360 Shift register 370 Buffer

Claims (5)

a comparator element that outputs a match signal indicative of whether a value of the first input signal matches a value of the second input signal;
a flip-flop circuit having a data input terminal and a clock input terminal to which a constant potential is supplied, the flip-flop circuit holding a value of the data input terminal in response to a self-clocking signal input to the clock input terminal;
a clock generating circuit that generates the self-clocked signal based on the output signal from the flip-flop circuit and the coincidence signal; The comparator circuit according to claim 1, wherein the output of the flip-flop circuit changes at the falling edge of the match signal after a reset signal that resets the output of the flip-flop circuit is input. the flip-flop circuit has an inverted output terminal that outputs an inverted output signal;
3. The comparator circuit according to claim 1, wherein the output signal from the flip-flop circuit is the inverted output signal. the clock generation circuit comprises a NAND circuit,
4. The comparator circuit according to claim 3, wherein the match signal from the comparator element and the inverted output signal from the flip-flop circuit are input to the NAND circuit. A comparator circuit according to any one of claims 1 to 4;
a latch circuit that holds image data and outputs the image data as the first input signal to the comparator element;
a counter that performs a counting operation in response to a counter clock signal and outputs a count value to the comparator element as the second input signal.

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