JP7601434B2 - Integrated circuit, computer system and data processing method - Google Patents

Description

This application relates to integrated circuits, computer systems and data processing methods, such as issuing load packets related to vector gather instructions to a memory system.

As exemplified in Patent Document 1, a vector gather instruction is an instruction that sets an address pointer containing an address in a memory system in a vector register, and instructs reading the data pointed to by this address into the vector register. A vector gather instruction is sometimes called a vector load instruction or simply a gather instruction. Typically, a vector gather instruction is broken down into load packets that indicate the reading of one word of data from a memory address, and the broken down load packets are issued to the memory system. At this stage, the relationship between multiple memory addresses is not taken into consideration. A reply packet to the load packet is returned from the memory system for each word of data.

In recent years, efforts have been made to increase the integration and speed of memory systems by making it possible to read and write multiple words of data at a time, rather than just one word. By including multiple words of data to be read within the processing unit of the memory system, it is possible to read multiple words of data in a single process.

Patent No. 2716254 Patent No. 5926754

To increase integration, multi-core systems in which multiple cores and memory systems are connected via an in-chip network are becoming more common. In multi-core systems, frequent data transmissions in the in-chip network can lead to performance degradation. For this reason, it is desirable to reduce the number of load packets and reply packets to avoid or alleviate network congestion. In this case, it is possible to generate load packets that can load multiple words of data at once, and return reply packets for the multiple words of data, thereby reducing the number of load packets and reply packets.

For example, Patent Document 2 describes a method for loading multiple words of data using a limited-range vector memory access instruction. The limited-range vector memory access instruction specifies an instruction that specifies a limited range of the memory system and a vector gather instruction that indicates multiple indexes in the limited range. However, the memory address on the memory system in the vector register is calculated when the instruction is executed. Therefore, it is not possible to determine whether the memory address is included in the limited range of the memory system before the instruction is executed, and to generate an instruction that specifies the limited range and a vector gather instruction that indicates multiple indexes within the limited range.

This application has been made to solve the above-mentioned problems, and its main objective is to improve the performance of a computer system equipped with a memory system.

In order to achieve the above object, an arithmetic circuit according to a first aspect of the present application determines whether a processing unit including a plurality of element areas corresponding to a plurality of memory addresses indicated by an acquired vector gather instruction exists in a memory system, and if the processing unit exists, outputs a load packet to the memory system indicating an element number and offset for each of the element areas in the processing unit, writes a data element included corresponding to the element number of a reply packet input from the memory system to a vector register, and is provided with an address register for storing the memory address, determines whether a processing unit including a plurality of element areas corresponding to a memory address stored in an address register whose usage state is unused exists, and when outputting the load packet, changes the usage state of the address register in which the memory addresses corresponding to the plurality of element areas are stored to used .

A data processing method in an arithmetic circuit according to a second aspect of the present application comprises the arithmetic circuit comprising an address register for storing a memory address, the arithmetic circuit determining whether or not a processing unit including a plurality of element areas each corresponding to a plurality of acquired memory addresses indicated by an acquired vector gather instruction exists in a memory system, and if the processing unit exists, the arithmetic circuit outputs a load packet to the memory system indicating an element number and an offset for each of the element areas in the processing unit, writes a data element included corresponding to the element number of a reply packet input from the memory system to a vector register, determines whether or not a processing unit including a plurality of element areas corresponding to a memory address stored in an address register whose usage state is unused exists, and when outputting the load packet, changes the usage state of the address register in which the memory addresses corresponding to the plurality of element areas are stored to used .

According to one aspect of the present application, it is possible to improve the performance of a computer system.

FIG. 1 is a schematic block diagram showing an example of the configuration of a computer system according to an embodiment of the present invention. 11 is an explanatory diagram showing an example of the operation of a vector gather instruction according to the embodiment; FIG. FIG. 2 is a configuration diagram showing an example of the configuration of a processing unit according to the embodiment; FIG. 2 is a diagram showing an example of a memory address configuration according to the embodiment; FIG. 2 is a schematic block diagram showing an example of the configuration of a core according to the embodiment. 4 is a schematic block diagram showing an example of the configuration of a vector unit according to the present embodiment. FIG. 2 is a schematic block diagram showing a configuration example of a load packet generating circuit according to the present embodiment; FIG. FIG. 2 is a diagram showing a configuration example of a multiple element detection circuit according to the present embodiment. 13 is a diagram showing a first example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. FIG. 13 is a diagram showing a second example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. 13 is a diagram showing a third example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. 13 is a diagram showing a fourth example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. 13 is a diagram showing a fifth example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. 13 is a diagram showing a sixth example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. 13 is a diagram showing a seventh example of a rule for determining a data element to be read by a load packet according to the embodiment; FIG. 13 is a diagram showing an eighth example of a rule for determining a data element to be read by a load packet according to the embodiment; 11 is a diagram illustrating an example of a configuration of a load packet according to the embodiment. FIG. 11 is a diagram illustrating an example of a reply packet according to the embodiment of the present invention. FIG. 11 is an explanatory diagram showing an example of a vector gather operation according to the embodiment; FIG. 11 is an explanatory diagram showing an example of transmission of a memory address from a vector unit to a load packet generation circuit according to the embodiment; FIG. 1 is a schematic block diagram illustrating an arithmetic circuit according to a minimum configuration example of the present embodiment.

Hereinafter, an embodiment of the present application will be described with reference to the drawings. FIG. 1 is a schematic block diagram showing an example of the configuration of a computer system according to this embodiment. The computer system according to this embodiment includes a plurality of cores 101 and a memory system 103. Each of the cores 101 is connected to the memory system 103 by wire so that various data can be transmitted via an in-chip network 102. In this embodiment, the number of cores 101 may be one, or may be two or more. Each of the cores 101 corresponds to a processor core. Each of the cores 101 can perform independent arithmetic processing. Each of the cores 101 includes a logic circuit for interpreting and executing an instruction sequence.

Next, an example of the configuration of the core 501 according to this embodiment will be described. Fig. 5 is a schematic block diagram showing an example of the configuration of the core 501 according to this embodiment. The configuration of the core 501 is similar to the configuration of each core 101 illustrated in Fig. 1. The core 501 includes a scalar unit 502, a vector unit 503, and a load packet generation circuit 505.
The scalar unit 502 is an arithmetic circuit that decodes various instructions provided to it and executes various scalar operations.
The vector unit 503 is an arithmetic circuit that performs various vector operations.
The load packet generating circuit 505 generates a load packet for notifying an instruction to read data, and outputs the generated load packet to the memory system 504.

Next, the vector unit 601 according to this embodiment will be described. Fig. 6 is a schematic block diagram showing an example of the configuration of the vector unit 601 according to this embodiment. The configuration of the vector unit 601 is similar to the configuration of the vector unit 503 exemplified in Fig. 5.
The vector unit 601 includes a vector register file 602 and an arithmetic unit 603. The vector register file 602 includes one or more vector registers. Each vector register includes multiple element registers. The number of vector registers in the vector register file 602 may be any number as long as it is one or more than one. The number of element registers in each vector register may be any number as long as it is more than one. In the following description, a case is exemplified in which the number of vector registers in the vector register file 602 is 64, and the number of element registers in each vector register is 64. It is assumed that the load packet generation circuit 701 can simultaneously read out memory addresses stored in each of the eight element registers from each vector register.

Next, the load packet generating circuit 701 according to this embodiment will be described. Fig. 7 is a schematic block diagram showing an example of the configuration of the load packet generating circuit 701 according to this embodiment. The configuration of the load packet generating circuit 701 is similar to the configuration of the load packet generating circuit 505 exemplified in Fig. 5.
The load packet generation circuit 701 includes a multiple element detection circuit 702 and a load packet issuance circuit 703. The multiple element detection circuit 702 identifies eight memory addresses read from the vector register, and detects the presence or absence of a processing unit including multiple element areas indicated by the identified memory addresses in the memory system.

The load packet issuing circuit 703 generates a load packet to instruct the reading of multiple data elements or the reading of one data element as a result of detection by the multiple element detection circuit 702. The load packet generating circuit 701 issues the generated load packet to the memory system 504. Note that in the following description, the load packet generating circuit 701 mainly exemplifies a case in which it instructs the reading of two or one data element at the same time, but is not limited to this. The load packet generating circuit 701 may also be able to instruct the reading of 3 to N data elements in response to determining the presence of 3 to N data elements (described below) in the same processing unit.

Next, the multiple element detection circuit 702 according to this embodiment will be described. FIG. 8 is a configuration diagram showing an example of the configuration of the multiple element detection circuit 702 according to this embodiment. The multiple element detection circuit 702 includes N address registers A801 to H808 and N(N-1)/2 comparators 809 to 816. N is a natural number corresponding to the number of read addresses. The number of read addresses is the number of addresses that the multiple element detection circuit 702 is instructed to simultaneously read from the vector register. In the example of FIG. 8, the number of read addresses N is 8. The number of read addresses is not limited to 8, and may be 2 to 7 or less, or 9 or more.

The multiple element detection circuit 702 writes the eight memory addresses read from the vector register to the address registers A801 to H808. The multiple element detection circuit 702 determines whether or not a processing unit containing multiple element areas corresponding to each memory address exists based on the memory addresses stored in each of the eight address registers A801 to H808. In the example of FIG. 8, the presence or absence of a processing unit containing element areas corresponding to memory addresses stored in any two of the address registers A801 to H808 is determined. Here, 21 ((8-1) x (8-2)/2) comparators compare the upper addresses of each pair of memory addresses, each consisting of two memory addresses. The multiple element detection circuit 702 can determine whether or not the element areas corresponding to each of the two memory addresses belong to the same processing unit depending on whether or not the upper addresses are the same. The processing unit is specified by the upper addresses determined to be the same.

Note that a processing unit refers to a unit in which data can be read and written at one time in memory system 504. In this embodiment, one processing unit allows access to multiple data elements. In the example of FIG. 3, processing unit 301 in memory system 504 occupies a 64-byte memory area. Processing unit 301 is divided into 8 words, and each word occupies an 8-byte memory area. The area of each word is indicated by an offset. Data element A 302 is indicated by offset 0x8. Data element B 303 is indicated by offset 0x20.

The upper address refers to a portion of the multiple bits that make up a memory address, represented by the upper bits. The other portion of the memory address, represented by the lower bits, corresponds to the offset. In the example of FIG. 4, memory address 401 is represented by 64 bits. Upper address 403 is represented by 58 bits, and indicates the processing unit of the memory system. Offset 402 is represented by 6 bits, and indicates an individual element area within one processing unit. Therefore, the fact that upper addresses 403 match between multiple memory addresses means that the element areas associated with each memory address exist in the same processing unit.

Next, an example of a load packet according to this embodiment will be described. The load packet is issued to the memory system 504 by the load packet issuing circuit 703. FIG. 17 is a configuration diagram showing an example of a load packet according to this embodiment. The offset or the number of element numbers (hereinafter sometimes referred to as the "number of elements") each corresponds to the number of memory addresses. In the example of FIG. 17, both are two.

Load packet 1701 includes upper address 1702, offset 0 1703, offset 1 1704, element number 0 1705, element number 1 1705, type 1707, and vector register number 1708. Type 1707 indicates the number of valid elements. In this example, the number of elements is specified as two or one. Vector register number 1708 indicates the vector register from which the memory address is obtained. In other words, load packet 1701 includes a command to instruct memory system 504 to read data elements from element areas specified by two offsets 0 and 1, respectively, of the processing unit specified by upper address 1702. Element numbers 0 and 1 correspond to two data elements or element areas, respectively, and are included in a reply packet that is a response to load packet 1701.

Next, an example of a reply packet according to this embodiment will be described. The reply packet is returned to the vector unit 503 by the memory system 504. FIG. 18 is a configuration diagram showing an example of a reply packet according to this embodiment. In the example of FIG. 18, the number of elements is two.

Reply packet 1801 is configured by storing element number 0 1802, element number 1 1803, data 0 1804, data 1 1805, and vector register number 1806. Data 0 1804 and data 1 1805 correspond to element number 0 1802 and element number 1 1803, respectively, and are element data stored in the element area indicated by offset 0 1703 and offset 1 1704 of the processing unit indicated by upper address 1702. Type 1807 indicates the number of valid elements. For example, when type 1807 is set to 2, it is indicated that element number 0 1802, element number 1 1803, data 0 1804, and data 1 1805 are all valid. For example, if type 1807 is set to 1, it indicates that the first pair of element number 0 1802 and data 0 1804 is valid, and the subsequent pair of element number 1 1803 and data 1 1805 is invalid.

Next, an example of the operation of the vector gather instruction according to this embodiment will be described. FIG. 2 is an explanatory diagram showing an example of the operation of the vector gather instruction according to this embodiment. The vector gather instruction is an instruction to read multiple data elements from data stored in a memory system and write the read data elements to a vector register. In the example of FIG. 2, n memory addresses A0 202, A1 203, A2 204, ..., An-1 206 are stored in vector register V0 201. The vector gather instruction instructs reading element data D0 208, D1 209, D2 210, ..., Dn-1 212 stored in each of the element areas specified by the n memory addresses of memory system 207, and writing the read element data to vector register V1 213.

Figure 19 is an explanatory diagram showing an example of the vector gather operation according to this embodiment. In the following explanation, the vector gather operation will be performed by the core 501 illustrated in Figure 5 as an example. The scalar unit 1901 decodes an instruction provided to itself. When the decoded instruction is a vector gather instruction, the scalar unit 1901 generates vector gather instructions 1904 and 1905 based on the vector gather instruction. The scalar unit 1901 issues the generated vector gather instructions 1904 and 1905 to the vector unit 1902 and the load packet generation circuit 1903, respectively. The vector gather instruction 1904 indicates the vector register number of the vector register in which the memory address indicating the data read destination is stored, and the vector register in which the gather result is stored, i.e., the vector register number of the vector register to which the data is written.

A vector gather instruction 1904 is input to the vector unit 1902 from the scalar unit 1901. The vector unit 1902 reads a memory address 1906 stored in a vector register specified by the vector register number of the vector gather instruction 1904. The vector unit 1902 sends the read memory address 1906 to the load packet generation circuit 1903. In the example of FIG. 19, eight memory addresses 1906 are read at a time, and the read memory addresses 1906 are sent to the load packet generation circuit 1903.

The load packet generation circuit 1903 receives a memory address 1906 from the vector unit 1902. The load packet generation circuit 1903 generates a load packet 1908 based on the memory address 1906. The load packet generation circuit 1903 identifies the eight memory addresses 1906 read from the vector register, and detects the presence or absence of a processing unit including multiple element areas indicated by the identified memory addresses 1906 in the memory system 1907. As a result of the detection, the load packet issue circuit 703 generates a load packet 1908 for instructing the reading of multiple data elements at once or the reading of one data element. The data structure of the load packet 1908 can be the same as the data structure of the load packet 1701 illustrated in FIG. 17. The load packet generation circuit 1903 sends the generated load packet 1908 to the memory system 1907.

A load packet 1908 is input to the memory system 1907 from the load packet generation circuit 1903. The memory system 1907 reads a data element from an element area specified by the offset notified in the load packet 1908. The memory system 1907 generates a reply packet 1909 including the read data element and an element number associated with the offset. The data structure of the reply packet 1909 can be similar to the data structure of the reply packet 1801 illustrated in FIG. 18. The memory system 1907 returns the generated reply packet 1909 to the vector unit 1902 as a response to the load packet 1908.
The vector unit 1902 writes the data elements stored in the reply packet 1909 received from the memory system 1907 into the vector register.

An example of a write operation to a vector register will now be described in more detail.
20 is an explanatory diagram showing an example of transmission of a memory address from the vector unit 1902 to the load packet generation circuit 1903 according to this embodiment. The vector unit 1902 reads an address element from an element area in which a memory address specified by a vector gather instruction is stored, from a vector register in the vector register file 2001. An address element is a data fragment that constitutes an element of a memory address. The vector unit 1902 transmits the read address element to the load packet generation circuit 1903. In the example of FIG. 20, 64 address elements 0 2002 to 63 2003 are sequentially read from the vector register in groups of eight elements and transmitted to the load packet generation circuit 1903.

The load packet generation circuit 1903 writes the address elements input from the vector unit 1902 in groups of eight elements as memory addresses to address registers A 2004 to H 2005. The load packet generation circuit 1903 may hold usage status information indicating the usage status of the address registers. For example, the load packet generation circuit 1903 resets the usage status indicated in the usage status information related to the write destination address register to unused each time it writes a memory address. The load packet generation circuit 1903 may set the usage status indicated in the usage status information of the address register that stores the memory address used to generate the load packet to used, among the address registers that store memory addresses.

The multiple element detection circuit (FIG. 7) of the load packet generation circuit 1903 detects whether the element areas indicated by each pair of two memory addresses out of the eight memory addresses stored in the address registers A 2004-H 2005 belong to the same processing unit. FIGS. 9-16 illustrate examples of the determination rules used by the load packet generation circuit 1903 to determine the data elements to be read by one load packet based on the comparison results of each comparator. In this determination, it is determined whether two data elements or one data element is to be read. The load packet generation circuit 1903 executes a determination based on the determination rules illustrated in each of FIGS. 9-16, generates a load packet based on each determination result, and transmits the generated load packet to the memory system 1907.

The judgment rule illustrated in FIG. 9 is used to generate a load packet based on the result of a comparison between the memory address stored in address register A and one of the memory addresses stored in address registers B to H. The judgment rule instructs the next process (A1) to (A8) depending on the comparison result.

(A1) When the upper address of address register A and the upper address of address register B match, a load packet is generated to obtain a data element stored in the memory address stored in each of address register A and address register B, and the usage status indicated in the usage status information of address register B is changed to used.
(A2) When the upper address of address register A and the upper address of address register C match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register A and address register C, respectively, and the usage status indicated in the usage status information of address register C is changed to used.

(A3) When the upper address of address register A and the upper address of address register D match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register A and address register D, respectively, and the usage status indicated in the usage status information of address register D is changed to used.
(A4) When the upper address of address register A and the upper address of address register E match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register A and address register E, respectively, and the usage status indicated in the usage status information of address register E is changed to used.

(A5) When the upper address of address register A and the upper address of address register F match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register A and address register F, respectively, and the usage status indicated in the usage status information of address register F is changed to used.
(A6) When the upper address of address register A and the upper address of address register G match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register A and address register G, respectively, and the usage status indicated in the usage status information of address register G is changed to used.

(A7) When the upper address of address register A and the upper address of address register H match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register A and address register H, respectively, and the usage status indicated in the usage status information of address register H is changed to used.
(A8) When the upper address of address register A does not match any of the upper addresses of address registers B to H, a single load packet is generated to obtain only the data element stored at the memory address stored in address register A.

The judgment rule illustrated in FIG. 10 is used to generate a load packet based on the result of comparing the memory address stored in address register B with one of the memory addresses stored in address registers C to H. This judgment rule is executed when the usage status indicated in the usage status information of address register B indicates unused, and is not executed when the usage status indicates used. This judgment rule instructs the following processes (B1) to (B7).

(B1) When the upper address of address register B and the upper address of address register C match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register B and address register C, and the usage status indicated in the usage status information of address register C is changed to used.
(B2) When the upper address of address register B and the upper address of address register D match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register B and address register D, respectively, and the usage status indicated in the usage status information of address register D is changed to used.

(B3) When the upper address of address register B and the upper address of address register E match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register B and address register E, respectively, and the usage status indicated in the usage status information of address register E is changed to used.
(B4) When the upper address of address register B and the upper address of address register F match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register B and address register F, respectively, and the usage status indicated in the usage status information of address register F is changed to used.

(B5) When the upper address of address register B and the upper address of address register G match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register B and address register G, and the usage status indicated in the usage status information of address register G is changed to used.
(B6) When the upper address of address register B and the upper address of address register H match, a load packet is generated to obtain the data elements stored at the memory addresses stored in address register B and address register H, respectively, and the usage status indicated in the usage status information of address register H is changed to used.
(B7) When the upper address of address register B does not match any of the upper addresses of address registers C to H, a single load packet is generated to obtain only the data element stored at the memory address stored in address register B.

The judgment rule illustrated in FIG. 11 is used to generate a load packet based on the result of comparing the memory address stored in address register C with one of the memory addresses stored in address registers D to H. This judgment rule is executed when the usage status indicated in the usage status information of address register C indicates unused, and is not executed when the usage status indicates used. This judgment rule instructs the following processes (C1) to (C6).

(C1) When the upper address of address register C and the upper address of address register D match, a load packet is generated to obtain a data element stored in the memory address stored in each of address register C and address register D, and the usage status indicated in the usage status information of address register D is changed to used.
(C2) When the upper address of address register C and the upper address of address register E match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register C and address register E, respectively, and the usage status indicated in the usage status information of address register E is changed to used.

(C3) When the upper address of address register C and the upper address of address register F match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register C and address register F, respectively, and the usage status indicated in the usage status information of address register F is changed to used.
(C4) When the upper address of address register C and the upper address of address register G match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register C and address register G, respectively, and the usage status indicated in the usage status information of address register G is changed to used.

(C5) When the upper address of address register C and the upper address of address register H match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register C and address register H, respectively, and the usage status indicated in the usage status information of address register H is changed to used.
(C6) When the upper address of address register C does not match any of the upper addresses of address registers D to H, a single load packet is generated to obtain only the data element stored at the memory address stored in address register C.

The judgment rule illustrated in FIG. 12 is used to generate a load packet based on the result of comparing the memory address stored in address register D with one of the memory addresses stored in address registers E to H. This judgment rule is executed when the usage status indicated in the usage status information of address register D indicates unused, and is not executed when the usage status indicates used. This judgment rule instructs the following processes (D1) to (D5).

(D1) When the upper address of address register D and the upper address of address register E match, a load packet is generated to obtain a data element stored in the memory address stored in each of address register D and address register E, and the usage status indicated in the usage status information of address register E is changed to used.
(D2) When the upper address of address register D and the upper address of address register F match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register D and address register F, respectively, and the usage status indicated in the usage status information of address register F is changed to used.

(D3) When the upper address of address register D and the upper address of address register G match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register D and address register G, respectively, and the usage status indicated in the usage status information of address register G is changed to used.
(D4) When the upper address of address register D and the upper address of address register H match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register D and address register H, respectively, and the usage status indicated in the usage status information of address register H is changed to used.
(D5) When the upper address of address register D does not match any of the upper addresses of address registers E to H, a single load packet is generated to obtain only the data element stored at the memory address stored in address register D.

The judgment rule illustrated in FIG. 13 is used to generate a load packet based on the result of comparing the memory address stored in address register E with one of the memory addresses stored in address registers F to H. This judgment rule is executed when the usage status indicated in the usage status information of address register E indicates unused, and is not executed when the usage status indicates used. This judgment rule instructs the following processes (E1) to (E4).

(E1) When the upper address of address register E and the upper address of address register F match, one load packet is generated to obtain the data elements stored in the memory addresses stored in address register E and address register F, respectively, and the usage status indicated in the usage status information of address register F is changed to used.
(E2) When the upper address of address register E and the upper address of address register G match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register E and address register G, respectively, and the usage status indicated in the usage status information of address register G is changed to used.

(E3) When the upper address of address register E and the upper address of address register H match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register E and address register H, respectively, and the usage status indicated in the usage status information of address register H is changed to used.
(E4) When the upper address of address register E does not match any of the upper addresses of address registers F to H, a single load packet is generated to obtain only the data element stored at the memory address stored in address register E.

The judgment rule illustrated in FIG. 14 is used to generate a load packet based on the result of comparing the memory address stored in address register F with one of the memory addresses stored in address registers G to H. This judgment rule is executed when the usage status indicated in the usage status information of address register F indicates unused, and is not executed when the usage status indicates used. This judgment rule instructs the following processes (F1) to (F3).

(F1) When the upper address of address register F and the upper address of address register G match, one load packet is generated to obtain the data elements stored in the memory addresses stored in address register F and address register G, and the usage status indicated in the usage status information of address register G is changed to used.
(F2) When the upper address of address register F and the upper address of address register H match, a load packet is generated to obtain the data elements stored at the memory addresses stored in address register F and address register H, respectively, and the usage status indicated in the usage status information of address register H is changed to used.
(F3) When the upper address of address register F does not match any of the upper addresses of address registers G and H, a single load packet is generated to obtain only the data element stored at the memory address stored in address register F.

The judgment rule illustrated in FIG. 15 is used to generate a load packet based on the result of comparing the memory address stored in address register G with the memory address stored in address register H. This judgment rule is executed when the usage status indicated in the usage status information of address register G indicates unused, and is not executed when the usage status indicates used. This judgment rule instructs the following processes (G1) and (G2).

(G1) When the upper address of address register G and the upper address of address register H match, a load packet is generated to obtain the data elements stored in the memory addresses stored in address register F and address register H, and the usage status indicated in the usage status information of address register H is changed to used.
(G2) When the upper address of address register G does not match the upper address of address register H, one load packet is generated to obtain only the data element stored at the memory address stored in address register G.

The judgment rule illustrated in FIG. 16 is executed when the usage status indicated in the usage status information of address register G indicates unused, and is not executed when the usage status indicates used. This judgment rule generates one load packet for obtaining only the data element stored in the memory address stored in address register G.

The load packet issuing circuit (FIG. 7) of the load packet generating circuit 1903 generates a load packet in accordance with the result of the determination made by the above-mentioned determination rule, and sends the generated load packet to the memory system 1907 .
When generating a load packet for reading two data elements, the load packet issuing circuit includes offsets 0 and 1 and element numbers 0 and 1 as the offsets and element numbers of the two specified memory addresses, respectively, in association with each other. The load packet issuing circuit also includes the upper addresses of those memory addresses and the number of elements related to reading, 2, as the type in the load packet.

When generating a load packet for reading one data element, the load packet issuing circuit includes offset 0 and element number 0 of the identified memory address in the load packet, and also includes the upper address of the memory address and the number of elements to be read, 1, as the type. In addition, the load packet issuing circuit extracts the vector register number to be written to from the vector gather instruction, and includes the extracted vector register number in the load packet.

The memory system 1907 identifies the processing unit indicated by the upper address stored in the load packet input from the load packet generation circuit 1903. The memory system 1907 determines whether to read two data elements or one data element from the identified processing unit based on the type stored in the load packet. The memory system 1907 identifies the element area from which to read the data element in the processing unit using the offset stored in the load packet. The memory system 1907 generates a reply packet including the element number associated with the offset in the load packet and the data element read from the element area identified based on the offset. Here, the memory system 1907 includes the type and vector register number stored in the load packet in the reply packet. The memory system 1907 sends the generated reply packet to the core (FIG. 5) that is the input source of the load packet.

The vector unit of the core (Figure 5) determines whether to write two data elements or one data element based on the type described in the reply packet received from the memory system 1907. The vector unit reads the data element corresponding to each vector register number and element number from the received reply packet. The vector unit writes the data element corresponding to the element area specified by the element number of the vector register specified by the vector register number.

In the above explanation, as shown in FIG. 17, a type indicating the number of elements of a data element is included in the load packet as an example, but this is not limited to this. The load packet generation circuit 1903 may generate a load packet including a validity bit indicating whether or not the element number is valid, in association with each element number other than element number 0 (for example, element number 1), instead of the type. The memory system 1907 to which the load packet is sent can determine the validity of each element number based on the validity bit described in the load packet, and determine whether or not element data needs to be read from the element area indicated by the corresponding offset. A variety of validity patterns can be indicated using multiple element numbers, rather than specifying the number of valid elements by type and specifying the element numbers of the number of elements indicated in the storage order in the load packet.

As shown in FIG. 18, the reply packet includes the type, but this is not limiting. Instead of the type, the memory system may generate a reply packet including a validity bit associated with each element number other than element number 0. The vector unit of the core to which the reply packet is sent can determine the validity of each element number based on the validity bit written in the received reply packet, and determine whether or not it is necessary to write the corresponding element data.

Next, an example of a minimum configuration according to this embodiment will be described. FIG. 21 is a schematic block diagram showing an arithmetic circuit 2102 according to an example of a minimum configuration according to this embodiment. The arithmetic circuit 2102 determines whether or not a processing unit including multiple element areas each corresponding to an acquired memory address exists in the memory system 2104. If such a processing unit exists, the arithmetic circuit 2102 outputs a load packet indicating the element number and offset for each element area in the processing unit to the memory system 2104. The arithmetic circuit 2102 writes the data elements included corresponding to the element numbers of the reply packet input from the memory system 2104 to the vector register 2106.

According to this configuration, when a processing unit including multiple element areas corresponding to a memory address specified by an instruction exists in the memory system 2104, the arithmetic circuit 2102 issues a load packet indicating the offset of the element area in the processing unit to the memory system 2104. The arithmetic circuit 2102 can also obtain data elements read from each element area by a reply packet obtained in response to the load packet, and write the data elements to the vector register 2106. Multiple data elements stored in an element area can be read by issuing one load packet. Therefore, the number of load packets and the number of reply packets can be reduced compared to the case of reading one data element each. Therefore, the load on the in-chip network connecting the arithmetic circuit 2102 and the memory system 2104 is reduced, and the performance of a computer system including the arithmetic circuit 2102 and the memory system 2104 can be improved.

This embodiment may be realized as a computer system including an arithmetic circuit 2102 and a memory system 2104. The memory system 2104 reads data elements for each offset specified by the load packet from a processing unit that includes multiple element areas corresponding to a specified memory address, and generates a reply packet that includes the data elements and element numbers corresponding to the offsets.

Each memory address has an upper address and an offset, and when the upper addresses are identical between multiple memory addresses, the arithmetic circuit 2102 may determine that there is a processing unit that includes multiple element areas corresponding to each of the multiple memory addresses, and may include the upper addresses that are determined to be identical in the load packet.
According to this configuration, the upper address is used to determine whether or not there is a processing unit having multiple element areas corresponding to the specified memory address, and the upper address indicating the processing unit is notified to the memory system 2104. Therefore, the memory system 2104 can easily identify the processing unit related to reading of the data elements.

The arithmetic circuit 2102 may include in the load packet the number of elements of memory addresses having the same upper address.
With this arrangement, memory system 2104 is informed of the number of valid data elements to be read.

The arithmetic circuit 2102 may include a validity flag in the load packet that indicates the validity of the element number.
With this arrangement, memory system 2104 is informed of valid data elements to be read.

The arithmetic circuit 2102 may include an address register for storing a memory address, and may determine whether or not there is a processing unit that includes multiple element areas corresponding to a memory address stored in the address register whose usage state is unused. When outputting a load packet, the usage state of the address register in which the memory addresses corresponding to the multiple element areas are stored may be changed to used.
According to this configuration, it is possible to avoid reading a data element again from a memory address designated as a target for reading a data element by outputting a load packet.

The arithmetic circuit 2102 may include the vector register number of the vector register in the load packet. Also, the present embodiment may be realized as a computer system including such an arithmetic circuit and a memory system 2104.
With this configuration, the memory system 2104 can be notified of the vector register number to which the data element is to be written, and a reply packet can be generated that includes the vector register number along with the data element to be read. When writing a data element, the vector register to which the data element is to be written can be specified by referring to the reply packet, without managing the reception status of the reply packet in response to the transmission of the load packet.

The above-mentioned vector gather instruction is often executed when executing an application program (hereinafter referred to as "application") related to matrix operations. The matrix to be operated on is generally a sparse matrix rather than a dense matrix. A sparse matrix is a matrix with few non-zero elements. Therefore, the operation performance of the sparse matrix vector product tends to dominate the operation performance of the entire application. When performing a sparse matrix vector product, a computer system may store only the non-zero elements of the sparse matrix in a contiguous area of the memory system. In this case, access to the non-zero elements stored in the memory system is contiguous access. On the other hand, access to the vector stored in the memory system is non-contiguous access. This is because the elements of the vector corresponding to the non-zero elements of the sparse matrix are accessed. In this case, the vector gather instruction may be used to access the vector. This embodiment improves the performance of the vector gather instruction, thereby realizing a computer system with high sparse matrix vector performance.

Although several embodiments of the present application have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents as set forth in the claims, as well as in the scope and gist of the invention.

101...core, 102...intra-chip network, 103...memory system, 201, 213...vector register, 207...memory system, 301...processing unit, 401...memory address, 402...offset, 403...upper address, 501...core, 502...scalar unit, 503...vector unit, 504...memory system, 505...load packet generation circuit, 601...vector unit, 602...vector register file, 603...arithmetic unit, 701...load packet generation circuit, 702...multiple element detection circuit, 703...load packet issuance circuit, 801-808...address register, 810-816...comparator, 1901...scalar unit, 1902...vector unit, 1903...load packet generation circuit, 1907...memory system, 2001...vector register file, 2004, 2005...address register, 2102...arithmetic circuit, 2104...memory system, 2106...vector register

Claims (8)

determining whether or not a processing unit including a plurality of element areas respectively corresponding to a plurality of memory addresses designated by the obtained vector gather instruction exists in the memory system;
If the processing unit exists, outputting a load packet to the memory system indicating an element number and an offset for each element area in the processing unit;
writing a data element included in a reply packet input from the memory system corresponding to the element number into a vector register;
an address register for storing the memory address;
determining whether or not there is a processing unit including a plurality of element areas corresponding to a memory address stored in an address register whose usage state is unused;
When the load packet is output, the usage state of the address register in which the memory addresses corresponding to the plurality of element areas are stored is changed to "used."
Arithmetic circuit. Each of the memory addresses has an upper address and an offset,
When multiple memory addresses have the same upper address,
determining that there is a processing unit including a plurality of element areas corresponding to each of the plurality of memory addresses;
The arithmetic circuit according to claim 1 , wherein the load packet includes the same upper address. The arithmetic circuit according to claim 1 , wherein the load packet includes the number of elements of the memory addresses having the same upper address. The arithmetic circuit according to claim 1 , wherein the load packet includes a validity flag indicating validity of the element number. The arithmetic circuit according to claim 1 , wherein the load packet includes a vector register number of the vector register. A computer system comprising an arithmetic circuit and a memory system,
The arithmetic circuit includes:
determining whether or not a processing unit including a plurality of element regions respectively corresponding to a plurality of memory addresses designated by the obtained vector gather instruction exists in the memory system;
If the processing unit exists, outputting a load packet to the memory system indicating an element number and an offset for each element area in the processing unit;
writing a data element included in a reply packet input from the memory system corresponding to the element number into a vector register;
The memory system includes:
reading data elements from said processing unit at each offset indicated by said load packet;
generating said reply packet including said data element and an element number corresponding to said offset. 7. The computer system of claim 6, further comprising a plurality of said arithmetic circuits for including in said load packet a vector register number of said vector register . A data processing method in an arithmetic circuit, comprising the steps of:
the arithmetic circuit includes an address register for storing a memory address;
The arithmetic circuit comprises:
determining whether or not a processing unit including a plurality of element areas respectively corresponding to a plurality of memory addresses designated by the obtained vector gather instruction exists in the memory system;
If the processing unit exists, outputting a load packet to the memory system indicating an element number and an offset for each element area in the processing unit;
writing a data element included in a reply packet input from the memory system corresponding to the element number into a vector register;
determining whether or not there is a processing unit including a plurality of element areas corresponding to a memory address stored in an address register whose usage state is unused;
When the load packet is output, the usage state of the address register in which the memory addresses corresponding to the plurality of element areas are stored is changed to "used."
Data processing methods.

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