JP7609966B2 - Wiring structure of control line, railway power converter having the same, and control line laying method - Google Patents

Description

The present invention relates to a wiring structure for a control line, a railway power converter having the same, and a method for laying a control line.

In recent years, power converters that convert power between AC and DC, or between AC and AC, are widely used in power electronics equipment for railways, electric vehicles, wind power generation, etc. These power converters use semiconductor elements called power devices that are capable of controlling high voltages and large currents, and high-voltage power converters in particular use power devices called IGBTs (Insulated Gate Bipolar Transistors). IGBTs are semiconductor elements that combine the advantages of MOS gate devices, such as high-speed switching, with the advantages of bipolar devices, such as low conduction resistance.

Various technologies have been developed to reduce the losses of the IGBT mentioned above. For example, there is a technology that reduces the switching losses of the IGBT by providing multiple gate electrodes and applying voltages to them in a specified sequence. These elements are also called multi-gate semiconductor elements because they have multiple gates. Patent Document 1 describes a dual-gate IGBT. A dual-gate IGBT is a power semiconductor element that has two gate terminals (a switching gate Gs and a carrier control gate Gc) for one collector terminal and one emitter terminal. By controlling the gate signals input to the two gate terminals, it is possible to reduce switching losses more than with conventional IGBTs. Another example is the MOS-controlled diode described in Patent Document 2. In order to reduce diode losses, a MOS-structured insulating gate Gd is provided in the diode, and the amount of charge inside can be controlled by applying a gate voltage to this gate. This is the MOS-controlled diode.

JP 2019-161720 A JP 2015-204723 A

As will be described later, in IGBTs, it is necessary to reduce the inductance of the gate wiring. For this reason, the gate wiring and auxiliary emitter wiring (hereinafter, both are referred to as "control lines") are often placed close to each other, and sometimes even twisted together. Furthermore, in the case of multi-gate IGBTs, since there are multiple gate wirings, simply placing them adjacent to the auxiliary emitter wiring makes it difficult in terms of layout to place all the gate wirings and auxiliary emitter wirings at the same distance, resulting in differences in inductance for each gate wiring.

When differences in inductance occur, the operational delay of multiple gates varies, making it difficult to control multi-gate IGBTs with precision. The present invention has been made to solve the above problem, and its purpose is to provide a wiring structure for control lines that reduces inductance evenly.

The present invention, which solves the above-mentioned problems, is a wiring structure of a control line connecting a multi-gate semiconductor element having a main terminal pair and a plurality of control terminals that control the current flowing through the main terminal pair to a gate driver that controls the current flowing through the main terminal pair with a control voltage applied to the control terminals, and has a first current path and a second current path connected between a terminal including the control terminal and the gate driver, and the first current path and the second current path are laid adjacent to each other so as to cancel out the electromagnetic fields formed by the currents flowing through them.

According to the present invention, a wiring structure for control lines can be provided that reduces inductance evenly.

1 is a circuit diagram of an inverter using a power semiconductor element to which the present invention is applied. 1 is a circuit diagram of an inverter employing a dual-gate IGBT to which the present invention is applied. 1 is a circuit diagram of an inverter employing a dual-gate IGBT and a MOS control diode to which the present invention is applied. 1A and 1B are a perspective view and a schematic cross-sectional view showing a wiring structure of a control line according to a first embodiment of the present invention; FIG. 1 is a diagram illustrating the principle of the present invention. 11A and 11B are a perspective view and a schematic cross-sectional view showing a wiring structure of a control line according to a second embodiment of the present invention. 11A and 11B are a perspective view and a schematic cross-sectional view showing a wiring structure of a control line according to a third embodiment of the present invention. 13A and 13B are a perspective view and a schematic cross-sectional view showing a wiring structure of a control line according to a fourth embodiment of the present invention. FIG. 13 is a perspective view showing a wiring structure of a control line according to a fifth embodiment of the present invention.

The configuration of a power converter to which the present invention is applicable will be described with reference to Figures 1 to 3. Note that the two-level three-phase inverter shown below is merely an example, and the present invention can also be applied to three-level as well as single-phase inverters or AC-DC converters. Figure 1 is a circuit diagram of an inverter using power semiconductor elements to which the present invention is applicable.

That is, Figure 1 shows an example of a two-level three-phase inverter as a power converter that performs variable speed control of a three-phase motor 003. Such high-voltage, high-current three-phase inverters generally use IGBTs 011g-032g and diodes 011d-032d as power semiconductor elements. The IGBTs 011g-032g can be switched between conductive and non-conductive states by inputting an on/off signal to the gate terminal, thereby controlling the voltage and current of the inverter's main circuit.

For example, if the gate signal of the upper arm IGBT 011g is on and the lower arm IGBT 012g is off, the upper arm is conductive and so a voltage equal to the DC voltage on the input side is output to the inverter output (terminal) 010. A flywheel diode 011d is connected in parallel to the IGBT 011g. For example, when the upper arm IGBT 011g is on and current is flowing from the IGBT 011g to the motor side, when the IGBT 011g transitions to off, the current is commutated to the lower arm freewheel diode 012d.

Next, we will explain the gate driver (gate driving circuit) and gate wiring (control line). The gate driver outputs the IGBT on/off signal based on a PWM signal from a microcomputer or other device mounted in the control logic unit. The gate wiring is the means for transmitting this gate driver signal to the power semiconductor element. When implementing this gate wiring, care must be taken with the following points. For example, if the gate wiring is long, the inductance of the gate wiring will increase, which may result in unintended gate voltage fluctuations when noise current flows.

In addition, the influence of magnetic fields generated by the current in the main circuit wiring of the inverter can also cause unnecessary gate voltage fluctuations, leading to malfunction of the IGBT. Furthermore, if the inductance of the gate wiring is large, it takes a long time for the gate driver signal to be transmitted to the power semiconductor element, and this signal delay can sometimes prevent the desired inverter output from being obtained.

Figure 2 is a circuit diagram of an inverter that employs dual-gate IGBTs 011gd-032gd to which the present invention is applied. As shown in the inverter in Figure 2, the practical application of multi-gate semiconductor elements, i.e., dual-gate IGBTs 011gd-032gd, is progressing. Each IGBT 011gd-032gd has a switching gate (first control terminal) Gs, a carrier control gate (second control terminal) Gc, and an auxiliary emitter Es, as well as corresponding terminals. Each of these terminals is connected to gate drivers 011k-032k. These gate wirings (control lines) 221-223 (Figure 4) need to have low inductance to suppress circuit malfunctions and signal delays, just like the gate wiring that drives conventional IGBTs.

Figure 3 is a circuit diagram of an inverter that employs dual-gate IGBTs 011gd-032gd and MOS-controlled diodes 011dm-032dm to which the present invention is applied. This has led to the practical application of MOS-controlled diodes 011dm-032dm as well. The dual-gate IGBTs 011gd-032gd illustrated in Figure 3 have four gate wirings each connecting the semiconductor elements that make up each arm to each gate driver 011k-032k by adding the MOS-controlled gate (third control terminal) Gd. These gate wirings (control lines) 221-224 (Figure 6) also need to have low inductance, like the gate wirings that drive the IGBTs shown in Figure 2.

Example 1 is a wiring structure of a control line that realizes an inverter device using dual-gate IGBTs 011gd and 012gd in the circuit configuration of FIG. 2. FIG. 4 is a perspective view and a schematic cross-sectional view showing the wiring structure of a control line according to Example 1 of the present invention (hereinafter, also referred to as the "wiring structure of Example 1"). The perspective view is a view in which a support base and the like have been removed in order to explain the shape of one pair of upper and lower arms in a power converter, i.e., one phase equivalent to two levels. In FIG. 4, the area circled by a dashed line is a schematic cross-sectional view showing the cross-sectional structure at line A-A', and this is also a view in which insulating supports and the like have been removed in order to explain the relative positions.

In Figure 4, reference numeral 211 denotes a module (hereinafter referred to as the "IGBT module") 211 having implemented therein a dual-gate IGBT 011gd which constitutes the upper arm of the two-level conversion device, and reference numeral 11 denotes a module (hereinafter referred to as the "IGBT module") 11 having implemented therein a dual-gate IGBT 012gd which constitutes the lower arm.

The IGBT module 11 is provided with a collector main terminal 12 and an emitter main terminal 13, which are connected to the main circuit wiring. Although not shown in the figure, the main circuit wiring is often composed of a plate-shaped conductor (bus bar). For example, the collector main terminal 12 of the IGBT module 11 is connected to the emitter main terminal 213 of the IGBT module 211 by a bus bar, and the emitter main terminal 13 is connected to the negative potential side of the power supply by another bus bar. The collector main terminal 212 of the IGBT module 211 is also connected to the high potential side of the power supply by a bus bar.

The IGBT module 11 has three gate terminals: a gate terminal 121 constituting a switching gate Gs, a gate terminal 123 constituting a carrier control gate Gc, and an emitter terminal 122 constituting an auxiliary emitter Es that serves as a reference potential for these terminals.

These three gate terminals are connected to three corresponding gate wiring bus bars 221, 222, and 223. These gate wirings are connected to the gate driver 114 and serve to transmit the drive signal from the gate driver 114 to the IGBT module 11.

The feature of this embodiment 1 is that two gate wiring bus bars 221 and gate wiring bus bar 223 are arranged on opposite sides, facing the auxiliary emitter wiring bus bar 222. The auxiliary emitter wiring bus bar 222 is arranged facing both the gate wiring bus bar 221 and the gate wiring bus bar 223. Because these gate wirings are arranged facing each other, low inductance can be achieved by the principle explained using Figure 5.

Figure 5 shows the cross-sectional structure of the gate wiring (control lines) 221-223 in a direction perpendicular to the A-A' direction in Figure 4 (longitudinal direction of the gate wiring), and the arrows in Figure 4 indicate the gate currents Igc, Igs flowing through each gate wiring bus bar 221-223. The gate currents Igc, Igs that flow when driving the gate of the IGBT have a waveform close to an impulse and therefore contain many high-frequency components.

The higher the frequency of an alternating current, the more pronounced the skin effect is, causing it to flow closer to the surface of the conductor. Due to the same principle as the skin effect, when high-frequency components flow through two parallel conductors, most of the current flows unevenly at biased positions on the cross section of each conductor. Whether the uneven current distribution between the two conductors is close or distant depends on the relative direction of the currents. If the currents flow in opposite directions, it is a close position, and if they flow in the same direction, it is a distant position.

In the first embodiment, the gate current flows in a reciprocating direction between the gate wiring (221, 223) and the auxiliary emitter wiring (222) arranged opposite each other. In other words, because the current flows in the opposite directions, the current is biased in the two wirings in the vicinity of each other. Due to this proximity effect, the current in each conductor flows near the surfaces that are adjacent to each other. In addition, the gate current Igs for driving the switching gate Gs and the gate current Igc for driving the carrier control gate Gc are each passed in the opposite direction to each other through the auxiliary emitter wiring (222) located between the two. Therefore, as shown by the arrows in Figure 5, the current flows in each conductor with a biased distribution near the opposing surfaces.

As described above, the Igs of gate wiring bus bar 221 and the gate current Igs in auxiliary emitter wiring bus bar 222 flow close to each other, so the magnetic flux generated by these currents is cancelled. Similarly, the gate current Igc of gate wiring bus bar 223 and the gate current Igc in auxiliary emitter wiring bus bar 222 flow close to each other, so the magnetic flux generated by these currents is cancelled. In this way, the magnetic flux is cancelled for both gate currents, so the wiring structure of Example 1 has low inductance.

To obtain an effect similar to that of Example 1, it is also possible to provide auxiliary emitter wiring for each gate wiring using a similar principle, and to cancel the magnetic flux by opposing each other to achieve low inductance. In that case, providing auxiliary emitter wiring for each gate wiring increases the number of wirings and complicates the wiring structure.

In contrast, by adopting the wiring structure of Example 1, a small, area-saving bus bar structure can be used to achieve low inductance, and it is possible to prevent delays in gate malfunctions and noise contamination. In addition, according to the wiring structure of Example 1, the gate wiring bus bar Gs and the gate wiring bus bar Gc are arranged on opposite sides, away from each other, via the auxiliary emitter wiring bus bar 222, which makes it possible to prevent interference between them and achieve stable gate operation.

In addition, it is desirable that the wiring structures of Example 1 are each plate-shaped, and that the width W of each wiring bus bar and the distance d between each wiring line satisfy the condition W>d. By satisfying such a condition, it is possible to sufficiently reduce the inductance value of the wiring.

The material of each wiring bus bar is preferably copper, which has a small skin depth for high frequency currents (current is more concentrated on the surface of the opposing bus bars, resulting in a large magnetic flux cancellation effect and small inductance). However, even if aluminum is used from the standpoint of weight reduction, the effect is not significantly reduced compared to copper.

Example 2 is, for example, a control line wiring structure that realizes an inverter device that employs dual-gate IGBTs 011gd-032gd and MOS control diodes 011dm-032dm in the circuit configuration of Figure 3. Example 2 adds a gate terminal 124 and a gate wiring bus bar 224 that control the MOS control diode 012dm to the wiring structure of Example 1. Since other points are similar to Example 1, parts that have the same effect are given the same reference numerals to avoid duplication of explanation.

Figure 6 is an oblique view and a schematic cross-sectional view showing the wiring structure of a control line according to Example 2 of the present invention (hereinafter also referred to as "wiring structure of Example 2"). The oblique view is a view of one pair of upper and lower arms in a power converter, i.e., one phase equivalent to two levels, with the support base etc. removed in order to explain the shape. Also, in Figure 6, the area circled by a dashed line is a schematic cross-sectional view showing the cross-sectional structure on line A-A', and again, with the insulating supports etc. removed in order to explain the relative positions.

The gate wiring bus bar 224, which is a feature of this embodiment 2, is connected to the gate driver 114,012k via a path similar to that of the gate bus bar wiring 221-223 of embodiment 1. In the hierarchical structure of the gate wiring bus bars 221-224 of embodiment 2, the gate wiring bus bar 224 of the MOS control diode 012dm is arranged outside (above on the paper) the gate wiring bus bar 223 of the dual gate IGBT 012gd.

It is desirable that the gate wiring that controls the MOS control diode 012dm also have as low an inductance as possible to suppress noise and malfunction. For this reason, this gate wiring 224 is also structured to run parallel to the auxiliary emitter wiring 222 so as to be laminated. However, between the gate wiring 224 and the auxiliary emitter wiring 222, the gate wiring 223 that drives the dual gate IGBT 012gd is arranged. As a result, the wiring space between the gate wiring 224 and the auxiliary emitter wiring 222 is widened. Therefore, the gate wiring 224 has a small effect of canceling the magnetic flux due to the round-trip current, and its inductance is larger than that of the gate wiring 223. However, the damage is minimal for the following reasons.

A comparison of the gate drive timing of IGBTs 011gd-032gd and the MOS diode control timing in an inverter device is as follows. Firstly, the on or off timing of the gate signals of IGBTs 011gd-032gd causes a large change in the main circuit voltage (or main circuit current) applied to the IGBTs. In contrast, the on or off timing of the MOS controlled diodes 011dm-032dm causes only a small change in the main circuit voltage (or current) applied to these diodes. Therefore, the noise induced in the gate wiring by the on or off timing of the MOS controlled diodes 011dm-032dm is very small.

In this way, when comparing partial inductance, it does not matter if the gate wiring 224 of the MOS control diode 012dm is larger than the gate wiring 223 of the IGBT. Therefore, when considering partial reduction in inductance, it is desirable to minimize the inductance of the gate wiring 223 of the IGBT by placing it as close as possible to the auxiliary emitter wiring 222, as in Example 2.

To minimize the inductance of all gate wiring, it is possible to further increase the auxiliary emitter wiring or to add wiring width and run the gate wiring of the MOS diode parallel to it, but this would increase the area and volume of the gate wiring structure. To prevent this from happening, the structure of Example 2, which can achieve both low inductance and compact size, is effective.

In the second embodiment, three gate wiring bus bars 221, 223, and 224 were described assuming the combined use of dual gate IGBTs 011gd and 012gd and MOS control diodes 011dm and 012dm. Even when using a power semiconductor element having multiple gate terminals, it is possible to achieve both low inductance and compact size of the gate wiring by arranging the gate wiring to which the gate signal that significantly changes the main circuit voltage (or main circuit current) is input near the auxiliary emitter wiring and arranging the other gate wirings outside of that.

Example 3 shown in Figure 7 is characterized in that the control lines of Example 2 shown in Figure 6 are sealed with insulating material 225, and other parts having the same effect are indicated with the same reference numerals. Figure 7 is a perspective view and a schematic cross-sectional view showing the wiring structure of the control lines according to Example 3 of the present invention (hereinafter also referred to as the "wiring structure of Example 3"). The gate wiring bus bars 221-224 themselves are similar to those of Example 2 and are made of copper bars, etc., but in the wiring structure of Example 3, these gate wiring bus bars 221-224 are sealed with insulating material 225.

The gate wiring bus bars 221-224 are made of thin copper plates, etc., and if the wiring length is long, it may be deformed by gravity, which may cause a short circuit between adjacent copper plates. Therefore, as shown in Figure 7, it is effective to seal and hold them with insulating material 225 to maintain the distance between the conductors and to provide and fix them with a support part, ensuring insulation and supporting the components.

Example 4 shown in Figure 8 is a modified version of Example 2 shown in Figure 6. Compared to Example 2, it is characterized in that the gate wiring of the MOS diode is not stacked with other wiring but runs parallel to the auxiliary emitter wiring, and other parts with the same effect are indicated with the same symbols. Figure 8 is a perspective view and a schematic cross-sectional view showing the wiring structure of the control line according to Example 4 of the present invention (hereinafter also referred to as the "wiring structure of Example 4"). The area circled by the dashed line in Figure 8 is a diagram showing the cross-sectional structure at A-A' in Figure 8.

The wiring structure of Example 4 shown in Figure 8, like Example 3 in Figure 7, minimizes the inductance of the gate wiring 221, 223 on the IGBT side, but the inductance of the gate wiring 224 on the diode side is not opposed to the main surface of the auxiliary emitter wiring, so the magnetic flux cancellation is weak and the reduction in inductance is small. However, as described in Example 2, there is no need to minimize the inductance of the gate wiring of the diode, so the wiring structure of Example 4 does not reduce the effect.

Figure 9 is a perspective view showing the wiring structure of the control line according to the fifth embodiment of the present invention (hereinafter also referred to as the "wiring structure of the fifth embodiment"). In the first embodiment (Figure 4) to the fourth embodiment (Figure 8), the wiring structure of the control line was mainly explained, but the fifth embodiment (Figure 9), which is an application of these, also illustrates the wiring structure on the main circuit side. That is, as in the fifth embodiment shown in Figure 9, it is possible to connect the sheet metal main circuit wiring 311, 312, 313 directly above the IGBT modules 11 and 211.

The collector terminal of the upper arm module is connected to main circuit wiring 311, which constitutes the high potential side of the power supply. The emitter terminal of the upper arm module and the collector terminal of the lower arm are connected to main circuit wiring 312, and connected to the motor side as inverter output (terminal) 010 (Figures 1 to 3). The emitter terminal of the lower arm module is connected to main circuit wiring 313, which constitutes the low potential side of the power supply. These main circuit wirings 311, 312, and 313 constitute one phase of the inverter.

A large current flows through the main circuit wiring 311, 312, 313, generating a large magnetic flux in the vicinity. This magnetic flux can generate induced currents in the control lines, potentially causing malfunctions. For example, gate wiring and auxiliary emitter wiring made of copper wires may be used as twisted pair control lines. Twisted pair control lines may not only not be twisted into a twisted pair near the connection points to each terminal, but may also have points where the distance between the two lines is large due to the flexible structure causing the twist to come undone. Such points are susceptible to the effects of magnetic flux.

The twisted pair control wires must be placed at a considerable distance from the main circuit wiring to avoid the effects of magnetic flux. Therefore, it has been difficult to place the main circuit wiring directly above an IGBT module having twisted pair control wires. Therefore, if the control wires are made of a rigid and sturdy bus bar, the distance between the gate wiring and the auxiliary emitter wiring can be kept small and uniform. In Example 5, to more reliably realize such a configuration, the main circuit wirings 311, 312, and 313 are placed directly above the IGBT modules 11 and 211. As a result, the control wires made of bus bars are less susceptible to the effects of magnetic flux caused by the large current flowing through the main circuit wirings 311, 312, and 313.

[supplement]
Here, the control lines of Examples 1 to 4 and the wiring structure of Example 5 are compared with the laminated bus bar. The laminated bus bar is a laminated wiring structure that aims to improve the characteristics for high-speed operation by suppressing abnormal voltages during high-speed switching in power circuits (power converters) that use power semiconductor elements such as IPMs (Intelligent Power Modules) that incorporate drive circuits, etc., in addition to IGBTs. This laminated bus bar forms a multi-layer composite structure by laminating insulating film sheets and metal conductors, and can solve the following problems 1 to 4.

1. High-speed switching due to reduced inductance between conductors 2. Reduced assembly space 3. High reliability of electrical connections 4. Rationalized wiring and reduced assembly time due to reduced number of parts

In this way, the laminated bus bar achieves low inductance for the gate wiring in inverters that use IGBTs. The laminated bus bar employs plate-shaped conductor bars for the gate wiring and auxiliary emitter wiring, and is structured so that these conductor bars are arranged facing each other with a distance d that is narrower than their width W. In other words, width W > distance d. It is also possible to realize a lightweight laminated bus bar that uses an aluminum conductor instead of the typical copper conductor.

This structure cancels the magnetic flux generated by the current flowing back and forth between the gate wiring and the auxiliary emitter wiring, achieving low wiring inductance. To apply this to inverters that use dual-gate IGBTs 011gd to 032gd, it is possible to reduce the inductance of both wirings by providing a pair of laminated bus bars on the switching gate Gs and a pair of laminated bus bars on the carrier control gate Gc.

However, inverters consisting of dual-gate IGBTs 011gd-032gd and MOS control diodes 011dm-032dm (multi-gate semiconductor elements) require more than twice as much wiring as IGBT inverters that do not. Therefore, when laminated bus bars are applied to inverters using multi-gate semiconductor elements, the volume and area required for the wiring structure become an issue. Furthermore, an increase in the number of wires results in an increase in the size of the inverter device (power converter).

Therefore, the wiring structures of Examples 1 to 5 are designed to suppress increases in the volume and area of the gate wiring structure in a power converter that employs a multi-gate semiconductor element, avoiding an increase in the size of the device, and enabling installation with reduced inductance. Note that a multi-gate semiconductor element refers to a power semiconductor element that has multiple gate control terminals Gs, Gc, Gd, and Es, such as dual-gate IGBTs 011gd to 032gd and MOS control diodes 011dm to 032dm.

The wiring structure of the control lines according to the embodiment of the present invention (hereinafter, simply referred to as the "wiring structure") can be summarized as follows.
[1] This wiring structure is a gate wiring and an auxiliary emitter wiring that connect a multi-gate semiconductor element to a gate driver. This multi-gate semiconductor element has a main terminal pair, such as a collector-emitter or a drain-source, and a plurality of gates as corresponding control terminals. The gate driver controls a control current flowing through the main terminal pair by a control voltage applied to the control terminal.

This wiring structure is composed of a control line in which a control current flows between a gate driver and a control terminal via a first current path and a second current path. These first and second current paths are adjacent to each other and are laid so as to cancel out the electromagnetic fields formed by the currents flowing through each of them. This wiring structure allows the inductance to be reduced evenly.

As a result, it is possible to operate multi-gate semiconductor elements with high precision without variation in operational delay in response to commands. This makes it possible to control railway power converters that operate at 1 kV or more with high precision. It is also effective in stabilizing power sources using power converters and driving motors smoothly. In addition, since multiple gate wiring can be consolidated into a single wiring, the space required for wiring can be reduced, contributing to the miniaturization of power converters.

[2] As shown in Example 2 of Figure 6, in the wiring structure of [1] above, the multi-gate semiconductor elements 011gd, 012gd (Figure 2) have a first main terminal 212 on the high potential side, a second main terminal 213 on the low potential side, a plurality of control terminals Gs, Gc, Gd, and a control voltage reference terminal Es that serves as a reference for the voltages applied to these plurality of control terminals Gs, Gc, Gd.

These control lines 221-224 are suitable for an inverter using the dual-gate IGBTs 011gd, 012gd and MOS control diodes 011dm, 012dm shown in the circuit diagram of Figure 3. Each IGBT has multiple control terminals Gs, Gc, Gd, Es, including a switching gate (first control terminal) Gs, a carrier control gate (second control terminal) Gc, an auxiliary emitter Es, and a MOS control gate (third control terminal) Gd. Each of these terminals is connected to the gate driver 114.

The multiple control terminals Gs, Gc, Gd, Es are connected as follows. First, the first control terminal Gs is connected to the gate driver 114,011k by a plate-shaped first control signal conductor 221. Similarly, the second control terminal Gc is connected to the gate driver 114,011k by a plate-shaped second control signal conductor 223. Similarly, the control voltage reference terminal Es is connected to the gate driver 114,011k by a plate-shaped control voltage reference conductor 222. The first control signal conductor 221 and the second control signal conductor 223 are arranged in close proximity to the control voltage reference conductor 222.

Each of the conductors 221, 223, and 222 is plate-shaped, and the principal surfaces of the respective large areas are arranged in the following mutual positional relationship. First, overall, each of the conductors 221 and 223 is arranged parallel to the principal surface of the control voltage reference conductor 222. In addition, the control voltage reference conductor 222 is arranged midway between the first control signal conductor 221 and the second control signal conductor 223.

This wiring structure is suitable for power converters such as inverters. That is, in an inverter using the dual-gate IGBTs 011gd-032gd and MOS control diodes 011dm-032dm shown in the circuit diagram of Figure 3, there are four gate wirings (control lines) connecting the semiconductor elements constituting each arm to the gate driver, but by locating the above-mentioned control voltage reference conductor 222 between the first control signal conductor 221 and the second control signal conductor 223, it is possible to avoid an increase in size.

In this wiring structure, the gate current flows in a reciprocating direction between the gate wiring and the auxiliary emitter wiring, which are arranged opposite each other. In other words, because the currents flow in opposite directions, they flow close to each other between the wirings, and the magnetic flux generated by these currents is cancelled. In this way, because the magnetic flux is cancelled for both gate currents, this wiring structure can have low inductance, thereby suppressing circuit malfunctions and signal delays.

[3] As shown in Example 2 of Figure 6, in the wiring structure of [1] above, each IGBT has a switching gate (first control terminal) Gs, a carrier control gate (second control terminal) Gc, an auxiliary emitter Es, and a MOS control gate (third control terminal) Gd, and each of these terminals is connected to a gate driver 114.

The multiple control terminals Gs, Gc, Gd, Es are arranged in the following mutual positional relationship. The third control terminal (MOS control gate) Gd is connected to the gate driver 114,011k by the plate-shaped third control signal conductor 224. The third control signal conductor 224 is arranged close to the first control signal conductor 221 or the second control signal conductor 223, with their main surfaces parallel. In this way, if the wide main surfaces of the plate-shaped conductors are arranged facing each other, the magnetic flux cancellation effect of nearby reverse currents can be used to further reduce inductance.

[4] As shown in Example 4 of FIG. 8, in the wiring structure of [1] above, the multiple control terminals Gs, Gc, Gd, and Es are arranged in the following mutual positional relationship. The third control terminal (MOS control gate) Gd is a plate-shaped third control signal conductor 224, which is connected to the gate driver 114, 011k. The third control signal conductor 224 is arranged close to the control voltage reference conductor 222. However, the main surface of the third control signal conductor 224 does not need to be arranged parallel to and opposite the main surfaces of other conductors. Therefore, the reverse currents due to the third control signal conductor 224 and the control voltage reference conductor 222 are not close to each other, and the magnetic flux cancellation effect is small, and the inductance reduction is also small, but the reason why this is acceptable is as follows.

When the MOS controlled diodes 011dm to 032dm are turned on or off, the change in the main circuit voltage (or current) applied to the diode is very small. Therefore, the noise induced in the gate wiring when the MOS controlled diodes 011dm to 032dm are turned on or off is very small.

Even when using multi-gate semiconductor elements 011gd to 032gd (Figure 3) having multiple gate terminals Gs, Gc, Gd, and Es, it is possible to achieve both low inductance and compactness in this wiring structure (gate wiring) by arranging the gate wiring to which the gate signal that significantly changes the main circuit voltage (or main circuit current) is input near the auxiliary emitter wiring and arranging the other gate wiring, i.e., the plate-shaped third control signal conductor 224 connected to the third control terminal (MOS control gate) Gd, outside it.

[5] As shown in Example 3 of FIG. 7, in the wiring structure of [2] above, the first control signal conductor 221, the second control signal conductor 223, and the control voltage reference conductor 222 are electrically separated by the insulating material (insulator) 225 and are sealed and held. The wiring structure of Example 3 maintains the distance between the conductors arranged in parallel over the entire length of the line, ensuring insulation and being fixed by a reliable support. As a result, the wiring structure of Example 3, i.e., the gate wiring bus bars 221-224 made of thin copper plates or the like, does not deform due to gravity even when the wiring length is long, and the risk of shorting between adjacent copper plates is avoided.

[6] As shown in Example 5 of Figure 9, in the wiring structure of [1] above, the first main circuit conductor 311 and the second main circuit conductor 312 are arranged directly above the multi-gate semiconductor elements 011gd, 012gd (Figure 3). The first main circuit conductor 311 is plate-shaped and is connected to the first main terminal 212 of the multi-gate semiconductor element 011gd. The second main circuit conductor 312 is also plate-shaped and is connected to the second main terminal 213 of the multi-gate semiconductor element 011gd.

[7] In the wiring structure of [1] above, it is preferable that the width W of the wiring bus bars 221-224 forming it and the distance d between each of the wiring bus bars 221-224 satisfy the condition W>d. By satisfying such a condition, the effect of enhancing the skin effect and the proximity effect is strengthened, and the inductance value of each of the wiring bus bars 221-224 can be sufficiently reduced.

[8] It is advisable to adopt any of the wiring structures [1] to [7] above for a railway power converter that operates at 1 kV or more. A railway vehicle equipped with such a railway power converter can be controlled with high precision, and the effect of improving the ride comfort due to the stabilization of the power supply and the smooth operation of the motor can be obtained. In addition, the power converter itself can be made smaller, and its quality and performance can be improved, leading to cost reduction due to the ease of production and repair.

001: Power supply, 002: Smoothing capacitor, 003: Motor, 010, 020, 030: Inverter output, 011g to 32g: IGBT, 011d to 032d: Diode, 011k to 032k, 114, 214: Gate driver (gate drive circuit), 011gd to 032gd: Dual gate IGBT, 011dm to 032dm: MOS controlled diode, 11, 211: Dual gate IGBT 011gd, 012gd module, 12, 212: collector (first) main terminal, 13, 213: emitter (second) main terminal, 121: switching gate terminal, 122: auxiliary emitter terminal, 123: carrier control gate terminal, 124: gate terminal of MOS control diodes 011dm, 012dm, 221: switching gate wiring bus bar (control line, conductor bar), 222: auxiliary emitter wiring bus bar (control line, conductor bar), 223: Carrier control gate wiring bus bar (control line, conductor bar), 224: (MOS control diode 011dm, 012dm) gate wiring bus bar (control line, conductor bar), 225: insulating material, 311, 312, 313: main circuit wiring, d: distance (between each wiring bus bar 221 to 224), Gs: switching gate (first control terminal), Gc: carrier control gate (second control terminal), Es: auxiliary emitter, W: width (of wiring bus bars 221 to 224)

Claims (9)

A wiring structure of a control line connecting a multi-gate semiconductor element having a main terminal pair and a plurality of control terminals for controlling a current flowing through the main terminal pair to a gate driver that controls a current flowing through the main terminal pair by a control voltage applied to the control terminals,
The multi-gate semiconductor device comprises:
A first main terminal on a high potential side;
A second main terminal on the low potential side;
A plurality of control terminals;
a control voltage reference terminal that serves as a reference for voltages applied to the plurality of control terminals;
Equipped with
Among the plurality of control terminals,
The first control terminal, which is a switching gate , is connected to the gate driver by a plate-shaped first control signal conductor;
The second control terminal, which is a carrier control gate , is connected to the gate driver by a plate-shaped second control signal conductor,
The control voltage reference terminal is connected to a gate driver by a plate-shaped control voltage reference conductor;
the first control signal conductor and the second control signal conductor are adjacent to the control voltage reference conductor;
The main surfaces of the first control signal conductor and the second control signal conductor are
arranged parallel to a major surface of the control voltage reference conductor;
the control voltage reference conductor is disposed intermediate the first control signal conductor and the second control signal conductor;
Among the plurality of control terminals,
The third control terminal, which is a MOS control gate , is connected to the gate driver by a plate-shaped third control signal conductor;
the third control signal conductor is either adjacent to the first control signal conductor or the second control signal conductor so that their principal surfaces are parallel to each other, or adjacent to a control voltage reference conductor;
a first current path and a second current path connected between a terminal including the control terminal and the gate driver;
The first current path and the second current path are laid adjacent to each other so as to cancel out electromagnetic fields formed by currents flowing through the first current path and the second current path.
Wiring structure of control lines. the first control signal conductor, the second control signal conductor and the control voltage reference conductor are electrically isolated by being sealed with an insulator;
The wiring structure of the control line according to claim 1 . a plate-shaped first main circuit conductor connected to a first main terminal of the multi-gate semiconductor device;
a plate-shaped second main circuit conductor connected to a second main terminal of the multi-gate semiconductor element;
is disposed directly above the multi-gate semiconductor element;
The wiring structure of the control lines according to claim 1 . a width W of the wiring bus bar forming the control line and a distance d between the wiring bus bars satisfy the condition W>d;
The wiring structure of the control line according to claim 1 . A railway power converter having the wiring structure of a control line according to any one of claims 1 to 4 . A method for laying a control line connecting a multi-gate semiconductor element having a main terminal pair and a plurality of control terminals for controlling a current flowing through the main terminal pair to a gate driver that controls a current flowing through the main terminal pair by a control voltage applied to the control terminals, comprising:
The multi-gate semiconductor element includes a plurality of control terminals, a control voltage reference terminal that is a reference for voltages applied to the plurality of control terminals, a first main terminal on a high potential side, and a second main terminal on a low potential side;
Among the plurality of control terminals,
The first control terminal, which is a switching gate , is connected to the gate driver using a plate-shaped first control signal conductor;
The second control terminal, which is a carrier control gate , is connected to the gate driver using a plate-shaped second control signal conductor;
the control voltage reference terminal is connected to the gate driver using a plate-shaped control voltage reference conductor;
the first control signal conductor and the second control signal conductor are adjacent to the control voltage reference conductor;
The main surfaces of the first control signal conductor and the second control signal conductor are
arranged parallel to the main surface of the control voltage reference conductor;
The control voltage reference conductor is disposed intermediate the first control signal conductor and the second control signal conductor;
Among the plurality of control terminals,
The third control terminal, which is a MOS control gate , is connected to the gate driver using a plate-shaped third control signal conductor;
the third control signal conductor is arranged adjacent to the first control signal conductor or the second control signal conductor and arranged so that their main surfaces are parallel to each other, or the third control signal conductor is arranged adjacent to a control voltage reference conductor;
a first current path and a second current path are connected between the terminal including the control terminal and the gate driver;
The first current path and the second current path are adjacent to each other and are laid so as to cancel out electromagnetic fields formed by currents flowing through the first current path and the second current path.
Method of laying control lines. the first control signal conductor, the second control signal conductor, and the control voltage reference conductor are sealed with an insulator to ensure electrical insulation and to be fixed.
The control line installation method according to claim 6 . a plate-shaped first main circuit conductor connected to a first main terminal of the multi-gate semiconductor device;
a plate-shaped second main circuit conductor connected to a second main terminal of the multi-gate semiconductor element;
directly above the multi-gate semiconductor device;
The control line installation method according to claim 6 . a relationship between a width W of the wiring bus bar forming the control line and a distance d between each of the wiring bus bars satisfies the condition W>d;
The control line installation method according to claim 6 .