JP7613149B2 - Semiconductor chip manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor chip containing gallium nitride (hereinafter also simply referred to as GaN).

A manufacturing method has been proposed in the past in which an epitaxial film is formed on a semiconductor wafer to form a processed wafer, and semiconductor elements are formed on the processed wafer, followed by dividing the processed wafer into chip units to manufacture semiconductor chips (see, for example, Patent Document 1). Specifically, in this manufacturing method, assuming that the surface of the processed wafer facing the epitaxial film is one surface and the surface of the processed wafer facing the semiconductor wafer is the other surface, first, one-surface element components constituting the one-surface side of the semiconductor element, such as a diffusion layer and a front surface electrode, are formed on the one surface side of the processed wafer. Next, the other surface side of the processed wafer is ground to a predetermined thickness, and other-surface element components constituting the other surface side of the semiconductor element, such as a back surface electrode, are formed on the other surface side of the processed wafer. After that, the processed wafer is divided into chip units.

JP 2016-207908 A

The inventors are currently investigating semiconductor chips that contain GaN, which has the advantages of a wide band gap and a high electron saturation velocity. When such a semiconductor chip is manufactured using the above manufacturing method, it will be as follows.

That is, a GaN wafer is prepared as a semiconductor wafer, and an epitaxial film made of GaN is grown on the GaN wafer to form a processed wafer. Then, after forming element components on one side of the processed wafer, the other side of the processed wafer is ground. After that, element components on the other side are formed, and the processed wafer is divided into chip units.

However, in this manufacturing method, the processed wafer is ground from the other side. In other words, the GaN wafer is ground. This requires a GaN wafer to be prepared each time a semiconductor chip is manufactured, which can reduce productivity.

In view of the above, an object of the present invention is to provide a method for manufacturing semiconductor chips that can improve productivity.

In claim 1 to achieve the above object, a method for manufacturing a semiconductor chip on which a semiconductor element is formed is provided, comprising: preparing a GaN wafer (1) made of GaN and having one surface (1a) and another surface (1b) opposite to the one surface; forming an epitaxial film (3) on one surface of the GaN wafer, the surface on the epitaxial film side being the one surface (10a) and the surface on the GaN wafer side being the other surface (10b), thereby forming a processed wafer (10) having a plurality of chip formation regions (RA) on one surface side; and forming a one-surface element structure of a semiconductor element on the plurality of chip formation regions. a semiconductor chip (S1) is removed from the chip-configured wafer; a deteriorated layer (15) is formed inside the processed wafer along the surface direction of the processed wafer by irradiating the inside of the processed wafer with laser light (L) from the other side of the processed wafer; the processed wafer is divided at the deteriorated layer as a boundary to divide the processed wafer into a chip-configured wafer (30) on one side of the processed wafer and a recycled wafer (40) on the other side of the processed wafer; the semiconductor chip (S1) is removed from the chip-configured wafer; and the recycled wafer is reused as a GaN wafer. The GaN wafer is prepared by preparing a bulk wafer (100) made of GaN, with a first main surface (100a) being a gallium surface and a second main surface (100b) opposite the first main surface being a nitrogen surface; preparing an auxiliary wafer (110) in which a GaN layer (112) is laminated on a base wafer (111) made of a material other than GaN; separating the GaN layer from the auxiliary wafer to form a bonded wafer (114) in which a first main surface (114a) is a gallium surface and a second main surface (114b) opposite the first main surface is a nitrogen surface; and bonding the nitrogen surface of the bulk wafer to the nitrogen surface of the bonded wafer to prepare a GaN wafer with one and the other surfaces being gallium surfaces.

According to this method, recycled wafers are reused as GaN wafers. Therefore, there is no need to prepare new GaN wafers every time a semiconductor chip is manufactured, and GaN wafers can be used effectively. This improves the productivity of semiconductor chips. In addition, GaN wafers with one and other surfaces made of gallium are prepared. This prevents fine irregularities from being formed on the other surface of the processed wafer when each process before irradiating the laser light to form the altered layer is performed. This prevents the laser light from being diffusely reflected on the other surface of the processed wafer when irradiating the laser light from the other surface of the processed wafer. This allows an altered layer to be formed appropriately inside the processed wafer, and further improves productivity.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor chip in the first embodiment. 1B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1A. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1B. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 1C. 1D; FIG. 1E is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1E. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 1F. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 1G. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 1H. 1I is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 1C is a cross-sectional view showing a manufacturing process of the semiconductor chip following FIG. 1J. 1B is a cross-sectional view showing a manufacturing process of the GaN wafer shown in FIG. 1A. 2B is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 2A. 2C is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 2B. 2D is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 2C. 6A to 6C are cross-sectional views showing a manufacturing process of a GaN wafer in the second embodiment. 3B is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 3A. 3C is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 3B. 3D is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 3C. 3D is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 3D. 11A to 11C are cross-sectional views showing a manufacturing process of a GaN wafer in the third embodiment. 4B is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 4A. 4C is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 4B. 4D is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 4C. 4E is a cross-sectional view showing a manufacturing process of the GaN wafer subsequent to FIG. 4D.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
A first embodiment will be described with reference to the drawings. Hereinafter, a method for manufacturing a semiconductor chip S1 made of GaN will be described.

First, as shown in FIG. 1A, a GaN wafer 1 having one surface 1a and the other surface 1b and in the form of a bulk wafer is prepared. For example, the GaN wafer 1 is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of 5×10 ¹⁷ to 5×10 ¹⁹ cm ⁻³ . However, the GaN wafer 1 of this embodiment has a discontinuous impurity concentration at a predetermined location in the thickness direction, as described later. The thickness of the GaN wafer 1 is arbitrary, but for example, a wafer of about 400 μm is prepared. Note that the GaN wafer 1 of this embodiment has one surface 1a as a gallium surface and the other surface 1b as a gallium surface. In addition, after the manufacturing process of the semiconductor chip S1 described below is performed, this GaN wafer 1 is prepared by reusing a recycled wafer 40 of FIG. 1K described later.

Here, the process for preparing the GaN wafer 1 of this embodiment will be described in detail.

In this embodiment, as shown in FIG. 2A, a bulk wafer 100 is prepared that is made of GaN, with the first main surface 100a being a gallium surface and the second main surface 100b being a nitrogen surface. Then, although not shown, the second main surface 100b is polished or the like as necessary.

In addition, in a separate process from FIG. 2A, an auxiliary wafer 110 is prepared in which a GaN layer 112 is disposed on a base wafer 111, as shown in FIG. 2B. In this embodiment, the base wafer 111 is composed of a silicon wafer, a sapphire wafer, a silicon carbide wafer, an aluminum nitride polycrystalline wafer, or the like. The GaN layer 112 is epitaxially grown on the base wafer 111 via a buffer layer 113. The buffer layer 113 in this embodiment is composed of a first base layer 113a composed of a Si(111) layer or the like, and a second base layer 113b made of AlGaN or the like laminated on the first base layer 113a. The buffer layer 113 is intended to improve the crystallinity of the GaN layer 112 and increase its thickness.

Next, as shown in FIG. 2C, the GaN layer 112 is separated from the auxiliary wafer 110 to form a bonded wafer 114 composed of the GaN layer 112, with the first main surface 114a being a gallium surface and the second main surface 114b being a nitrogen surface. Note that this bonded wafer 114 is formed, for example, by grinding, polishing, etc. the base wafer 111, etc. to separate the GaN layer 112. Also, the bonded wafer 114 is formed, for example, by separating the GaN layer 112 from the base wafer 111 by laser slicing, etc.

After that, as shown in FIG. 2D, the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are bonded by direct bonding or the like. In other words, the nitrogen face of the bulk wafer 100 and the nitrogen face of the bonded wafer 114 are bonded by direct bonding or the like. This results in the formation of a GaN wafer 1 whose one surface 1a and the other surface 1b are gallium surfaces.

The direct bonding is performed, for example, as follows. That is, first, the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are irradiated with N ₂ plasma, O ₂ plasma, Ar ion beam, or the like to activate the main surfaces 100b, 114b. Then, alignment is performed using an infrared microscope or the like using an appropriately formed alignment mark, and the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are bonded together at room temperature to 550°C. As a result, the bulk wafer 100 and the bonded wafer 114 are directly bonded to each other to form the GaN wafer 1.

Such a GaN wafer 1 is constructed by bonding two different wafers, a bulk wafer 100 and a bonded wafer 114. Therefore, this GaN wafer 1 is a wafer in which the impurity concentration changes discontinuously at the interface between the bulk wafer 100 and the bonded wafer 114. Furthermore, this GaN wafer 1 is a wafer in which the crystal defect density changes discontinuously at the interface between the bulk wafer 100 and the bonded wafer 114. Note that a discontinuous change means, in other words, a sudden change in value.

1B, an epitaxial film 3 made of GaN with a thickness of about 10 to 100 μm is formed on one surface 1a of the GaN wafer 1 to prepare a processed wafer 10 having a plurality of chip formation regions RA. In this embodiment, the epitaxial film 3 is made up of an n ⁺ type epitaxial layer 3a and an n ^- type epitaxial layer 3b, which are formed in this order from the GaN wafer 1 side. For example, the n ⁺ type epitaxial layer 3a is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of about 5×10 ¹⁷ to 5×10 ¹⁹ cm ^-3 . The n ^- type epitaxial layer 3b is doped with silicon, etc., and has an impurity concentration of about 1×10 ¹⁷ to 4×10 ¹⁷ cm ^-3 .

The n ^- type epitaxial layer 3b is a portion where one-surface side element components 11 such as a diffusion layer 12 described later are formed, and has a thickness of, for example, about 8 to 10 μm. The n ⁺ type epitaxial layer 3a is a portion for ensuring the thickness of the semiconductor chip S1 described later, and has a thickness of, for example, about 40 to 100 μm. The thicknesses of the n ⁺ type epitaxial layer 3a and the n ^- type epitaxial layer 3b can be any desired value, but here the n ⁺ type epitaxial layer 3a is made thicker than the n ^- type epitaxial layer 3b so as to ensure the thickness of the semiconductor chip S1.

In the following, the surface of the processed wafer 10 facing the epitaxial film 3 is referred to as one surface 10a of the processed wafer 10, and the surface of the processed wafer 10 facing the GaN wafer 1 is referred to as the other surface 10b of the processed wafer 10. As described above, in this embodiment, the one surface 1a and the other surface 10b of the GaN wafer 1 are gallium surfaces, and therefore the one surface 10a and the other surface 10b of the processed wafer 10 are gallium surfaces. Each chip formation region RA is configured on the one surface 10a side of the processed wafer 10.

Here, in this step, the process temperature when growing the epitaxial film 3 is about 1000°C. Therefore, when each epitaxial film 3 is formed, nitrogen is easily gasified and escapes from the processed wafer 10. Specifically, nitrogen is easily escaped from the nitrogen face, which is easily chemically activated. However, in the processed wafer 10 of this embodiment, one surface 10a and the other surface 10b are gallium surfaces. Therefore, in the processed wafer 10 of this embodiment, nitrogen is less likely to escape from the processed wafer 10, and the formation of minute irregularities on the one surface 10a and the other surface 10b is suppressed.

Next, as shown in FIG. 1C, a surface side process is performed, which is a process for the one surface 10a side of a typical semiconductor manufacturing process. Specifically, as the surface side process, ion implantation, deposition, wet processes, etc. are appropriately performed to form the one surface side element components 11 of the semiconductor element, such as the diffusion layer 12, gate electrode 13, surface electrodes not shown, wiring patterns, and passivation films, in each chip formation area RA. Note that the semiconductor elements used here are of various configurations, such as power devices such as vertical MOS transistors, optical semiconductor elements such as light-emitting diodes, and semiconductor lasers. Thereafter, a surface protection film made of resist or the like is formed on the one surface 10a side of the processed wafer 10 as necessary.

In this process, there is a possibility that the chemical solution from the wet process will react with the processed wafer 10. Specifically, the nitrogen surface, which is chemically active, may react with the chemical solution. However, in the processed wafer 10 of this embodiment, the one surface 10a and the other surface 10b are gallium surfaces. Therefore, in the processed wafer 10 of this embodiment, the one surface 10a and the other surface 10b are less likely to react with the chemical solution, and the formation of minute irregularities on the one surface 10a and the other surface 10b is suppressed.

Next, as shown in FIG. 1D, a holding member 20 is placed on one surface 10a of the processed wafer 10. For example, a dicing tape having a support base 21 and an adhesive 22 is used as the holding member 20. The support base 21 is made of a material that is not easily warped during the manufacturing process, such as glass, a silicon substrate, or ceramics. The adhesive 22 is made of a material that can change its adhesive strength, such as a material whose adhesive strength changes depending on temperature or light. In this case, the adhesive 22 is made of, for example, an ultraviolet curing resin, wax, or double-sided tape. However, the adhesive 22 is made of a material that maintains its adhesive strength even when forming the other surface side element component 60 in FIG. 1G, which will be described later.

Next, as shown in FIG. 1E, laser light L is irradiated from the other surface 10b of the processed wafer 10 to form an altered layer 15 along the surface direction of the processed wafer 10 at a position at a predetermined depth D from the one surface 10a of the processed wafer 10.

Specifically, a laser device (not shown) is prepared, which includes a laser light source that oscillates laser light L, a dichroic mirror arranged to change the direction of the optical axis of the laser light, i.e., the optical path, a focusing lens for focusing the laser light, and a displaceable stage. When forming the altered layer 15, the position of the stage, etc. is adjusted so that the focal point of the laser light L is scanned relatively along the surface direction of the processed wafer 10. As a result, an altered layer 15 is formed on the processed wafer 10 along the surface direction. More specifically, by irradiating the laser light L, nitrogen evaporates as a gas and gallium is precipitated to form the altered layer 15.

In this case, as described above, the processed wafer 10 of this embodiment is unlikely to form fine irregularities on the other surface 10b even if each process before irradiating the laser light L is performed. Therefore, when the laser light L is irradiated from the other surface 10b side of the processed wafer 10, the laser light L is prevented from being diffusely reflected by the other surface 10b of the processed wafer 10. Therefore, an altered layer 15 can be suitably formed inside the processed wafer 10.

In this embodiment, although not particularly limited, the laser light L used when forming the altered layer 15 has a wavelength range from infrared to visible light, and is set in consideration of the transmittance of the target wafer (i.e., the transmittance of GaN). In this embodiment, the processing point output and pulse width of such laser light L are appropriately adjusted to form the altered layer 15.

The predetermined depth D when forming the altered layer 15 is set according to the ease of handling and pressure resistance of the semiconductor chip S1, and is about 10 to 200 μm. In this case, the location where the altered layer 15 is formed changes depending on the thickness of the epitaxial film 3, and the altered layer 15 is formed either inside the epitaxial film 3, at the boundary between the epitaxial film 3 and the GaN wafer 1, or inside the GaN wafer 1. Note that FIG. 1E shows an example in which the altered layer 15 is formed at the boundary between the epitaxial film 3 and the GaN wafer 1.

However, as described below, at least a part of the GaN wafer 1 in the processed wafer 10 is reused as a recycled wafer 40. For this reason, the altered layer 15 is preferably formed inside the epitaxial film 3 or at the boundary between the epitaxial film 3 and the GaN wafer 1. When the altered layer 15 is formed inside the GaN wafer 1, the altered layer 15 is preferably formed on the one surface 1a side of the GaN wafer 1. When the altered layer 15 is formed inside the epitaxial film 3, the altered layer 15 is preferably formed inside the n ⁺ type epitaxial layer 3a, not the n ⁻ type epitaxial layer 3b constituting the semiconductor element.

In the following, the portion of the processed wafer 10 on the side 10a of the altered layer 15 will be referred to as the chip configuration wafer 30, and the portion of the processed wafer 10 on the side 10b of the altered layer 15 will be referred to as the recycled wafer 40.

Next, as shown in FIG. 1F, an auxiliary member 50 is placed on the other surface 10b of the processed wafer 10. Although the auxiliary member 50 is shown simplified in FIG. 1F, it is composed of, for example, a base material and an adhesive capable of changing the adhesive strength. In this case, the base material in the auxiliary member 50 is composed of, for example, glass, a silicon substrate, ceramics, etc., and the adhesive in the auxiliary member 50 is composed of, for example, ultraviolet curing resin, wax, double-sided tape, etc. Then, the support base 21 and the auxiliary member 50 are grasped and a tensile force or the like is applied in the thickness direction of the processed wafer 10, and the chip configuration wafer 30 and the recycled wafer 40 are separated with the altered layer 15 as the boundary (i.e., the starting point of the branching).

In the following description, the side of the chip configuration wafer 30 on which the one-side element configuration portion 11 is formed is referred to as one side 30a, the divided side of the chip configuration wafer 30 is referred to as the other side 30b, and the divided side of the recycled wafer 40 is referred to as one side 40a. In addition, in each of the figures from FIG. 1F onwards, the altered layer 15 remaining on the other side 30b of the chip configuration wafer 30 and the one side 40a of the recycled wafer 40 are omitted as appropriate.

Then, as shown in FIG. 1G, the remaining semiconductor manufacturing process involves a back-side process in which the back-side element component 60 of the semiconductor element, such as the metal film 61 that constitutes the back-side electrode, is formed on the other side 30b of the chip-configured wafer 30.

Note that, prior to the step of forming the other surface side element component 60, a step of planarizing the other surface 30b of the chip configuration wafer 30 by a CMP (short for chemical mechanical polishing) method or the like may be performed as necessary. Figure 1G shows a diagram of the other surface 30b of the chip configuration wafer 30 after it has been planarized. In addition, after the step of forming the other surface side element component 60, a heat treatment such as laser annealing may be performed as necessary to make ohmic contact between the metal film 61 and the other surface 30b of the chip configuration wafer 30.

Next, as shown in FIG. 1H, a holding member 51 is placed on the other surface 30b of the chip configuration wafer 30, that is, on the metal film 61 side. For example, a dicing tape having a base material 52 and an adhesive 53 is used as the holding member 51. Note that the adhesive 53 is made of a material whose adhesive strength can be changed, and for example, one whose adhesive strength changes depending on temperature or light is used.

Then, as shown in FIG. 1I, the support base 21 attached to one surface 30a of the chip configuration wafer 30 is peeled off. Here, a process is performed to reduce the adhesive strength of the adhesive 22 that attaches the support base 21 to the chip configuration wafer 30, for example, UV irradiation is performed if the adhesive 22 is made of a UV resin adhesive.

Next, as shown in FIG. 1J, the chip configuration wafer 30 is divided into individual chip units using a dicing saw or laser dicing, to form each semiconductor chip S1. At this time, it is preferable to adjust the dicing depth so that the holding members 51 remain connected without being cut while the chip configuration wafer 30 is divided into chip units.

The subsequent steps for the semiconductor chip S1 are not shown, but the holding member 51 is expanded to widen the gap between each semiconductor chip S1 at the diced cut portion. After that, the adhesive strength of the adhesive 53 is weakened by heating or irradiating it with light, and the semiconductor chip S1 is picked up. In this way, the semiconductor chip S1 is manufactured.

As shown in FIG. 1K, one surface 40a of the recycled wafer 40 constructed as shown in FIG. 1F is planarized by performing a CMP method using a polishing device 70 or the like. The planarized recycled wafer 40 is then made into a GaN wafer 1, and the steps from FIG. 1A onwards are carried out again. This allows the GaN wafer 1 to be used multiple times to construct a semiconductor chip S1.

According to the present embodiment described above, the recycled wafer 40 is reused as the GaN wafer 1. Therefore, there is no need to prepare a new GaN wafer 1 each time a semiconductor chip S1 is manufactured, and the GaN wafer 1 can be used effectively. Therefore, the productivity of the semiconductor chip S1 can be improved.

In addition, in this embodiment, a GaN wafer 1 is prepared in which one surface 1a and the other surface 1b are gallium surfaces. Therefore, when each process before irradiating the laser light L to form the altered layer 15 is performed, the formation of fine irregularities on the other surface 10b of the processed wafer 10 can be suppressed. Therefore, when the laser light L is irradiated from the other surface 10b side of the processed wafer 10, diffuse reflection of the laser light L on the other surface 10b of the processed wafer 10 is suppressed. This allows the altered layer 15 to be suitably formed inside the processed wafer 10, further improving productivity.

(1) In this embodiment, the GaN layer 112 is disposed on the base wafer 111 via the buffer layer 113. This makes it easier to increase the thickness of the GaN layer 112, and makes it easier to increase the thickness of the bonded wafer 114 composed of the GaN layer 112. This makes it easier to increase the thickness of the GaN wafer 1, and increases the number of times the GaN wafer 1 can be effectively used.

Second Embodiment
A second embodiment will be described. This embodiment is different from the first embodiment in that the process of preparing the GaN wafer 1 is changed. As the rest of the process is the same as the first embodiment, the description will be omitted here.

In this embodiment, as shown in FIG. 3A, an auxiliary wafer 110 is prepared in which a GaN layer 112 is disposed directly on a base wafer 111. In other words, an auxiliary wafer 110 is prepared that does not include a buffer layer 113. Note that in this embodiment, since the GaN layer 112 is disposed directly on the base wafer 111, the auxiliary wafer 110 is prone to warping due to the difference in thermal expansion coefficient between the base wafer 111 and the GaN layer 112. For this reason, the GaN layer 112 of this embodiment is thinner than the GaN layer 112 of the first embodiment.

Next, as shown in FIG. 3B, a holding substrate 120 is prepared, and the GaN layer 112 and the holding substrate 120 are bonded to each other. The holding substrate 120 is for holding the thin GaN layer 112, and is made of, for example, a glass substrate, and is bonded to the GaN layer 112 by direct bonding or the like.

Next, as shown in FIG. 3C, the GaN layer 112 is separated from the auxiliary wafer 110 while being held on the holding substrate 120. As a result, a bonded wafer 114 having a first main surface 114a that is a gallium surface and a second main surface 114b that is a nitrogen surface is prepared while being held on the holding substrate 120. Note that this bonded wafer 114 is formed, for example, by grinding or polishing the base wafer 111 or the like to separate the GaN layer 112. Also, the bonded wafer 114 is formed, for example, by separating the GaN layer 112 from the base wafer 111 by laser slicing or the like.

Next, as shown in FIG. 3D, the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are bonded together by direct bonding or the like.

Then, as shown in FIG. 3E, the holding substrate 120 is removed by grinding, polishing, laser slicing, wet etching, or the like to prepare a GaN wafer 1 having one surface 1a and the other surface 1b as gallium surfaces.

Then, the steps in FIG. 1B and onwards are carried out on each GaN wafer 1 to manufacture semiconductor chips S1.

According to the present embodiment described above, the GaN wafer 1 has one surface 1a and the other surface 1b made of gallium, so that the same effects as those of the first embodiment can be obtained.

Third Embodiment
A third embodiment will be described. This embodiment is different from the first embodiment in that the process of preparing the GaN wafer 1 is changed. As the rest of the process is the same as the first embodiment, the description will be omitted here.

In this embodiment, as shown in FIG. 4A, after preparing a bulk wafer 100, laser light L is irradiated from the second main surface 100b side to form an altered layer 100C inside. Note that the process of irradiating laser light L to form the altered layer 100C is performed under the same conditions as the process of forming the altered layer 15 in FIG. 1E above.

Next, as shown in FIG. 4B, the bulk wafer 100 is separated into a first divided bulk wafer 101 and a second divided bulk wafer 102, with the altered layer 100c as the boundary (i.e., the starting point of branching). In this process, although not shown, auxiliary members, etc. are appropriately placed on the first main surface 100a and the second main surface 100b of the bulk wafer 100. Then, similar to FIG. 1F above, the bulk wafer 100 is divided into the first divided bulk wafer 101 and the second divided bulk wafer 102 by applying a tensile force, etc. in the thickness direction.

In the following, in the first divided bulk wafer 101, the surface that was the first main surface 100a of the bulk wafer 100 will be referred to as the first divided main surface 101a of the first divided bulk wafer 101, and the divided surface will be referred to as the second divided main surface 102b of the first divided bulk wafer 101. Therefore, in the first divided bulk wafer 101, the first divided main surface 101a will be a gallium surface, and the second divided main surface 101b will be a nitrogen surface.

In addition, in the second divided bulk wafer 102, the divided surface is the first divided main surface 102a of the second divided bulk wafer 102, and the surface that was the second main surface 100b of the bulk wafer 100 is the second divided main surface 102b of the second divided bulk wafer 102. Therefore, in the second divided bulk wafer 102, the first divided main surface 102a is a gallium surface, and the second divided main surface 102b is a nitrogen surface.

After that, although not shown, the remaining altered layer 100c is removed by a CMP method or the like, and the divided surfaces are planarized. Specifically, the second divided main surface 101b of the first divided bulk wafer 101 is planarized, and the first divided main surface 102a of the second divided bulk wafer 102 is planarized.

Also, as shown in FIG. 4C, an auxiliary wafer 110 similar to that shown in FIG. 2B is prepared. However, compared to the first embodiment, the auxiliary wafer 110 of this embodiment is a large-diameter substrate having a larger diameter than the bulk wafer 100. Specifically, the auxiliary wafer 110 has a diameter that allows multiple wafers of the same size as the bulk wafer 100 to be obtained in the surface direction.

Next, as shown in FIG. 4D, the GaN layer 112 is separated from the auxiliary wafer 110 to form a bonded wafer 114 in which the first main surface 114a is a gallium surface and the second main surface 114b is a nitrogen surface. In this case, in this embodiment, two bonded wafers 114 corresponding to the diameters of the first divided bulk wafer 101 and the second divided bulk wafer 102 are formed from the auxiliary wafer 110. The bonded wafer 114 is formed, for example, by grinding, polishing, etc. the base wafer 111 to separate the GaN layer 112 and processing it to a predetermined diameter. The bonded wafer 114 is also formed, for example, by separating the GaN layer 112 from the base wafer 111 by laser slicing or the like and processing it to a predetermined diameter.

Then, as shown in FIG. 4E, the second divided main surface 101b of the first divided bulk wafer 101 is bonded to the second main surface 114b of the bonded wafer 114 by direct bonding or the like to form a GaN wafer 1 whose one surface 1a and the other surface 1b are gallium surfaces. Similarly, the second divided main surface 102b of the second divided bulk wafer 102 is bonded to the second main surface 114b of the bonded wafer 114 by direct bonding or the like to form a GaN wafer 1 whose one surface 1a and the other surface 1b are gallium surfaces. In other words, in this embodiment, multiple GaN wafers 1 are formed simultaneously.

Then, the steps in FIG. 1B and onwards are carried out on each GaN wafer 1 to manufacture semiconductor chips S1.

According to the present embodiment described above, the GaN wafer 1 has one surface 1a and the other surface 1b made of gallium, so that the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, multiple GaN wafers 1 can be constructed from one bulk wafer 100 and one auxiliary wafer 110. This allows for further improvement in productivity.

Other Embodiments
Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in each of the above embodiments, the epitaxial film 3 may be composed of only the n ^- type epitaxial layer 3b.

In each of the above embodiments, in the step of FIG. 1G, the metal film 61 may be formed without polishing the other surface 30b of the chip configuration wafer 30. For example, when forming an optical semiconductor element as a semiconductor element, forming an uneven structure on the other surface of the semiconductor chip S1 makes it possible to effectively extract light from the other surface. Then, immediately after dividing the processed wafer 10 into the chip configuration wafer 30 and the recycled wafer 40, the other surface 30b of the chip configuration wafer 30 has the altered layer 15 remaining thereon, and minute irregularities are formed. Therefore, when forming an optical semiconductor element, the other surface 30b of the chip configuration wafer 30 may not be polished, and the unevenness of the altered layer 15 may be utilized.

Furthermore, in each of the above embodiments, in the step of forming the epitaxial film 3 in FIG. 1B, an epitaxial film may also be formed on the other surface 1b of the GaN wafer 1. This makes it easier to leave a predetermined thickness or more as a recycled wafer 40 even when, for example, an altered layer 15 is formed in the GaN wafer 1, thereby increasing the number of times the wafer can be reused.

In addition, in the third embodiment, the bulk wafer 100 may be divided into three or more bulk wafers, and three or more bonded wafers 114 may be constructed from the auxiliary wafer 110, so that three or more GaN wafers 1 may be formed simultaneously.

The above embodiments can also be combined as appropriate. For example, the above second embodiment can be combined with the above third embodiment, and the auxiliary wafer 110 can be configured by placing the GaN layer 112 directly on the base wafer 111.

Reference Signs List 1a One surface 1b Other surface 1 GaN wafer 3 Epitaxial film 10 Processed wafer 10a One surface 10b Other surface 11 One surface side element component 15 Affected layer 30 Chip component wafer 40 Recycled wafer 100 Bulk wafer 100a First main surface 100b Second main surface 110 Auxiliary wafer 111 Base wafer 112 GaN layer 114 Bonded wafer 114a First main surface 114b Second main surface L Laser light S1 Semiconductor chip

Claims (4)

A method for manufacturing a semiconductor chip having a semiconductor element formed thereon, comprising the steps of:
Preparing a gallium nitride wafer (1) made of gallium nitride and having one surface (1a) and another surface (1b) opposite to the one surface;
forming an epitaxial film (3) on the one surface of the gallium nitride wafer, the surface on the epitaxial film side being one surface (10a) and the surface on the gallium nitride wafer side being the other surface (10b), thereby forming a processed wafer (10) having a plurality of chip formation areas (RA) on the one surface side;
forming one-surface-side element constituent parts (11) of the semiconductor element in the plurality of chip formation regions;
forming an altered layer (15) along a surface direction of the processed wafer inside the processed wafer by irradiating a laser beam (L) into the inside of the processed wafer from the other surface side of the processed wafer;
Dividing the processed wafer at the deteriorated layer as a boundary, thereby dividing the processed wafer into a chip configuration wafer (30) on one side of the processed wafer and a recycled wafer (40) on the other side of the processed wafer;
Extracting a semiconductor chip (S1) from the chip configuration wafer;
and reusing the recycled wafer as the gallium nitride wafer.
The gallium nitride wafer is prepared by:
A bulk wafer (100) is prepared, the bulk wafer (100) being made of gallium nitride, the first main surface (100a) being a gallium surface and the second main surface (100b) opposite to the first main surface being a nitrogen surface;
A method for manufacturing a semiconductor device comprising the steps of: preparing an auxiliary wafer (110) having a gallium nitride layer (112) laminated on a base wafer (111) made of a material other than gallium nitride;
Separating the gallium nitride layer from the auxiliary wafer to form a bonded wafer (114) having a first main surface (114a) that is a gallium surface and a second main surface (114b) opposite to the first main surface that is a nitrogen surface;
and preparing the gallium nitride wafer having the one surface and the other surface made into gallium surfaces by bonding the nitrogen surface of the bulk wafer and the nitrogen surface of the bonded wafer. The method for manufacturing a semiconductor chip according to claim 1, wherein the auxiliary wafer is prepared by stacking the gallium nitride layer on the base wafer via a buffer layer (113). The method for manufacturing a semiconductor chip according to claim 1 or 2, wherein the base wafer is a silicon wafer, a sapphire wafer, a silicon carbide wafer, or an aluminum nitride polycrystalline wafer. After providing the bulk wafer,
forming an altered layer (100c) along a surface direction of the bulk wafer inside the bulk wafer by irradiating the inside of the bulk wafer with laser light (L);
dividing the bulk wafer at the affected layer as a boundary, so that the surface of the bulk wafer on the first main surface side is a first divided main surface (101a, 102a) and the surface of the bulk wafer on the second main surface side is a second divided main surface (101b, 102b), and the first divided main surface is a gallium surface and the second divided main surface is a nitrogen surface, forming a plurality of divided bulk wafers (101, 102);
and planarizing the divided surfaces of the divided bulk wafers.
In preparing the auxiliary wafer, a diameter of the auxiliary wafer is prepared that is larger than a diameter of the bulk wafer;
In the step of preparing the bonded wafer, a plurality of bonded wafers each having a diameter corresponding to a diameter of the divided bulk wafers are prepared;
4. The method for manufacturing a semiconductor chip according to claim 1, wherein the step of preparing the gallium nitride wafer comprises bonding the nitrogen faces of the plurality of divided bulk wafers to the nitrogen faces of the bonded wafer, respectively.

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