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JP7614295B2 - Substrate for semiconductor device and semiconductor device - Google Patents
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JP7614295B2 - Substrate for semiconductor device and semiconductor device - Google Patents

Substrate for semiconductor device and semiconductor device Download PDF

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JP7614295B2
JP7614295B2 JP2023186256A JP2023186256A JP7614295B2 JP 7614295 B2 JP7614295 B2 JP 7614295B2 JP 2023186256 A JP2023186256 A JP 2023186256A JP 2023186256 A JP2023186256 A JP 2023186256A JP 7614295 B2 JP7614295 B2 JP 7614295B2
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semiconductor device
resist layer
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JP2023181386A (en
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佑也 五郎丸
達也 古賀
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Maxell Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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Description

本発明は、母型基板上に半導体素子搭載部や電極部となる金属部を備える半導体装置用基板、該半導体装置用基板を用いてなる半導体装置に関する。 The present invention relates to a substrate for a semiconductor device that has a metal part that serves as a semiconductor element mounting part and an electrode part on a mother substrate, and a semiconductor device that uses the substrate for a semiconductor device.

半導体素子支持用基板(プリント基板)上に半導体素子を搭載し、半導体素子と外部導出用の端子とを電気的に接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した構成とされる半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載部や電極部となる金属部を備え、この金属部上に半導体素子を搭載して電気的接続等の処理後、半導体素子や金属部の表面側を樹脂等の封止材で封止し、金属部が底部から露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れる他、露出した金属部を通じて半導体素子で生じた熱を外部に放出でき、放熱の面でも優れるといった特長を有しており、チップサイズなど小型の半導体装置の分野で利用が進んでいる。 A semiconductor device in which a semiconductor element is mounted on a substrate (printed circuit board) for supporting the semiconductor element, the semiconductor element is electrically connected to a terminal for external output, and the entire substrate including the semiconductor element is covered with a protective material such as resin, has a limit to how small it can be made due to its structure. In contrast, a semiconductor device in which a metal part that serves as a semiconductor element mounting part and an electrode part is provided, the semiconductor element is mounted on this metal part, and after processing such as electrical connection, the surface side of the semiconductor element and the metal part are sealed with a sealing material such as resin, and the metal part is exposed from the bottom, can be made low in height to save space, and has the advantage of being excellent in terms of heat dissipation, as heat generated by the semiconductor element can be released to the outside through the exposed metal part, and is therefore increasingly used in the field of small semiconductor devices such as chip size.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部や電極部となる金属部を、メッキ(電鋳)により半導体装置の所望個数分まとめて形成し、半導体素子搭載、半導体素子と電極部との電気的接続等の処理を経た金属部の表面側を封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造方法の一例として、特許文献1、特許文献2に開示されている。 Such semiconductor devices are mainly manufactured through a manufacturing process in which metal parts that will become the semiconductor element mounting parts and electrode parts are formed on a conductive mother substrate by plating (electroforming) in the desired number of semiconductor devices at once, the surface side of the metal parts that have been subjected to processes such as mounting the semiconductor elements and electrically connecting the semiconductor elements to the electrode parts is sealed with a sealant, and then only the mother substrate is removed and the many integrated semiconductor devices are cut into individual pieces. Examples of manufacturing methods for such semiconductor devices are disclosed in Patent Documents 1 and 2.

特開2002-9196号公報JP 2002-9196 A 特開2004-214265号公報JP 2004-214265 A

従来の半導体装置の製造方法は前記特許文献に示されるように、母型基板上への金属部の形成にあたり、母型基板における金属部の非配置部分にレジスト層をあらかじめ形成して、金属部が電解メッキにより適切な位置に形成されるようにしていた。この金属部には、メッキによる形成に適したニッケル等の金属が使用されていた。そして、このレジスト層を溶剤等で溶解除去した上で、母型基板とその表面に形成された金属部が、半導体装置用基板として供給された。この半導体装置用基板を用いて、実際の半導体装置の製造工程において、半導体素子の搭載や配線、封止材による封止等を行うようにしていた。 As shown in the above-mentioned patent document, in the conventional method of manufacturing a semiconductor device, when forming metal parts on a mother substrate, a resist layer is formed in advance on the parts of the mother substrate where the metal parts are not to be placed, so that the metal parts are formed in the appropriate positions by electrolytic plating. Metals such as nickel, which are suitable for formation by plating, are used for these metal parts. Then, after dissolving and removing this resist layer with a solvent or the like, the mother substrate and the metal parts formed on its surface are supplied as a substrate for a semiconductor device. Using this substrate for a semiconductor device, the mounting of semiconductor elements, wiring, sealing with a sealing material, etc. are carried out in the actual manufacturing process of the semiconductor device.

本発明は、上記課題を解消するためになされたもので、半導体装置の一層の小型化が図れるとともに、半導体装置としての形成密度を高めることができる半導体装置用基板、この半導体装置用基板を用いてなる半導体装置を提供することを目的とする。 The present invention has been made to solve the above problems, and aims to provide a substrate for a semiconductor device that can further reduce the size of the semiconductor device and increase the formation density of the semiconductor device, and a semiconductor device that uses this substrate for a semiconductor device.

しかしながら、従来の工程では金属部上部の張出部の張出し量を厳密に管理することは難しいため、張出部同士の間隔が後のレジスト層除去を妨げる狭小なものとならないように、金属部の配置間隔を広めに取らざるを得ず、これにより、半導体装置の更なる小型化、半導体装置用基板上での半導体装置の形成密度を高めることによる生産効率の向上が困難なものとなっていた。 However, in conventional processes, it is difficult to precisely control the amount of overhang of the overhanging parts on the upper part of the metal part, so the metal parts must be spaced apart widely so that the gap between the overhanging parts is not so narrow that it would prevent the subsequent removal of the resist layer. This makes it difficult to further miniaturize the semiconductor device and to improve production efficiency by increasing the formation density of the semiconductor device on the semiconductor device substrate.

本発明は、上記課題を解消するためになされたもので、半導体装置の一層の小型化が図れるとともに、半導体装置としての形成密度を高めることができる半導体装置用基板、この半導体装置用基板を用いてなる半導体装置を提供することを目的とする。 The present invention has been made to solve the above problems, and aims to provide a substrate for a semiconductor device that can further reduce the size of the semiconductor device and increase the formation density of the semiconductor device, and a semiconductor device that uses this substrate for a semiconductor device.

本発明に係る半導体装置用基板は、母型基板10上に半導体素子搭載部11a及び/又は電極部11bとなる金属部11を備える。金属部11には張出部11cが形成されている。そして、この張出部11cは、金属部11の軸方向と直交する方向に平行な下面と、金属部11の上面に連続して形成される上面と、下面と上面の間に形成される側面とを有するものである。 The substrate for semiconductor device according to the present invention comprises a metal part 11 which becomes a semiconductor element mounting part 11a and/or an electrode part 11b on a mother substrate 10. A protruding part 11c is formed on the metal part 11. The protruding part 11c has a lower surface which is parallel to a direction perpendicular to the axial direction of the metal part 11, an upper surface which is formed continuously with the upper surface of the metal part 11, and a side surface which is formed between the lower surface and the upper surface.

また、張出部11cの側面は、金属部11の軸方向と平行となっているものである。また、張出部11cの高さ寸法は、張出部11cの幅寸法と同じ、あるいはそれよりも大きいものである。 The side of the protrusion 11c is parallel to the axial direction of the metal part 11. The height of the protrusion 11c is the same as or greater than the width of the protrusion 11c.

また、金属部11の上面及び張出部11cの上面に表面金属層13が形成されており、表面金属層13の厚み分が張出部11cの側面として現れるものである。 In addition, a surface metal layer 13 is formed on the upper surface of the metal portion 11 and the upper surface of the protruding portion 11c, and the thickness of the surface metal layer 13 appears as the side surface of the protruding portion 11c.

さらに、金属部11には前記張出部11c及び/又は張出部11c’が形成されており、この張出部11c’は、金属部11の軸方向と直交する方向に平行な下面と、金属部11の上面に連続して形成される上面とを有するものである。このように、金属部11には側面を有する張出部11cおよび/または側面を有さない張出部11c’が形成され、異なる張出部が混在した構成となる。 Furthermore, the metal part 11 is formed with the protruding part 11c and/or the protruding part 11c', and this protruding part 11c' has a lower surface parallel to a direction perpendicular to the axial direction of the metal part 11, and an upper surface formed continuous with the upper surface of the metal part 11. In this way, the metal part 11 is formed with the protruding part 11c having a side surface and/or the protruding part 11c' not having a side surface, resulting in a configuration in which different protruding parts are mixed.

また、本発明は、母型基板10上に半導体素子搭載部11a及び/又は電極部11bとなる金属部11を備える半導体装置用基板の製造方法であって、母型基板10上に、金属部11を形成するための所定パターンから成る第一レジスト層12を形成する工程と、第一レジスト層12上に、所定パターンから成る第二レジスト層16を形成する工程と、母型基板10の第一レジスト層12で覆われていない露出領域に対し、金属部11を形成する工程とを含み、金属部11を形成する工程において、金属部11は第一レジスト層12の厚さを越える一方、第二レジスト層16の厚さを越えない所定厚さであって、第二レジスト層16の側面に接する部位を伴いつつ形成されることで、金属部11に張出部11cが形成されるものである。 The present invention also provides a method for manufacturing a substrate for a semiconductor device having a metal portion 11 that becomes a semiconductor element mounting portion 11a and/or an electrode portion 11b on a mother substrate 10, the method including the steps of forming a first resist layer 12 of a predetermined pattern for forming the metal portion 11 on the mother substrate 10, forming a second resist layer 16 of a predetermined pattern on the first resist layer 12, and forming the metal portion 11 on the exposed area of the mother substrate 10 that is not covered by the first resist layer 12. In the step of forming the metal portion 11, the metal portion 11 is formed to a predetermined thickness that exceeds the thickness of the first resist layer 12 but does not exceed the thickness of the second resist layer 16, and includes a portion that contacts the side surface of the second resist layer 16, thereby forming a protruding portion 11c on the metal portion 11.

また、第二レジスト層16の所定パターンの開口内面が母型基板10の面方向と直交する方向に平行となるように形成されるものである。ここで、「第二レジスト層16の所定パターンの開口内面が母型基板10の面方向と直交」とは、第二レジスト層16の所定パターンの開口内面から母型基板10面に向けて直線(仮想線)を引いた時に、直角に交差することを言う。 The second resist layer 16 is formed so that the inner surface of the opening of the predetermined pattern is parallel to a direction perpendicular to the surface direction of the mother substrate 10. Here, "the inner surface of the opening of the predetermined pattern of the second resist layer 16 is perpendicular to the surface direction of the mother substrate 10" means that when a straight line (imaginary line) is drawn from the inner surface of the opening of the predetermined pattern of the second resist layer 16 toward the surface of the mother substrate 10, it intersects at a right angle.

また、第一レジスト層12の所定パターンの開口内面と、第二レジスト層16の所定パターンの開口内面との間に段差部20が形成されており、段差部20の幅寸法が5μm以上に設定されているものである。なお、この段差部20が形成されていない箇所があっても良く、つまり、第一レジスト層12上に第二レジスト層16を形成しない領域があっても良く、これにより、金属部11を形成する工程において、第一レジスト層12の厚さを越えて金属層11を形成することで、金属部11に張出部11c’が形成される。 A step portion 20 is formed between the inner surface of the opening of the predetermined pattern of the first resist layer 12 and the inner surface of the opening of the predetermined pattern of the second resist layer 16, and the width dimension of the step portion 20 is set to 5 μm or more. Note that there may be a portion where this step portion 20 is not formed, that is, there may be an area where the second resist layer 16 is not formed on the first resist layer 12, and thus, in the process of forming the metal portion 11, the metal layer 11 is formed to a thickness exceeding that of the first resist layer 12, thereby forming a protruding portion 11c' in the metal portion 11.

また、本発明は、半導体素子14と、半導体素子搭載部11a及び/又は電極部11bとなる金属部11とを備え、金属部11は張出部11cが形成されており、金属部11への半導体素子14の搭載及び電気的接続がなされ、封止材19によって封止された半導体装置であって、張出部11cは、金属部11の軸方向と直交する方向に平行な下面と、金属部11の上面に連続して形成される上面と、該下面と上面の間に形成される側面とを有するものである。 The present invention also provides a semiconductor device that includes a semiconductor element 14 and a metal part 11 that serves as a semiconductor element mounting part 11a and/or an electrode part 11b, the metal part 11 having a protruding part 11c formed therein, the semiconductor element 14 being mounted and electrically connected to the metal part 11, and sealed with a sealing material 19, the protruding part 11c having a lower surface parallel to a direction perpendicular to the axial direction of the metal part 11, an upper surface formed continuously with the upper surface of the metal part 11, and a side surface formed between the lower surface and the upper surface.

本発明によれば、張出部11cで封止材からの抜けに対する十分な強度を得られる必要最小限の張出し量を確保しつつ、隣り合う張出部11c同士があらかじめ設定された適切な間隔をなす状態に調整できることから、母型基板10上における金属部11の配置間隔を従来に比べて小さくすることができ、半導体装置用基板1上で形成される半導体装置の一層の小型化が図れると共に、半導体装置用基板1上での半導体装置の形成密度を高められ、半導体装置の製造を効率化できる。そして、係る張出部11cは、第一レジスト層12及び第二レジスト層16を所望の形状に形成することにより、容易に得ることができる。 According to the present invention, the protrusions 11c can be adjusted to a predetermined appropriate distance between adjacent protrusions 11c while ensuring the minimum amount of protrusion necessary to provide sufficient strength against leakage from the sealing material. This allows the arrangement interval of the metal parts 11 on the mother substrate 10 to be smaller than in the past, further miniaturizing the semiconductor device formed on the substrate 1 for semiconductor device, and increasing the formation density of the semiconductor device on the substrate 1 for semiconductor device, thereby making the manufacturing of semiconductor devices more efficient. Moreover, the protrusions 11c can be easily obtained by forming the first resist layer 12 and the second resist layer 16 into the desired shape.

本発明の第1の実施形態に係る半導体装置用基板の部分拡大図である。1 is a partially enlarged view of a substrate for a semiconductor device according to a first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板の断面図である。1 is a cross-sectional view of a substrate for a semiconductor device according to a first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板における金属部の説明図である。3A and 3B are explanatory views of a metal portion in the substrate for the semiconductor device according to the first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置の説明図である。1 is an explanatory diagram of a semiconductor device according to a first embodiment of the present invention; 本発明の第1の実施形態に係る半導体装置用基板の製造方法における工程説明図である。1A to 1C are diagrams illustrating steps in a method for manufacturing a substrate for a semiconductor device according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置用基板の製造方法における工程説明図である。1A to 1C are diagrams illustrating steps in a method for manufacturing a substrate for a semiconductor device according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置用基板における金属部の状態説明図である。3A to 3C are diagrams illustrating a state of a metal portion in the substrate for the semiconductor device according to the first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置の製造方法における工程説明図である。1A to 1C are diagrams illustrating steps in a manufacturing method of a semiconductor device according to a first embodiment of the present invention. 本発明の他実施形態に係る半導体装置用基板における金属部の説明図である。11 is an explanatory diagram of a metal portion in a substrate for a semiconductor device according to another embodiment of the present invention. 本発明の他実施形態に係る半導体装置の説明図である。11 is an explanatory diagram of a semiconductor device according to another embodiment of the present invention. 本発明の他実施形態に係る半導体装置用基板の製造方法における工程説明図である。10A to 10C are diagrams illustrating steps in a method for manufacturing a substrate for a semiconductor device according to another embodiment of the present invention. 本発明の他実施形態に係る半導体装置用基板の説明図である。11 is an explanatory diagram of a substrate for a semiconductor device according to another embodiment of the present invention. FIG. 従来の半導体装置用基板を示す断面図である。FIG. 1 is a cross-sectional view showing a conventional substrate for a semiconductor device.

(第1実施形態)
以下、本発明の第1の実施形態に係る半導体装置用基板を図1ないし図3に基づいて説明する。前記各図に示すように、本実施形態に係る半導体装置用基板1は、導電性を有する材質からなる母型基板10と、この母型基板10上に複数組形成され、本半導体装置用基板1を用いて製造される半導体装置70の半導体素子搭載部11a又は電極部11bとなる金属部11とを備える構成であり、金属部11表面にはメッキにより表面金属層13が形成されている。
First Embodiment
A substrate for a semiconductor device according to a first embodiment of the present invention will now be described with reference to Figures 1 to 3. As shown in the figures, the substrate for a semiconductor device 1 according to this embodiment includes a mother substrate 10 made of a conductive material, and a plurality of metal parts 11 formed on the mother substrate 10 to serve as semiconductor element mounting parts 11a or electrode parts 11b of a semiconductor device 70 manufactured using the substrate for a semiconductor device 1. A surface metal layer 13 is formed on the surface of the metal parts 11 by plating.

図2は、半導体装置用基板の概略構成を示すものであり、図3は、金属部11の構成を模式的に示すものであって、図3(A)は上面図、図3(B)は断面図、図3(C)は下面図、図3(D)は斜視図である。図3に示すように、金属部11の周縁、好ましくは上端周縁には張出部11cが設けられており、この張出部11cは、金属部11の軸方向と直交する方向に平行な下面Aと、金属部11の上面Dに連続して形成される上面Cと、該下面と上面の間に形成される側面Bとを有するものである。金属部11及び張出部11cは、上面視で円形状に形成されている。なお、図3において、金属部11の上面Dと張出部11cの上面Cとの境に線が描画されているが、これは金属部11の上面Dと張出部11cの上面Cの領域を明確に示すためであり、実際は、金属部11の上面Dと張出部11cの上面Cとは境のない連続する面である。 Figure 2 shows a schematic configuration of a substrate for a semiconductor device, and Figure 3 shows a schematic configuration of metal part 11, with Figure 3(A) being a top view, Figure 3(B) being a cross-sectional view, Figure 3(C) being a bottom view, and Figure 3(D) being a perspective view. As shown in Figure 3, a protruding part 11c is provided on the periphery of metal part 11, preferably on the upper end periphery, and this protruding part 11c has a lower surface A parallel to a direction perpendicular to the axial direction of metal part 11, an upper surface C formed continuously with upper surface D of metal part 11, and a side surface B formed between the lower surface and the upper surface. Metal part 11 and protruding part 11c are formed in a circular shape when viewed from above. In FIG. 3, a line is drawn at the boundary between the top surface D of the metal part 11 and the top surface C of the protruding part 11c, but this is to clearly show the area of the top surface D of the metal part 11 and the top surface C of the protruding part 11c. In reality, the top surface D of the metal part 11 and the top surface C of the protruding part 11c are continuous surfaces with no boundary.

また、張出部11cの上面Cは、曲面となっている。具体的には、張出部11cの上面Cは、金属部11の上面Dから張出部11cの側面Bに連続形成された曲面となっている。なお、金属部11の表面(上面D、側面、下面)及び張出部11cの表面(上面C、側面B、下面A)は凸面であっても凹面であっても良い。 The upper surface C of the protruding portion 11c is a curved surface. Specifically, the upper surface C of the protruding portion 11c is a curved surface that is continuously formed from the upper surface D of the metal portion 11 to the side surface B of the protruding portion 11c. Note that the surfaces of the metal portion 11 (upper surface D, side surface, lower surface) and the surfaces of the protruding portion 11c (upper surface C, side surface B, lower surface A) may be convex or concave.

ここで、金属部11(半導体素子搭載部11a、電極部11b)と張出部11cの寸法について説明すると、図3(B)に示すように、金属部11の幅寸法W1は50μm以上、金属部11の高さ寸法H1は20~100μm、張出部11cの幅寸法W2は5μm以上、張出部11cの高さ(厚さ)寸法H2は5~50μmの範囲が好ましい。また、張出部11cの幅寸法(張出し長さ)W2と張出部11cの高さ寸法H2は、W2≦H2の関係を満たすことが好ましい。これにより、張出部11cとしての強度を確保しつつ、金属部11の配置間隔を小さくすることができる。このような金属部11及び張出部11cの外形寸法は、後述する第一レジスト層12及び第二レジスト層16を所望の形状に形成することで容易に設定することができる。なお、本実施形態では、金属部11として、半導体素子搭載部11aの幅寸法W1を500μm、電極部11bの幅寸法W1を250μm、金属部11の高さ寸法H1を70μm、張出部11cの幅寸法W2を20μm、張出部11cの高さ(厚さ)寸法H2を30μmに設定している。 Here, the dimensions of the metal part 11 (semiconductor element mounting part 11a, electrode part 11b) and the overhanging part 11c will be described. As shown in FIG. 3B, the width dimension W1 of the metal part 11 is preferably 50 μm or more, the height dimension H1 of the metal part 11 is preferably 20 to 100 μm, the width dimension W2 of the overhanging part 11c is preferably 5 μm or more, and the height (thickness) dimension H2 of the overhanging part 11c is preferably in the range of 5 to 50 μm. In addition, it is preferable that the width dimension (overhang length) W2 of the overhanging part 11c and the height dimension H2 of the overhanging part 11c satisfy the relationship W2≦H2. This allows the arrangement interval of the metal part 11 to be reduced while ensuring the strength of the overhanging part 11c. The outer dimensions of the metal part 11 and the overhanging part 11c can be easily set by forming the first resist layer 12 and the second resist layer 16 described later into the desired shape. In this embodiment, the width dimension W1 of the semiconductor element mounting portion 11a of the metal portion 11 is set to 500 μm, the width dimension W1 of the electrode portion 11b is set to 250 μm, the height dimension H1 of the metal portion 11 is set to 70 μm, the width dimension W2 of the protruding portion 11c is set to 20 μm, and the height (thickness) dimension H2 of the protruding portion 11c is set to 30 μm.

係る半導体装置用基板1を用いて製造される半導体装置70は、図4に示すように、半導体装置用基板1から得られる金属部11及び表面金属層13に加えて、金属部11のうち半導体素子搭載部11aに搭載される半導体素子14と、この半導体素子14と金属部11のうちの電極部11bとを電気的に接続するワイヤ15と、半導体素子14やワイヤ15を含む金属部11の表面側を覆って封止する封止材19とを備える構成である。 As shown in FIG. 4, the semiconductor device 70 manufactured using the semiconductor device substrate 1 includes, in addition to the metal part 11 and surface metal layer 13 obtained from the semiconductor device substrate 1, a semiconductor element 14 mounted on the semiconductor element mounting portion 11a of the metal part 11, a wire 15 electrically connecting the semiconductor element 14 to the electrode portion 11b of the metal part 11, and a sealant 19 that covers and seals the surface side of the metal part 11 including the semiconductor element 14 and the wire 15.

この半導体装置70は、その底部において、金属部11の裏面が電極や放熱パッド等として封止材19から露出した状態となっている(図4(B)参照)。また、この露出する金属部11の裏面側と、装置外装の一部として現れる封止材19の裏面側とが略同一平面上に位置する構成である。半導体装置70における底部以外の各面は、装置外装をなす封止材19のみがそれぞれ現れた状態となっている。なお、これに限らず、半導体装置70における上部を除く各面(正面、背面、左右側面、底面 )に、金属部11の一部(金属部11の側部)が露出されていても良い。 At the bottom of this semiconductor device 70, the back surface of the metal part 11 is exposed from the sealing material 19 as an electrode, heat dissipation pad, etc. (see FIG. 4B). The exposed back surface of the metal part 11 and the back surface of the sealing material 19 that appears as part of the device exterior are located on approximately the same plane. On each surface of the semiconductor device 70 other than the bottom, only the sealing material 19 that forms the device exterior is exposed. However, this is not limited to this, and a part of the metal part 11 (the side of the metal part 11) may be exposed on each surface of the semiconductor device 70 other than the top (front, back, left and right side surfaces, bottom surface).

半導体装置用基板1は、母型基板10上に金属部11の非配置部分に対応する第一レジスト層12を形成するのに続いて、金属部11の上部形状(張出部11cの張出し量)を調整制御する第二レジスト層16を形成し、その後、メッキで金属部11を形成して、第一レジスト層12及び第二レジスト層16を除去することで製造されるものである。表面金属層13は、金属部11の形成に続いて、張出部11c表面を含む金属部11表面にメッキすることで形成できる。ここで、表面金属層13を張出部11の上面Cに形成することで、表面金属層13の厚み分、張出部11cの側面Bに現れるが、表面金属層13を張出部11cの側面B全面に形成するようにしても良い。これにより、張出部11cとしての強度と金属部11の配置間隔を確保しながら、ワイヤ15との接合性に優れる領域をより拡げることができる。また、表面金属層13を張出部11cの側面B全面に形成すれば、表面金属層13の厚み分、張出部11cの下面Aに現れることになる。このように、表面金属層13は、張出部11の上面Cだけでなく、張出部11の側面B及び下面Aの一部または全面に形成しても良い。 The semiconductor device substrate 1 is manufactured by forming a first resist layer 12 corresponding to the non-placement portion of the metal portion 11 on the mother substrate 10, forming a second resist layer 16 that adjusts and controls the shape of the upper portion of the metal portion 11 (the amount of protrusion of the protruding portion 11c), and then forming the metal portion 11 by plating, and removing the first resist layer 12 and the second resist layer 16. The surface metal layer 13 can be formed by plating the surface of the metal portion 11 including the surface of the protruding portion 11c following the formation of the metal portion 11. Here, by forming the surface metal layer 13 on the upper surface C of the protruding portion 11, the thickness of the surface metal layer 13 appears on the side surface B of the protruding portion 11c, but the surface metal layer 13 may be formed on the entire side surface B of the protruding portion 11c. This makes it possible to further expand the area that has excellent bonding properties with the wire 15 while ensuring the strength of the protruding portion 11c and the placement interval of the metal portion 11. Furthermore, if the surface metal layer 13 is formed on the entire side surface B of the protruding portion 11c, the thickness of the surface metal layer 13 will be present on the underside A of the protruding portion 11c. In this way, the surface metal layer 13 may be formed not only on the upper surface C of the protruding portion 11, but also on part or the entire surface of the side surface B and underside A of the protruding portion 11.

また、この半導体装置用基板1を用いた半導体装置の製造の際は、この半導体装置用基板1に対し、金属部11表面側への半導体素子14の搭載及び配線、封止材19による封止がなされた後、半導体装置部分(封止材による封止部分)から母型基板10を除去して半導体装置70を得る仕組みである。 When manufacturing a semiconductor device using this semiconductor device substrate 1, the semiconductor element 14 is mounted and wired on the surface side of the metal part 11 of the semiconductor device substrate 1, and then the substrate 10 is sealed with a sealing material 19, and the mother substrate 10 is removed from the semiconductor device portion (the portion sealed with the sealing material) to obtain the semiconductor device 70.

母型基板10は、厚さ約0.1mmのステンレス(SUS430等)やアルミニウム、銅等の導電性の金属板で形成され、半導体装置の製造工程で除去されるまで、半導体装置用基板1の要部をなすものであり、半導体装置用基板製造工程の各段階で、表面側に第一レジスト層12、第二レジスト層16、金属部11が形成され、また裏面側にレジスト層18が配設される。金属部11の形成の際には、この母型基板10を介した通電がなされることで、母型基板10表面の第一レジスト層12及び第二レジスト層16に覆われない通電可能な部分に電解メッキで金属部11が形成されることとなる。また、表面金属層13も電解メッキで形成する場合には、母型基板10を介して通電がなされる。 The mother substrate 10 is formed of a conductive metal plate of stainless steel (e.g., SUS430), aluminum, copper, etc., with a thickness of about 0.1 mm, and constitutes a major part of the substrate 1 for the semiconductor device until it is removed in the manufacturing process of the semiconductor device. At each stage of the manufacturing process of the substrate for the semiconductor device, a first resist layer 12, a second resist layer 16, and a metal part 11 are formed on the front side, and a resist layer 18 is disposed on the back side. When forming the metal part 11, electricity is passed through the mother substrate 10, and the metal part 11 is formed by electrolytic plating on the part of the mother substrate 10 surface that is not covered by the first resist layer 12 and the second resist layer 16 and can be electrically conducted. In addition, when the surface metal layer 13 is also formed by electrolytic plating, electricity is passed through the mother substrate 10.

金属部11は、電解メッキに適したニッケルや銅、又はニッケル-コバルト等のニッケル合金からなり、母型基板10上の第一レジスト層12のない部分に、電解メッキで形成される構成である。半導体装置用基板1において、金属部11は、母型基板10表面で、半導体素子搭載部11aとその近傍に配置される電極部11bの組み合わせを一つの単位として、この組み合わせを製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。 The metal parts 11 are made of nickel or copper suitable for electrolytic plating, or a nickel alloy such as nickel-cobalt, and are formed by electrolytic plating in the areas of the mother substrate 10 where there is no first resist layer 12. In the substrate 1 for semiconductor device, the metal parts 11 are formed on the surface of the mother substrate 10 in a form in which a combination of a semiconductor element mounting part 11a and an electrode part 11b arranged in the vicinity thereof is regarded as one unit, and a large number of such combinations are aligned in an order equal to the number of semiconductor devices to be manufactured.

この金属部11は、第一レジスト層12の厚さを越える厚さ(例えば、厚さ約20~100μm)で、且つ上端周縁には第二レジスト層16側に向かって張出した略庇状の張出部11cを有する形状として形成される。張出部11cは、電解メッキの際、金属部11を第一レジスト層12の厚さまで形成した後も電解メッキを継続することで、金属部11の成長を厚さ方向(金属部11の軸方向)に加えて第二レジスト層16に向かう方向(金属部11の軸方向に直交する方向)にも進行させることで、第一レジスト層12を越えた金属部11上端部から第二レジスト層16側へ張出した形状として得られるものである。ここで、電解メッキによる金属部11の第二レジスト層16に向かう方向への成長は、第二レジスト層16が存在することで、係る方向へそれ以上成長することを規制でき、金属部11間の間隔を一定にすることができる。なお、この張出部11cは、封止材19による封止に伴って、封止材19で挟まれて固定された状態となる。 The metal part 11 is formed to a thickness (for example, about 20 to 100 μm) that exceeds the thickness of the first resist layer 12, and has a shape with a generally eaves-like protruding part 11c that protrudes toward the second resist layer 16 at the upper end periphery. The protruding part 11c is obtained as a shape that protrudes from the upper end of the metal part 11 beyond the first resist layer 12 to the second resist layer 16 side by continuing the electrolytic plating even after the metal part 11 is formed to the thickness of the first resist layer 12, so that the growth of the metal part 11 proceeds not only in the thickness direction (the axial direction of the metal part 11) but also in the direction toward the second resist layer 16 (the direction perpendicular to the axial direction of the metal part 11). Here, the growth of the metal part 11 toward the second resist layer 16 by electrolytic plating can be restricted from further growth in that direction by the presence of the second resist layer 16, and the interval between the metal parts 11 can be made constant. Furthermore, when the protruding portion 11c is sealed with the sealing material 19, it becomes sandwiched and fixed by the sealing material 19.

この他、金属部11のうち、半導体素子搭載部11aには、半導体装置製造の際に半導体素子14を挿入して搭載可能な凹部を設けることができる。この凹部に半導体素子14が挿入配設されると、その凹部の深さの分、従来のように半導体素子搭載部の上面に搭載される場合と比べて、半導体素子14の配設位置を下げることができる。この凹部は、凹部の下側に半導体素子搭載部11aが必要な強度を維持する厚さを十分確保可能な程度の深さとされる。また、電極部11bにも凹部を設けることができる。この凹部に封止材19が封止されると、その凹部の分、電極部上面と半導体装置の封止材とが広く接触することとなり、半導体装置における電極部の支持強度が向上し、耐久性を高めることができる。また、半導体装置の実装上の必要等から、電極部を底部だけでなく側面にも露出させる構造を採用する場合に、電極部11bに凹部を設け、この凹部を切断して切り分けることで、その凹部の深さの分、切断位置が下がり、切断加工における金属の切断量を減らすことができ、切断に伴う切断加工用装置の負担を減らし、刃部の劣化を抑えられる。なお、凹部の形状は有底に限らず、貫通形成されたものであっても良い。 In addition, the semiconductor element mounting portion 11a of the metal portion 11 can be provided with a recess into which the semiconductor element 14 can be inserted and mounted during the manufacture of the semiconductor device. When the semiconductor element 14 is inserted and arranged in this recess, the position of the semiconductor element 14 can be lowered by the depth of the recess compared to the conventional case where the semiconductor element 14 is mounted on the upper surface of the semiconductor element mounting portion. This recess is deep enough to ensure a thickness below the recess that maintains the necessary strength of the semiconductor element mounting portion 11a. A recess can also be provided in the electrode portion 11b. When the sealing material 19 is sealed in this recess, the upper surface of the electrode portion and the sealing material of the semiconductor device come into contact widely due to the recess, improving the support strength of the electrode portion in the semiconductor device and increasing durability. In addition, when a structure is adopted in which the electrode portion is exposed not only to the bottom but also to the side due to the need for mounting the semiconductor device, a recess is provided in the electrode portion 11b and this recess is cut and separated, so that the cutting position is lowered by the depth of the recess, reducing the amount of metal cut in the cutting process, reducing the burden on the cutting device associated with cutting, and suppressing deterioration of the blade portion. The shape of the recess is not limited to a bottomed one, but may be a through hole.

金属部11は、大部分を電解メッキに適したニッケルやニッケル合金等で形成されるが、金属部11の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするために、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば、金、錫、パラジウム、ハンダ等の薄膜11dが配設される構成である(図6(B)参照)。この薄膜11dの厚さは0.01~1μm程度とするのが好ましい。また、薄膜11dには、母型基板10のエッチング除去の際に、エッチング液による金属部11の侵食劣化を防ぐ機能を与えることもでき、その場合、金や銀、錫などの薄膜を配設するのが好ましい。なお、この金属部11裏面側の薄膜形成は、電解メッキで金属部11主材質部を形成する前に限られるものではなく、半導体装置70の完成後、メッキにより金属部11の露出した裏面側に薄膜11dを形成するようにしてもかまわない。 The metal part 11 is mostly made of nickel or a nickel alloy suitable for electrolytic plating, but on the back side of the metal part 11, a thin film 11d of a metal with better solder wettability than the main material part such as nickel, for example, gold, tin, palladium, solder, etc. is arranged so that soldering can be performed appropriately when mounting the semiconductor device (see FIG. 6(B)). The thickness of this thin film 11d is preferably about 0.01 to 1 μm. In addition, the thin film 11d can also be given a function to prevent the metal part 11 from being corroded and deteriorated by the etching solution when the mother substrate 10 is etched away, and in that case, it is preferable to arrange a thin film of gold, silver, tin, etc. Note that the formation of this thin film on the back side of the metal part 11 is not limited to before forming the main material part of the metal part 11 by electrolytic plating, but may be formed on the exposed back side of the metal part 11 by plating after the semiconductor device 70 is completed.

表面金属層13は、配線用のワイヤ15をなす金線等との接合性に優れる金属、例えば、金や銀等からなるメッキ膜として形成される。この表面金属層13は、母型基板10ごとのメッキ浴により金属部11及び張出部11cの表面に所定の厚さ、例えば、金メッキの場合は約0.1~1μm、銀メッキの場合は約1~10μmの厚さのメッキとして形成される。この表面金属層13のメッキの際、母型基板10の裏面側はレジスト層18で覆われていることから、メッキの付着等は生じない(図6(D)参照)。このように、金属部11の上面Dと張出部11cの上面Cに表面金属層13を形成することで、表面金属層13の厚み分、張出部11cの側面Bとして現れることになるので、ワイヤ15との接合性に優れる表面金属層13の表面積を大きくすることができる。なお、この表面金属層13へのメッキに際しては、金属部11のメッキの場合とはメッキ液を異ならせるなど、メッキの金属に対応するメッキ液を使用することとなる。 The surface metal layer 13 is formed as a plating film made of a metal, such as gold or silver, that has excellent bonding properties with the gold wires that form the wiring wires 15. This surface metal layer 13 is formed as a plating of a predetermined thickness, for example, about 0.1 to 1 μm in the case of gold plating and about 1 to 10 μm in the case of silver plating, on the surface of the metal part 11 and the protruding part 11c by a plating bath for each mother substrate 10. When plating the surface metal layer 13, the back side of the mother substrate 10 is covered with a resist layer 18, so that no plating adhesion occurs (see FIG. 6 (D)). In this way, by forming the surface metal layer 13 on the upper surface D of the metal part 11 and the upper surface C of the protruding part 11c, the thickness of the surface metal layer 13 appears as the side surface B of the protruding part 11c, so that the surface area of the surface metal layer 13 that has excellent bonding properties with the wires 15 can be increased. When plating the surface metal layer 13, a plating solution that corresponds to the metal to be plated will be used, such as a plating solution that is different from that used for plating the metal portion 11.

この表面金属層13をメッキ形成する際、メッキが付着しにくい場合、表面金属層13のメッキの前にあらかじめ金属部11表面に下地メッキ(銅ストライクメッキ、銀ストライクメッキ、又は金ストライクメッキ)を行い、表面金属層13の金属部11への密着性を高めることが望ましい。 When plating this surface metal layer 13, if the plating is difficult to adhere, it is desirable to first perform a base plating (copper strike plating, silver strike plating, or gold strike plating) on the surface of the metal part 11 before plating the surface metal layer 13, in order to improve the adhesion of the surface metal layer 13 to the metal part 11.

次に、本実施形態に係る半導体装置用基板の製造方法及び半導体装置用基板を用いた半導体装置の製造方法について説明する。 Next, we will explain the method for manufacturing a substrate for a semiconductor device according to this embodiment and the method for manufacturing a semiconductor device using the substrate for a semiconductor device.

半導体装置用基板の製造方法としては、母型基板10の表裏にレジスト層12、18をそれぞれ形成する工程と、さらに第一レジスト層12の上側で、張出部11cとして形成される金属部11の形成を抑えたい位置に対応させて、第二レジスト層16を形成する工程と、母型基板10表面の第一レジスト層12及び第二レジスト層16で覆われていない部分に金属部11を所定厚さまで形成する工程と、金属部11の表面に表面金属層13を形成する工程と、母型基板10表面側の第一レジスト層12、第二レジスト層16、及び裏面側のレジスト層18をそれぞれ除去する工程とを含むものであるといえる。以下にこれらの半導体装置用基板製造の各工程について具体的に説明する。 The method for manufacturing a substrate for a semiconductor device includes the steps of forming resist layers 12 and 18 on the front and back of the mother substrate 10, forming a second resist layer 16 on the upper side of the first resist layer 12 in a position where it is desired to suppress the formation of the metal portion 11 formed as the protruding portion 11c, forming the metal portion 11 to a predetermined thickness on the portion of the surface of the mother substrate 10 that is not covered by the first resist layer 12 and the second resist layer 16, forming a surface metal layer 13 on the surface of the metal portion 11, and removing the first resist layer 12, the second resist layer 16 on the front side of the mother substrate 10, and the resist layer 18 on the back side. Each of these steps for manufacturing a substrate for a semiconductor device is specifically described below.

はじめに、母型基板10上に金属部11をメッキ形成するために、金属部11の配置部分を露出(金属部11の非配置部分に対応)するように母型基板10に第一レジスト層12を形成する。具体的には、母型基板10の表面側に、感光性レジスト12aを、形成する金属部11に対応する所定厚さ(例えば約50μm)となるようにして形成する(図5(A)参照)。感光性レジスト12aに対しては、金属部11の配置位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジストを除去する現像等の処理を行い、金属部11の非配置部分に対応する開口パターンを有する第一レジスト層12を形成する(図5(B)参照)。また、母型基板10の裏面側にも、感光性レジストを表面側同様に形成し、そのまま全面に対する露光等の処理を経て、裏面全面にわたりレジスト層18を形成する。 First, in order to plate the metal parts 11 on the mother substrate 10, a first resist layer 12 is formed on the mother substrate 10 so that the parts where the metal parts 11 are to be disposed are exposed (corresponding to the parts where the metal parts 11 are not disposed). Specifically, a photosensitive resist 12a is formed on the front side of the mother substrate 10 to a predetermined thickness (for example, about 50 μm) corresponding to the metal parts 11 to be formed (see FIG. 5(A)). The photosensitive resist 12a is subjected to processes such as curing by exposure to ultraviolet light and development to remove the resist from the non-irradiated parts while a mask film of a predetermined pattern corresponding to the positions where the metal parts 11 are disposed is placed on the photosensitive resist 12a, thereby forming a first resist layer 12 having an opening pattern corresponding to the parts where the metal parts 11 are not disposed (see FIG. 5(B)). In addition, a photosensitive resist is also formed on the back side of the mother substrate 10 in the same manner as on the front side, and a resist layer 18 is formed over the entire back side through a process such as exposure to light.

続いて、第二レジスト層16を形成する工程では、最初に形成された第一レジスト層12の上に、金属部11の形成を抑えたい範囲に対応させて第二レジスト層16を配設する。具体的には、母型基板10と第一レジスト層12の表面側に、感光性レジスト16aを、所定厚さ(例えば約40μm)となるようにして密着配設する(図5(C)参照)。この感光性レジスト16aに対し、張出部11cの形成を抑えたい位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジスト剤を除去する現像等の処理を行い、金属部11を形成させない箇所に対応する開口パターンを有する第二レジスト層16を形成する(図6(A)参照)。この第二レジスト層16の存在により、金属部11をメッキ形成する際に、張出部11cの張出量を規制することができる。なお、第一レジスト層12の所定パターンの開口内面と、第二レジスト層16の所定パターンの開口内面との間には段差部20が形成されており(図6(A)参照)、この段差部20の幅寸法を設定することで、所望の張出量とすることができる。段差部20の幅寸法は、5μm以上が好ましく、本実施形態では、20μmとしている。段差部20の幅寸法が5μm未満であると、十分な張出量とならず、張出部11cとしての効果が得られにくい。 In the process of forming the second resist layer 16, the second resist layer 16 is disposed on the first resist layer 12 formed initially, corresponding to the area where the formation of the metal portion 11 is to be suppressed. Specifically, a photosensitive resist 16a is disposed in close contact with the surface side of the mother substrate 10 and the first resist layer 12 so as to have a predetermined thickness (for example, about 40 μm) (see FIG. 5 (C)). With a mask film of a predetermined pattern corresponding to the position where the formation of the protruding portion 11c is to be suppressed placed on this photosensitive resist 16a, the photosensitive resist 16a is cured by exposure to ultraviolet light, and developed to remove the resist agent in the non-irradiated portion, forming a second resist layer 16 having an opening pattern corresponding to the area where the metal portion 11 is not to be formed (see FIG. 6 (A)). The presence of this second resist layer 16 makes it possible to regulate the amount of protrusion of the protruding portion 11c when the metal portion 11 is formed by plating. A step 20 is formed between the inner surface of the opening of the predetermined pattern in the first resist layer 12 and the inner surface of the opening of the predetermined pattern in the second resist layer 16 (see FIG. 6A), and the desired amount of protrusion can be achieved by setting the width dimension of this step 20. The width dimension of the step 20 is preferably 5 μm or more, and in this embodiment, it is set to 20 μm. If the width dimension of the step 20 is less than 5 μm, the amount of protrusion is insufficient, and it is difficult to obtain the effect of the protrusion 11c.

第二レジスト層16を形成したら、母型基板10表面の第一レジスト層12並びに第二レジスト層16で覆われていない露出領域に対し、めっき前処理(酸浸漬、陰極電解、化学エッチング、ストライクメッキなど)を行う。その後、この露出領域にメッキ等によりハンダぬれ性改善用の金の薄膜11dを、例えば0.01~1μm厚で形成する(図6(B)参照)。そして、この薄膜11d上に、電解メッキによりニッケルを積層して金属部11を形成する(図6(C)参照)。 After the second resist layer 16 is formed, the exposed areas of the surface of the mother substrate 10 that are not covered by the first resist layer 12 and the second resist layer 16 are pre-treated for plating (acid immersion, cathodic electrolysis, chemical etching, strike plating, etc.). After that, a thin gold film 11d for improving solder wettability is formed on the exposed areas by plating or the like to a thickness of, for example, 0.01 to 1 μm (see FIG. 6(B)). Nickel is then layered on top of this thin film 11d by electrolytic plating to form the metal part 11 (see FIG. 6(C)).

この金属部11の形成工程で、金属部11は、第一レジスト層12の厚さを越える一方、第二レジスト層16の上面を越えない所定厚さ(例えば、厚さ約60μm)として形成され、第一レジスト層12寄りの金属部11上端周縁には、第一レジスト層12側に張出した略庇状の張出部11cが、第二レジスト層16の側面に接する部位を伴いつつ形成される(図6(C)参照)。この張出部11cの形成範囲は、金属部11が形成されないように配置された第二レジスト層16で規制されることから、張出部11cの張出し量はあらかじめ設定されたものとなる。また、金属部11は、母型基板10表面において、半導体素子搭載部11aとその近傍に複数配置される電極部11bの組合せを一つの単位として、製造する半導体装置の数だけ前記組合せが多数整列状態で並べられた形態で形成されることとなる。 In this metal part 11 forming process, the metal part 11 is formed to a predetermined thickness (for example, about 60 μm) that exceeds the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16, and a roughly eaves-shaped protruding part 11c that protrudes toward the first resist layer 12 side is formed on the upper edge of the metal part 11 near the first resist layer 12, with a portion that contacts the side of the second resist layer 16 (see FIG. 6 (C)). The formation range of this protruding part 11c is restricted by the second resist layer 16 that is arranged so that the metal part 11 is not formed, so the protruding amount of the protruding part 11c is preset. In addition, the metal part 11 is formed in a form in which a combination of a semiconductor element mounting part 11a and a plurality of electrode parts 11b arranged in the vicinity thereof is treated as one unit on the surface of the mother substrate 10, and a large number of such combinations are arranged in an aligned state in the number of semiconductor devices to be manufactured.

金属部11を所定厚さまで形成した後は、金属部11の表面に、表面金属層13を所定の厚さ、例えば銀メッキの場合、厚さ約1~10μmとなるように形成する(図6(D)参照)。メッキ浴に用いられるメッキ液に対し、第一レジスト層12及び第二レジスト層16は十分な耐性を有しているため、変質等が生じることはなく、レジスト層としての機能を維持し、金属部11等必要箇所以外へのメッキ付着を防ぐことができる。また、この表面金属層13のメッキの際、母型基板10の裏面側はレジスト層18で覆われていることから、メッキの付着はない。 After the metal portion 11 has been formed to a predetermined thickness, a surface metal layer 13 is formed on the surface of the metal portion 11 to a predetermined thickness, for example, about 1 to 10 μm in the case of silver plating (see FIG. 6(D)). The first resist layer 12 and the second resist layer 16 have sufficient resistance to the plating solution used in the plating bath, so they do not deteriorate and maintain their function as resist layers, preventing plating from adhering to areas other than the required areas, such as the metal portion 11. In addition, when plating the surface metal layer 13, the back side of the mother substrate 10 is covered with the resist layer 18, so no plating adheres to it.

表面金属層13形成後、母型基板10表面側の第一レジスト層12、第二レジスト層16、及び裏面側のレジスト層18を所定の除去剤で溶解させてそれぞれ除去すると、図2に示す半導体装置用基板1が完成する。 After the surface metal layer 13 is formed, the first resist layer 12 on the surface side of the mother substrate 10, the second resist layer 16, and the resist layer 18 on the back side are dissolved and removed with a specific remover, completing the semiconductor device substrate 1 shown in FIG. 2.

このように、金属部11が第一レジスト層12の厚さを越えて形成されることで、第一レジスト層12寄りの金属部11の上端周縁には第一レジスト層12側に張出した略庇状の張出部11cが形成される(図6(C)参照)。この時、第一レジスト層12上に第二レジスト層16が配設されていることで、張出部11cは、その形成範囲を第二レジスト層16で規制され、第二レジスト層16の側面に接する部位を伴いつつ形成される。結果として、張出部11cの張出し量は、あらかじめ設定された第二レジスト層16の配置に基づいた所定量に管理されることとなる。この場合、母型基板10上で隣り合う金属部11のそれぞれが上部に張出部11cを備えつつ、これら張出部11c同士があらかじめ設定された適切な間隔をなす状態に調整できることから、母型基板10上における金属部の配置間隔を従来に比べて小さくすることができる。すなわち、従来の工程では金属部の張出部の張出し量を厳密に管理できないため、張出部同士の間隔が後のレジスト除去を妨げる狭小なものとならないように金属部11の配置間隔を広めにとる必要があったのに対し、本実施形態では、張出部11cの張出し量を第二レジスト層16の配置で調整できることから、金属部11の配置間隔を詰めた場合でも、張出部11cの張出し量をレジスト除去が問題なく行える程度に抑えて、隣り合う金属部11の最小間隔を適切な量とすることができる。また、半導体装置(封止材19)の側面と対向位置関係にある金属部11において、張出部としての張出し量を調整することで、封止材19から金属部11がはみ出すことを防止できる。なお、金属部11の配置間隔は、張出部11cで抜けに対する十分な強度を得られる必要最小限の張出し量を確保でき、且つ金属部11間に第一レジスト層12の除去剤が到達して第一レジスト層12が適切に除去できる状態が維持される範囲で、小さくすることができる(図7参照)。そして、張出部11cの側面Bを金属部11の軸方向と平行とすることで、金属部11の配置間隔をより正確かつ適切なものとすることができる。これにより、半導体装置用基板1上で形成される半導体装置の一層の小型化が図れると共に、半導体装置用基板1上での半導体装置の形成密度を高められ、半導体装置の製造を効率化できる。 In this way, the metal part 11 is formed beyond the thickness of the first resist layer 12, and a generally eaves-shaped protruding part 11c that protrudes toward the first resist layer 12 is formed at the upper end periphery of the metal part 11 near the first resist layer 12 (see FIG. 6(C)). At this time, since the second resist layer 16 is disposed on the first resist layer 12, the protruding part 11c is formed with a portion that contacts the side of the second resist layer 16, with its formation range being regulated by the second resist layer 16. As a result, the protruding amount of the protruding part 11c is managed to a predetermined amount based on the arrangement of the second resist layer 16 that is set in advance. In this case, since each of the adjacent metal parts 11 on the mother substrate 10 has a protruding part 11c at the top, and these protruding parts 11c can be adjusted to a state where they are spaced apart from each other at a predetermined appropriate interval, the arrangement interval of the metal parts on the mother substrate 10 can be made smaller than in the past. That is, in the conventional process, since the amount of overhang of the overhanging portion of the metal portion cannot be strictly controlled, it was necessary to arrange the metal portions 11 at a wide interval so that the interval between the overhanging portions would not become too narrow to prevent the subsequent removal of the resist, whereas in the present embodiment, since the amount of overhang of the overhanging portion 11c can be adjusted by the arrangement of the second resist layer 16, even if the arrangement interval of the metal portions 11 is narrowed, the amount of overhang of the overhanging portion 11c can be suppressed to an extent that the resist can be removed without problems, and the minimum interval between adjacent metal portions 11 can be made an appropriate amount. Also, by adjusting the amount of overhang of the overhanging portion of the metal portion 11 that faces the side surface of the semiconductor device (sealing material 19), it is possible to prevent the metal portion 11 from protruding from the sealing material 19. The spacing between the metal parts 11 can be made small to the extent that the minimum amount of overhang required to provide sufficient strength against removal at the overhanging parts 11c is ensured, and the remover for the first resist layer 12 can reach between the metal parts 11 to properly remove the first resist layer 12 (see FIG. 7). By making the side surface B of the overhanging parts 11c parallel to the axial direction of the metal parts 11, the spacing between the metal parts 11 can be made more accurate and appropriate. This allows the semiconductor device formed on the substrate 1 for semiconductor device to be further miniaturized, and increases the formation density of the semiconductor device on the substrate 1 for semiconductor device, making the manufacturing of the semiconductor device more efficient.

また、母型基板10上に第一レジスト層12を形成する工程に続いて、第二レジスト層16を形成し、その後に金属部11を形成するようにすることで、第一レジスト層12上側に達する金属部11(張出部11c)の形成範囲を制御できることに加え、各レジスト層12・16を先にまとめて形成し、金属部11の形成を一工程(1回のメッキ)で行うことができ、生産効率の向上が図れることとなる。なお、上記説明では、第一レジスト層12及び第二レジスト層16を形成するにあたり、第一レジスト層12を形成してから第二レジスト層16を形成しているが、第一レジスト層12を形成する工程において、感光性レジスト12aに対して所定パターンで露光後、現像を行わずに、引き続き感光性レジスト12a上に感光性レジスト16aを形成し、感光性レジスト16aに対して所定パターンで露光した後に、感光性レジスト12a及び感光性レジスト16a(未露光部)を併せて現像するようにしても良い。この場合、感光性レジスト16a(第二レジスト層16)は、母型基板10の一面に形成した感光性レジスト12a上に形成するので、感光性レジスト16aの形成が容易になるとともに、現像処理を1回で済ませることができる。さらに、感光性レジスト12aと感光性レジスト16aとで露光感度が異なるものを使用して形成することもでき、例えば、母型基板10上に感光性レジスト12aと、感光性レジスト12aよりも露光感度が低い感光性レジスト16aとを順に積層すれば、1回の露光・現像処理より、図6(A)に示す、第一レジスト層12上に第二レジスト層16を形成した状態を得ることができる。また、感光性レジスト12a及び感光性レジスト16aに対する露光は、所定パターンが形成されたマスクを用いて行っているが、直描露光装置を用いて直接露光するようにしても良い。 In addition, by forming the second resist layer 16 following the process of forming the first resist layer 12 on the mother substrate 10 and then forming the metal portion 11, the formation range of the metal portion 11 (protruding portion 11c) that reaches the upper side of the first resist layer 12 can be controlled, and the resist layers 12 and 16 can be formed together in advance to form the metal portion 11 in one process (one plating), thereby improving production efficiency. In the above explanation, when forming the first resist layer 12 and the second resist layer 16, the first resist layer 12 is formed and then the second resist layer 16 is formed, but in the process of forming the first resist layer 12, after the photosensitive resist 12a is exposed to light in a predetermined pattern, the photosensitive resist 16a may be formed on the photosensitive resist 12a without development, and after the photosensitive resist 16a is exposed to light in a predetermined pattern, the photosensitive resist 12a and the photosensitive resist 16a (unexposed portion) may be developed together. In this case, the photosensitive resist 16a (second resist layer 16) is formed on the photosensitive resist 12a formed on one side of the mother substrate 10, so that the photosensitive resist 16a can be easily formed and the development process can be completed in one step. Furthermore, the photosensitive resist 12a and the photosensitive resist 16a can be formed using resists having different exposure sensitivities. For example, if the photosensitive resist 12a and the photosensitive resist 16a having a lower exposure sensitivity than the photosensitive resist 12a are laminated in order on the mother substrate 10, the state in which the second resist layer 16 is formed on the first resist layer 12 as shown in FIG. 6(A) can be obtained by one exposure and development process. Furthermore, the exposure of the photosensitive resist 12a and the photosensitive resist 16a is performed using a mask having a predetermined pattern formed thereon, but it is also possible to directly expose them using a direct writing exposure device.

続いて、得られた半導体装置用基板1を用いた半導体装置の製造方法について説明すると、まず、半導体装置用基板1における金属部11のうち半導体素子搭載部11aに、接着剤を介在させた上で半導体素子14を搭載し、接着固定状態とし、さらに、半導体素子14表面の電極と、これに対応する各電極部11bとを、金線等のワイヤ15によって接合し、半導体素子14と各電極部11bとを電気的接続状態とする(図8(A)参照)。この配線による電気的接続は、超音波ボンディング装置等により実施される。電極部11bの表面には表面金属層13が形成されているため、ワイヤ15との接合を確実なものとすることができ、接続の信頼性を高められる。この半導体素子14は、微細な電子回路が形成されたいわゆるチップである。なお、接着材としては、固体状、粘体状、液体状のものがあり、例えば、銀ペースト、樹脂ペースト、ダイアタッチフィルムが挙げられる。また、半導体素子14と電極部11bとの電気的接続をワイヤボンディング方式で行っているが、フリップチップ方式で行ってもよい。 Next, a method for manufacturing a semiconductor device using the obtained semiconductor device substrate 1 will be described. First, a semiconductor element 14 is mounted on the semiconductor element mounting portion 11a of the metal portion 11 of the semiconductor device substrate 1 with an adhesive interposed therebetween, and the semiconductor element 14 is fixed in an adhesive state. Furthermore, the electrodes on the surface of the semiconductor element 14 are joined to the corresponding electrode portions 11b by wires 15 such as gold wires, and the semiconductor element 14 and each electrode portion 11b are electrically connected (see FIG. 8(A)). This electrical connection by wiring is performed by an ultrasonic bonding device or the like. Since a surface metal layer 13 is formed on the surface of the electrode portion 11b, the connection with the wire 15 can be made reliable, and the reliability of the connection can be improved. This semiconductor element 14 is a so-called chip on which a fine electronic circuit is formed. The adhesive may be solid, viscous, or liquid, and examples of the adhesive include silver paste, resin paste, and die attach film. Although the electrical connection between the semiconductor element 14 and the electrode portion 11b is performed by wire bonding, it may also be performed by flip chip method.

半導体素子14と各電極部11bとの接続が完了したら、母型基板10の表面側における金属部11等のある半導体装置となる範囲を、物理的強度の高い熱硬化性エポキシ樹脂等の封止材19で封止し、半導体素子14やワイヤ15を外部から隔離した保護状態とする(図8(B)参照)。詳細には、母型基板10の表面側を上型となるモールド金型に装着し、母型基板10に下型の役割を担わせつつ、モールド金型内に封止材19となる硬化前のエポキシ樹脂を圧入するという過程で封止が実行され、母型基板10上では、一つの半導体装置となる半導体素子搭載部11aと複数の電極部11bとの組合せが多数整列状態のままで一様に封止され、半導体装置が多数つながった状態で現れることとなる。なお、半導体素子14がLED等の発光素子の場合は、透光性の材質が用いられる。 After the connection between the semiconductor element 14 and each electrode portion 11b is completed, the area on the surface side of the mother substrate 10 that will become the semiconductor device, including the metal portion 11, etc., is sealed with a sealing material 19 such as a thermosetting epoxy resin with high physical strength, isolating the semiconductor element 14 and wires 15 from the outside and protecting them (see FIG. 8(B)). In detail, the surface side of the mother substrate 10 is attached to a mold die that will become the upper die, and the sealing is performed in the process of pressing the epoxy resin before hardening that will become the sealing material 19 into the mold die while the mother substrate 10 plays the role of the lower die, and on the mother substrate 10, the combination of the semiconductor element mounting portion 11a and the multiple electrode portions 11b that will become one semiconductor device is uniformly sealed in a multiplicity of aligned states, and the semiconductor device appears in a multiplicity of connected states. Note that when the semiconductor element 14 is a light-emitting element such as an LED, a light-transmitting material is used.

この多数つながった状態の半導体装置が得られたら、母型基板10を除去し、各半導体装置の底部に金属部11の裏面側が露出した状態を得る(図8(C)参照)。ステンレス材製である母型基板10の除去には、半導体装置側から母型基板10を物理的に引き剥がして除去する方法を用いる。母型基板10として強度及び剥離性に優れるステンレス材を用いることで、半導体装置側から母型基板10を引き剥がして速やかに分離除去することができる。この時、封止材19を十分な物理的強度を有するものとすることで、母型基板10を引き剥がし除去する場合にも、割れ等の破損もなく金属部11との一体化状態を維持することができる。 Once these multiple connected semiconductor devices are obtained, the mother substrate 10 is removed, leaving the back side of the metal part 11 exposed at the bottom of each semiconductor device (see FIG. 8(C)). The mother substrate 10, which is made of stainless steel, is removed by physically peeling it off from the semiconductor device. By using stainless steel, which has excellent strength and peelability, as the mother substrate 10, it can be peeled off from the semiconductor device and quickly removed. At this time, by making the sealing material 19 have sufficient physical strength, even when the mother substrate 10 is peeled off and removed, it can maintain its integrated state with the metal part 11 without cracking or other damage.

この他、母型基板10が他の金属材、例えば、銅材である場合には、母型基板10を除去する方法として、母型基板10をエッチング液に浸漬して溶解させる方法を用いることもできる。このエッチングの場合、母型基板10は溶解するが金属部11や表面金属層13の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、半導体装置側に過大な力が加わらないため、母型基板10の除去に伴って悪影響が生じる確率を小さくできる。 In addition, when the mother substrate 10 is made of another metal material, for example, copper, the mother substrate 10 can be removed by immersing it in an etching solution and dissolving it. In this etching, an etching solution is used that has selective etching properties such that the mother substrate 10 dissolves but the material of the metal portion 11 and the surface metal layer 13 is not damaged. When removing by dissolution, no excessive force is applied to the semiconductor device, so the probability of adverse effects occurring due to removal of the mother substrate 10 can be reduced.

母型基板10を除去された半導体装置の底部では、露出する金属部11の裏面側と、封止材19の裏面側とが略同一平面上に位置する状態となっている。母型基板10の除去後、多数つながった状態の半導体装置を一つ一つ切り離せば、半導体装置70としての完成となる。 At the bottom of the semiconductor device after the mother substrate 10 has been removed, the exposed back side of the metal part 11 and the back side of the sealing material 19 are positioned on approximately the same plane. After removing the mother substrate 10, the multiple connected semiconductor devices are separated one by one to complete the semiconductor device 70.

得られた半導体装置70内部において、金属部11の上端周縁を張出部11cとして略庇状に張り出し形成し、封止材19による封止状態で、この張出部11cが硬化した封止材19に囲まれて固定されていることから、樹脂同士で密着し強固に一体化した封止材19に張出部11cが食込んで、金属部11に加わる外力に対する抵抗体の役割を果すこととなり、母型基板10にステンレス材等を用い、半導体装置側から母型基板10を物理的に引き剥がして除去する場合など、金属部11裏面側に装置外装から引離そうとする外力が加わっても、張出部11cが金属部11の移動を妨げ、金属部11の他部分に対するずれ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。 Inside the obtained semiconductor device 70, the upper edge of the metal part 11 is formed as a protruding part 11c that protrudes in a roughly eave-like shape, and in a sealed state with the sealing material 19, this protruding part 11c is surrounded and fixed by the hardened sealing material 19. Therefore, the protruding part 11c bites into the sealing material 19, which is tightly integrated with the resin, and acts as a resistor against external forces applied to the metal part 11. Even if an external force is applied to the back side of the metal part 11 to separate it from the device exterior, such as when stainless steel or the like is used for the mother substrate 10 and the mother substrate 10 is physically peeled off and removed from the semiconductor device side, the protruding part 11c prevents the metal part 11 from moving, and it is possible to eliminate the misalignment of the metal part 11 with respect to other parts, thereby improving the yield during manufacturing, increasing the strength of the semiconductor device, and improving the durability during use and the reliability of the operation of the semiconductor device.

第一レジスト層12、第二レジスト層16、及びレジスト層18は、金属部11のメッキや表面金属層13のメッキで使用するメッキ液に対する耐溶解性を備えた絶縁性材で形成されている。また、第一レジスト層12、第二レジスト層16、及びレジスト層18は、例えば、アルカリ現像タイプの感光性フィルムレジストを熱圧着等により配設し、露光や現像等の各処理を経て、形成することができる。なお、この第一レジスト層12、第二レジスト層16、及びレジスト層18については、上記した感光性レジストに限られるものではなく、メッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基板10上における金属部11の非配置部分や張出部11cの形成を規制したい位置に、電着塗装等により必要な塗膜厚さとなるように塗装して形成することもできる。 The first resist layer 12, the second resist layer 16, and the resist layer 18 are formed of an insulating material that is resistant to dissolution in the plating solution used in plating the metal part 11 and the surface metal layer 13. The first resist layer 12, the second resist layer 16, and the resist layer 18 can be formed, for example, by disposing an alkali-developable photosensitive film resist by thermocompression bonding or the like, and then undergoing various processes such as exposure and development. The first resist layer 12, the second resist layer 16, and the resist layer 18 are not limited to the above-mentioned photosensitive resist, and can also be formed by applying a paint that is not altered by the plating solution and can provide a strong coating film to the non-positioned parts of the metal part 11 on the mother substrate 10 and the positions where the formation of the protruding parts 11c is to be restricted, to the required coating thickness by electrochemical coating or the like.

また、上記実施形態では、金属部11は円柱状としているが、これに限らず、図9に示す四角柱状、その他にも三角柱状など種々の形状であっても良い。また、金属部11の下部分(第一レジスト層12の厚さ内に形成される部分)の外形と金属部11の上部分及び張出部11c(第二レジスト層16の厚さ内に形成される部分)の外形との形状を異ならせても良く、例えば、金属部11の下部分を四角柱状に、金属部11の上部分及び張出部11cを円柱状に形成することができる。係る形状は、第一レジスト層12における開口パターンを四角状に形成し、第二レジスト層16における開口パターンを円状に形成することで得られる。このように、金属部11及び張出部11cの形状は、第一レジスト層12及び第二レジスト層16の開口パターンを所望の形状にすることで自由に設定することができる。 In the above embodiment, the metal part 11 is cylindrical, but it may be a square prism as shown in FIG. 9 or a triangular prism. The shape of the lower part of the metal part 11 (the part formed within the thickness of the first resist layer 12) may be different from the shape of the upper part and the protruding part 11c of the metal part 11 (the part formed within the thickness of the second resist layer 16). For example, the lower part of the metal part 11 may be formed in a square prism shape, and the upper part of the metal part 11 and the protruding part 11c may be formed in a cylindrical shape. Such a shape can be obtained by forming the opening pattern in the first resist layer 12 in a square shape and the opening pattern in the second resist layer 16 in a circular shape. In this way, the shapes of the metal part 11 and the protruding part 11c can be freely set by forming the opening patterns of the first resist layer 12 and the second resist layer 16 in the desired shapes.

また、張出部11cの張出し量を規制するために第一レジスト層12上に形成している第二レジスト層16は部分的に形成しても良い。これは、金属部11(半導体素子搭載部11a)上に半導体素子14を搭載する際に使用する接着剤(ペースト)が金属部11(半導体素子搭載部11a)表面から落ちないようにするために、金属部11(半導体素子搭載部11a)表面の面積をできるだけ大きく確保することが求められているが、半導体装置としての形状・寸法及び半導体装置の底部(封止材19の裏面)から外部電極や放熱パッドなどとして露出する金属部11の裏面の位置・形状・寸法は仕様として決まっているため、金属部11の表面の形状・寸法を金属部11の裏面の形状・寸法と同じにしてしまうと、金属部11の表面積は小さいものとなってしまう。そこで、張出部として側面Bを有するものと有さないものが混在する構成、具体的には、図10に示すように、半導体装置(封止材19)の側面と対向位置関係にある張出部11cのみが側面Bを有する構成とすることにより、金属部11の表面積を大きく確保することができる。係る構成は、第二レジスト層16を部分的に形成すること、つまり、金属部11cにおいて、半導体装置(封止材19)の側面と対向する側では張出部11cの張出し量を規制し、金属部11と隣接する側では張出部11cの張出し量を規制しないようにしている。以下に、係る構成の半導体装置用基板の製造方法を図11に基づいて説明する。 In addition, the second resist layer 16 formed on the first resist layer 12 may be partially formed to regulate the amount of overhang of the overhang 11c. This is because it is required to secure as large an area as possible for the surface of the metal part 11 (semiconductor element mounting part 11a) in order to prevent the adhesive (paste) used when mounting the semiconductor element 14 on the metal part 11 (semiconductor element mounting part 11a) from falling off the surface of the metal part 11 (semiconductor element mounting part 11a). However, since the shape and dimensions of the semiconductor device and the position, shape and dimensions of the back surface of the metal part 11 exposed from the bottom of the semiconductor device (the back surface of the sealing material 19) as an external electrode or heat dissipation pad are determined as specifications, if the shape and dimensions of the front surface of the metal part 11 are made the same as the shape and dimensions of the back surface of the metal part 11, the surface area of the metal part 11 will be small. Therefore, by adopting a configuration in which some overhanging portions have side B and others do not, specifically, as shown in FIG. 10, only the overhanging portion 11c that faces the side of the semiconductor device (sealing material 19) has side B, it is possible to ensure a large surface area of the metal portion 11. This configuration is achieved by partially forming the second resist layer 16, that is, the overhang amount of the overhanging portion 11c on the side of the metal portion 11c that faces the side of the semiconductor device (sealing material 19) is restricted, and the overhang amount of the overhanging portion 11c on the side adjacent to the metal portion 11 is not restricted. Below, a method for manufacturing a substrate for a semiconductor device having such a configuration will be described with reference to FIG. 11.

まず、母型基板10の表面側に感光性レジスト12aを形成し、この感光性レジスト12aに対して、露光・現像等の処理を行って第一レジスト層12を形成した後、母型基板10と第一レジスト層12の表面側に感光性レジスト16aを形成する。また、母型基板10の裏面側にもレジスト層18を形成する。ここまでの工程は上記実施形態(図5参照)と同じなので、具体的な説明は省略するが、感光性レジスト12aを20~40μm(ここでは25μm)の厚さで形成し、感光性レジスト16aを30~80μm(ここでは45μm)の厚さで形成する。次に、感光性レジスト16aに対して、張出部11cの形成を抑えたい位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジストを除去する現像等の処理を行い、金属部11を形成させない箇所に対応する開口パターンを有する第二レジスト層16を形成する(図11(A)参照)。この第二レジスト層16の存在により、金属部11をメッキ形成する際に、張出部11cの張出量を規制することができ、ここでは、半導体装置(封止材19)の側面と対向する位置にあたる箇所に第二レジスト層16を形成する。なお、第一レジスト層12の所定パターンの開口内面と、第二レジスト層16の所定パターンの開口内面との間には段差部20が形成され、この段差部20の幅寸法が張出部11cの張出し量となり、段差部20の幅寸法は、5μm以上が好ましい。 First, a photosensitive resist 12a is formed on the surface side of the mother substrate 10, and the photosensitive resist 12a is exposed, developed, and other processes are performed to form a first resist layer 12. Then, a photosensitive resist 16a is formed on the surface side of the mother substrate 10 and the first resist layer 12. A resist layer 18 is also formed on the back side of the mother substrate 10. Since the process up to this point is the same as the above embodiment (see FIG. 5), a detailed description is omitted, but the photosensitive resist 12a is formed to a thickness of 20 to 40 μm (25 μm in this case), and the photosensitive resist 16a is formed to a thickness of 30 to 80 μm (45 μm in this case). Next, with a mask film of a predetermined pattern corresponding to the position where the formation of the protruding portion 11c is to be suppressed placed on the photosensitive resist 16a, a process such as curing by exposure to ultraviolet light irradiation and development to remove the resist in the non-irradiated portion is performed to form a second resist layer 16 having an opening pattern corresponding to the position where the metal portion 11 is not to be formed (see FIG. 11 (A)). The presence of this second resist layer 16 makes it possible to regulate the amount of overhang of the overhang 11c when the metal portion 11 is plated. Here, the second resist layer 16 is formed at a position facing the side of the semiconductor device (sealing material 19). A step 20 is formed between the inner surface of the opening of the predetermined pattern of the first resist layer 12 and the inner surface of the opening of the predetermined pattern of the second resist layer 16. The width of this step 20 is the amount of overhang of the overhang 11c, and the width of the step 20 is preferably 5 μm or more.

第二レジスト層16を形成したら、母型基板10表面の第一レジスト層12並びに第二レジスト層16で覆われていない露出領域に対し、めっき前処理(酸浸漬、陰極電解、化学エッチング、ストライクメッキなど)を行った後、この露出領域に薄膜11dと金属部11とを積層形成する(図11(B)参照)。ここでは、薄膜11dとして金を0.01~1μm厚でめっき形成し、この薄膜11d上に、金属部11としてニッケルを50~100μm厚でめっき形成する。この時、金属部11は、第一レジスト層12の厚さを越えて形成され、第二レジスト層16が形成されている領域では、第二レジスト層16の上面を越えない所定厚さ(ここでは60μm)として形成され、第一レジスト層12寄りの金属部11上端周縁には、第一レジスト層12側に張出した略庇状の張出部11cが、第二レジスト層16の側面に接する部位を伴いつつ形成される。なお、第二レジスト層16が形成されている領域と形成されていない領域とでは張出部の形状が異なるものであり、特徴として、第二レジスト層16が形成されている領域では側面Bを有する張出部11cが形成され、第二レジスト層16が形成されていない領域では側面Bを有さない張出部11c’が形成されることとなる。 After the second resist layer 16 is formed, the exposed area of the surface of the mother substrate 10 that is not covered by the first resist layer 12 and the second resist layer 16 is pre-treated for plating (acid immersion, cathodic electrolysis, chemical etching, strike plating, etc.), and then the thin film 11d and the metal part 11 are laminated on the exposed area (see FIG. 11(B)). Here, the thin film 11d is plated with gold to a thickness of 0.01 to 1 μm, and the metal part 11 is plated with nickel to a thickness of 50 to 100 μm on the thin film 11d. At this time, the metal part 11 is formed to a thickness exceeding that of the first resist layer 12, and in the area where the second resist layer 16 is formed, it is formed to a predetermined thickness (here, 60 μm) that does not exceed the upper surface of the second resist layer 16, and at the upper end periphery of the metal part 11 near the first resist layer 12, a roughly eaves-shaped protruding part 11c protruding toward the first resist layer 12 side is formed with a part that contacts the side of the second resist layer 16. The shape of the protrusion is different in the area where the second resist layer 16 is formed and the area where it is not formed. The characteristic is that in the area where the second resist layer 16 is formed, a protrusion 11c having a side B is formed, and in the area where the second resist layer 16 is not formed, a protrusion 11c' without a side B is formed.

金属部11を形成した後は、金属部11の表面に、表面金属層13を形成する(図11(C)参照)。ここでは、表面金属層13として銀を1~10μm厚でめっき形成する。表面金属層13を形成した後、母型基板10表裏の第一レジスト層12、第二レジスト層16、及びレジスト層18を除去することで、半導体装置用基板1が完成する(図11(D)参照)。 After the metal portion 11 is formed, a surface metal layer 13 is formed on the surface of the metal portion 11 (see FIG. 11(C)). Here, the surface metal layer 13 is formed by plating silver to a thickness of 1 to 10 μm. After the surface metal layer 13 is formed, the first resist layer 12, the second resist layer 16, and the resist layer 18 on the front and back of the mother substrate 10 are removed, completing the substrate 1 for the semiconductor device (see FIG. 11(D)).

こうして得られた半導体装置用基板1を用いた半導体装置の製造方法については、上記実施形態(図8参照)のように、半導体素子搭載部11a上に半導体素子14を搭載し、この半導体素子14の電極と、これに対応する各電極部11bとをワイヤ15によって接合して半導体素子14と各電極部11bとを電気的接続した後、封止材19によって封止し、母型基板10を除去して半導体装置として一つ一つ切り出すことで半導体装置用が完成する。これにより、半導体装置の底部(封止材19の裏面)において、露出する金属部11の裏面が外部電極や放熱パッドとして位置・形状・寸法が仕様として決められていても、金属部11の表面形状を自由に設定でき、金属部11の表面積を大きく確保することができる。 As for the manufacturing method of the semiconductor device using the semiconductor device substrate 1 obtained in this way, as in the above embodiment (see FIG. 8), the semiconductor element 14 is mounted on the semiconductor element mounting portion 11a, the electrodes of this semiconductor element 14 are joined to the corresponding electrode portions 11b by wires 15 to electrically connect the semiconductor element 14 to each electrode portion 11b, and then the semiconductor device is sealed with a sealing material 19, and the mother substrate 10 is removed and cut out one by one as a semiconductor device to complete the semiconductor device. As a result, even if the position, shape, and dimensions of the exposed back surface of the metal portion 11 at the bottom of the semiconductor device (back surface of the sealing material 19) are specified as an external electrode or heat dissipation pad, the surface shape of the metal portion 11 can be freely set, and a large surface area of the metal portion 11 can be secured.

なお、第二レジスト層16の形状(幅寸法)を小さくする(段差部20の幅寸法を大きくする)ことでも、金属部11の表面積を大きくすることはできるが、第二レジスト層16の形状(幅寸法)を小さくし過ぎると、第二レジスト層16の下部に形成されている第一レジスト層12の除去が困難となるおそれがあるので、生産性も考慮すると、図11に示す製造方法が好ましい。また、図10に示す半導体装置及び図11(D)に示す半導体装置用基板では、第二レジスト層16を部分的に形成し、半導体装置(封止材19)の側面と対向する側における張出部11cの張出し量を規制しているが、図12に示すように、金属部11が隣接する側において張出部11cの張出し量を規制するようにしても良い。この場合、金属部11(半導体素子搭載部11aや電極部11b)が隣接する側を規制することで、金属部11の配置間隔を小さくできつつ、金属部11の表面積を大きく確保することができる。 The surface area of the metal part 11 can be increased by reducing the shape (width) of the second resist layer 16 (increasing the width of the step part 20). However, if the shape (width) of the second resist layer 16 is made too small, it may be difficult to remove the first resist layer 12 formed under the second resist layer 16. Therefore, in consideration of productivity, the manufacturing method shown in FIG. 11 is preferable. In addition, in the semiconductor device shown in FIG. 10 and the semiconductor device substrate shown in FIG. 11(D), the second resist layer 16 is partially formed to restrict the protrusion amount of the protrusion part 11c on the side facing the side of the semiconductor device (sealing material 19). However, as shown in FIG. 12, the protrusion amount of the protrusion part 11c may be restricted on the side adjacent to the metal part 11. In this case, by restricting the side adjacent to the metal part 11 (semiconductor element mounting part 11a and electrode part 11b), the arrangement interval of the metal part 11 can be reduced while ensuring a large surface area of the metal part 11.

1 半導体装置用基板
10 母型基板
11 金属部
11a 半導体素子搭載部
11b 電極部
11c 張出部(第一張出部)
11c’ 張出部(第二張出部)
11d 薄膜
12 第一レジスト層
13 表面金属層
14 半導体素子
15 ワイヤ
16 第二レジスト層
18 レジスト層
19 封止材
20 段差部
70 半導体装置
REFERENCE SIGNS LIST 1 Substrate for semiconductor device 10 Mother substrate 11 Metal part 11a Semiconductor element mounting part 11b Electrode part 11c Extension part (first extension part)
11c' Overhanging part (second overhanging part)
Reference Signs List 11d thin film 12 first resist layer 13 surface metal layer 14 semiconductor element 15 wire 16 second resist layer 18 resist layer 19 sealing material 20 step portion 70 semiconductor device

Claims (2)

母型基板(10)上に半導体素子搭載部(11a)及び/又は電極部(11b)となる金属部(11)を複数備える半導体装置用基板であって、
前記金属部(11)には張出部が形成され、
前記張出部は、前記金属部(11)の軸方向と直交する方向に前記金属部(11)から張出し形成されており、
前記張出部を含めた前記金属部(11)の上面の面積は、前記母型基板(10)の表面と接する前記金属部(11)の裏面の面積より大きく形成され、
前記張出部は、形状が異なる第一張出部(11c)と第二張出部(11c’)とを有し、
前記第一張出部(11c)は、前記金属部(11)の軸方向と直交する方向に平行な下面と、前記金属部(11)の上面に連続して形成される上面と、該下面と上面の間に形成される側面とを有し、
前記第一張出部(11c)の上面は、前記金属部(11)の上面から前記第一張出部(11c)の側面に連続形成された曲面であり、
前記第二張出部(11c’)は、前記金属部(11)の軸方向と直交する方向に平行な下面と、前記金属部(11)の上面に連続して形成される上面とを有しており、
前記各金属部(11)において、隣接する前記金属部(11)と対向する側に前記第二張出部(11c’)が形成され、隣接する前記金属部(11)と対向する側を除く位置に前記第一張出部(11c)が形成され、
前記各金属部(11)において、隣接する前記金属部(11)と対向する側における前記第二張出部(11c’)の張出し量は、隣接する前記金属部(11)と対向する側を除く位置における前記第一張出部(11c)の張出し量より大きく形成されていることを特徴とする半導体装置用基板。
A substrate for a semiconductor device comprising a mother substrate (10) and a plurality of metal portions (11) serving as semiconductor element mounting portions (11a) and/or electrode portions (11b),
A protruding portion is formed on the metal portion (11),
The protruding portion is formed to protrude from the metal portion (11) in a direction perpendicular to an axial direction of the metal portion (11),
The area of the upper surface of the metal portion (11), including the protruding portion, is formed to be larger than the area of the rear surface of the metal portion (11) that is in contact with the front surface of the mother substrate (10);
The protruding portion has a first protruding portion (11c) and a second protruding portion (11c') having different shapes,
The first protruding portion (11c) has a lower surface parallel to a direction perpendicular to the axial direction of the metal portion (11), an upper surface formed continuously with the upper surface of the metal portion (11), and a side surface formed between the lower surface and the upper surface,
an upper surface of the first protruding portion (11c) is a curved surface that is continuously formed from an upper surface of the metal portion (11) to a side surface of the first protruding portion (11c);
The second protruding portion (11c') has a lower surface parallel to a direction perpendicular to the axial direction of the metal portion (11) and an upper surface formed continuously with the upper surface of the metal portion (11),
In each of the metal portions (11), the second protruding portion (11c') is formed on a side facing the adjacent metal portion (11), and the first protruding portion (11c) is formed at a position other than the side facing the adjacent metal portion (11),
A substrate for a semiconductor device, characterized in that in each of the metal portions (11), the amount of protrusion of the second protrusion portion (11c') on the side facing the adjacent metal portion (11) is formed to be greater than the amount of protrusion of the first protrusion portion (11c) at a position other than the side facing the adjacent metal portion (11).
半導体素子(14)と、半導体素子搭載部(11a)及び/又は電極部(11b)となる金属部(11)とを備え、前記金属部(11)を複数有し、前記半導体素子(14)と前記金属部(11)とが電気的に接続され、封止材(19)によって封止された半導体装置であって、
前記金属部(11)には張出部が形成され、
前記張出部は、前記金属部(11)の軸方向と直交する方向に前記金属部(11)から張出し形成されており、
前記張出部を含めた前記金属部(11)の上面の面積は、前記封止材(19)の底面から露出する前記金属部(11)の裏面の面積より大きく形成され、
前記張出部は、形状が異なる第一張出部(11c)と第二張出部(11c’)とを有し、
前記第一張出部(11c)は、前記金属部(11)の軸方向と直交する方向に平行な下面と、前記金属部(11)の上面に連続して形成される上面と、該下面と上面の間に形成される側面とを有し、
前記第一張出部(11c)の上面は、前記金属部(11)の上面から前記第一張出部(11c)の側面に連続形成された曲面であり、
前記第二張出部(11c’)は、前記金属部(11)の軸方向と直交する方向に平行な下面と、前記金属部(11)の上面に連続して形成される上面とを有しており、
前記各金属部(11)において、隣接する前記金属部(11)と対向する側に前記第二張出部(11c’)が形成され、隣接する前記金属部(11)と対向する側を除く位置に前記第一張出部(11c)が形成され、
前記各金属部(11)において、隣接する前記金属部(11)と対向する側における前記第二張出部(11c’)の張出し量は、隣接する前記金属部(11)と対向する側を除く位置における前記第一張出部(11c)の張出し量より大きく形成されていることを特徴とする半導体装置。
A semiconductor device comprising a semiconductor element (14) and a metal portion (11) serving as a semiconductor element mounting portion (11a) and/or an electrode portion (11b), the semiconductor element (14) and the metal portion (11) are electrically connected to each other, and the semiconductor element (14) and the metal portion (11) are sealed with a sealing material (19),
A protruding portion is formed on the metal portion (11),
The protruding portion is formed to protrude from the metal portion (11) in a direction perpendicular to an axial direction of the metal portion (11),
The area of the upper surface of the metal portion (11) including the protruding portion is formed to be larger than the area of the back surface of the metal portion (11) exposed from the bottom surface of the sealing material (19),
The protruding portion has a first protruding portion (11c) and a second protruding portion (11c') having different shapes,
The first protruding portion (11c) has a lower surface parallel to a direction perpendicular to the axial direction of the metal portion (11), an upper surface formed continuously with the upper surface of the metal portion (11), and a side surface formed between the lower surface and the upper surface,
an upper surface of the first protruding portion (11c) is a curved surface that is continuously formed from an upper surface of the metal portion (11) to a side surface of the first protruding portion (11c);
The second protruding portion (11c') has a lower surface parallel to a direction perpendicular to the axial direction of the metal portion (11) and an upper surface formed continuously with the upper surface of the metal portion (11),
In each of the metal portions (11), the second protruding portion (11c') is formed on a side facing the adjacent metal portion (11), and the first protruding portion (11c) is formed in a position other than the side facing the adjacent metal portion (11),
A semiconductor device characterized in that, in each of the metal portions (11), the amount of protrusion of the second protrusion portion (11c') on the side facing the adjacent metal portion (11) is formed to be greater than the amount of protrusion of the first protrusion portion (11c) at a position other than the side facing the adjacent metal portion (11).
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