JP7625455B2 - Semiconductor device manufacturing method - Google Patents

Description

The embodiment relates to a method for manufacturing a semiconductor device.

In semiconductor devices in which semiconductor elements such as transistors are provided on the front side of a semiconductor substrate, via holes may be formed from the back side of the semiconductor substrate to the semiconductor elements, electrically connecting the electrodes on the back side to the semiconductor elements.

JP 2010-163938 A

The embodiment provides a method for manufacturing a semiconductor device that reduces the electrical resistance between the front and back electrodes of a semiconductor element.

The semiconductor device according to the embodiment includes a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, an electrode provided on the semiconductor layer, a metal layer provided on the back surface of the semiconductor substrate opposite to the semiconductor layer, and a conductor extending through the semiconductor substrate and the semiconductor layer and electrically connecting the electrode and the metal layer. The method for manufacturing the semiconductor device includes the steps of: forming a through hole communicating from the back surface of the semiconductor substrate to the electrode by dry etching the semiconductor substrate and the semiconductor layer; removing a reaction product formed on the back surface of the electrode exposed at the bottom surface of the through hole by an etching gas used in the dry etching of the semiconductor layer; forming the conductor electrically connected to the electrode in the through hole; and forming the metal layer electrically connected to the conductor on the back surface of the semiconductor layer.

1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. 3A to 3C are schematic cross-sectional views showing a manufacturing process following FIG. 2 . 4A to 4C are schematic cross-sectional views showing a manufacturing process following FIG. 3. FIG. 11 is a schematic cross-sectional view showing a semiconductor device according to a modified example of the embodiment. FIG. 13 is a schematic diagram showing a semiconductor device according to another modified example of the embodiment. FIG. 13 is a schematic diagram showing another semiconductor device according to the embodiment.

The following describes the embodiments with reference to the drawings. Identical parts in the drawings are given the same numbers, and detailed descriptions thereof are omitted as appropriate, while different parts are described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, and the like are not necessarily the same as in reality. Even when the same parts are shown, the dimensions and ratios between them may be different depending on the drawing.

The arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward and the opposite direction as downward.

FIG. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a field effect transistor (FET). The semiconductor device 1 includes a semiconductor substrate 10, a first semiconductor layer 20, a second semiconductor layer 30, a first electrode 40, a second electrode 50, and a third electrode 60.

The first semiconductor layer 20 is provided on a semiconductor substrate 10. The second semiconductor layer 30 is provided on the first semiconductor layer 20. The semiconductor substrate 10 is, for example, a high resistance substrate or a semi-insulating substrate. The semiconductor substrate 10 is, for example, a silicon carbide (SiC) substrate. The first semiconductor layer 20 is, for example, an n-type gallium nitride (GaN) layer. The second semiconductor layer 30 has, for example, a band gap wider than the band gap of the first semiconductor layer 20. The second semiconductor layer 30 includes, for example, a semiconductor alloy expressed by a composition formula Al _1-x Ga _x N (0<x<1), hereinafter referred to as AlGaN.

The first electrode 40, the second electrode 50, and the third electrode 60 are provided on the second semiconductor layer 30. The first electrode 40, the second electrode 50, and the third electrode 60 are aligned along the surface of the second semiconductor layer 30. The third electrode 60 is provided between the first electrode 40 and the second electrode 50.

The first electrode 40 is, for example, a source electrode. The first electrode 40 includes a first metal layer ML1 and a second metal layer ML2. The first metal layer ML1 contacts the third semiconductor layer 30. The second metal layer ML2 is provided on the first metal layer ML1. The first electrode 40 is electrically connected to the second semiconductor layer 30. The first metal layer ML1 includes, for example, titanium (Ti), nickel (Ni), aluminum (Al), etc. The second metal layer ML2 includes, for example, gold (Au). The first electrode 40 is in ohmic contact with the second semiconductor layer 30 via the first metal layer ML1, for example. The first metal layer ML1 may have a structure in which multiple metal layers are stacked.

The second electrode 50 is, for example, a drain electrode. The second electrode 50 includes a first metal layer ML1 and a second metal layer ML2. The first metal layer ML1 is in contact with the third semiconductor layer 30. The second metal layer ML2 is provided on the first metal layer ML1. The second electrode 50 is electrically connected to the second semiconductor layer 30. The second electrode 50 is in ohmic contact with the second semiconductor layer 30 via, for example, the first metal layer ML1.

The third electrode 60 is, for example, a gate electrode. The third electrode 60 includes a third metal layer ML3 and a fourth metal layer ML4. The third metal layer ML3 is in contact with the third semiconductor layer 30. The fourth metal layer ML4 is provided on the third metal layer ML3. The third metal layer ML3 includes, for example, nickel (Ni), titanium nitride (TiN), etc. The fourth metal layer ML4 includes, for example, gold (Au). The third electrode 60 is in Schottky contact with the second semiconductor layer 30 via, for example, the third metal layer ML3.

The semiconductor device 1 further includes a metal layer 70 and a conductor 80. The metal layer 70 is provided, for example, on the back surface of the semiconductor substrate 10 opposite the first semiconductor layer 20. That is, the semiconductor substrate 10 is located between the first semiconductor layer 20 and the metal layer 70.

The conductor 80 is provided in the semiconductor substrate 10, the first semiconductor layer 20, and the second semiconductor layer 30. The conductor 80 extends, for example, in a direction from the metal layer 70 toward the first electrode 40 (for example, the Z direction). The conductor 80 electrically connects the metal layer 70 and the first electrode 40. The conductor 80 is connected, for example, to the first electrode 40 and the metal layer 70. The conductor 80 is provided, for example, so as to be in contact with the semiconductor substrate 10, the first semiconductor layer 20, and the second semiconductor layer 30.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 2(a) to 4(b). Figures 2(a) to 4(b) are schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment.

The semiconductor substrate 10 is, for example, a SiC substrate. The semiconductor substrate 10 is, for example, a high-resistance substrate or a semi-insulating substrate. The first semiconductor layer 20 and the second semiconductor layer 30 are epitaxially grown on the semiconductor substrate 10, for example, by MOCVD (Metal Organic Chemical Vapor Deposition). The first semiconductor layer 20 is, for example, an n-type GaN layer. The first semiconductor layer 20 is, for example, an undoped layer that is not intentionally doped with impurities. The second semiconductor layer 30 is, for example, an n-type AlGaN layer. The second semiconductor layer 30 is doped with silicon, which is an n-type impurity, during epitaxial growth. The first semiconductor layer 20 has, for example, a higher resistance than the second semiconductor layer 30.

As shown in FIG. 2(a), a first electrode 40, a second electrode 50, and a third electrode 60 are formed on the second semiconductor layer 30. For example, the first electrode 40 and the second electrode 50 are formed simultaneously.

The first electrode 40 and the second electrode 50 are formed by stacking the first metal layer ML1 and the second metal layer ML2, for example, using a sputtering method. The third electrode 60 is formed by stacking the third metal layer ML3 and the fourth metal layer ML4, for example, using a sputtering method. The first electrode 40, the second electrode 50, and the third electrode 60 are patterned into a predetermined planar shape, for example, using a lift-off method.

The third electrode 60 is formed after the first electrode 40 and the second electrode 50. The third electrode 60 is formed, for example, after the first electrode 40 and the second electrode 50 are ohmically connected to the second semiconductor layer 30 by heat treatment.

As shown in FIG. 2B, a via hole VH is formed on the back side of the semiconductor substrate 10. The semiconductor substrate 10 is thinned to a predetermined thickness, for example, by grinding the back side. Then, the semiconductor substrate 10 is selectively removed using, for example, an etching mask 105 to form the via hole VH. The etching mask 105 is, for example, a silicon oxide film.

The via hole VH is formed, for example, by dry etching using an inductively coupled plasma method. When the semiconductor substrate 10 is a SiC substrate, etching is performed using an etching gas containing fluorine. The via hole VH is formed to a depth that penetrates the semiconductor substrate 10 and reaches the first semiconductor layer 20.

As shown in FIG. 3(a), the first semiconductor layer 20 and the second semiconductor layer 30 are selectively removed to form a deeper via hole VH. When the first semiconductor layer 20 is a GaN layer and the second semiconductor layer 30 is AlGaN, etching is continued using, for example, an etching gas containing chlorine (Cl). For example, when the dry etching endpoint detector detects gallium (Ga), etching of the semiconductor substrate 10 is stopped and the etching gas is switched.

The via hole VH is formed, for example, so as to communicate with the first electrode 40 from the rear surface of the semiconductor substrate 10. The via hole VH is a through hole that penetrates the semiconductor substrate 10, the first semiconductor layer 20, and the second semiconductor layer 30.

During the process of forming the via hole VH, the first metal layer ML1 is exposed on its bottom surface, and a reaction product ML5 containing the metal element of the first metal layer ML1 is formed. When the first semiconductor layer 20 and the second semiconductor layer 30 are etched using a gas containing chlorine, a reaction product ML5 containing a chloride of the metal element of the first metal layer ML1 is formed on the bottom surface of the via hole VH.

As shown in FIG. 3(b), the reaction product ML5 is removed by, for example, dry etching. The reaction product ML5 is removed by, for example, dry etching using an etching gas containing argon (Ar). That is, the reaction product ML5 is physically removed by argon ions accelerated by the plasma electric field.

As shown in FIG. 4(a), a conductive layer 80f is formed on the back surface side of the semiconductor substrate 10. The conductive layer 80f is formed so as to fill the inside of the via hole VH and to be in contact with the first metal layer ML1. The conductive layer 80f is formed, for example, by using a plating method. The conductive layer 80f contains, for example, gold (Au).

As shown in FIG. 4(b), a conductor 80 is formed inside the via hole VH by removing the portion of the conductive layer 80f formed on the rear surface of the semiconductor substrate 10, and then a metal layer 70 is formed. The metal layer 70 is formed on the rear surface of the semiconductor substrate 10 by using, for example, a sputtering method. The metal layer 70 contains, for example, nickel and gold. The conductor 80 is in contact with and electrically connected to the metal layer 70.

In addition, the conductive layer 80f may be left on the back surface of the semiconductor substrate 10 to form the metal layer 70. In other words, the metal layer 70 and the conductor 80 may be formed integrally.

In the manufacturing method according to the embodiment, the reaction product ML5 formed on the bottom surface of the via hole VH can be removed to reduce the electrical resistance between the first electrode 40 and the metal layer 70. In other words, the reaction product ML5 has high resistance, and by removing it, the contact resistance between the conductor 80 and the first metal layer ML1 can be reduced.

Figure 5 is a schematic cross-sectional view showing a semiconductor device 2 according to a modified embodiment. In the semiconductor device 2, the conductor 80 is provided so as to contact the second metal layer ML2 of the first electrode 40. In this example, in the process of removing the reaction product ML5 shown in Figure 3 (a), the first metal layer ML1 is also removed, exposing the second metal layer ML2 at the bottom surface of the via hole VH. For example, if the second metal layer ML2 and the conductor 80 are both metals containing gold (Au), the contact resistance between the second metal layer ML2 and the conductor 80 can be further reduced. In addition, the bonding strength between the second metal layer ML2 and the conductor 80 can also be improved.

Figures 6(a) and (b) are schematic diagrams showing a semiconductor device 3 according to a modified embodiment. Figure 6(a) is a schematic plan view showing the top surface of the semiconductor device 3. Figure 6(b) is a schematic cross-sectional view taken along line A-A shown in Figure 6(a).

As shown in FIG. 6A, the first electrode 40 includes a plurality of finger portions 40F and a bonding pad portion 40P. The plurality of finger portions 40F extend, for example, in the Y direction and are provided so as to be connected to the bonding pad portion 40P.

The second electrode 50 includes a plurality of finger portions 50F and a bonding pad portion 50P. The plurality of finger portions 50F extend, for example, in the Y direction from the bonding pad portion 50P. The plurality of finger portions 50F are provided so as to be connected to the bonding pad portion 50P.

The finger portions 40F of the first electrode 40 and the finger portions 50F of the second electrode 50 are arranged alternately in the X direction, for example.

The third electrode 60 includes a plurality of finger portions 60F, a wiring portion 60L, and a bonding pad portion 60P.

The finger portions 60F each extend in the Y direction between the finger portion 40F of the first electrode 40 and the finger portion 50F of the second electrode 50.

The wiring portion 60L extends in the X direction, and the finger portion 60F is connected to the wiring portion 60L. The wiring portion 60L is connected to the bonding pad portion 60P.

As shown in FIG. 6(b), the conductor 80 extends into the semiconductor substrate 10, the first semiconductor layer 20, and the second semiconductor layer 30, and is electrically connected to the bonding pad portion 40P of the first electrode 40. The metal layer 70 provided on the back surface of the semiconductor substrate 10 is electrically connected to the bonding pad portion 40P of the first electrode 40 via the conductor 80.

The wiring portion 60L of the third electrode 60 is provided on the second semiconductor layer 30 between the bonding pad portion 40P of the first electrode 40 and the finger portion 50F of the second electrode 50. The wiring portion 60L is electrically insulated from the bonding pad portion 40P of the first electrode 40 by an insulating film 65. The insulating film 65 is provided between the bonding pad portion 40P of the first electrode 40 and the wiring portion 60L of the third electrode 60, and covers the wiring portion 60L. The insulating film 65 is, for example, a silicon oxide film.

Figures 7(a) and (b) are schematic diagrams showing another semiconductor device 4 according to the embodiment. Figure 7(a) is a plan view showing a capacitor 90. Figure 7(b) is a schematic cross-sectional view showing a semiconductor device 4 having a capacitor 90 on a second semiconductor layer 30.

As shown in FIG. 7(a), the capacitor 90 includes a first metal electrode 93, a dielectric film 95, and a second metal electrode 97. The first metal electrode 93, the dielectric film 95, and the second metal electrode 97 are stacked, for example, in the Z direction, and the dielectric film 95 is provided between the first metal electrode 93 and the second metal electrode 97.

The first metal electrode 93 includes a first metal layer ML1 and a second metal layer ML2. The first metal layer ML1 contacts the third semiconductor layer 30. The second metal layer ML2 is provided on the first metal layer ML1. The second metal electrode 97 includes, for example, gold and chromium. The dielectric film 95 includes, for example, a high dielectric constant material such as aluminum oxide or hafnium oxide.

As shown in FIG. 7B, the capacitor 90 is provided on the second semiconductor layer 30. The capacitor 90, together with the semiconductor device 1 shown in FIG. 1, constitutes, for example, a monolithic microwave integrated circuit (MMIC).

The semiconductor device 4 further includes another conductor 80. The conductor 80 extends into the semiconductor substrate 10, the first semiconductor layer 20, and the inside of the first semiconductor layer 20, and is provided so as to contact the first metal layer ML1 of the first metal electrode 93. The conductor 80 is electrically connected to the first metal electrode 93. The metal layer 70 on the back surface of the semiconductor substrate 10 is electrically connected to the first metal electrode 93 via the conductor 80. That is, the capacitor 90 is electrically connected to the metal layer 70 via the conductor 80.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

1, 2, 3, 4...semiconductor device, 10...semiconductor substrate, 20...first semiconductor layer, 30...second semiconductor layer, 40...first electrode, 40F, 50F, 60F...finger portion, 40P, 50P, 60P...bonding pad portion, 50...second electrode, 60...third electrode, 60L...wiring portion, 65...insulating film, 70...metal layer, 80...conductor, 80f...conductive layer, 90...capacitor, 93, 97...metal electrode, 95...dielectric film, 105...etching mask, ML1...first metal layer, ML2...second metal layer, ML3...third metal layer, ML4...fourth metal layer, ML5...reaction product, VH...via hole

Claims (5)

A method for manufacturing a semiconductor device including a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, an electrode provided on the semiconductor layer, a metal layer provided on a back surface of the semiconductor substrate opposite to the semiconductor layer, and a conductor extending into the semiconductor substrate and the semiconductor layer and electrically connecting the electrode and the metal layer, comprising:
forming a through hole communicating from the back surface of the semiconductor substrate to the electrode by dry etching the semiconductor substrate and the semiconductor layer;
removing a reaction product formed on a rear surface of the electrode exposed at a bottom surface of the through hole by an etching gas used in dry etching of the semiconductor layer;
forming the conductor electrically connected to the electrode within the through hole;
forming a metal layer on the back surface of the semiconductor layer, the metal layer being electrically connected to the conductor;
Equipped with
the etching gas used in the dry etching of the semiconductor layer contains chlorine;
the reaction product is a chloride of the electrode material;
The reaction products are removed by dry etching using an inert gas . the electrode includes a first layer in contact with and electrically connected to the semiconductor layer, and a second layer including a material different from that of the first layer and stacked on the first layer;
The method according to claim 1 , wherein the reaction product contains the constituent elements of the first layer. The manufacturing method according to claim 2 , wherein the conductor is formed so as to be in contact with the first layer. 3. The method of claim 2 , wherein the first layer of the electrode is removed together with the reaction product, and the conductor is formed in contact with the second layer of the electrode. 5. The manufacturing method according to claim 1 , wherein the semiconductor substrate and the semiconductor layer have high electrical resistance, and the conductor is in contact with the semiconductor substrate and the semiconductor layer within the through hole.

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