JP7626638B2 - Constant voltage power supply circuit - Google Patents

Description

The present invention relates to a constant voltage power supply circuit capable of supplying a predetermined output voltage.

A constant voltage power supply circuit composed of, for example, a regulator circuit, is used as a power supply circuit capable of supplying a predetermined output voltage.

As a conventional example of a constant-voltage power supply circuit, for example, Patent Document 1 discloses a constant-voltage power supply circuit that limits the internal current consumption during startup or overload, making it possible to suppress the occurrence of overshoot.

JP 2010-079653 A

In constant-voltage power supply circuits, the issue is how to improve the fluctuation characteristics of the output voltage relative to the output current, known as the load regulation characteristics. Recently, in order to extend the operating time of battery-powered devices and other equipment equipped with constant-voltage power supply circuits, the current consumption of constant-voltage power supply circuits has been reduced year by year. Under these circumstances, there is a large drop in the output voltage relative to the output current, especially when the output current is low and the load is light, so there is a demand for improvements in the load regulation characteristics.

The present invention aims to provide a constant voltage power supply circuit that can improve load regulation characteristics, including under light loads with low output current.

The present invention provides a constant voltage power supply circuit comprising: a first transistor of a first conductivity type having a source connected to a first power supply and obtaining a predetermined output voltage from a drain; an error amplifier that outputs a voltage proportional to a difference between the output voltage and a reference voltage from an output terminal and supplies the voltage to a gate of the first transistor; a second transistor of a first conductivity type having a source mutually connected to the first transistor and through which flows a drain current corresponding to the output current of the first transistor, a positive feedback circuit that draws a current corresponding to the drain current of the second transistor from the output terminal of the error amplifier and transitions the output characteristics of the error amplifier; and a bias circuit that is provided between the output terminal of the error amplifier and the positive feedback circuit and supplies a bias voltage, which is a voltage displaced with respect to the gate voltage of the first transistor , to the gate of the second transistor, thereby increasing the drain current of the second transistor .

The present invention also provides the above constant voltage power supply circuit, in which the positive feedback circuit has the second transistor and a third and fourth transistor of a second conductivity type that form a current mirror, the drain and gate of the third transistor are connected to the drain of the second transistor, and the drain of the fourth transistor is connected to the output terminal of the error amplifier.

The present invention also provides the above constant voltage power supply circuit, in which the bias circuit includes a fifth transistor of a second conductivity type, the gate of which is connected to the output terminal of the error amplifier and the drain of which is connected to the first power supply, and the gate of the second transistor is connected to the source of the fifth transistor.

The present invention also provides a constant-voltage power supply circuit as described above, in which the bias voltage supplied by the bias circuit increases in response to an increase in the output current of the first transistor.

The present invention also provides the above constant voltage power supply circuit, in which the bias circuit includes a fifth transistor of a second conductivity type, the gate of which is connected to the output terminal of the error amplifier and the drain of which is connected to the first power supply, a first current source connected in series to the fifth transistor and supplying a constant current to the drain of the fifth transistor, and a second current source connected in parallel to the first current source and supplying a current proportional to the output current to the fifth transistor, and the gate of the second transistor is connected to the source of the fifth transistor.

The present invention provides a constant voltage power supply circuit that can improve load regulation characteristics, including under light loads with low output current.

1 is a circuit diagram showing a configuration of a constant voltage power supply circuit according to a first embodiment; 10 is a characteristic diagram showing an example of a change in drain current characteristic in transistor MP2 depending on the presence or absence of a bias voltage. 1 is a circuit diagram showing a specific configuration example of a constant voltage power supply circuit according to a first embodiment; FIG. 4 is a characteristic diagram showing an example of an output voltage characteristic in the present embodiment. FIG. 11 is a circuit diagram showing a configuration of a constant voltage power supply circuit according to a second embodiment. FIG. 11 is a circuit diagram showing a configuration of a constant voltage power supply circuit according to a third embodiment. FIG. 13 is a circuit diagram showing a configuration of a constant voltage power supply circuit according to a fourth embodiment. FIG. 13 is a circuit diagram showing a configuration of a constant voltage power supply circuit according to a fifth embodiment. 10 is a characteristic diagram showing an example of a change in drain current characteristic due to the presence or absence and an increase in bias voltage in transistor MP2. FIG. 13 is a circuit diagram showing a specific configuration example of a constant voltage power supply circuit according to a fifth embodiment. FIG. 13 is a characteristic diagram illustrating an example of an output voltage characteristic in the fifth embodiment. FIG. 1 is a circuit diagram showing a configuration of a constant voltage power supply circuit of a comparative example.

Hereinafter, an embodiment of the constant voltage power supply circuit according to the present invention (hereinafter, referred to as the "present embodiment") will be described in detail with reference to the drawings.

(Background to the present embodiment)
First, an example of a conventional constant voltage power supply circuit will be described as a comparative example.

Figure 12 is a circuit diagram showing the configuration of a constant voltage power supply circuit of a comparative example. The constant voltage power supply circuit 50 has a first power supply terminal 51, a second power supply terminal 52, an output terminal 53, a current source 54, a reference voltage source 55, and an error amplifier 56. The first power supply terminal 51 is applied with a first power supply voltage VDD as a high potential power supply. The second power supply terminal 52 is applied with a second power supply voltage VSS (VSS < VDD) as a low potential power supply. The output terminal 53 outputs an output voltage VREG as the output of the power supply circuit.

The constant voltage power supply circuit 50 has an error amplifier 56 composed of transistors MN4, MN5, MN6, MP3, and MP4. The error amplifier 56 has a differential circuit composed of NMOS transistors MN4, MN5, and MN6, and an active load of the differential circuit composed of PMOS transistors MP3 and MP4 connected in a current mirror. It also has an NMOS transistor MN7 connected in a current mirror with transistor MN6. The gate and drain of transistor MN7 are connected to a current source 54, and the current IS of the current source 54 is supplied to transistor MN6 as a bias current.

The error amplifier 56 has a reference voltage source 55 that supplies a reference voltage VR connected to its inverting input terminal 561, and an output voltage detection circuit 57 connected to its non-inverting input terminal 562. The gate of an output PMOS transistor MP1 is connected to the output terminal 563 of the error amplifier 56. The source of the transistor MP1 is connected to the first power supply terminal 51, and the drain is connected to the output terminal 53 and the output voltage detection circuit 57. The output voltage detection circuit 57 is composed of resistors R3 and R4 connected in series between the output terminal 53 and the second power supply terminal 52, and the common connection point of the resistors R3 and R4 is connected to the non-inverting input terminal 562 of the error amplifier 56 to detect the output voltage VREG. The constant voltage power supply circuit 50 is configured such that the difference between the reference voltage VR of the reference voltage source 55 and the feedback signal voltage obtained by resistively dividing the output voltage by the resistors R3 and R4 is amplified by the error amplifier 56 and applied to the output transistor MP1, so that the output voltage VREG becomes a predetermined value.

The constant voltage power supply circuit 50 has a positive feedback circuit 58 that includes a PMOS transistor MP2 and NMOS transistors MN1 and MN2. The source of the transistor MP2 is connected to the first power supply terminal 51, and the gate is connected to the output terminal 563 of the error amplifier 56. The transistors MN1 and MN2 form a current mirror, with the gate and drain of the transistor MN1 connected to the drain of the transistor MP2, and the drain of the transistor MN2 connected to the output terminal 563 of the error amplifier 56, mirroring the drain current of the transistor MP2 to the drain of the transistor MN2.

In the constant voltage power supply circuit 50 configured as described above, a drain current proportional to the output current flows through the drain of transistor MP2 of the positive feedback circuit 58 in response to the output current flowing through the drain of transistor MP1. Also, in the positive feedback circuit 58, a current proportional to the drain current of transistor MP2 is mirrored to the drain of transistor MN2. Therefore, at the output terminal 563 of the error amplifier 56, a current proportional to the output current of transistor MP1 is drawn by transistor MN2, and the output characteristics of the error amplifier 56 transition. By providing the positive feedback circuit 58, the gain of the positive feedback circuit 58 is added to the inherent gain of the error amplifier 56, and the gate voltage can be changed according to the output voltage of transistor MP1, improving the load regulation characteristics of the output voltage.

In the configuration of FIG. 12, during normal load conditions when the output current is large, transistor MP1 operates in the strong inversion region, and the drain current of transistor MP2 is also sufficiently large, so the positive feedback circuit 58 significantly improves the load regulation characteristics. However, during light load conditions when the output current is small, transistor MP1 operates in the subthreshold region (weak inversion region), and the drain current of transistor MP2 becomes very small, so there is an issue that the effect of the positive feedback circuit 58 cannot be fully obtained.

In this embodiment, in consideration of the above circumstances, an example of the configuration of a constant voltage power supply circuit that can improve the load regulation characteristics in areas with low output current is shown.

(First embodiment)
1 is a circuit diagram showing the configuration of a constant voltage power supply circuit according to a first embodiment. The constant voltage power supply circuit 10 according to this embodiment has a first power supply terminal (VDD) 1, a second power supply terminal (VSS) 2, an output terminal (VREG) 3, a current source (IS) 4, a reference voltage source (VR) 5, and an error amplifier 6. The first power supply terminal 1 is applied with a first power supply voltage VDD as a high potential power supply, which is a first power supply. The second power supply terminal 2 is applied with a second power supply voltage VSS (VSS<VDD) as a low potential power supply, which is a second power supply. The output terminal 3 outputs an output voltage VREG as an output of the power supply circuit. The current source 4 is connected to the first power supply terminal 1 and is a current source that supplies a current IS. The reference voltage source 5 is a voltage source that supplies a reference voltage VR.

The constant voltage power supply circuit 10 has an error amplifier 6 that includes NMOS transistors (NMOS transistors) MN4, MN5, and MN6, and PMOS transistors (PMOS transistors) MP3 and MP4. The transistors MN4, MN5, and MN6 form a differential circuit. The transistors MP3 and MP4 are current mirror connected, and form an active load for the differential circuit made up of the transistors MN4 to MN6. The constant voltage power supply circuit 10 also has an NMOS transistor MN7 that is current mirror connected to the transistor MN6. The gate and drain of the transistor MN7 are connected to the current source 4, and the current IS of the current source 4 is supplied to the transistor MN6 as a bias current.

The error amplifier 6 has a reference voltage source 5 connected to its inverting input terminal 61 and an output voltage detection circuit 7 connected to its non-inverting input terminal 62. The gate of a PMOS type transistor MP1, which is an output transistor, is connected to the output terminal 63 of the error amplifier 6. The transistor MP1 corresponds to a first transistor of a first conductivity type, and has a source connected to the first power supply terminal 1 and a drain connected to the output terminal 3 and the output voltage detection circuit 7, and a predetermined output voltage is obtained from the drain. The output voltage detection circuit 7 is composed of resistors R3 and R4 connected in series between the output terminal 3 and the second power supply terminal 2, and the common connection point of the resistors R3 and R4 is connected to the non-inverting input terminal 62 of the error amplifier 6 to detect the output voltage VREG. The error amplifier 6 supplies a voltage proportional to the difference between the output voltage VREG and the reference voltage VR to the gate of the transistor MP1.

In this way, the constant voltage power supply circuit 10 is configured such that the difference between the reference voltage VR of the reference voltage source 5 and the feedback signal voltage obtained by resistively dividing the output voltage with resistors R3 and R4 is amplified by the error amplifier 6 and applied to the output transistor MP1. As a result, the difference between the reference voltage and the feedback signal voltage is controlled to be zero, and the output voltage VREG becomes a constant voltage of a predetermined value.

The constant voltage power supply circuit 10 has a positive feedback circuit 8 including a PMOS transistor MP2 and NMOS transistors MN1 and MN2. The transistor MP2 corresponds to a second transistor of a first conductivity type, and the source of the transistor MP2 is connected to the transistor MP1, and the gate of the transistor MP2 is connected to the output terminal 63 of the error amplifier 6 via a bias circuit 9 described later. The transistor MN1 corresponds to a third transistor of a second conductivity type, and the gate and drain of the transistor MN1 are connected to the drain of the transistor MP2, and the source of the transistor MN1 is connected to the second power supply terminal 2. The transistor MN2 corresponds to a fourth transistor of a second conductivity type, and the drain of the transistor MN2 is connected to the output terminal 63 of the error amplifier 6, the gate of the transistor MN1 is connected to the gate of the transistor MN1, and the source of the transistor MN2 is connected to the second power supply terminal 2. These transistors MN1 and MN2 form a current mirror, and the drain current of the transistor MP2 is mirrored to the drain of the transistor MN2.

In the constant voltage power supply circuit 10, a drain current proportional to the output current flows through the drain of transistor MP2 in the positive feedback circuit 8 in response to the output current flowing through the drain of transistor MP1. Also, in the positive feedback circuit 8, a current proportional to the drain current of transistor MP2 is mirrored to the drain of transistor MN2.

Transistor MP2 has the same gate length as transistor MP1, and the ratio of the gate widths of transistors MP2 and MP1 is set to MP2:MP1 = 1:n (n>1). When no bias voltage is applied to transistor MP2, the gate-source voltage of transistors MP2 and MP1 is common, so the drain current of transistor MP2 is 1/n of the drain current of transistor MP1.

The gate width ratio of transistors MN1 and MN2 in the positive feedback circuit 8 is set to MN1:MN2 = m:1 (m is a positive value). Therefore, when the drain of transistor MN2 is connected to the output terminal 63 of the error amplifier 6, transistor MN2 draws a current of 1/(m x n) the amount of output current of transistor MP1 from the output terminal 63 of the error amplifier 6, and can greatly shift the output characteristics of the error amplifier 6. As a result, the gain of the positive feedback circuit 8 is added to the inherent gain of the error amplifier 6, so that the gate voltage can be changed according to the output voltage of transistor MP1, and the load regulation characteristics can be improved.

When there is no load and no output current, transistor MP1 supplies only the current flowing through resistors R3 and R4. When low current consumption is required for the constant voltage power supply circuit, resistors R3 and R4 with a high resistance value of several MΩ are used. At this time, transistor MP1, which drives the load, is controlled by error amplifier 6 so that it operates in the subthreshold region (weak inversion region). When the output current gradually increases, transistor MP1 transitions to operating in the strong inversion region.

In the light load region where the output current is small, the output voltage VREG of the constant voltage power supply circuit 10 fluctuates greatly because the transistor MP1 operates in the subthreshold region (weak inversion region). When the output current increases further, the circuit operates in the strong inversion region, and the output voltage VREG shifts to a square characteristic with respect to the output current, tracing a downward voltage trajectory.

The output voltage characteristic of the constant voltage power supply circuit 10 can be expressed as a load regulation characteristic. The load regulation characteristic is expressed by the degree of downward slope of the output voltage VREG between any two points I1 and I2 of the output current, and is generally defined by the following equation (1).

In the above formula, VR1 is the output voltage when the output current is I1, and VR2 is the output voltage when the output current is I2. The load regulation characteristic is used as one of the performance indicators of a constant voltage power supply circuit, and the quality of this characteristic is an important factor in circuit selection. To improve the load regulation characteristic over the entire range of output current, it is desirable for the value of LR in formula (1) to be small.

The constant voltage power supply circuit 10 of this embodiment has a bias circuit 9 that applies a bias voltage VB between the gate of the transistor MP2 in the positive feedback circuit 8 and the output terminal 63 of the error amplifier 6. The bias circuit 9 functions as a constant voltage source, and by applying the bias voltage VB from the bias circuit 9 to the gate of the transistor MP2 to bias it in the forward direction, it becomes possible to pass a drain current of a predetermined amount or more through the transistor MP2.

Figure 2 is a characteristic diagram showing an example of the change in drain current characteristics of transistor MP2 depending on whether or not a bias voltage is applied. Figure 2 shows the change in the drain current of transistor MP2 relative to the output current of the constant-voltage power supply circuit 10. When no bias voltage is applied, transistor MP2 has a drain current proportional to the output current, as shown by the dashed line. When a bias voltage is applied, transistor MP2 has a large drain current in the region where the output current is small, as shown by the solid line.

Figure 3 is a circuit diagram showing a specific example of the configuration of the constant-voltage power supply circuit of the first embodiment. The constant-voltage power supply circuit 10A in Figure 3 shows a specific example of the circuit configuration of the bias circuit 9. Here, the following description focuses on the parts that differ from the configuration of the constant-voltage power supply circuit 10 shown in Figure 1, and similar components are given the same reference numerals and will not be described.

The bias circuit 9 is composed of NMOS type transistors MN8 and MN9. The transistor MN8 functions as a first current source, is connected to the transistors MN6 and MN7 in a current mirror configuration, and supplies the current IS (constant current) of the current source 4 to the transistor MN9. The transistor MN9 corresponds to a fifth transistor of the second conductivity type, and is provided between the gate of the transistor MP2 and the output terminal 63 of the error amplifier 6. Specifically, the gate of the transistor MN9 is connected to the output terminal 63 of the error amplifier 6, the drain is connected to the first power supply terminal 1, and the source of the transistor MN9 and the drain of the transistor MN8 are connected to each other. The gate of the transistor MP2 is connected to the connection point between the source of the transistor MN9 and the drain of the transistor MN8.

In the configuration of FIG. 3, the gate-source voltage of transistor MP1 is Vgs1, and the gate-source voltage of transistor MP2 is Vgs2. The gate-source voltage of transistor MN9 of bias circuit 9 corresponds to bias voltage VB. By providing bias circuit 9 and applying bias voltage VB, the gate voltage of transistor MP2 of positive feedback circuit 8 becomes lower than the voltage of output terminal 63 of error amplifier 6. Specifically, the gate-source voltage Vgs2 of transistor MP2 becomes larger by the gate-source voltage of transistor MN9, Vgs2=Vgs1+VB, and Vgs2>Vgs1, so the gate voltage of transistor MP2 becomes lower than the gate voltage of transistor MP1. Therefore, the drain current of transistor MP2 increases compared to when no bias voltage is applied. At this time, the drain current of transistor MP2 becomes 1/n+α of the drain current of transistor MP1 (α is the current increased by applying the bias voltage).

Figure 4 is a characteristic diagram showing an example of the output voltage characteristic in this embodiment. In Figure 4, the solid line shows the change in output voltage with respect to the output current in the configuration of this embodiment shown in Figures 1 and 3, and the dashed line shows the change in output voltage with respect to the output current in the configuration of the comparative example shown in Figure 12.

In the comparative example, in the region where the output current is small, transistor MP1 operates in the subthreshold region (weak inversion region), so the output voltage drops significantly. In contrast, in the configuration of this embodiment, by providing a bias circuit 9, even when the output current is low and the load is light, the gain of the positive feedback circuit 8 is added to the gain of the error amplifier 6, just as with normal load, and the gate voltage of transistor MP1 can be changed. Therefore, in the region where the output current is small, the drain current of transistor MP2 can be made to flow by a predetermined amount or more, and correction can be applied to the error amplifier 6 even in the region where the output current is small. Therefore, the voltage drop of the output voltage can be improved to a significantly more gradual characteristic.

In the output voltage characteristic of FIG. 4, the output voltage value VR2 at the point where the output current becomes I2 increases from VR2b in the comparative example to VR2a in this embodiment, and the load regulation characteristic LR improves from LRb in the comparative example to LRa in this embodiment. In this way, according to this embodiment, it is possible to further improve the load regulation characteristic over the entire range of the output current. In particular, it is possible to suppress output voltage fluctuations during light loads where the output current is small, and it is possible to improve the load regulation characteristic over the entire range of the output current.

Second Embodiment
5 is a circuit diagram showing the configuration of a constant-voltage power supply circuit according to the second embodiment. In addition to the configuration of the constant-voltage power supply circuit 10A according to the first embodiment, the constant-voltage power supply circuit 10B according to the second embodiment includes a resistor R1 as a first resistor element between the drain of the transistor MP2 and the drain of the transistor MN1 in the positive feedback circuit 8B. Here, the following description will focus on the parts that are different from the configuration of the constant-voltage power supply circuit 10A shown in FIG. 3, and the same components are denoted by the same reference numerals and will not be described.

In the first embodiment of the constant voltage power supply circuit 10A, a current generated from the voltage at the output terminal 63 of the error amplifier 6 is used to apply positive feedback to the output terminal 63 of the error amplifier 6. For this reason, depending on the amount of feedback, there may be a risk of oscillation.

In the constant voltage power supply circuit 10B of the second embodiment, a resistor R1 is inserted between the drain of transistor MP2 and the drain of transistor MN1 in the positive feedback circuit 8B to limit the amount of feedback in the positive feedback circuit 8B. This resistor R1 reduces the amount of feedback to the output terminal 63 of the error amplifier 6 when the output current of transistor MP1 increases and the drain current of transistor MP2 increases significantly, thereby reducing the risk of oscillation. In this way, according to this embodiment, it is possible to improve the load regulation characteristics in the region where the output current is low, and to suppress oscillation caused by applying positive feedback.

Third Embodiment
6 is a circuit diagram showing the configuration of a constant-voltage power supply circuit according to the third embodiment. The constant-voltage power supply circuit 10C of the third embodiment is another configuration example in which the resistor R1 of the constant-voltage power supply circuit 10B of the second embodiment is replaced. Here, the following description will focus on the parts that are different from the configuration of the constant-voltage power supply circuit 10B shown in FIG. 5, and the same components are denoted by the same reference numerals and will not be described.

In the constant voltage power supply circuit 10C, a transistor MN3 with its gate and source connected is provided between the drain of the transistor MP2 and the drain of the transistor MN1 in the positive feedback circuit 8C. The transistor MN3 corresponds to a depletion type transistor of the second conductivity type, and is composed of an NMOS type depletion transistor. The drain of the transistor MN3 is connected to the drain of the transistor MP2, the gate and source are connected to the drain of the transistor MN1, and the backgate is connected to the source and backgate of the transistor MN1.

If the risk of oscillation cannot be reduced even if resistor R1 is inserted and connected to positive feedback circuit 8B as in the second embodiment, transistor MN3 is inserted and connected instead of resistor R1 as in positive feedback circuit 8C of the third embodiment. When the drain current flowing through transistor MP2 increases, the drain voltage of transistor MN3 increases, and the potential difference between the source and backgate of transistor MN3 increases. As a result, the backgate effect of transistor MN3 increases its threshold voltage, and the resistance between the drain and source becomes higher. This makes it possible to further reduce the amount of feedback to error amplifier 6 when transistor MP1 passes a large output current. Therefore, according to this embodiment, it is possible to improve the load regulation characteristics in the region where the output current is small, and further reduce the risk of oscillation due to positive feedback.

(Fourth embodiment)
7 is a circuit diagram showing the configuration of a constant-voltage power supply circuit according to the fourth embodiment. In addition to the configuration of the constant-voltage power supply circuit 10A according to the first embodiment, a constant-voltage power supply circuit 10D according to the fourth embodiment includes a resistor R2 as a second resistive element between the source and back gate of the output-side transistor MN2 and the second power supply terminal 2 in a positive feedback circuit 8D. Here, the following description will focus on the parts that are different from the configuration of the constant-voltage power supply circuit 10A shown in FIG. 3, and the same components are denoted by the same reference numerals and will not be described.

In the constant voltage power supply circuit 10D, in the positive feedback circuit 8D, a resistor R2 is inserted between the source and back gate of the transistor MN2 and the second power supply terminal 2, so that the current flowing through the transistor MN2 is limited. Even with this configuration, as with the constant voltage power supply circuit 10B of the second embodiment and the constant voltage power supply circuit 10C of the third embodiment, when the transistor MP1 passes a large output current, the amount of feedback to the error amplifier 6 can be reduced. Therefore, according to this embodiment, it is possible to improve the load regulation characteristics in the region where the output current is small, and to suppress oscillation caused by applying positive feedback.

Fifth Embodiment
8 is a circuit diagram showing the configuration of a constant voltage power supply circuit of the fifth embodiment. A constant voltage power supply circuit 10E of the fifth embodiment is provided with a bias circuit 9E instead of the bias circuit 9 constituting the constant voltage power supply circuit 10 of the first embodiment. The bias circuit 9E of the fifth embodiment is configured so that the bias voltage VB increases as the output current increases. Specifically, a transistor MP5 is provided which is current-mirror connected to the transistor MP1. A drain current proportional to the output current flowing through the drain of the transistor MP1 flows through the transistor MP5. The bias voltage VB increases as the drain current of the transistor MP5 increases.

In the above-mentioned error amplifier 6, as the output current increases, the voltage difference (offset) between the input terminals 61 and 62 increases, which causes the output voltage VREG to decrease. According to the fifth embodiment, as the output current increases, the amount of current (offset correction amount) drawn by the positive feedback circuit 8 from the output terminal 63 of the error amplifier 6 can be increased more than in the first embodiment, so that the amount of change in the output voltage relative to the output current can be further reduced.

Figure 9 is a characteristic diagram showing an example of the change in drain current characteristics due to the presence or absence and increase of bias voltage in transistor MP2. As shown in the figure, when no bias voltage is applied, transistor MP2 has a drain current proportional to the output current as shown by the dashed line. When a constant bias voltage is applied, transistor MP2 has a large drain current in the region where the output current is small as shown by the dashed line, but in the region where the output current is large, the increase in drain current with respect to the increase in output current is smaller than when no bias is applied. When the bias voltage is increased in response to the increase in output current, transistor MP2 has a large drain current in the region where the output current is small, as in the case where a constant bias voltage is applied, as shown by the solid line. Furthermore, in the region where the output current is large, the drain current flows in proportion to the output current almost the same as when no bias is applied.

Figure 10 is a circuit diagram showing a specific example of the configuration of the constant-voltage power supply circuit of the fifth embodiment. The constant-voltage power supply circuit 10F in Figure 10 shows a specific example of the circuit of the bias circuit 9E. Here, the following description focuses on the parts that differ from the configuration of the constant-voltage power supply circuit 10E shown in Figure 8, and similar components are given the same reference numerals and will not be described.

The bias circuit 9E is configured to include NMOS transistors MN8, MN9, MN10, and MN11, and a PMOS transistor MP5. The connection of the transistors MN8 and MN9 is the same as that in the embodiment shown in FIG. 3 described above, so a detailed description is omitted here.

Transistors MP5, MN10, and MN11 function as a second current source that supplies a current proportional to the output current to the drain of transistor MN9. The source and gate of transistor MP5 are connected to those of transistor MP1, and a drain current proportional to the output current flowing to the drain of transistor MP1 flows through the transistors. Transistors MN10 and MN11 are connected in a current mirror configuration. The gate and drain of transistor MN10 are connected to the drain of transistor MP5, and the source is connected to the second power supply voltage VSS. The gate of transistor MN11 is connected to that of transistor MN10, and the source is connected to the second power supply voltage VSS, and the drain is connected to the source of transistor MN9 and the drain of transistor MN8. In this way, in the constant voltage power supply circuit 10F of FIG. 10, the second current source is connected in parallel to the first current source.

With the above configuration, a drain current proportional to the output current of transistor MP5 is mirrored to the drain of transistor MN11. The drain current of transistor MN9 is the sum of the constant current IS mirrored to transistor MN8 and the current proportional to the output current mirrored to transistor MN11. As a result, the gate-source voltage of transistor MN9, which is the bias voltage VB, is a voltage proportional to both the constant current IS and the output current, and the bias voltage VB can also increase in accordance with an increase in the output current.

Figure 11 is a characteristic diagram showing an example of the output voltage characteristic in the fifth embodiment. In Figure 11, the solid line shows the change in output voltage with respect to the output current in the configuration of the fifth embodiment shown in Figures 8 and 10, and the dashed line shows the change in output voltage with respect to the output current in the configuration of the first embodiment shown in Figures 1 and 3.

In the configuration of the first embodiment, the bias voltage VB is constant, so in areas where the output current is large, the output voltage drops somewhat as the output current increases. In contrast, in the configuration of the fifth embodiment, the bias voltage VB is increased as the output current increases, making it possible to improve the voltage drop of the output voltage in areas where the output current is large, to an even more gradual characteristic.

As described above, according to this embodiment, even in regions where the output current of the constant voltage power supply circuit is small, the output voltage fluctuation can be suppressed, and the load regulation characteristics can be improved over the entire range of output current. This enables high-precision operation over the entire current range, improving user convenience.

In the constant voltage power supply circuit of this embodiment, one of the PMOS transistor and the NMOS transistor is also referred to as a transistor of the first conductivity type, and the other, which has the opposite polarity, is also referred to as a transistor of the second conductivity type. In the configuration example of the above-mentioned embodiment, the PMOS transistor is the first conductivity type, and the NMOS transistor is the second conductivity type.

In the above embodiment, the power supply voltage is VDD>VSS. However, if the power supply voltage relationship is reversed, the PMOS transistors can be replaced with NMOS transistors, and the NMOS transistors can be replaced with PMOS transistors. In this case, the NMOS transistors are the first conductivity type, and the PMOS transistors are the second conductivity type.

Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modified or revised examples within the scope of the claims, and it is understood that these also naturally fall within the technical scope of the present invention. Furthermore, the components in the above embodiments may be combined in any manner as long as it does not deviate from the spirit of the present invention.

The present invention has the effect of improving the load regulation characteristics, including under light loads with low output current, and is useful for constant voltage power supply circuits capable of supplying a specified output voltage.

1: First power supply terminal (high potential power supply VDD)
2: Second power supply terminal (low potential power supply VSS)
3: Output terminal (VREG)
4: Current source (IS)
5: Reference voltage source (VR)
6: Error amplifier 7: Output voltage detection circuit 8: Positive feedback circuit 9: Bias circuit 10, 10A to 10F: Constant voltage power supply circuit 61: Inverting input terminal, 62: Non-inverting input terminal, 63: Output terminal MP1, MP2, MP3, MP4, MP5: Transistors (PMOS transistors)

MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11: Transistor (NMOS transistor)

Claims (5)

a first transistor of a first conductivity type having a source connected to a first power supply and having a drain from which a predetermined output voltage is obtained;
an error amplifier that outputs a voltage proportional to a difference between the output voltage and a reference voltage from an output terminal and supplies the voltage to a gate of the first transistor;
a positive feedback circuit including a second transistor of a first conductivity type , the source of which is connected to the first transistor and through which a drain current corresponding to an output current of the first transistor flows , the positive feedback circuit drawing a current corresponding to the drain current of the second transistor from an output terminal of the error amplifier and shifting an output characteristic of the error amplifier ;
a bias circuit provided between an output terminal of the error amplifier and the positive feedback circuit, the bias circuit supplying a bias voltage, which is a voltage offset with respect to a gate voltage of the first transistor , to a gate of the second transistor to increase the drain current of the second transistor ;
A constant voltage power supply circuit comprising: 2. The constant voltage power supply circuit according to claim 1,
The positive feedback circuit includes:
a third transistor and a fourth transistor of a second conductivity type which constitute a current mirror with the second transistor, the drain and gate of the third transistor being connected to the drain of the second transistor, and the drain of the fourth transistor being connected to an output terminal of the error amplifier;
Constant voltage power supply circuit. 3. The constant voltage power supply circuit according to claim 1,
The bias circuit includes:
a fifth transistor of a second conductivity type having a gate connected to an output terminal of the error amplifier and a drain connected to the first power supply, the gate of the second transistor being connected to a source of the fifth transistor;
Constant voltage power supply circuit. 3. The constant voltage power supply circuit according to claim 1,
the bias voltage supplied by the bias circuit increases in accordance with an increase in the output current of the first transistor;
Constant voltage power supply circuit. 5. The constant voltage power supply circuit according to claim 4,
The bias circuit includes:
a fifth transistor of a second conductivity type, the gate of which is connected to an output terminal of the error amplifier and the drain of which is connected to the first power supply; a first current source connected in series to the fifth transistor and supplying a constant current to the drain of the fifth transistor; and a second current source connected in parallel to the first current source and supplying a current proportional to the output current to the fifth transistor, wherein the gate of the second transistor is connected to the source of the fifth transistor.
Constant voltage power supply circuit.

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