JP7626637B2 - Stabilized Power Supply Circuit - Google Patents

Description

The present invention relates to a stabilized power supply circuit capable of supplying a stabilized output voltage.

As a conventional example of a stabilized power supply circuit composed of a regulator circuit, etc., for example, Patent Document 1 discloses a stabilized power supply circuit in which a phase compensation resistor is provided between the output terminal of an output transistor and the output terminal of the stabilized power supply circuit. In this stabilized power supply circuit, a phase compensation signal generated by the phase compensation resistor is fed back to the comparison amplifier means, making it possible to use a low ESR capacitor as the output stabilization capacitor without inserting a resistor equivalent to the ESR.

JP 2002-032133 A

Stabilized power supply circuits have a phase compensation circuit to stabilize the output, but a particular challenge is obtaining a stable output voltage even in areas where the output current is low. Recently, efforts have been made to reduce the current consumption of stabilized power supply circuits year by year in order to extend the operating time of battery-powered devices and other equipment equipped with stabilized power supply circuits. Under these circumstances, there is a demand for improved phase compensation characteristics, especially when the output current is low under light loads.

The present invention aims to provide a stabilized power supply circuit that can improve phase compensation characteristics, including under light load conditions with low output current.

The present invention provides a stabilized power supply circuit that outputs an output voltage stabilized such that a difference between a reference voltage and a voltage obtained by dividing an output voltage becomes zero, the stabilized output voltage comprising: a first transistor of a first conductivity type having a source connected to a first power supply and obtaining the output voltage from a drain; a second transistor of a first conductivity type having a source connected to the first transistor; a phase compensation resistor provided between the drain of the second transistor and ground or a second power supply; a phase compensation capacitor connected to the second transistor side of the phase compensation resistor; and a bias circuit that supplies a bias voltage to the gate of the second transistor , the bias voltage being a voltage shifted with respect to the gate voltage of the first transistor , the voltage of the phase compensation resistor being superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor ; the bias circuit has a third transistor of a second conductivity type and a constant current source, the gate of the third transistor being connected to the gate of the first transistor, the drain being connected to the source of the first transistor, and the source being connected to the gate of the second transistor and the constant current source.
Provide a stabilized power supply circuit.

The present invention also provides the above-mentioned stabilized power supply circuit, which includes a voltage divider circuit having one end connected to the drain of the first transistor and dividing the output voltage, and an error amplifier supplying a voltage proportional to the difference between the voltage obtained by dividing the output voltage and the reference voltage to the gate of the first transistor, and the phase compensation capacitor has one end connected to the drain of the second transistor and the phase compensation resistor element, and the other end connected to a common connection point of the voltage divider circuit.

The present invention also provides a stabilized power supply circuit that outputs an output voltage stabilized such that a difference between a reference voltage and a voltage obtained by dividing an output voltage becomes zero, the stabilized power supply circuit comprising: a first transistor of a first conductivity type having a source connected to a first power supply and obtaining the output voltage from a drain; a second transistor of the first conductivity type having a source connected to the first transistor; a phase compensation resistor element provided between the drain of the second transistor and ground or a second power supply; a phase compensation capacitor connected to the second transistor side of the phase compensation resistor element; and a bias circuit that supplies a bias voltage, which is a voltage displaced with respect to the gate voltage of the first transistor, to the gate of the second transistor, wherein a voltage of the phase compensation resistor element is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor, and the bias voltage supplied by the bias circuit increases in accordance with an increase in the output current of the first transistor.

The present invention also provides the above-mentioned stabilized power supply circuit, in which the bias circuit includes a third transistor of the second conductivity type, a constant current source, and a current source connected in parallel to the constant current source and supplying a current proportional to the output current, and the third transistor has a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor, the constant current source, and the current source.

The present invention provides a stabilized power supply circuit that can improve phase compensation characteristics, even under light loads with low output current.

1 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a first embodiment; 10 is a characteristic diagram showing an example of a change in drain current characteristic in transistor MP2 depending on the presence or absence of a bias voltage. 1 is a circuit diagram showing a specific configuration example of a stabilized power supply circuit according to a first embodiment; 4 is a characteristic diagram illustrating an example of gain and phase characteristics in the stabilized power supply circuit of the first embodiment. 4 is a characteristic diagram illustrating an example of a phase margin characteristic with respect to an output current in the stabilized power supply circuit according to the first embodiment. FIG. FIG. 11 is a circuit diagram showing a configuration of a stabilized power supply circuit according to a second embodiment. 10A and 10B are characteristic diagrams showing an example of changes in drain current characteristics with and without a bias voltage in transistor MP2 and with an increase in the bias voltage. FIG. 11 is a circuit diagram showing a specific configuration example of a stabilized power supply circuit according to a second embodiment. 10 is a characteristic diagram showing an example of a phase margin characteristic with respect to an output current in the stabilized power supply circuit according to the second embodiment; FIG. FIG. 1 is a circuit diagram showing a configuration of a stabilized power supply circuit of a comparative example.

Hereinafter, an embodiment of the stabilized power supply circuit according to the present invention (hereinafter, referred to as the "present embodiment") will be described in detail with reference to the drawings.

(Background to the present embodiment)
First, an example of a conventional stabilized power supply circuit will be described as a comparative example.

Figure 10 is a circuit diagram showing the configuration of a stabilized power supply circuit of a comparative example. Figure 6 shows an example of the configuration of a power supply circuit (hereinafter referred to as an "LDO regulator circuit") that is capable of low saturation operation (LDO (Low Drop-Out)) and is configured to output a stabilized voltage.

The stabilized power supply circuit 50 has a power supply terminal 51, an output terminal 53, a reference voltage source 55, and an error amplifier 56. A power supply voltage VDD is applied to the power supply terminal 51, and an output voltage VOUT is output from the output terminal 53 as the output of the power supply circuit. The error amplifier 56 has a reference voltage source 55 that supplies a reference voltage VREF connected to its inverting input terminal, and a gate of a PMOS type transistor Tr1 for output connected to its output terminal. The source of the transistor Tr1 is connected to the power supply terminal 51, and the drain is connected to the output terminal 53 and a voltage divider circuit 57. The voltage divider circuit 57 is composed of voltage divider resistors R1 and R2 connected in series between the output terminal 53 and ground, and the common connection point of the voltage divider resistors R1 and R2 is connected to the non-inverting input terminal of the error amplifier 56.

The stabilized power supply circuit 50 is configured such that the difference between the reference voltage VREF of the reference voltage source 55 and the feedback signal voltage obtained by resistively dividing the output voltage VOUT using voltage-dividing resistors R1 and R2 is amplified by the error amplifier 56 and applied to the output transistor Tr1, thereby causing the output voltage VOUT to become a predetermined value.

The output terminal of the error amplifier 56 is connected to the gates of the output transistor Tr1 and the phase compensation transistor Tr2. The drain of the transistor Tr2 is connected to ground via the phase compensation resistor R3. The phase compensation transistor Tr2 mirrors the drain current of the output transistor Tr1. A phase compensation capacitor C1 is connected between the connection point between the drain of the transistor Tr2 and the resistor R3 and the connection point between the voltage dividing resistors R1 and R2. The connection point between the voltage dividing resistors R1 and R2 and the capacitor C1 is connected to the non-inverting input terminal of the error amplifier 56. A stabilization capacitor CL having an equivalent series resistance ESR is connected between the output terminal 53 and ground. In addition, a load resistor RL is connected to the output terminal 53 as a circuit load of the stabilized power supply circuit 50.

In the stabilized power supply circuit 50, the capacitance of the phase compensation capacitor C1 is set to a value sufficiently smaller than that of the stabilized capacitor CL, thereby avoiding the occurrence of phase delay up to high frequencies. In addition, the phase compensation signal generated by the phase compensation resistor R3 is applied to the non-inverting input terminal of the error amplifier 56 via the capacitor C1, together with the feedback signal voltage obtained by dividing the output voltage VOUT. This cancels out the phase delay due to the frequency characteristics at the non-inverting input terminal of the error amplifier 56, and acts to cancel out the pole generated by the stabilized capacitor CL connected to the output terminal 53. Therefore, even if the equivalent series resistance ESR of the stabilized capacitor CL is small and the zero point frequency determined by the capacitance value of the stabilized capacitor CL and the resistance value of the equivalent series resistance ESR becomes a high frequency, the output voltage VOUT of the stabilized power supply circuit is prevented from becoming unstable.

In the configuration of the above comparative example, under normal load conditions, a ceramic capacitor with a low equivalent series resistance ESR can be used as the output voltage stabilization capacitor CL. However, under light load conditions with a small output current, the drain current of the output transistor Tr1 is small and the phase compensation transistor Tr2 has a smaller aspect ratio than the transistor Tr1, so that the transistor Tr2 operates in the subthreshold region. During subthreshold operation, the phase compensation transistor Tr2 cannot supply current to the phase compensation resistor R3 and therefore cannot apply a sufficient phase compensation signal, resulting in an insufficient phase compensation effect and possible oscillation.

In this embodiment, in consideration of the above circumstances, an example of the configuration of a stabilized power supply circuit that can perform sufficient phase compensation even when the output current is low and the load is light is shown.

First Embodiment
1 is a circuit diagram showing the configuration of a stabilized power supply circuit according to a first embodiment. In this embodiment, a power supply circuit configured to output a stabilized voltage is shown having a configuration that enables the use of a capacitor with a low equivalent series resistance as a capacitor for stabilizing the output voltage.

The stabilized power supply circuit 10 has a first power supply terminal (VDD) 1, an output terminal (VOUT) 3, a reference voltage source (VREF) 5, and an error amplifier (OP) 6. The first power supply terminal 1 is applied with a power supply voltage VDD as a high potential power supply, which is the first power supply. The output terminal 3 outputs an output voltage VOUT as the output of the power supply circuit. The error amplifier 6 has a reference voltage source 5 that supplies a reference voltage VREF connected to its inverting input terminal, and a gate of a PMOS type transistor MP1, which is an output transistor, connected to its output terminal. The transistor MP1 corresponds to a first transistor of a first conductivity type, and has a source connected to the first power supply terminal 1 and a drain connected to the output terminal 3 and a voltage dividing circuit 7, and obtains a predetermined output voltage from the drain. The voltage dividing circuit 7 is composed of voltage dividing resistors R1 and R2 connected in series between the output terminal 3 and ground, and the common connection point of the voltage dividing resistors R1 and R2 is connected to the non-inverting input terminal of the error amplifier 6 to divide the output voltage VOUT.

In the stabilized power supply circuit 10, the output voltage VOUT is resistively divided by voltage-dividing resistors R1 and R2 and applied as a feedback signal voltage to the non-inverting input terminal of the error amplifier 6. The difference between the reference voltage VREF at the inverting input terminal and the feedback signal voltage is then amplified and output by the error amplifier 6, and applied to the gate of the output transistor MP1. This controls the difference between the reference voltage and the feedback signal voltage to zero, and configures the output voltage VOUT to be a stabilized predetermined value.

The stabilized power supply circuit 10 is provided with a PMOS-type transistor MP2 for phase compensation, the source of which is connected to the transistor MP1 for output, and is configured so that the transistor MP2 mirrors the drain current of the transistor MP1. The transistor MP2 corresponds to a second transistor of a first conductivity type. The output terminal of the error amplifier 6 is connected to the gate of the transistor MP1 for output and to the gate of the transistor MP2 for phase compensation via a bias circuit 9 described later. The transistor MP2 for phase compensation has an aspect ratio smaller than that of the transistor MP1 for output. For example, the gate lengths of the transistors MP1 and MP2 are equal, and the ratio of the gate widths is set to MP1:MP2=n:1 (n>1). When no bias voltage is applied to the transistor MP2, the gate-source voltages of the transistors MP1 and MP2 are common, so that the drain current of the transistor MP2 is 1/n of the drain current of the transistor MP1.

The drain of the transistor MP2 is connected to ground via resistor R3, which serves as a phase compensation resistor element. A capacitor C1, which serves as a phase compensation capacitor, is connected between the connection point between the drain of the transistor MP2 and resistor R3 and the connection point between the voltage-dividing resistors R1 and R2. The connection point between the voltage-dividing resistors R1 and R2 and capacitor C1 is connected to the non-inverting input terminal of the error amplifier 6. A stabilization capacitor CL having an equivalent series resistance ESR is connected between the output terminal 3 and ground. In addition, a load resistor RL, which serves as a circuit load of the stabilizing power supply circuit 10, is connected to the output terminal 3.

In the stabilized power supply circuit 10 constituting the LDO regulator circuit, a pole frequency fp1 and a zero point frequency fz1 generated at the output terminal are expressed by the following equations.
fp1=1/(2π×CL×RL)…(1)
fz1=1/(2π×CL×ESR)…(2)

In the above formula, CL is the capacitance value of the stabilization capacitor CL, RL is the resistance value of the load resistor RL, and ESR is the equivalent series resistance value of the stabilization capacitor CL.

As shown in equation (1), the frequency fp1 of the pole generated at the output terminal changes depending on the value of the load resistor RL, and moves to a lower frequency when the resistance value of the load resistor RL is large. On the other hand, since a pole is generated in the error amplifier 6 and the output transistor MP1, if these two poles are close to each other, the feedback voltage may oscillate with a phase delay of 180°. This phenomenon tends to occur when the two poles are in a low frequency band and a ceramic capacitor with a small equivalent series resistance ESR is used as the stabilization capacitor CL, as the zero point frequency fz1 is in a high frequency band.

In the first embodiment of the stabilized power supply circuit 10, the voltage generated across resistor R3 acts as a phase compensation signal in response to the drain current of the phase compensation transistor MP2, and phase compensation is performed. The phase compensation signal from resistor R3 for phase compensation is superimposed on the feedback signal voltage obtained by dividing the output voltage VOUT by voltage divider resistors R1 and R2 via capacitor C1, and is applied to the non-inverting input terminal of error amplifier 6.

The stabilized power supply circuit 10 of the first embodiment has a bias circuit 9 that applies a bias voltage VB between the gate of the phase compensation transistor MP2 and the output terminal of the error amplifier 6. The bias circuit 9 functions as a constant voltage source, and by applying the bias voltage VB from the bias circuit 9 to the gate of the phase compensation transistor MP2 to bias it in the forward direction, it becomes possible to pass a drain current of a predetermined amount or more through the transistor MP2.

Figure 2 is a characteristic diagram showing an example of the change in drain current characteristics of transistor MP2 depending on whether or not a bias voltage is applied. Figure 2 shows the change in the drain current of transistor MP2 relative to the output current of the stabilized power supply circuit 10. When no bias voltage is applied, transistor MP2 has a drain current proportional to the output current, as shown by the dashed line. When a bias voltage is applied, transistor MP2 has a large drain current in the region where the output current is small, as shown by the solid line.

In the configuration of FIG. 1, the gate-source voltage of transistor MP1 is Vgs1, and the gate-source voltage of transistor MP2 is Vgs2. By providing a bias circuit 9 and applying a bias voltage VB, the gate voltage of the phase compensation transistor MP2 becomes lower than the voltage at the output terminal of the error amplifier 6. Specifically, the gate-source voltage Vgs2 of transistor MP2 becomes larger by the bias voltage VB, Vgs2 = Vgs1 + VB, and since Vgs2 > Vgs1, the gate voltage of transistor MP2 becomes lower than the gate voltage of transistor MP1. As a result, the drain current of the phase compensation transistor MP2 increases compared to when no bias voltage is applied.

The voltage at resistor R3 for phase compensation is set by the drain current of transistor MP2 for phase compensation and the resistance value of resistor R3. By applying bias voltage VB so that the gate-source voltage Vgs2 of transistor MP2 is greater than the gate-source voltage Vgs1 of transistor MP1, even in the region where the drain current of transistor MP1 is small, transistor MP2 is ensured to have a sufficient gate-source voltage and does not enter subthreshold operation.

In this embodiment, the voltage at the resistor R3 for phase compensation increases compared to when the bias voltage is not applied, and acts to cancel the pole (the above formula (1)) generated at the output terminal. At this time, it is possible to generate a zero point by the capacitor C1 for phase compensation even in an area where the output current is small, and the phase delay can be canceled. As a result, even when the drain current of the output transistor MP1 is low and the load is light, the frequency characteristics in the loop from the non-inverting input terminal of the error amplifier 6 to the output terminal of the error amplifier 6 to the output transistor MP1 to the output terminal 3 to the resistor R1 to the non-inverting input terminal of the error amplifier 6 are improved. In this case, unlike when the bias voltage is not applied, the phase is prevented from delaying by 180° at low frequencies, and the output voltage VOUT is output stably even if the equivalent series resistance ESR of the stabilization capacitor CL is small.

The values of the phase compensation capacitor C1, resistor R3, and voltage divider resistors R1 and R2 of the voltage divider circuit 7 are set to appropriate values so that a stable output voltage is obtained.

Figure 3 is a circuit diagram showing a specific example of the configuration of the stabilized power supply circuit of the first embodiment. The stabilized power supply circuit 10A in Figure 3 shows a specific example of the circuit configuration of the stabilized power supply circuit 10 and the bias circuit 9. Here, the following description focuses on the parts that differ from the configuration of the stabilized power supply circuit 10 shown in Figure 1, and similar components are given the same reference numerals and will not be described.

The stabilized power supply circuit 10A has a first power supply terminal (VDD) 1, a second power supply terminal (VSS) 2, an output terminal (VOUT) 3, a current source (IS) 4, a reference voltage source (VREF) 5, and an error amplifier (OP) 6. A first power supply voltage VDD is applied to the first power supply terminal 1 as a high potential power supply, which is the first power supply. A second power supply voltage VSS (VSS<VDD) is applied to the second power supply terminal 2 as a low potential power supply, which is the second power supply. The current source 4 is connected to the first power supply terminal 1 and is a current source that supplies a current IS.

The stabilized power supply circuit 10A has an error amplifier 6 that includes NMOS transistors (NMOS transistors) MN2, MN3, and MN5, and PMOS transistors (PMOS transistors) MP3 and MP4. The transistors MN2, MN3, and MN5 form a differential circuit. The transistors MP3 and MP4 are current-mirror connected, and form an active load for the differential circuit formed by the transistors MN2, MN3, and MN5. The stabilized power supply circuit 10A also has an NMOS transistor MN4 that is current-mirror connected to the transistor MN5. The gate and drain of the transistor MN4 are connected to the current source 4, and the current IS of the current source 4 is supplied to the transistor MN5 as a bias current.

The error amplifier 6 has an inverting input terminal 61 (gate of transistor MN2) connected to the reference voltage source 5, and a non-inverting input terminal 62 (gate of transistor MN3) connected to the common connection point of the voltage-dividing resistors R1 and R2 of the voltage-dividing circuit 7. The output terminal 63 (common connection point of the drains of transistors MN2 and MP3) of the error amplifier 6 is connected to the gate of the output PMOS transistor MP1. The source of transistor MP1 is connected to the first power supply terminal 1, and the drain is connected to the output terminal 3 and the voltage-dividing circuit 7. The voltage-dividing circuit 7 is connected between the output terminal 3 and the second power supply terminal 2.

The stabilized power supply circuit 10A has an output transistor MP1 and a PMOS-type transistor MP2 for phase compensation, the sources of which are connected to each other. The source of the transistor MP2 is connected to the first power supply terminal 1, and the gate is connected to the output terminal 63 of the error amplifier 6 via the bias circuit 9. The drain of the transistor MP2 is connected to the second power supply terminal 2 via a phase compensation resistor R3, and is also connected to one end of a phase compensation capacitor C1. The other end of the capacitor C1 is connected to the non-inverting input terminal 62 of the error amplifier 6.

The bias circuit 9 is composed of NMOS type transistors MN1 and MN6. Transistor MN6 functions as a constant current source, is connected to transistors MN4 and MN5 in a current mirror configuration, and supplies the current IS of the current source 4 to transistor MN1. Transistor MN1 corresponds to a third transistor of the second conductivity type, and is provided between the gate of transistor MP2 and the output terminal 63 of the error amplifier 6. Specifically, the gate of transistor MN1 is connected to the output terminal 63 of the error amplifier 6, the drain is connected to the first power supply terminal 1, and the source of transistor MN1 and the drain of transistor MN6 are connected to each other. The gate of transistor MP2 for phase compensation is connected to the connection point between the source of transistor MN1 and the drain of transistor MN6.

In the configuration of FIG. 3, the gate-source voltage of transistor MN1 of bias circuit 9 corresponds to bias voltage VB in FIG. 1. As described above, the gate-source voltage Vgs2 of transistor MP2 for phase compensation is greater than the gate-source voltage Vgs1 of transistor MP1 for output by the gate-source voltage VB of transistor MN1. At this time, the drain current of transistor MP2 is 1/n+α of the drain current of transistor MP1. Therefore, even during light loads when the drain current of transistor MP1 for output is small, the drain current of transistor MP2 for phase compensation is ensured to be equal to or greater than a predetermined amount, and the voltage generated in resistor R3 for phase compensation cancels out the pole generated at output terminal 3, resulting in a stable output voltage VOUT.

Figure 4 is a characteristic diagram showing an example of gain and phase characteristics in the stabilized power supply circuit of the first embodiment. In Figure 4, the phase characteristics in the configuration of the first embodiment shown in Figures 1 and 3 are shown by solid lines, the gain characteristics are shown by dashed lines, and the phase characteristics in the configuration of the comparative example shown in Figure 10 are shown by dashed lines, and the gain characteristics are shown by two-dot chain lines.

In the illustrated example, in the configuration of the embodiment, the phase margin at a gain of 0 dB is 96 deg, which is a significant improvement over the phase margin of 3.6 deg in the comparative example. By applying a bias voltage to the gate of the phase compensation transistor MP2, even in areas where the output current is low, the phase delay can be cancelled out by the zero point generated by the phase compensation capacitor C1, and the phase margin can be secured.

Figure 5 is a characteristic diagram showing an example of the phase margin characteristic with respect to the output current in the stabilized power supply circuit of the first embodiment. In the configuration of the embodiment, a large phase margin can be secured in the region where the drain current of the output transistor MP1 is small. In this embodiment, even in the region where the output current is small, a sufficient current is passed through the phase compensation resistor to cancel out the phase delay and obtain the effect of phase compensation. Therefore, even under light load, a phase margin can be secured, the phase compensation effect can be enhanced, and the stability of the power supply circuit can be improved.

Second Embodiment
6 is a circuit diagram showing the configuration of a stabilized power supply circuit of the second embodiment. The stabilized power supply circuit 10B of the second embodiment is provided with a bias circuit 9B instead of the bias circuit 9 constituting the stabilized power supply circuit 10 of the first embodiment. The bias circuit 9B of the second embodiment is configured so that the bias voltage VB increases as the output current increases. Specifically, a transistor MP5 is provided, the source and gate of which are mutually connected to those of the transistor MP1, and the drain of which is connected to the current mirror circuit 11. A drain current proportional to the output current flowing through the drain of the transistor MP1 flows through the transistor MP5. The bias voltage VB increases as the drain current of the transistor MP5 increases.

In the stabilized power supply circuit 10 of the first embodiment described above, the phase lag increases as the output current increases, which causes the output voltage VOUT to become unstable. According to the second embodiment, the phase compensation signal can be increased more than in the first embodiment as the output current increases, so that the output current VOUT can be further stabilized.

Figure 7 is a characteristic diagram showing an example of the change in drain current characteristics due to the presence or absence and increase of bias voltage in transistor MP2. As shown in the figure, when no bias voltage is applied, transistor MP2 has a drain current proportional to the output current as shown by the dashed line. When a constant bias voltage is applied, transistor MP2 has a large drain current in the region where the output current is small as shown by the dashed line, but in the region where the output current is large, the increase in drain current with respect to the increase in output current is smaller than when no bias is applied. When the bias voltage is increased in response to the increase in output current, transistor MP2 has a large drain current in the region where the output current is small, as in the case where a constant bias voltage is applied, as shown by the solid line. Furthermore, in the region where the output current is large, the drain current flows in proportion to the output current almost the same as when no bias is applied.

Figure 8 is a circuit diagram showing a specific example of the configuration of a stabilized power supply circuit of the second embodiment. The stabilized power supply circuit 10C in Figure 8 shows a specific example of the circuit of the bias circuit 9B. Here, the following description focuses on the differences from the stabilized power supply circuit 10B shown in Figure 6, and similar components are given the same reference numerals and will not be described.

The bias circuit 9B is configured to include NMOS transistors MN1 and MN6, a PMOS transistor MP5, and a current mirror circuit 11. The connection between the transistors MN1 and MN6 is the same as in the embodiment shown in FIG. 3 described above, so a detailed description is omitted here.

The transistor MP5 and the current mirror circuit 11 function as a current source that supplies a current proportional to the output current to the drain of the transistor MN1. The source and gate of the transistor MP5 are mutually connected to the transistor MP1, and a drain current proportional to the output current flowing to the drain of the transistor MP1 flows. The current mirror circuit 11 is composed of NMOS type transistors MN7 and MN8. The gate and drain of the transistor MN7 are connected to the drain of the transistor MP5, and the source is connected to the second power supply voltage VSS. The gate of the transistor MN8 is mutually connected to the transistor MN7, the source is connected to the second power supply voltage VSS, and the drain is connected to the source of the transistor MN1 and the drain of the transistor MN6. Thus, in the bias circuit 9B of FIG. 9, the current mirror circuit 11 is connected in parallel to the transistor MN6, which is a constant current source.

With the above configuration, the drain current proportional to the output current of transistor MP5 is mirrored to the drain of transistor MN8. The drain current of transistor MN1 is the sum of the current IS mirrored to transistor MN6 and the current proportional to the output current mirrored to transistor MN8. As a result, the gate-source voltage of transistor MN1, which is the bias voltage VB, is a voltage proportional to both the current IS and the output current, and the bias voltage VB can also increase in accordance with an increase in the output current.

Figure 9 is a characteristic diagram showing an example of the phase margin characteristic with respect to the output current in the stabilized power supply circuit of the second embodiment. In the configurations of the first and second embodiments, a large phase margin can be ensured in the region where the drain current of the output transistor MP1 is small. In addition, in the configuration of the second embodiment, a larger phase margin can be ensured than in the first embodiment in the region where the drain current of the output transistor MP1 is large.

As described above, according to this embodiment, by applying a bias voltage to the gate of the phase compensation transistor, sufficient phase compensation is possible even when the drain current of the output transistor is small and the load is light. In other words, even in the region where the output current of the stabilized power supply circuit is small, a phase margin can be secured and a sufficient phase compensation effect can be obtained, and the phase compensation characteristics can be improved in the entire range of the output current. Therefore, a stable output voltage can be obtained in the entire current range. Therefore, it is possible to use a ceramic capacitor with a low equivalent series resistance ESR as the output voltage stabilization capacitor CL while improving stability in the entire current range. This embodiment is useful for low-voltage output LDO regulator circuits and voltage trackers, where it is difficult to generate a zero point at a low frequency.

In the stabilized power supply circuit of this embodiment, one of the PMOS transistor and the NMOS transistor is also referred to as a transistor of a first conductivity type, and the other, which has the opposite polarity, is also referred to as a transistor of a second conductivity type. In the configuration example of the above-mentioned embodiment, the PMOS transistor is the first conductivity type, and the NMOS transistor is the second conductivity type.

In the above embodiment, the power supply voltage is VDD>VSS. However, if the power supply voltage relationship is reversed, the PMOS transistors can be replaced with NMOS transistors, and the NMOS transistors can be replaced with PMOS transistors. In this case, the NMOS transistors are the first conductivity type, and the PMOS transistors are the second conductivity type.

Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modified or revised examples within the scope of the claims, and it is understood that these also naturally fall within the technical scope of the present invention. Furthermore, the components in the above embodiments may be combined in any manner as long as it does not deviate from the spirit of the present invention.

The present invention has the effect of improving phase compensation characteristics, including under light loads with low output current, and is useful for stabilized power supply circuits such as LDO regulator circuits.

10, 10A to 10C: Stabilized power supply circuit 1: First power supply terminal (VDD)
2: Second power supply terminal (VSS)
3: Output terminal (VOUT)
4: Current source (IS)
5: Reference voltage source (VREF)
6: Error amplifier 61: Inverting input terminal, 62: Non-inverting input terminal, 63: Output terminal 7: Voltage divider circuit 9, 9B: Bias circuit Tr1, MP1: Output transistor (PMOS transistor)
Tr2, MP2: Phase compensation transistors (PMOS transistors)
MP3, MP4, MP5: Transistors (PMOS transistors)

MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8: transistors (NMOS transistors)
R3: Resistor for phase compensation C1: Capacitor for phase compensation CL: Capacitor for stabilization ESR: Equivalent series resistance of the stabilization capacitor CL RL: Load resistance

Claims (4)

A stabilized power supply circuit that outputs a stabilized output voltage so that the difference between a reference voltage and a voltage obtained by dividing an output voltage is zero,
a first transistor of a first conductivity type having a source connected to a first power supply and having a drain from which the output voltage is obtained;
a second transistor of a first conductivity type having a source connected to that of the first transistor;
a phase compensation resistor element provided between the drain of the second transistor and a ground or a second power supply;
a phase compensation capacitor connected to the second transistor side of the phase compensation resistor;
a bias circuit that supplies a bias voltage to a gate of the second transistor, the bias voltage being a voltage offset with respect to a gate voltage of the first transistor ;
a voltage of the phase compensation resistor is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor ;
the bias circuit includes a third transistor of a second conductivity type and a constant current source;
the third transistor has a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor and the constant current source;
Stabilized power supply circuit. 2. The stabilized power supply circuit according to claim 1,
a voltage divider circuit having one end connected to the drain of the first transistor and dividing the output voltage;
an error amplifier that supplies a voltage proportional to a difference between a voltage obtained by dividing the output voltage and the reference voltage to a gate of the first transistor;
one end of the phase compensation capacitor is connected to the drain of the second transistor and the phase compensation resistor element, and the other end is connected to a common connection point of the voltage divider circuit;
Stabilized power supply circuit. A stabilized power supply circuit that outputs a stabilized output voltage so that the difference between a reference voltage and a voltage obtained by dividing an output voltage is zero,
a first transistor of a first conductivity type having a source connected to a first power supply and having a drain from which the output voltage is obtained;
a second transistor of a first conductivity type having a source connected to that of the first transistor;
a phase compensation resistor element provided between the drain of the second transistor and a ground or a second power supply;
a phase compensation capacitor connected to the second transistor side of the phase compensation resistor;
a bias circuit that supplies a bias voltage to a gate of the second transistor, the bias voltage being a voltage offset with respect to a gate voltage of the first transistor;
a voltage of the phase compensation resistor is superimposed on a voltage obtained by dividing the output voltage via the phase compensation capacitor;
the bias voltage supplied by the bias circuit increases in accordance with an increase in the output current of the first transistor;
Stabilized power supply circuit. 4. The stabilized power supply circuit according to claim 3 ,
The bias circuit includes:
a third transistor of a second conductivity type; a constant current source; and a current source connected in parallel to the constant current source and supplying a current proportional to the output current;
the third transistor has a gate connected to the gate of the first transistor, a drain connected to the source of the first transistor, and a source connected to the gate of the second transistor, the constant current source, and the current source;
Stabilized power supply circuit.

Images