JP7631809B2 - Metal Base Board - Google Patents

Description

The present invention relates to a metal-based substrate.

Metal base substrates are known as one type of substrate for mounting electronic components such as semiconductor elements and LEDs. Metal base substrates are laminates in which a metal substrate, an insulating layer, and a circuit layer are laminated in this order. The insulating layer is generally formed from an insulating composition containing a resin with excellent insulating properties and voltage resistance, and an inorganic filler with excellent thermal conductivity. Electronic components are mounted on the circuit layer via solder. In a metal base substrate configured in this way, heat generated by the electronic components is transferred to the metal substrate via the insulating layer, and dissipated from the metal substrate to the outside.

In a metal base substrate, if there is a large difference in the thermal expansion coefficient between the metal base substrate and the electronic components joined to the metal base substrate via solder, the stress applied to the solder joining the electronic components to the metal base substrate increases when the electronic components are turned on and off or when the electronic components are subjected to thermal cycles due to the external environment, which can lead to solder cracks. For this reason, it has been considered to reduce the elastic modulus of the insulating layer of the metal base substrate and to use the insulating layer to alleviate the difference in the thermal expansion coefficient between the metal substrate of the metal base substrate and the electronic components (Patent Documents 1 and 2).

Japanese Patent Application Publication No. 11-87866 JP 2016-111171 A

In order to prevent the occurrence of solder cracks due to thermal cycles when electronic components are mounted and to improve reliability against thermal cycles, it is effective to reduce the elastic modulus of the insulating layer of the metal base substrate to make the insulating layer easier to deform, thereby mitigating thermal stress due to the expansion of the metal base. However, since there is also stress on the solder due to the expansion of the circuit layer, there is a limit to how much reliability against thermal cycles can be improved simply by reducing the elastic modulus of the insulating layer of the metal base substrate. Furthermore, if the elastic modulus of the insulating layer is reduced too much, the restraining force of the insulating layer on the circuit layer decreases, which can reduce reliability against thermal cycles.

The present invention was made in consideration of the above circumstances, and aims to provide a metal base substrate that has excellent reliability against thermal cycles when electronic components are mounted on it.

In order to solve the above problems, the metal base substrate of the present invention is a metal base substrate comprising a metal substrate, at least one insulating layer, and a circuit layer laminated in this order, the insulating layer containing an insulating resin and an inorganic filler, the inorganic filler having an average particle diameter in the range of 0.1 μm or more and 20 μm or less, and E defined by the following formula (1) being 3.10 × 10 ⁸ or less.

However, in formula (1), S represents a number calculated using formula (2) below.

In the formula (2), f ₀ is 3.14, f ₁ is −3.25, R ₀ represents a value calculated from the following formula (3-0), and R ₁ represents a value calculated from the following formula (3-1).

In formula (3-0) and formula (3-1), d ₀ is −0.423, d ₁ is −2.03, d ₂ is 0.804, e ₀ is 5.23, e ₁ is 4.30, e ₂ is −4.40, Q ₀ represents a value calculated by the following formula (4-0), Q ₁ represents a value calculated by the following formula (4-1), and Q ₂ represents a value calculated by the following formula (4-2).

However, in formula (4-0), formula (4-1), and formula (4-2), a ₀ is 7.53, a ₁ is 3.09, a ₂ is 0.308, a ₃ is −0.137, a ₄ is 0.0342, a ₅ is 0.451, b 0 is 0.839, b ₁ is −0.127, b ₂ is 0.0380, b ₃ is −2.78, b ₄ is −0.828, _{b 5} is −0.762, c 0 is −3.64, c ₁ is _6.98 , c ₂ is 0.319, c ₃ is −0.451, c ₄ is −0.776, and c ₅ is 0.189. _P0 represents a value calculated by the following formula (5-0), _P1 represents a value calculated by the following formula (5-1), _P2 represents a value calculated by the following formula (5-2), _P3 represents a value calculated by the following formula (5-3), _P4 represents a value calculated by the following formula (5-4), and _P5 represents a value calculated by the following formula (5-5).

In the formulas (5-0), (5-1), (5-2), (5-3), (5-4), and (5-5), K _resin represents the elastic modulus (unit: GPa) of the insulating layer at 100° C., K _electrode represents the elastic modulus (unit: GPa) of the circuit layer at 100° C., K _base represents the elastic modulus (unit: GPa) of the metal substrate at 100° C., T _resin represents the thickness (unit: μm) of the insulating layer, T _electrode represents the thickness (unit: μm) of the circuit layer, T _base represents the thickness (unit: μm) of the metal substrate, and CTE _base represents the thermal expansion coefficient (unit: ppm) of the metal substrate at 100° C.

According to the metal base substrate of the present invention, the value of E calculated by the above formula (1) is highly correlated with the von Mises stress imparted to the solder during a thermal cycle when electronic components such as semiconductor elements and LEDs are mounted on the metal base substrate using solder, and since the value of E is 3.10×10 ⁸ or less, the von Mises stress imparted to the solder when subjected to a thermal cycle is small. In addition, since it is not necessary to excessively reduce the elastic modulus of the insulating layer, the restraining force of the circuit layer by the insulating layer is not reduced. Therefore, the metal base substrate of the present invention has excellent reliability against thermal cycles when electronic components are mounted.

In the metal base board of the present invention, the insulating layer may be configured so that the ratio of the thickness (unit: μm) to the elastic modulus (unit: GPa) at 100° C. is 10 or more.
In this case, since the thickness/elastic modulus of the insulating layer is large, at 10 or more, the insulating layer is easily deformed, and the insulating layer can easily reduce the difference in thermal expansion coefficient between the metal substrate and the electronic components due to thermal cycles. Therefore, the reliability of this metal base substrate against thermal cycles when electronic components are mounted is improved.

In the metal base board of the present invention, the insulating layer may be a laminate of two or more layers each having a different elastic modulus at 100°C.
In this case, since there are two insulating layers, one with a high withstand voltage and one with high flexibility, it is possible to improve both the withstand voltage and reliability while keeping the thermal resistance small.

The present invention provides a metal base substrate that is highly reliable against thermal cycles when electronic components are mounted on it.

1 is a schematic cross-sectional view of a metal base substrate according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a schematic diagram of a joint structure used in calculating a simulation value of the von Mises stress. FIG. 3 is a plan view of the joint structure shown in FIG. 2 . 1 is a graph showing the relationship between the E value calculated in the examples and the simulated value of the Mises stress.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a metal base substrate according to one embodiment of the present invention.
1, the metal base substrate 10 is a laminate in which a metal substrate 20, an insulating layer 30, and a circuit layer 40 are laminated in this order. An electrode terminal 61 of an electronic component 60 is connected to the circuit layer 40 of the metal base substrate 10 via solder 50.

The metal substrate 20 is the base member of the metal base substrate 10. The metal substrate 20 is a copper substrate or an aluminum substrate. The copper substrate is made of copper or a copper alloy. The aluminum substrate is made of aluminum or an aluminum alloy.

The insulating layer 30 is a layer for insulating the metal substrate 20 and the circuit layer 40. The insulating layer 30 is formed from an insulating resin composition containing an insulating resin 31 and an inorganic filler 32. By forming the insulating layer 30 from an insulating resin composition containing an insulating resin 31 having high insulation properties and an inorganic filler 32 having high thermal conductivity, it is possible to further reduce the thermal resistance of the entire metal base substrate 10 from the circuit layer 40 to the metal substrate 20 while maintaining insulation. The insulating layer 30 may be a single layer body consisting of only one layer, or a laminate body consisting of two or more layers. It is preferable that the insulating layer 30 is a single layer body or a two-layer laminate body.

The insulating resin 31 preferably contains a polyimide resin, a polyamide-imide resin, or a mixture thereof. These resins have excellent properties such as insulation, voltage resistance, chemical resistance, and mechanical properties, and therefore improve these properties of the metal base substrate 10.

The inorganic filler 32 preferably has an average particle diameter in the range of 0.1 μm to 20 μm. When the inorganic filler 32 has an average particle diameter of 0.1 μm or more, the thermal conductivity of the insulating layer 30 is improved. When the inorganic filler 32 has an average particle diameter of 20 μm or less, the voltage resistance of the insulating layer 30 is improved. In addition, when the average particle diameter of the inorganic filler 32 is within the above range, the inorganic filler 32 is less likely to form aggregated particles, and the inorganic filler 32 is more likely to be uniformly dispersed in the insulating resin 31. When the inorganic filler 32 does not form aggregated particles and is dispersed in the insulating resin 31 as primary particles or fine particles close to primary particles, the voltage resistance of the insulating layer 30 is improved. From the viewpoint of improving the thermal conductivity of the insulating layer 30, the average particle diameter of the inorganic filler 32 is preferably in the range of 0.3 μm to 20 μm.

The content of the inorganic filler 32 in the insulating layer 30 is preferably in the range of 50 volume % or more and 85 volume % or less. When the content of the inorganic filler 32 is 50 volume % or more, the thermal conductivity of the insulating layer 30 is improved. On the other hand, when the content of the inorganic filler 32 is 85 volume % or less, the voltage resistance of the insulating layer 30 is improved. In addition, when the content of the inorganic filler 32 is within the above range, the inorganic filler 32 is easily uniformly dispersed in the insulating resin 31. When the inorganic filler 32 is uniformly dispersed in the insulating resin 31, the mechanical strength of the insulating layer 30 is improved. From the viewpoint of improving the thermal conductivity of the insulating layer 30, it is particularly preferable that the content of the inorganic filler 32 is in the range of 50 volume % or more and 80 volume % or less.

As the inorganic filler 32, alumina (Al ₂ O ₃ ) particles, alumina hydrate particles, aluminum nitride (AlN) particles, silica (SiO ₂ ) particles, silicon carbide (SiC) particles, titanium oxide (TiO ₂ ) particles, boron nitride (BN) particles, etc. can be used. Among these fillers, alumina particles are preferred. The alumina particles are more preferably α-alumina particles. The α-alumina particles preferably have a ratio of tap density to true density (tap density/true density) of 0.1 or more. The tap density/true density correlates with the packing density of the α-alumina particles in the insulating layer 30, and a high tap density/true density can increase the packing density of the α-alumina particles in the insulating layer 30. When the packing density of the α-alumina particles in the insulating layer 30 increases, the spacing between the α-alumina particles in the insulating layer 30 becomes narrower, and voids (pores) are less likely to occur in the insulating layer 30. The ratio of tap density to true density is preferably in the range of 0.2 to 0.9. The α-alumina may be in the form of polycrystalline particles, but is particularly preferably in the form of single crystal particles.

The insulating layer 30 preferably has a ratio (thickness/elastic modulus) of the thickness (unit: μm) to the elastic modulus (unit: GPa) at 100°C of 10 or more. The thickness/elastic modulus of the insulating layer 30 is preferably in the range of 10 to 200,000, more preferably in the range of 20 to 20,000, and even more preferably in the range of 50 to 200. The elastic modulus of the insulating layer 30 at 100°C is preferably in the range of 0.001 GPa to 20 GPa. The thickness of the insulating layer 30 is preferably in the range of 10 μm to 200 μm.

The circuit layer 40 is formed in a circuit pattern. Electrode terminals 61 of the electronic components 60 are joined onto the circuit layer 40 formed in the circuit pattern via solder 50 or the like. The circuit layer 40 may be made of a metal such as copper, aluminum, or gold. The circuit layer 40 is preferably made of copper foil. The circuit layer 40 preferably has an elastic modulus in the range of 30 GPa or more and 200 GPa or less. The circuit layer 40 also preferably has a thickness in the range of 2 μm or more and 200 μm or less.

In the metal base substrate 10 of this embodiment, E defined by the following formula (1) is 3.10×10 ⁸ or less.

ただし、式（１）において、Ｓは、下記の式（２）より算出される数を表す。

In the formula (1), S represents a number calculated by the following formula (2).

In the formula (2), _f0 is 3.14 and _f1 is −3.25. _R0 represents a value calculated from the following formula (3-0), and _R1 represents a value calculated from the following formula (3-1).

In the formulas (3-0) and (3-1), d ₀ is −0.423, d ₁ is −2.03, d ₂ is 0.804, e ₀ is 5.23, e ₁ is 4.30, and e ₂ is −4.40. Q ₀ represents a value calculated from the following formula (4-0), Q ₁ represents a value calculated from the following formula (4-1), and Q ₂ represents a value calculated from the following formula (4-2).

In the formulas (4-0), (4-1) and (4-2), a ₀ is 7.53, a ₁ is 3.09, a ₂ is 0.308, a ₃ is −0.137, a ₄ is 0.0342, a ₅ is 0.451, b ₀ is 0.839, b ₁ is −0.127, b ₂ is 0.0380, b 3 is −2.78, b ₄ is −0.828, b ₅ is −0.762, c ₀ is −3.64, c ₁ is 6.98, c ₂ is _0.319 , c ₃ is −0.451, c ₄ is −0.776, c ₅ is 0.189, and P _{P 0} represents a value calculated by the following formula (5-0), P ₁ represents a value calculated by the following formula (5-1), P ₂ represents a value calculated by the following formula (5-2), P ₃ represents a value calculated by the following formula (5-3), P ₄ represents a value calculated by the following formula (5-4), and P ₅ represents a value calculated by the following formula (5-5).

In the formulas (5-0), (5-1), (5-2), (5-3), (5-4), and (5-5), K _resin represents the elastic modulus (unit: GPa) of the insulating layer 30 at 100° C., K _electrode represents the elastic modulus (unit: GPa) of the circuit layer 40 at 100° C., K _base represents the elastic modulus (unit: GPa) of the metal substrate 20 at 100° C., T _resin represents the thickness (unit: μm) of the insulating layer 30, T _electrode represents the thickness (unit: μm) of the circuit layer 40, and T _base represents the thickness (unit: μm) of the metal substrate 20 and the thermal expansion coefficient (unit: ppm) of the metal substrate 20 at 100° C. The above formula can be determined by machine learning using the elastic modulus (unit: GPa) of the insulating layer 30 at 100°C, the elastic modulus (unit: GPa) of the circuit layer 40 at 100°C, the elastic modulus (unit: GPa) of the metal substrate 20 at 100°C, the thickness of the insulating layer 30 (unit: μm), the thickness of the circuit layer 40 (unit: μm), the thickness of the metal substrate 20 (unit: μm), and the thermal expansion coefficient (unit: ppm) of the metal substrate 20 at 100°C as input variables, and the von Mises stress value as the objective function.

The value of E is highly correlated with the Mises stress applied to the solder 50 during a thermal cycle when the electronic component 60 is mounted on the metal base substrate 10 using the solder 50. Since the value of E of the metal base substrate 10 is set to 3.10×10 ⁸ or less, the Mises stress applied to the solder 50 during a thermal cycle is suppressed to 3.10×10 ⁸ Pa or less. Therefore, when a thermal cycle is applied, cracks are unlikely to occur in the solder 50. In addition, since it is not necessary to excessively lower the elastic modulus of the insulating layer 30, the restraining force of the circuit layer 40 by the insulating layer 30 is unlikely to decrease. Therefore, the stress applied to the solder 50 from the circuit layer 40 can be suppressed. The value of E is preferably 2.30×10 ⁸ or less. In addition, the value of E may be 0.50×10 ⁸ or more.

The value of E of the metal base substrate 10 can be calculated, for example, as follows.
First, the elastic modulus (K _resin ) of the insulating layer 30 at 100°C, the elastic modulus (K _electrode ) of the circuit layer 40 at 100°C, the elastic modulus (K _base ) of the metal substrate 20 at 100°C, the thermal expansion coefficient (CTE _base ) of the metal substrate 20 at 100°C, the thickness (T _resin ) of the insulating layer 30, the thickness (T _electrode ) of the circuit layer 40, and the thickness (T _base ) of the metal substrate 20 are measured.

The elastic modulus of the insulating layer 30 at 100°C can be measured, for example, as follows. The metal substrate 20 and the circuit layer 40 of the metal base substrate 10 are removed by etching to isolate the insulating layer 30. The elastic modulus (tensile modulus) of the obtained insulating layer 30 is measured by dynamic mechanical analysis (DMA).

The elastic modulus of the circuit layer 40 at 100°C can be measured by a resonance method (apparatus: TE-RT manufactured by Nippon Technoplus Co., Ltd., etc.). The elastic modulus (tensile modulus) of the metal substrate 20 at 100°C can be measured by a tensile test (JIS Z2241:2011 Metallic material tensile test method). The thermal expansion coefficient of the metal substrate 20 at 100°C can be measured by a thermomechanical analyzer (TMA).

The thicknesses of the metal substrate 20, insulating layer 30, and circuit layer 40 of the metal base substrate 10 can be measured, for example, as follows. The metal base substrate 10 is filled with resin, and the cross section is exposed by mechanical polishing. The exposed cross section of the metal base substrate 10 is then observed using an optical microscope, and the thicknesses of the metal substrate 20, insulating layer 30, and circuit layer 40 are measured.

Next, the obtained K _resin , K _electrode , K _base , CTE _base , T _resin , T _electrode , and T _base are substituted into the above formulas (5-0) to (5-5) to calculate P ₀ to P ₅ .
When the insulating layer 30 is a laminate of two or more layers, ΣT _resin /K _resin in the formula (5-0) is the sum of T _resin /K _resin of each insulating layer 30.

Next, the obtained _P0 to _P5 are substituted into the above formulas (4-0) to (4-2) to calculate _Q0 to _Q2 . Next, the obtained _Q0 to _Q2 are substituted into the above formulas (3-0) to (3-1) to calculate _R0 to _R1 . Next, the obtained _R0 to _R1 are substituted into the above formula (2) to calculate S. Then, the obtained S is substituted into the above formula (1) to calculate E.

Examples of the electronic components 60 mounted on the metal base substrate 10 of this embodiment are not particularly limited and include semiconductor elements, resistors, capacitors, and crystal oscillators. Examples of semiconductor elements include MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), LSIs (Large Scale Integration), LEDs (Light Emitting Diodes), LED chips, and LED-CSPs (LED-Chip Size Packages).

A method for manufacturing the metal base substrate 10 according to this embodiment will be described below.
The metal base board 10 according to this embodiment can be manufactured by a method including, for example, a design step, an insulating layer forming step, and a circuit layer compression bonding step.

In the design process, the material and thickness of the metal substrate 20, the material and thickness of the insulating layer 30, and the material and thickness of the circuit layer 40 are set.
First, the material and thickness of the metal substrate 20, the material and thickness of the insulating layer 30, and the material and thickness of the circuit layer 40 are provisionally set. The material and thickness of the metal substrate 20 are provisionally set based on, for example, the heat dissipation and size required for the metal base substrate 10. The material and thickness of the insulating layer 30 are provisionally set based on, for example, the insulation properties and voltage resistance required for the metal base substrate 10. The material and thickness of the circuit layer 40 are provisionally set based on, for example, the electrical properties of the electronic components 60 to be mounted on the metal base substrate 10.

Next, E is calculated using the provisionally set elastic modulus (K _base ) at 100 ° C., coefficient of thermal expansion (CTE _base ) at 100 ° C., and thickness (T _base ) of the metal substrate 20, the elastic modulus (K _resin ) and thickness (T _resin ) of the insulating layer 30 at 100 ° C., and the elastic modulus (K _electrode ) and thickness (T _electrode ) of the circuit layer 40 at 100 ° C. If the obtained value of E exceeds 3.10 × 10 ⁸ , the material and thickness of the metal substrate 20, the material and thickness of the insulating layer 30, and the material and thickness of the circuit layer 40 are provisionally set again. If the value of E is 3.10 × 10 ⁸ or less, the metal base substrate 10 is manufactured with the material and thickness of the metal substrate 20, the material and thickness of the insulating layer 30, and the material and thickness of the circuit layer 40.

In the insulating layer forming step, an insulating layer 30 is formed on the metal substrate 20 to obtain a metal substrate with an insulating layer. The insulating layer 30 can be formed by a coating method or an electrodeposition method.
The coating method is a method in which a coating liquid containing a solvent, an insulating resin, and an inorganic filler is applied onto the metal substrate 20 to form a coating layer, and then the coating layer is heated to obtain the insulating layer 30. The coating liquid can be a resin material solution in which an insulating resin is dissolved, and an inorganic filler-dispersed resin material solution containing an inorganic filler dispersed in the resin material solution. Methods for applying the coating liquid to the surface of the substrate include spin coating, bar coating, knife coating, roll coating, blade coating, die coating, gravure coating, and dip coating.

The electrodeposition method is a method in which a metal substrate 20 is immersed in an electrodeposition liquid containing insulating resin particles and an inorganic filler, the insulating resin particles and the inorganic filler are electrodeposited onto the surface of the substrate to form an electrodeposition film, and the resulting electrodeposition film is then heated to form an insulating layer 30. The electrodeposition liquid can be prepared by adding a poor solvent for the insulating resin material to an inorganic filler-dispersed insulating resin solution containing an insulating resin solution and an inorganic filler dispersed in the insulating resin solution, thereby precipitating the insulating resin as particles.

In the circuit layer compression step, a metal foil is laminated on the insulating layer 30 of the metal substrate with an insulating layer, and the resulting laminate is heated and pressurized to form the circuit layer 40, thereby obtaining the metal base substrate 10. The heating temperature of the laminate is, for example, 200°C or higher, and more preferably 250°C or higher. The upper limit of the heating temperature is less than the thermal decomposition temperature of the insulating resin, and is preferably a temperature 30°C lower than the heat decomposition temperature. The pressure applied during compression is, for example, in the range of 1 MPa to 30 MPa, and more preferably in the range of 3 MPa to 25 MPa. The compression time varies depending on the heating temperature and pressure, but is generally 60 minutes to 180 minutes.

According to the metal base substrate 10 of the present embodiment configured as described above, the value of E calculated by the above formula (1) has a high correlation with the von Mises stress applied to the solder during a thermal cycle when the electronic component 60 is mounted on the metal base substrate 10 using the solder 50, and since the value of E is 3.10×10 ⁸ or less, the von Mises stress applied to the solder 50 generated when the thermal cycle is applied is small. In addition, since it is not necessary to excessively reduce the elastic modulus of the insulating layer 30, the restraining force of the circuit layer 40 by the insulating layer 30 is not reduced. Therefore, the metal base substrate 10 of the present embodiment has excellent reliability against thermal cycles when the electronic component 60 is mounted.

In the metal base substrate 10 of this embodiment, when the ratio (thickness/elastic modulus) of the thickness (unit: μm) to the elastic modulus (unit: GPa) at 100°C of the insulating layer 30 is large, such as 10 or more, the insulating layer 30 becomes easily deformed, and the insulating layer 30 easily alleviates the difference in the thermal expansion coefficient between the metal substrate 20 and the electronic component 60 due to the thermal cycle. Therefore, the reliability of this metal base substrate 10 against the thermal cycle when the electronic component 60 is mounted is further improved. In addition, in the metal base substrate 10 of this embodiment, when the insulating layer 30 is configured as a laminate of two or more layers each having a different elastic modulus at 100°C, it is possible to improve both the withstand voltage and the reliability while suppressing the thermal resistance to a low level by dividing the insulating layer 30 into an insulating layer having a high withstand voltage and an insulating layer having a high flexibility.

The above describes an embodiment of the present invention, but the present invention is not limited to this and can be modified as appropriate without departing from the technical concept of the invention.

[Inventive Examples 1 to 88, Comparative Examples 1 to 9]
A metal base substrate was assumed in which the thickness of the metal substrate, the elastic modulus at 100°C, the thermal expansion coefficient at 100°C, the thickness of the insulating layer, the elastic modulus at 100°C, and the thickness of the circuit layer, the elastic modulus at 100°C, were the values shown in Tables 1 to 4 below. E in the above formula (1) was calculated for the assumed metal base substrate. The results are shown in Tables 1 to 4.

A simulation value of the Mises stress applied to the solder when an electronic component is mounted on a hypothetical metal base substrate via solder was calculated. Schematic diagrams of the joint structure used to calculate the simulation value of the Mises stress are shown in Figures 2 and 3. Figure 2 is a cross-sectional view of the joint structure, and Figure 3 is a plan view of the joint structure shown in Figure 2. As shown in Figures 2 and 3, the joint structure 1S includes a metal base substrate 10S and an electronic component 60S joined to a corner of the metal base substrate 10S. The metal base substrate 10S is a laminate in which a metal substrate 20S, an insulating layer 30S, and a copper foil 40S are laminated in this order. The copper foil 40S is formed on the entire insulating layer 30S. The electronic component 60S includes an AIN (aluminum nitride) member 62S and a terminal S61. The electronic component 60S is an LED chip. The electronic component 60S and the copper foil 40S of the metal base substrate 10S are connected via solder 50S. The simulated value of the von Mises stress applied to the solder 50S of this joint structure 1S was calculated. The simulated value of the von Mises stress was calculated using LISA (Sonnenhof Holdings). The properties of each member of the joint structure 1S are as follows. The following thermal expansion coefficients, elastic moduli, and Poisson's ratios are all values at 100°C. The results are shown in Tables 1 to 4.

(1) Metal substrate 20S
Copper substrate: Thermal expansion coefficient: 18 ppm, Elastic modulus: 117 GPa, Poisson's ratio: 0.343
Aluminum substrate: Thermal expansion coefficient: 24 ppm, Elastic modulus: 72 GPa, Poisson's ratio: 0.343
(2) Insulating layer 30S
Thermal expansion coefficient: 1.0×10 ⁻⁵ , Poisson's ratio: 0.343
(3) Copper foil 40S
Thermal expansion coefficient: 1.8×10 ⁻⁵ , Poisson's ratio: 0.343
(4) Solder 50S
Thermal expansion coefficient: 2.0×10 ⁻⁵ , Poisson's ratio: 0.38, elastic modulus: 30 GPa
(5) AIN (aluminum nitride) member 62S
Thermal expansion coefficient: 0.3×10 ⁻⁵ , Poisson's ratio: 0.3, elastic modulus: 170 GPa
(6) Joint member 70S (LED chip)
Thermal expansion coefficient: 0.7×10 ⁻⁵ , Poisson's ratio: 0.25, elastic modulus: 470 GPa

The relationship between the E value and the simulated value of the von Mises stress is shown in Figure 4. In Figure 4, the horizontal axis represents the E value, and the vertical axis represents the simulated value of the von Mises stress. The regression line between the E value and the simulated value of the von Mises stress is y = 0.9998x, and the coefficient of determination (R2) is 0.9927. This result shows that the E value and the simulated value of the von Mises stress show a high correlation and reproducibility.

[Example 3]
(Preparation of alumina particle-dispersed polyimide solution)
A polyimide resin having an elastic modulus of 1 GPa was mixed with NMP (N-methyl-2-pyrrolidone) and the polyimide resin was dissolved to prepare a polyimide resin solution having a polyimide resin concentration of 10% by mass. An α-alumina particle dispersion having an α-alumina particle concentration of 10% by mass was prepared by mixing alumina powder (average particle size: 0.3 μm) with NMP and subjecting the mixture to ultrasonic treatment for 30 minutes. The polyimide resin solution and the alumina particle dispersion were mixed in a ratio such that the alumina concentration was 70% by volume. The mixture obtained was subjected to a dispersion treatment by repeating a high-pressure injection treatment at a pressure of 50 MPa 10 times using a Starburst manufactured by Sugino Machine Co., Ltd., to prepare an alumina particle-dispersed polyimide resin solution. The alumina concentration is the content of alumina particles in a solid material generated when the alumina particle-dispersed polyimide resin solution is heated and dried.

(Preparation of polyimide resin solution)
A polyimide resin having an elastic modulus of 0.27 GPa was mixed with NMP, and the polyimide resin was dissolved therein to prepare a polyimide resin solution having a polyimide resin concentration of 10 mass %.

(Preparation of Aluminum-Based Substrate)
An aluminum substrate (length: 30 mm, width: 20 mm, thickness: 1000 μm, elastic modulus: 72 GPa, thermal expansion coefficient: 18 ppm) was prepared as the metal substrate. The above-prepared alumina particle-dispersed polyimide resin solution was applied onto the aluminum substrate by a bar coating method to form a coating film. The aluminum substrate on which the coating film was formed was then placed on a hot plate, heated from room temperature to 60° C. at 3° C./min, heated at 60° C. for 100 minutes, and then further heated to 120° C. at 1° C./min, and heated at 120° C. for 100 minutes to dry the coating layer. The aluminum substrate was then heated at 250° C. for 1 minute, and then heated at 400° C. for 1 minute. Thus, a first insulating layer (thickness: 20 μm, elastic modulus: 20 GPa) made of polyimide resin in which alumina particles were dispersed was formed on the surface of the aluminum substrate, and an aluminum substrate with a first insulating layer was obtained.

Next, the polyimide resin solution prepared above was applied by bar coating onto the first insulating layer of the aluminum substrate with the first insulating layer to form a coating film. The coating film thus formed was heated and dried at 300°C to form a second insulating layer (thickness: 29 μm, elastic modulus: 0.27 GPa) made of polyimide resin. In this way, an aluminum base substrate with an insulating layer consisting of a first insulating layer and a second insulating layer was obtained.

Copper foil (thickness: 140 μm, elastic modulus: 125 GPa) was layered as a circuit layer on top of the second insulating layer of the obtained aluminum substrate with insulating layer. The obtained laminate was then heated in a vacuum at a bonding temperature of 300°C for 120 minutes while applying a pressure of 5 MPa using a carbon jig, thereby bonding the second insulating layer and the copper foil. In this way, an aluminum base substrate was produced in which the aluminum substrate, insulating layer, and copper foil were layered in this order.

[Example 25 of the present invention]
(Preparation of alumina particle-dispersed epoxy solution)
An epoxy resin having an elastic modulus of 1 GPa and alumina powder (average particle size: 0.18 μm) were mixed in a ratio such that the alumina concentration was 50 volume %, and the mixture was kneaded in a kneader (ARE-501: manufactured by THINKY Corporation) to prepare an alumina particle-dispersed epoxy resin composition.

(Preparation of Aluminum-Based Substrate)
An aluminum base substrate was produced in the same manner as in Example 3 of the present invention, except that the thickness of the aluminum substrate was set to 1600 μm, the alumina particle-dispersed epoxy resin composition prepared above was applied onto this aluminum substrate using a bar coater, and the resulting coating film was dried by heating to form only one insulating layer (thickness: 110 μm, elastic modulus: 8 GPa), and a copper foil having a thickness of 140 μm and an elastic modulus of 75 GPa was used as the circuit layer.

[Example 38 of the present invention]
A copper-based substrate was produced in the same manner as in Example 3 of the present invention, except that a copper substrate having a thickness of 1000 μm, an elastic modulus of 117 GPa, and a thermal expansion coefficient of 18 ppm was used as the metal substrate, an NMP solution of a polyimide resin having an elastic modulus of 0.27 GPa was applied onto this copper substrate using a bar coater, and the resulting coating film was dried by heating to form only one insulating layer (thickness: 30 μm, elastic modulus: 0.27 GPa), and a copper foil having a thickness of 140 μm and an elastic modulus of 75 GPa was used as the circuit layer.

[Example 47]
A copper-based substrate was prepared in the same manner as in Inventive Example 38, except that the thickness of the copper substrate was 1400 μm.

[Example 53 of the present invention]
A copper-based substrate was produced in the same manner as in Example 38 of the present invention, except that a copper foil having a thickness of 35 μm and an elastic modulus of 100 GPa was used as the circuit layer.

[Example 54 of the present invention]
A copper-based substrate was prepared in the same manner as in Example 3 of the present invention, except that a copper substrate having a thickness of 1000 μm, an elastic modulus of 117 GPa, and a thermal expansion coefficient of 18 ppm was used as the metal substrate, and a copper foil having a thickness of 35 μm and an elastic modulus of 125 GPa was used as the circuit layer.

[Example 60 of the present invention]
A copper-based substrate was prepared in the same manner as in Example 54 of the present invention, except that only one insulating layer (thickness: 110 μm, elastic modulus: 8 GPa) was formed on the copper substrate in the same manner as in Example 25 of the present invention.

[Example 79 of the present invention]
A copper-based substrate was produced in the same manner as in Example 60 of the present invention, except that the thickness of the copper substrate was 1800 μm and the thickness of the copper foil was 140 μm.

[Comparative Example 4]
An aluminum base substrate was produced in the same manner as in Inventive Example 60, except that an aluminum substrate having a thickness of 1600 μm, an elastic modulus of 72 GPa, and a thermal expansion coefficient of 24 ppm was used as the metal substrate.

[evaluation]
The reliability against thermal cycles was measured by the following method for the metal base substrates produced in Inventive Examples 3, 25, 38, 47, 53, 54, 60, and 79 and Comparative Example 4. The results are shown in Table 5 below.

A Sn-Ag-Cu solder was applied to the copper foil of a metal base substrate to form a solder layer measuring 2.5 cm long x 2.5 cm wide x 100 μm thick, and a 2.5 cm square Si chip was mounted on the solder layer to prepare a test specimen. The test specimen was subjected to 3000 cycles of cold-heat cycles, with one cycle being -40°C x 30 minutes to 150°C x 30 minutes. The test specimen after the cold-heat cycles was filled with resin, and the cross section exposed by polishing was observed to measure the length (mm) of the cracks that occurred in the solder layer. The value calculated from the length of one side of the solder layer and the measured crack length using the following formula was taken as reliability.
Reliability (%) = {(length of one side of solder layer (25 mm) - 2 x crack length) / length of one side of bonding layer (25 mm)} x 100

It can be seen that the metal base substrates of Examples 3, 25, 38, 47, 53, 54, 60, and 79 of the present invention, in which the E value calculated by the above formula (1) is 3.10×10 ⁸ or less, have improved reliability against thermal cycles compared to the metal base substrate of Comparative Example ^4. This is because the elastic modulus of the insulating layer at 100° C., the elastic modulus of the copper foil (circuit layer) at 100° C., the elastic modulus of the metal substrate at 100° C., the thickness of the insulating layer, the thickness of the copper foil, the thickness of the metal substrate, and the thermal expansion coefficient of the metal substrate at 100° C. are set so that the E value is 3.10×10 ⁸ or less, thereby reducing the stress applied from the metal base substrate to the solder by the thermal cycle. It can also be seen that the metal base substrates of Examples 3, 38, 47, 53, 54, and 60 of the present invention, in which the E value is 2.30×10 8 or less, have significantly improved reliability against thermal cycles.

1S Bonded structure 10 Metal base substrate 10S Metal base substrate 20 Metal substrate 20S Metal substrate 30, 30S Insulating layer 31 Insulating resin 32 Inorganic filler 40 Circuit layer 40S Copper foil 50, 50S Solder 60, 60S Electronic component 61, 61S Electrode terminal 62S AIN (aluminum nitride) member

Claims (3)

A metal base substrate in which a metal substrate, at least one insulating layer, and a circuit layer are laminated in this order,
The insulating layer includes an insulating resin and an inorganic filler,
The inorganic filler has an average particle size in the range of 0.1 μm or more and 20 μm or less,
A metal base substrate, in which E defined by the following formula (1) is 3.10×10 ⁸ or less.

In the formula (1), S represents a number calculated by the following formula (2):

In the formula (2), f ₀ is 3.14, f ₁ is −3.25, R ₀ is a value calculated from the following formula (3-0), and R ₁ is a value calculated from the following formula (3-1):

In the formulas (3-0) and (3-1), d ₀ is −0.423, d ₁ is −2.03, d ₂ is 0.804, e ₀ is 5.23, e _{1 is 4.30, and e 2 is} −4.40; Q ₀ represents a value calculated from the following formula (4-0); Q ₁ represents a value calculated from the following formula (4-1); and Q ₂ represents a value calculated from the following formula (4-2);

In the formulas (4-0), (4-1) and (4-2), a ₀ is 7.53, a ₁ is 3.09, a ₂ is 0.308, a ₃ is −0.137, a ₄ is 0.0342, a ₅ is 0.451, b ₀ is 0.839, b ₁ is −0.127, b ₂ is 0.0380, b 3 is −2.78, b ₄ is −0.828, b ₅ is −0.762, c ₀ is −3.64, c ₁ is 6.98, c ₂ is _0.319 , c ₃ is −0.451, c ₄ is −0.776, c ₅ is 0.189, and P _{P 0} represents a value calculated by the following formula (5-0), P ₁ represents a value calculated by the following formula (5-1), P ₂ represents a value calculated by the following formula (5-2), P ₃ represents a value calculated by the following formula (5-3), P ₄ represents a value calculated by the following formula (5-4), and P ₅ represents a value calculated by the following formula (5-5),

In the formulas (5-0), (5-1), (5-2), (5-3), (5-4), and (5-5), K _resin represents the elastic modulus (unit: GPa) of the insulating layer at 100° C., K _electrode represents the elastic modulus (unit: GPa) of the circuit layer at 100° C., K _base represents the elastic modulus (unit: GPa) of the metal substrate at 100° C., T _resin represents the thickness (unit: μm) of the insulating layer, T _electrode represents the thickness (unit: μm) of the circuit layer, T _base represents the thickness (unit: μm) of the metal substrate, and CTE _base represents the thermal expansion coefficient (unit: ppm) of the metal substrate at 100° C. The metal base substrate according to claim 1, wherein the insulating layer has a ratio of thickness (unit: μm) to modulus of elasticity (unit: GPa) at 100°C of 10 or more. The metal base substrate according to claim 1 or 2, wherein the insulating layer is a laminate of two or more layers each having a different elastic modulus at 100°C.

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