JP7636716B2 - Infrared LED element and manufacturing method thereof - Google Patents

Description

The present invention relates to an infrared LED element, and in particular to an infrared LED element having an emission wavelength of 1000 nm or more. The present invention also relates to a method for manufacturing such an infrared LED element.

In recent years, semiconductor light-emitting elements that emit light in the infrared region with wavelengths of 1000 nm or more have been widely used in security and surveillance cameras, gas detectors, medical sensors, industrial equipment, and other applications.

Semiconductor light-emitting elements with an emission wavelength of 1000 nm or more have generally been manufactured using the following procedure (see Patent Document 1 below). That is, on an InP substrate used as a growth substrate, a first conductivity type semiconductor layer that is lattice-matched to the InP substrate, an active layer (sometimes called an "emitting layer"), and a second conductivity type semiconductor layer are epitaxially grown in that order. After that, electrodes for current injection are formed on the semiconductor wafer, and the wafer is cut into chips for manufacture.

Traditionally, semiconductor laser elements have been the leading semiconductor light-emitting element with an emission wavelength of 1000 nm or more in terms of development. On the other hand, LED elements have not been developed as much as laser elements, partly because there have not been many applications for them.

However, in recent years, with the expansion of applications, there has been a demand for improved light output for infrared LED elements as well. InP substrates, like GaAs substrates used in the visible light region, have a high refractive index of 3 or more. For this reason, when attempting to extract light through an InP substrate, total reflection occurs due to the difference in refractive index at the interface with air, limiting the light extraction efficiency. Furthermore, since InP substrates have high thermal resistance, the light output is likely to become saturated when driven with a large current. For these reasons, the structure disclosed in Patent Document 1 was not suitable for realizing an LED element that obtains high light output.

As a method for obtaining a higher optical output than the structure disclosed in Patent Document 1, for example, the structure disclosed in Patent Document 2 can be adopted. That is, a structure realized by bonding a growth substrate on which an epitaxial layer is formed to a conductive support substrate that exhibits high heat dissipation properties and then removing the growth substrate is considered to be effective. However, the light-emitting element described in Patent Document 2 targets a wavelength that is lower than 1000 nm.

Japanese Patent Application Publication No. 4-282875 JP 2012-129357 A

To increase the light-emitting efficiency of an LED element, it is important to spread the current flowing in the active layer in the surface direction of the substrate. This is because if the current concentrates in a specific location in the active layer, the brightness will vary between the location where the current is concentrated and other locations in the active layer, reducing the amount of light extracted from the entire light extraction surface. Another problem is that if the temperature in the location where the current is concentrated becomes too high, the element will be more susceptible to deterioration.

In order to diffuse the current flowing in the active layer in the surface direction of the substrate, it is important to precisely adjust the electrode formation position during manufacturing. In this specification, an LED element that emits light by placing one electrode above the active layer and the other electrode below the active layer and passing a current in the active layer in a direction perpendicular to the surface of the substrate is called a "vertical element." In such a vertical element, when the one electrode and the other electrode are positioned so as to face each other in a direction perpendicular to the surface of the substrate, when a voltage is applied between the two electrodes, the current tends to concentrate and flow in the area of the active layer where the two electrodes face each other. In order to avoid such a phenomenon, it is preferable to place the one electrode and the other electrode so that they do not face each other in the direction perpendicular to the surface of the substrate.

When manufacturing such a vertical element, a process of forming the other electrode is performed after aligning a wafer on which a semiconductor laminate including an active layer and one of the electrodes have already been formed. Specifically, the process is performed as follows.

First, the position of one of the electrodes (hereinafter referred to as the "internal electrode") formed in the lower layer of the semiconductor laminate is detected by penetrating the semiconductor laminate from above the wafer, and based on this detected position, the planned position for forming the other electrode (hereinafter referred to as the "upper electrode") is defined. Then, the upper electrode is formed at the defined position using photolithography.

However, when detecting the position of the internal electrode using the above-mentioned method, if the emission wavelength of the target light-emitting element is 1000 nm or longer, the following problem becomes apparent.

The light-emitting element has an active layer that emits light. This active layer absorbs most of the light with a higher energy wavelength than the emission wavelength, that is, the light with a shorter wavelength than the emission wavelength. Therefore, when manufacturing infrared LED elements with an emission wavelength of 1000 nm or more, it is not possible to adopt a method of detecting the position of the internal electrode with the human eye using visible light. In addition, even if a CCD sensor or CMOS sensor made of a Si-based material, which is a widely used image recognition device, is used, it is difficult to recognize light with a wavelength of 1000 nm or more. In other words, even if a light source (e.g., a halogen lamp) that shows a continuous emission spectrum in the wavelength range of 1000 nm or more is used to irradiate the light-emitting element with light, the CCD sensor or CMOS sensor cannot recognize the reflected light and cannot detect the formation position of the internal electrode.

In recent years, InGaAs-based image sensors have been developed that can also receive infrared light with long wavelengths around 2000 nm. Therefore, in principle, it is possible to detect the formation position of the internal electrode by irradiating the light from the halogen lamp described above onto the light-emitting element, receiving the reflected light with an InGaAs-based sensor, and analyzing the obtained information through image analysis. However, since the light from the halogen lamp shows a broad spectrum, light with a shorter wavelength than the emission wavelength is absorbed in the active layer, resulting in an insufficient amount of reflected light received by the InGaAs-based sensor, and the sensitivity is low. As a result, even if an InGaAs-based sensor is used, the edge of the internal electrode cannot be clearly recognized, and it is difficult to align the electrode with high precision.

If the alignment accuracy is low, it is necessary to increase the spacing between the internal electrodes in the surface direction in order to prevent the internal electrodes and the upper electrode from facing each other in a direction perpendicular to the surface direction of the substrate. As a result, the number of electrodes provided in an LED element of the same size decreases, and the amount of current that can be injected decreases. In other words, it becomes difficult to realize a small, high-brightness infrared LED element.

In view of the above problems, the present invention aims to provide an infrared LED element with an emission wavelength of 1000 nm or more that enables precise alignment of the internal electrode and the upper electrode. The present invention also aims to realize an infrared LED element with improved light emission efficiency by spreading the current flowing in the active layer in the planar direction through such alignment.

The infrared LED element according to the present invention is
A conductive supporting substrate;
an insulating layer formed on the support substrate;
a semiconductor laminate including a first semiconductor layer of p-type or n-type formed on the insulating layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a different conductivity type from the first semiconductor layer formed on the active layer;
an upper electrode formed on the upper layer of the semiconductor laminate;
internal electrodes penetrating the insulating layer at a plurality of positions distributed in a direction parallel to a main surface of the support substrate and electrically connecting the first semiconductor layer and the support substrate;
The thickness T [nm] of the active layer and the peak emission wavelength λ [nm] of the infrared LED element satisfy the relationship of the following formula (1).
T ≦ -3.5×λ + 6375…(1)
However, in formula (1), λ satisfies 1550≦λ≦1800.

In this specification, the "principal surface" of a component such as a substrate refers to the surface among the multiple surfaces that make up each component that is much larger in area than the other surfaces. Furthermore, "rectangular" includes shapes that have an approximately quadrangular overall appearance, in addition to rectangles and squares. An approximately quadrangular overall appearance is a concept that includes, for example, a quadrangular shape with slightly rounded vertices, shapes with minute irregularities on the sides, and shapes in which adjacent sides are inclined at an angle within the range of 90°±5°.

In this specification, the term "peak emission wavelength" refers to the wavelength at which the light intensity is the highest on the emission spectrum.

The inventors' intensive research has revealed that when an infrared LED element has an active layer with a thickness T that satisfies the relationship of formula (1) above, it is possible to align the internal electrode and the upper electrode with a high accuracy of 5 μm or less when an image sensor such as an InGaAs-based sensor with sensitivity up to wavelengths of around 2000 nm is used to capture the image. Details are given later in the section "Form for carrying out the invention."

If the thickness T of the active layer is too thin, the probability that electrons and holes will overflow without recombining within the active layer increases. To prevent this phenomenon, the active layer is preferably 20 nm or more, and more preferably 150 nm or more.

Preferably, the upper electrode is disposed in a position that does not face the internal electrode in a direction perpendicular to the main surface of the support substrate.

As a result, while a voltage is applied between the upper electrode and the internal electrode, the current flowing through the active layer can be expanded in a direction parallel to the main surface of the support substrate. As a result, an infrared LED element with high light emission efficiency is realized.

It is preferable that the variation in the distance between the upper electrode closest to the internal electrode and the internal electrode is 10 μm or less when viewed from a direction perpendicular to the main surface of the support substrate.

This variation in the distance is defined as follows: When an infrared LED element has a single upper electrode, the distance between each internal electrode and the upper electrode is measured when the light-emitting element is viewed in a direction perpendicular to the main surface of the supporting substrate, and the absolute value of the difference between the maximum and minimum values is calculated to determine the value of the variation.

On the other hand, when an infrared LED element has multiple upper electrodes, the value of the variation is calculated as follows. First, one upper electrode is identified (hereinafter referred to as "upper electrode α1"). Next, when the light-emitting element is viewed from a direction perpendicular to the main surface of the support substrate, the internal electrode that is closest to the upper electrode α1 is identified from among the multiple internal electrodes. There are usually multiple such internal electrodes, and hereinafter they are referred to as "internal electrode group β (α1)."

Then, when the light-emitting element is viewed from a direction perpendicular to the main surface of the support substrate, the distance between each internal electrode belonging to the internal electrode group β (α1) and the upper electrode α1 is measured, and the absolute value of the difference between the maximum and minimum values is calculated to obtain the variation Vr (α1).

By performing the same process on the other upper electrodes (α2, α3, ..., αn) (n is a natural number of 2 or more), the variations Vr(α2), Vr(α3), ..., Vr(αn) are obtained. The average value of these variations Vr(αi) (1 ≦ i ≦ n) is regarded as the value of the variation.

the second semiconductor layer is InP;
The active layer may comprise one or more materials from the group consisting of GaInAsP, AlGaInAs, and InGaAs.

Since InP has a higher band gap energy than GaInAsP, AlGaInAs, and InGaAs, it transmits light with shorter wavelengths than these materials. In other words, when an image is taken from the upper electrode side using an image sensor, light absorption in the second semiconductor layer located above the active layer is almost not a problem. In addition, by forming the active layer with the above-mentioned materials, an infrared LED element with an emission wavelength of 1000 nm or more is realized. In this case, by forming the active layer with a film thickness T that satisfies the above formula (1) according to the peak emission wavelength λ, light absorption in the active layer is suppressed, and an infrared LED element with high light emission efficiency in which the internal electrode and the upper electrode are precisely aligned is realized.

The infrared LED element may have a peak emission wavelength λ of 1000≦λ<1550 and a thickness T of the active layer of 1000 nm or less.

In addition, a method for manufacturing an infrared LED element according to the present invention includes the steps of:
(a) providing a growth substrate;
(b) forming the second semiconductor layer on the growth substrate;
a step (c) of forming the active layer made of a material having a peak emission wavelength λ [nm] on the second semiconductor layer to a thickness T [nm] that satisfies the formula (1);
(d) forming the first semiconductor layer and the insulating layer on the active layer;
(e) forming the internal electrodes inside the insulating layer;
a step (f) of bonding the support substrate to the upper layer of the insulating layer;
(g) peeling off the growth substrate to expose the second semiconductor layer;
(h) forming a photoresist on the second semiconductor layer, and then aligning and positioning a photomask patterned according to the shape of the upper electrode using an image sensor based on the position of the internal electrode;
(i) forming a material film for the upper electrode after exposing the material film through the photomask;
and (j) removing the photoresist.

According to the above method, the thickness T [nm] of the active layer formed during the execution of step (h) is set so that the relationship with the peak emission wavelength λ [nm] of the active layer satisfies the above formula (1). Therefore, when an image is captured by an image sensor while irradiating broad light that shows a light intensity in a wavelength range of 1000 nm or more, light absorption is suppressed in the active layer, so that the image sensor can receive a sufficient amount of light to accurately detect the formation position of the internal electrode. As a result, since the photomask can be aligned accurately in step (h), the upper electrode remaining after the execution of step (j) can be formed in a position with little overlap with the internal electrode in the direction perpendicular to the surface of the support substrate. Therefore, the current flowing in the active layer during energization can be spread in a direction parallel to the surface of the support substrate, and an infrared LED element with high light emission efficiency can be obtained.

The step (b) is a step of forming a film made of InP,
The step (c) may be a step of depositing a film containing one or more materials belonging to the group consisting of GaInAsP, AlGaInAs, and InGaAs.

According to the present invention, it is possible to precisely align the internal electrode and the upper electrode even when the emission wavelength is 1000 nm or more, and as a result, an infrared LED element is provided that spreads the current flowing in the active layer in the planar direction and exhibits high emission efficiency.

1 is a cross-sectional view showing a schematic configuration of an embodiment of an infrared LED element of the present invention. 2 is a schematic plan view of the infrared LED element shown in FIG. 1 when viewed in the −Y direction. 2A to 2C are schematic cross-sectional views for explaining a manufacturing method of the LED element shown in FIG. 1 in one step. 1. FIG. 4 is a schematic cross-sectional view for illustrating another step of the method for manufacturing the LED element shown in FIG. 5 is an enlarged view of the drawing range of FIG. 4. FIG. 2 is a schematic plan view of an epitaxial wafer on which alignment marks are formed. 1. FIG. 4 is a schematic cross-sectional view for illustrating another step of the method for manufacturing the LED element shown in FIG. 1. FIG. 4 is a schematic cross-sectional view for illustrating another step of the method for manufacturing the LED element shown in FIG. 1. FIG. 4 is a schematic cross-sectional view for illustrating another step of the method for manufacturing the LED element shown in FIG. 1. FIG. 4 is a schematic cross-sectional view for illustrating another step of the method for manufacturing the LED element shown in FIG. 2 is a schematic cross-sectional view illustrating a step S7 of the manufacturing method of the LED element shown in FIG. 1. FIG. 1. FIG. 4 is a schematic cross-sectional view illustrating another process for explaining step S7 of the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a schematic cross-sectional view illustrating another process for explaining step S7 of the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a schematic cross-sectional view illustrating another process for explaining step S7 of the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a schematic cross-sectional view illustrating another process for explaining step S7 of the manufacturing method of the LED element shown in FIG. 1 is a graph showing the results of verification 1, and is a graph showing the relationship between the peak emission wavelength and the maximum thickness of the active layer in which the internal electrode could be detected with high accuracy. 11 is a diagram for explaining a separation distance Ws between an upper electrode and an internal electrode. 1 is a graph showing the current-light output characteristics of the infrared LED elements of Sample #1 and Sample #2. 1 is a graph showing the current-forward voltage characteristics of the infrared LED elements of Sample #1 and Sample #2.

Embodiments of an infrared LED element and a manufacturing method thereof according to the present invention will be described with reference to the drawings. The following drawings are schematic illustrations, and the dimensional ratios in the drawings do not necessarily match the actual dimensional ratios. Furthermore, the dimensional ratios may not match between the drawings.

In this specification, the expression "layer Q2 is formed on layer Q1" is intended to include the case where layer Q2 is formed directly on the surface of layer Q1, as well as the case where layer Q2 is formed on the surface of layer Q1 via a thin film. Note that "thin film" here refers to a layer with a thickness of 20 nm or less, and preferably refers to a layer with a thickness of 10 nm or less.

In this specification, the term "GaInAsP" means a mixed crystal of Ga, In, As, and P, and is a description that simply omits the description of the composition ratio. The same applies to other descriptions such as "AlGaInAs."

Figure 1 is a cross-sectional view showing a schematic structure of an infrared LED element of this embodiment. The infrared LED element 1 shown in Figure 1 has a semiconductor laminate 20 formed on the upper layer of a support substrate 11. The infrared LED element 1 shown in Figure 1 corresponds to a schematic cross-sectional view when cut along the XY plane at a specified position. In the following description, the XYZ coordinate system shown in Figure 1 will be referred to as appropriate.

In the following description, when a positive or negative direction needs to be distinguished, the direction is described with a positive or negative sign, such as "+X direction" and "-X direction". When a direction is described without distinguishing between positive and negative directions, it is simply described as "X direction". In other words, in this specification, when simply describing the "X direction", both the "+X direction" and the "-X direction" are included. The same applies to the Y direction and the Z direction. In the following example, it is described that the main surface of the support substrate 11 is parallel to the XZ plane, and light is extracted in the normal direction (Y direction).

In the infrared LED element 1 of this embodiment, infrared light L is generated in the semiconductor laminate 20 (more specifically, in the active layer 25 described below). More specifically, as shown in FIG. 1, infrared light L (L1, L2) is extracted in the +Y direction when the active layer 25 is used as a reference. The infrared light L has a peak wavelength of 1000 nm or more.

[Element structure]
The structure of the infrared LED element 1 will now be described in detail.

(Support substrate 11)
The support substrate 11 is made of, for example, a semiconductor such as Si or Ge, or a metal material such as Cu or CuW. When the support substrate 11 is made of a semiconductor, it may be doped with a high concentration of a dopant so as to exhibit electrical conductivity. As an example, the support substrate 11 is a Si substrate doped with boron (B) at a dopant concentration of 1×10 ¹⁹ /cm ³ or more and having a resistivity of 10 mΩcm or less. As the dopant, for example, phosphorus (P), arsenic (As), antimony (Sb), etc. can be used other than boron (B). From the viewpoint of achieving both high heat dissipation and low manufacturing cost, a Si substrate is preferably used for the support substrate 11.

The thickness of the support substrate 11 (length in the Y direction) is not particularly limited, but is, for example, 50 μm to 500 μm, and preferably 100 μm to 300 μm.

(Bonding layer 13)
The infrared LED element 1 shown in Fig. 1 includes a bonding layer 13 formed on the upper layer of a support substrate 11. The bonding layer 13 is made of a low melting point solder material, such as Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn, or the like. As will be described later with reference to Fig. 9, this bonding layer 13 is used to bond the growth substrate 3 having the semiconductor laminate 20 formed on the upper surface thereof to the support substrate 11. The thickness of the bonding layer 13 is not particularly limited, but is, for example, 0.5 µm to 5.0 µm, and preferably 1.0 µm to 3.0 µm.

(Reflective layer 15)
The infrared LED element 1 shown in Fig. 1 includes a reflective layer 15 formed on the bonding layer 13. The reflective layer 15 has a function of reflecting infrared light L2, which is generated in the active layer 25 and travels toward the support substrate 11 (-Y direction), and guiding it in the +Y direction. The reflective layer 15 is made of a conductive material that exhibits high reflectance to the infrared light L. The reflectance of the reflective layer 15 to the infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm to 2000 nm, the reflective layer 15 can be made of a metal material such as Ag, an Ag alloy, Au, Al, or Cu. The material constituting the reflective layer 15 is appropriately selected according to the wavelength of the light generated in the active layer 25.

The thickness of the reflective layer 15 is not particularly limited, but is, for example, 0.1 μm to 2.0 μm or less, and preferably 0.3 μm to 1.0 μm or less.

Although not shown in FIG. 1, a barrier layer for suppressing diffusion of the solder material constituting the bonding layer 13 may be provided between the reflective layer 15 and the bonding layer 13. The material of the barrier layer may be, for example, a material containing Ti, Pt, W, Mo, Ni, etc. As an example, it is composed of a Ti/Pt/Au laminate. The thickness of the barrier layer is not particularly limited, but is, for example, 0.05 μm to 3 μm or less, and preferably 0.2 μm to 1 μm or less. The presence of this barrier layer can prevent the material constituting the bonding layer 13 from diffusing to the reflective layer 15 side, which would cause a decrease in the reflectance of the reflective layer 15. The barrier layer may also be provided between the bonding layer 13 and the support substrate 11.

From the viewpoint of improving the light extraction efficiency, it is preferable that the infrared LED element 1 has a reflective layer 15 as shown in FIG. 1, but in the present invention, it is optional whether or not the infrared LED element 1 has a reflective layer 15.

(Insulating layer 17)
The infrared LED element 1 shown in Fig. 1 includes an insulating layer 17 formed on the reflective layer 15. The insulating layer 17 is made of a material that exhibits electrical insulation and has high transparency to infrared light L. The transmittance of the insulating layer 17 to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm to 2000 nm, materials such as SiO ₂ , SiN, and Al ₂ O ₃ can be used for the insulating layer 17. The material constituting the insulating layer 17 is appropriately selected depending on the wavelength of the light generated in the active layer 25.

(Semiconductor laminate 20)
The infrared LED element 1 shown in Fig. 1 has a semiconductor laminate 20 formed on an insulating layer 17. The semiconductor laminate 20 is a laminate of multiple semiconductor layers, and includes, for example, a contact layer 21, a first cladding layer 23, an active layer 25, and a second cladding layer 27. Each of the semiconductor layers (21, 23, 25, 27) constituting the semiconductor laminate 20 is made of a material that is lattice-matched with a growth substrate 3 described below and can be epitaxially grown.

<<Contact layer 21, first cladding layer 23>>
In this embodiment, the contact layer 21 is made of, for example, p-type GaInAsP. The thickness of the contact layer 21 is not limited, but is, for example, 10 nm to 1000 nm, and preferably 50 nm to 500 nm. The p-type dopant concentration of the contact layer 21 is preferably 5×10 ¹⁷ /cm ³ to 3×10 ¹⁹ /cm ³ , and more preferably 1×10 ¹⁸ /cm ³ to 2×10 ¹⁹ /cm ³ .

In this embodiment, the first cladding layer 23 is formed on the contact layer 21 and is made of, for example, p-type InP. The thickness of the first cladding layer 23 is not limited, but is, for example, 1000 nm to 10000 nm, and preferably 2000 nm to 5000 nm. The p-type dopant concentration of the first cladding layer 23 at a position away from the active layer 25 is preferably 1×10 ¹⁷ /cm ³ to 3×10 ¹⁸ /cm ³ or less, and more preferably 5×10 ¹⁷ /cm ³ to 3×10 ¹⁸ /cm ³ or less.

As the p-type dopant contained in the contact layer 21 and the first cladding layer 23, Zn, Mg, Be, etc. can be used, with Zn or Mg being preferred, and Zn being particularly preferred. In this embodiment, the contact layer 21 and the first cladding layer 23 correspond to the "first semiconductor layer."

<<Active Layer 25>>
In this embodiment, the active layer 25 is composed of a semiconductor layer formed on the first cladding layer 23. The active layer 25 is appropriately selected from materials capable of generating light of a target wavelength and capable of epitaxial growth in lattice matching with a growth substrate 3 described later with reference to FIG.

When it is desired to realize an infrared LED element 1 that emits infrared light L with a peak wavelength of 1000 nm to 2000 nm, the active layer 25 may be a single layer structure of GaInAsP, AlGaInAs, or InGaAs, or may be an MQW (Multiple Quantum Well) structure including a well layer made of GaInAsP, AlGaInAs, or InGaAs, and a barrier layer made of GaInAsP, AlGaInAs, InGaAs, or InP that has a larger band gap energy than the well layer.

The film thickness T [nm] of the active layer 25 is set so that the relationship with the peak emission wavelength λ satisfies the following formula (1) when the peak emission wavelength λ [nm] is 1550≦λ≦1800.
T ≦ -3.5×λ + 6375…(1)

When the peak emission wavelength λ is 1000≦λ<1550, the thickness T of the active layer 25 is 1000 nm or less. In order to reduce the probability of the occurrence of a phenomenon (overflow phenomenon) in which electrons and holes flow into adjacent layers without recombining in the active layer 25, it is preferable that the thickness T of the active layer 25 is 20 nm or more, and more preferably 150 nm or more, regardless of the peak emission wavelength λ.

As will be described later with reference to FIG. 11C, when manufacturing the infrared LED element 1, a process is performed in which an image is taken from above the second cladding layer 27 using an image sensor to detect the formation position of the internal electrode 31 on the XZ plane. By setting the film thickness of the active layer 25 according to the peak emission wavelength λ as described above, the amount of light used for imaging that is absorbed in the active layer 25 is reduced, making it possible to accurately recognize the formation position of the internal electrode 31.

The active layer 25 may be doped to n-type or p-type, or may be undoped. If it is doped to n-type, the dopant may be, for example, Si.

Second Cladding Layer 27
In this embodiment, the second cladding layer 27 is formed on the active layer 25 and is made of, for example, n-type InP. The thickness of the second cladding layer 27 is not limited, but is, for example, 100 nm to 10,000 nm, and preferably 500 nm to 5,000 nm. The n-type dopant concentration of the second cladding layer 27 is preferably 1×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ , and more preferably 5×10 ¹⁷ /cm ³ to 4×10 ¹⁸ /cm ^3. As the n-type impurity material doped in the second cladding layer 27, Sn, Si, S, Ge, Se, etc. can be used, and Si is particularly preferable. The second cladding layer 27 corresponds to the "second semiconductor layer".

In the example shown in FIG. 1, an uneven portion 27a is formed on the surface on the +Y side of the second cladding layer 27. By forming the uneven portion 27a, the amount of infrared light L (L1, L2) traveling in the +Y direction from the active layer 25 that is reflected toward the active layer 25 by the surface of the second cladding layer 27 is reduced, and the light extraction efficiency is improved. However, in the present invention, it is optional whether or not to provide the uneven portion 27a on the surface of the second cladding layer 27.

The first cladding layer 23 and the second cladding layer 27 are appropriately selected from materials that do not absorb the infrared light L generated in the active layer 25 and that can be epitaxially grown by lattice matching with the growth substrate 3 (see FIG. 3 described later). When an InP substrate is used as the growth substrate 3, the first cladding layer 23 and the second cladding layer 27 can be made of materials other than InP, such as GaInAsP and AlGaInAs.

However, as described above, when manufacturing the infrared LED element 1, a process is carried out in which an image sensor is used to capture an image from above the second cladding layer 27 to detect the formation position of the internal electrode 31 on the XZ plane. From this perspective, in order to suppress absorption of imaging light in the first cladding layer 23 and the second cladding layer 27, these layers are preferably formed from a material whose band gap energy is sufficiently higher than that of the active layer 25, and more preferably from InP.

In the above description, the first semiconductor layer (21, 23) is a p-type semiconductor and the second semiconductor layer 27 is an n-type semiconductor, but the conductivity types of the two may be reversed.

(Internal electrode 31)
1 has internal electrodes 31 formed in a plurality of locations within the insulating layer 17, penetrating the insulating layer 17 in the Y direction. The internal electrodes 31 electrically connect the first semiconductor layers (21, 23) to the supporting substrate 11. The internal electrodes 31 are provided at a plurality of locations dispersed in a direction parallel to the XZ plane (i.e., a direction parallel to the main surface of the supporting substrate 11).

The internal electrode 31 is made of a material capable of forming an ohmic connection with the contact layer 21. As an example, the internal electrode 31 is made of AuZn, AuBe, or a laminated structure containing at least Au and Zn (e.g., Au/Zn/Au, etc.). These materials have a lower reflectance for infrared light L than the material that constitutes the reflective layer 15.

In this embodiment, as shown in FIG. 2 described later, an example of a configuration in which the internal electrodes 31 are regularly aligned is shown, but the arrangement pattern of the internal electrodes 31 when viewed in the Y direction can adopt any shape. However, from the viewpoint of flowing a current uniformly over a wide range in the active layer 25 in the direction parallel to the main surface of the support substrate 11, it is preferable that the internal electrodes 31 are arranged in a dispersed state having a regular shape in the planar direction.

Figure 2 is an example of a schematic plan view of the infrared LED element 1 when viewed in the Y direction from above the second cladding layer 27. However, in order to understand the shape pattern of the internal electrode 31, Figure 2 also illustrates the internal electrode 31. Figure 2 will be described later in the explanation of the upper electrode 32. Figure 2 illustrates a case in which the semiconductor laminate 20 has a rectangular shape when viewed from above.

When the infrared LED element 1 is viewed in the Y direction, the total area of all the internal electrodes 31 is preferably 30% or less, more preferably 20% or less, and particularly preferably 15% or less, of the area in the planar direction of the semiconductor laminate 20 (e.g., the second cladding layer 27). If the total area of the internal electrodes 31 is relatively large, the infrared light L2 traveling from the active layer 25 toward the support substrate 11 (-Y direction) is absorbed by the internal electrodes 31, reducing the extraction efficiency. On the other hand, if the total area of the internal electrodes 31 is too small, the resistance value increases and the forward voltage rises.

(Upper electrode 32)
The infrared LED element 1 shown in FIG. 1 has an upper electrode 32 formed on the upper layer of the semiconductor laminate 20. The upper electrode 32 is typically formed so that multiple electrodes extend in a predetermined direction. In the example shown in FIG. 2, the upper electrodes 32 extend in the X and Z directions along the sides of the semiconductor laminate 20 to form a comb shape. The arrangement pattern shape of the upper electrodes 32 is arbitrary, and may be, for example, a lattice shape or a spiral shape. The upper electrode 32 is formed over a wide range on the XZ plane while exposing the surface of the second cladding layer 27 located in the lower layer. This allows the current flowing in the active layer 25 to be spread in a direction parallel to the XZ plane, and allows light to be emitted over a wide range in the active layer 25.

The upper electrode 32 is, for example, made of materials such as AuGe/Ni/Au or AuGe, and may be made of multiple of these materials.

As shown in FIG. 2, the upper electrodes 32 and the internal electrodes 31 are arranged so as not to overlap in the Y direction when viewed in the Y direction. More preferably, the distance Ws (see FIG. 13) between each internal electrode 31 and the nearest upper electrode 32 when viewed in the Y direction is designed to be substantially uniform for almost all internal electrodes 31. Typically, when viewed in the Y direction, for 80% or more of the internal electrodes 31, the variation in the distance between the nearest upper electrode 32 and the internal electrode 31 is 10 μm or less. It is more preferable that the variation in the distance is 10 μm or less for 90% or more of the internal electrodes 31, and more preferably that the variation in the distance is 10 μm or less for 95% or more of the internal electrodes 31.

When the upper electrode 32 and the internal electrode 31 overlap when the infrared LED element 1 is viewed in the Y direction, the current flows easily in the Y direction in that region, and the current is concentrated locally. As a result, it becomes difficult to pass the current over a wide area in the active layer 25 in the direction parallel to the XZ plane, and the brightness on the surface of the second cladding layer 27 varies, and the light emission efficiency decreases. Even if the upper electrode 32 and the internal electrode 31 do not overlap when the infrared LED element 1 is viewed in the Y direction, if the variation in the distance between the internal electrode 31 and the upper electrode 32 is large, a large difference in the amount of current flowing in the direction of the XZ plane occurs. As a result, a place where the current is concentrated locally is created, and the same phenomenon as above may occur. From this perspective, it is preferable to make the variation in the distance between the internal electrode 31 and the upper electrode 32 as small as possible when the infrared LED element 1 is viewed in the Y direction.

For this reason, it is important to precisely align the upper electrode 32 and the internal electrode 31 when manufacturing the infrared LED element 1. As will be described in more detail later in the explanation of the manufacturing method of the infrared LED element 1, the process of forming the upper electrode 32 is performed after the process of forming the internal electrode 31. In other words, when forming the upper electrode 32, a process of adjusting the planned formation position of the upper electrode 32 is required after recognizing the position where the internal electrode 31 is formed. In the case of the infrared LED element 1 of the present invention, the thickness T of the active layer 25 is designed according to the wavelength λ, so that it is possible to precisely detect the formation position of the internal electrode 31.

(Pad electrode 34)
2, the infrared LED element 1 has a pad electrode 34 formed on the upper surface of part of the upper electrode 32. The pad electrode 34 is made of, for example, Ti/Au or Ti/Pt/Au. This pad electrode 34 is provided for the purpose of securing an area for contacting a bonding wire for power supply, but in the present invention, it is optional whether or not to provide the pad electrode 34.

When each side (chip size) of the semiconductor laminate 20 is about 800 μm to 2500 μm, for example, the pad electrode 34 has a circular shape with an inner diameter of about 90 μm to 120 μm. The line width of the upper electrode 32 is about 10 μm to 30 μm. In a high-output infrared LED element 1 with a chip size exceeding 800 μm, it is preferable to provide the pad electrodes 34 in multiple locations, as shown in FIG. 2, in order to inject a high current.

(Rear electrode 33)
1 includes a back electrode 33 formed on the surface of the support substrate 11 opposite to the semiconductor laminate 20 (−Y side). The back electrode 33 is in ohmic contact with the support substrate 11. As an example, the back electrode 33 is made of a material such as Ti/Au or Ti/Pt/Au, and may include a plurality of these materials.

[Production method]
An example of a method for manufacturing the above-mentioned infrared LED element 1 will be described with reference to Figures 3 to 11E. Figures 3 to 5 and 7 to 11E are all cross-sectional views of a step in the manufacturing process. Figure 6 will be described later. The order of the following steps may be changed as appropriate as long as it does not affect the manufacture of the infrared LED element 1.

(Step S1)
3, a growth substrate 3 made of, for example, InP is transferred into a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and a second cladding layer 27, an active layer 25, a first cladding layer 23, and a contact layer 21 are epitaxially grown in sequence on the growth substrate 3 to form a semiconductor laminate 20. In this step S1, the type and flow rate of source gas, processing time, environmental temperature, etc. are appropriately adjusted according to the material and film thickness of the layer to be grown. Examples of materials for each semiconductor layer (21, 23, 25, 27) are as described above.

InP is preferably used as the growth substrate 3. However, when manufacturing an infrared LED element 1 with a peak emission wavelength of 1070 nm or less, GaAs may be used as the growth substrate 3.

In step S1, when the peak emission wavelength calculated from the material of the active layer 25 is λ [nm], and 1550≦λ ≦1800, the active layer 25 is formed to a thickness T [nm] that satisfies the above formula (1).
T ≦ -3.5×λ + 6375…(1)

When the peak emission wavelength λ is 1000 ≦ λ < 1550, the active layer 25 is deposited so that the film thickness T is 1000 nm or less. Regardless of the peak emission wavelength λ, the active layer 25 is preferably deposited to a thickness of 100 nm or more.

This step S1 corresponds to steps (a) to (c).

(Step S2)
The epitaxial wafer is removed from the MOCVD apparatus, and a resist mask patterned by photolithography is formed on the surface of the contact layer 21. Then, a material (e.g., AuZn) for forming the internal electrode 31 is deposited using a vacuum deposition apparatus, and the resist mask is peeled off by a lift-off method. Then, an alloying process (annealing process) is performed by heating at 450° C. for 10 minutes, for example, to realize ohmic contact between the contact layer 21 and the internal electrode 31.

Next, the insulating layer 17 made of, for example, _SiO2 is formed by plasma CVD. After that, the insulating layer 17 located above the internal electrodes 31 is removed by photolithography and etching to expose the internal electrodes 31 (see FIG. 4).

As shown in FIG. 5, in step S2, alignment marks 41 made of the same material as the internal electrodes 31 are formed at the edge positions of the epitaxial wafer. FIG. 6 is a schematic plan view of the epitaxial wafer on which the alignment marks 41 are formed. In FIG. 6, in order to facilitate understanding of the alignment marks 41, only the insulating layer 17 formed on the top surface of the wafer and the alignment marks 41 formed penetrating the insulating layer 17 are shown, but in reality, the patterned internal electrodes 31 are also formed at this point.

In FIG. 6, the alignment mark 41 has a cross shape, but the shape of the alignment mark 41 is arbitrary.

This step S2 corresponds to steps (d) to (e).

(Step S3)
7, the reflective layer 15 is formed so as to cover the insulating layer 17 and the internal electrode 31, and then the bonding layer 13a is formed. For example, the reflective layer 15 is formed by depositing, for example, Al/Au to a predetermined thickness using a vacuum deposition device, and then the bonding layer 13a is formed by depositing, for example, Au-Sn to a predetermined thickness. Note that, as described above, a barrier layer may be formed between the reflective layer 15 and the bonding layer 13a by depositing, for example, Ti/Pt/Au to a predetermined thickness.

(Step S4)
8, a support substrate 11 separate from the growth substrate 3 is prepared, and a bonding layer 13b made of, for example, Au-Sn is formed on the upper surface of the support substrate 11. Although not shown, a metal layer (for example, Ti) for contact may be formed on the surface of the support substrate 11, and the bonding layer 13b may be formed on the metal layer. Furthermore, the above-mentioned barrier layer may be formed before forming the bonding layer 13b.

(Step S5)
9, the growth substrate 3 and the support substrate 11 are bonded together via the bonding layers 13 (13a, 13b) at a temperature of, for example, 280° C. and a pressure of 1 MPa. Through this process, the bonding layer 13a on the growth substrate 3 and the bonding layer 13b on the support substrate 11 are melted and integrated (bonding layer 13).

This step S5 corresponds to process (f).

(Step S6)
After a resist is applied to the surface on the semiconductor laminate 20 side for protection, the exposed growth substrate 3 is subjected to a grinding/polishing process or a wet etching process using a hydrochloric acid-based etchant, whereby the growth substrate 3 is peeled off to expose the second cladding layer 27 (see FIG. 10 ).

This step S6 corresponds to process (g).

(Step S7)
An upper electrode 32 is formed at a predetermined position on the upper surface of the second cladding layer 27. The detailed procedure of this step S7 will be described with reference to Figures 11A to 11E.

First, as shown in FIG. 11A, photoresist 43 is applied to the upper surface of the second cladding layer 27. Here, a negative type photoresist 43 is used as an example, but a positive type photoresist 43 may also be used.

Next, as shown in FIG. 11B, a photomask 45 patterned according to the shape of the upper electrode 32 is placed in a predetermined position, and exposure light L40 is irradiated through the photomask 45.

The photomask 45 preferably has an alignment mask region 45a at the end position. That is, as shown in FIG. 11C, the photomask 45 has a mask region 45b patterned according to the shape of the upper electrode 32, and an alignment mask region 45a.

As described above with reference to Figures 5 and 6, in step S2, alignment marks 41 made of the same material as the internal electrodes 31 are formed on the wafer. When adjusting the position of the photomask 45, light from, for example, a halogen lamp is irradiated from above the photomask 45, and an image is captured by an image sensor such as an InGaAs-based sensor. Then, while checking the obtained image, the position of the photomask 45 is adjusted so that the alignment marks 41 and the alignment mask region 45a overlap. Figure 11C shows the state after the alignment marks 41 and the alignment mask region 45a have been adjusted so that they overlap in the Y direction.

When the light from the halogen lamp passes through the semiconductor laminate 20 and reaches the location where the insulating layer 17 is formed, it is reflected by the internal electrode 31 and the alignment mark 41 and is received by the image sensor. Based on this captured image, the location where the alignment mark 41 is formed can be detected. As described above, the active layer 25 has a film thickness T adjusted according to the peak emission wavelength λ, and the amount of light from the image sensor absorbed in the active layer 25 is suppressed. In addition, the first cladding layer 23 and the second cladding layer 27 are made of a material with a higher band gap energy than the active layer 25, and are preferably made of InP. For this reason, the amount of light of 1000 nm or more absorbed in these layers is small, and does not pose a problem when detecting the formation position of the internal electrode 31. In addition, although some light may be absorbed in the contact layer 21, it does not pose a problem when detecting the formation position of the internal electrode 31 because the contact layer 21 is thin to begin with.

In other words, even if the peak emission wavelength of the active layer 25 is 1000 nm or more, the alignment mask region 45a provided on the photomask 45 can be adjusted to overlap the alignment mark 41. As a result, the mask region 45b for the upper electrode 32 provided on the photomask 45 can be adjusted to an appropriate position according to the formation position of the internal electrode 31.

The alignment mask region 45a may have a shape corresponding to the shape of the alignment mark 41. That is, as shown in FIG. 6, if the alignment mark 41 is cross-shaped, the alignment mask region 45a may also be cross-shaped.

When the exposure light L40 is irradiated onto the wafer through the photomask 45 set in a predetermined position, the photoresist 43 present below the mask areas (45a, 45b) remains, and the photoresist 43 present below the openings of the photomask 45 is removed (see FIG. 11D).

Next, as shown in FIG. 11E, a material film for the upper electrode 32 is formed using, for example, a vacuum deposition apparatus. As a result, a material film is formed on the upper surface of the remaining photoresist 43 and the upper surface of the exposed second cladding layer 27 (32a, 32). The photoresist 43 is then peeled off, and an annealing process is performed as necessary, to form the upper electrode 32 at a predetermined position on the upper surface of the second cladding layer 27 (see FIGS. 1 and 2).

This step S7 corresponds to steps (h) to (j).

(Later process)
After step S7, for example, the following steps are executed. Note that the following steps can be appropriately interchanged.

A pad electrode 34 is formed at a predetermined position on the upper surface of the upper electrode 32. In this case, as with the upper electrode 32, this can be achieved by film formation using a vacuum deposition device and a lift-off process.

Wet etching is performed on the surface of the second cladding layer 27 on which the upper electrode 32 (and pad electrode 34) is not formed, forming uneven portions 27a. Then, mesa etching is performed to separate each element. Specifically, wet etching is performed with a mixture of bromine and methanol while the non-etched areas of the surface of the second cladding layer 27 are masked with resist patterned by photolithography. This removes a portion of the semiconductor laminate 20 located in the unmasked areas (see FIG. 1).

After the thickness of the back side of the support substrate 11 is adjusted, a back electrode 33 is formed on the back side of the support substrate 11. As with the upper electrode 32, the back electrode 33 can be formed by depositing a film of the material for the back electrode 33 (e.g., Ti/Pt/Au) using a vacuum deposition device.

The adjustment of the thickness of the back side of the support substrate 11 can be performed as necessary and is not necessarily a required step. The thickness is also appropriately set depending on the application, etc.

Then, the support substrate 11 is diced together to create chips.

[Verification 1]
Steps S1 to S6 were performed under the same conditions, except that the material and film thickness of the active layer 25 were changed. Thereafter, the photomask 45 was aligned as in step S7, and the upper electrode 32 was formed. The results are shown in Table 1. In Table 1, the evaluation "C" corresponds to a case where the internal electrode 31 could not be recognized and the photomask 45 could not be aligned, or the alignment accuracy between the obtained upper electrode 32 and the internal electrode 31 exceeded 10 μm. Also, in Table 1, the evaluation "A" corresponds to a case where the alignment accuracy between the obtained upper electrode 32 and the internal electrode 31 was 5 μm or less.

According to Table 1, it can be seen that the longer the peak emission wavelength λ, the thinner the active layer 25 needs to be in order to improve the accuracy of the alignment between the upper electrode 32 and the internal electrode 31. This suggests that the thinner active layer 25 reduces the amount of light absorbed within the active layer 25, improving the recognition accuracy of the image sensor. On the other hand, it can be seen that within the range of peak emission wavelengths of 1550 nm or less, if the thickness of the active layer 25 is 1000 nm or less, the alignment between the upper electrode 32 and the internal electrode 31 can be achieved with high accuracy.

Figure 12 is a graph in which the thickness of the active layer 25 of the sample with the thickest active layer 25 among the samples that received an "A" rating in Table 1 is plotted for each wavelength. This graph also shows that the longer the peak emission wavelength λ, the more difficult it is to identify the position where the internal electrode 31 is formed unless the active layer 25 is made thinner.

According to the results of FIG. 12, when the peak emission wavelength λ is in the range of 1550 nm to 1800 nm, more specifically, in the range of 1550 nm to 1750 nm, the film thickness T [nm] of the active layer and the peak emission wavelength λ [nm] satisfy the following formula (1):
T ≦ -3.5×λ + 6375…(1)
It can be seen that by satisfying the above condition, the formation position of the internal electrode 31 can be detected with high accuracy by the image sensor. Also, it can be seen that when the peak emission wavelength λ is in the range of 1000 nm to 1550 nm, more specifically, in the range of 1050 nm to 1550 nm, the formation position of the internal electrode 31 can be detected with high accuracy by the image sensor by setting the film thickness T [nm] of the active layer to 1000 nm or less.

In other words, by setting the film thickness T of the active layer as described above, in step S7, the photomask 45 can be set at an appropriate position according to the position of the internal electrode 31. As a result, by forming the upper electrode 32 by exposure through this photomask 45, the upper electrode 32 does not overlap with the internal electrodes 31 in the Y direction, and the distance between each internal electrode 31 can be made approximately equal.

[Verification 2]
Sample #1 was obtained through steps S1 to S7 described above. In sample #1, the average variation in the separation distance Ws between the upper electrode 32 and the internal electrode 31 when viewed in the Y direction was 2.0 μm, and all variations were suppressed to within 5 μm. Note that FIG. 13 is a diagram for explaining the separation distance Ws between the upper electrode 32 and the internal electrode 31, and corresponds to the partially enlarged view of FIG. 2.

As another sample, sample #2 was obtained by the same method as sample #1, except that the position of the photomask 45 was intentionally shifted in step S7. In sample #2, the average variation in the separation distance Ws between the upper electrode 32 and the internal electrode 31 when viewed in the Y direction was 11 μm, which greatly exceeded 5 μm.

In addition, for both sample #1 and sample #2, the peak emission wavelength was 1300 nm, and the thickness of the active layer 25 was 200 nm.

Figure 14 is a graph showing the current-light output characteristics of the infrared LED elements of samples #1 and #2. Also, Figure 15 is a graph showing the current-forward voltage characteristics of the infrared LED elements of samples #1 and #2.

14 and 15 show that sample #1, in which the separation distance Ws between the upper electrode 32 and the internal electrode 31 was kept to 5 μm or less, has a higher light output and a lower forward voltage when the same current is supplied, compared to sample #2, in which the separation distance Ws significantly exceeds 5 μm. This result also shows that adjusting the positions of the upper electrode 32 and the internal electrode 31 is an important factor in improving the light emission efficiency of the infrared LED element 1.

1: infrared LED element 3: growth substrate 11: support substrate 13 (13a, 13b): bonding layer 15: reflective layer 17: insulating layer 20: semiconductor laminate 21: contact layer 23: first cladding layer 25: active layer 27: second cladding layer 27a: uneven portion 31: internal electrode 32: upper electrode 33: back electrode 34: pad electrode 41: alignment mark 43: photoresist 45: photomask 45a, 45b: mask area

Claims (6)

An infrared LED element,
A conductive supporting substrate;
an insulating layer formed on the support substrate;
a semiconductor laminate including a first semiconductor layer of p-type or n-type formed on the insulating layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a different conductivity type from the first semiconductor layer formed on the active layer;
an upper electrode formed on the upper layer of the semiconductor laminate;
internal electrodes penetrating the insulating layer at a plurality of positions distributed in a direction parallel to a main surface of the support substrate and electrically connecting the first semiconductor layer and the support substrate;
An infrared LED element, wherein a film thickness T [nm] of the active layer and a peak emission wavelength λ [nm] of the infrared LED element satisfy the relationship of the following formula (1):
T ≦ -3.5×λ + 6375…(1)
(However, λ is in the range of 1550≦λ≦1800.) The infrared LED element according to claim 1, characterized in that the upper electrode is disposed at a position not facing the internal electrode in a direction perpendicular to the main surface of the support substrate. The infrared LED element according to claim 1 or 2, characterized in that the variation in the distance between the upper electrode closest to the internal electrode and the internal electrode when viewed from a direction perpendicular to the main surface of the support substrate is 10 μm or less. the second semiconductor layer is InP;
3. The infrared LED element according to claim 1, wherein the active layer comprises one or more materials belonging to the group consisting of GaInAsP, AlGaInAs, and InGaAs. A method for manufacturing an infrared LED element according to claim 1 or 2, comprising the steps of:
(a) providing a growth substrate;
(b) forming the second semiconductor layer on the growth substrate;
a step (c) of forming the active layer made of a material having a peak emission wavelength λ [nm] on the second semiconductor layer to a thickness T [nm] that satisfies the formula (1);
(d) forming the first semiconductor layer and the insulating layer on the active layer;
(e) forming the internal electrodes inside the insulating layer;
a step (f) of bonding the support substrate to the upper layer of the insulating layer;
(g) peeling off the growth substrate to expose the second semiconductor layer;
(h) forming a photoresist on the second semiconductor layer, and then aligning and positioning a photomask patterned according to the shape of the upper electrode using an image sensor based on the position of the internal electrode;
(i) forming a material film for the upper electrode after exposing the material film through the photomask;
and (j) removing the photoresist. The step (b) is a step of forming a film made of InP,
6. The method for producing an infrared LED element according to claim 5 , wherein the step (c) is a step of depositing a film containing one or more materials belonging to the group consisting of GaInAsP, AlGaInAs, and InGaAs.

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