JP7653078B2 - Infrared LED element - Google Patents

Description

The present invention relates to infrared LED elements, and in particular to infrared LED elements with a peak emission wavelength of 1000 nm or more.

In recent years, semiconductor light-emitting elements that emit light in the infrared region with wavelengths of 1000 nm or more have been widely used in security and surveillance cameras, gas detectors, medical sensors, industrial equipment, and other applications.

Semiconductor light-emitting elements with an emission wavelength of 1000 nm or more have generally been manufactured using the following procedure (see Patent Document 1 below). That is, on an InP substrate used as a growth substrate, a first conductivity type semiconductor layer that is lattice-matched to the InP substrate, an active layer (sometimes called an "emitting layer"), and a second conductivity type semiconductor layer are epitaxially grown in that order. After that, electrodes for current injection are formed on the semiconductor wafer, and the wafer is cut into chips for manufacture.

Traditionally, semiconductor laser elements have been the leading semiconductor light-emitting element with an emission wavelength of 1000 nm or more in terms of development. On the other hand, LED elements have not been developed as much as laser elements, partly because there have not been many applications for them.

However, in recent years, with the expansion of applications, there has been a demand for improved light output for infrared LED elements as well. InP substrates, like GaAs substrates used in the visible light region, have a high refractive index of 3 or more. For this reason, when attempting to extract light through an InP substrate, total reflection occurs due to the difference in refractive index at the interface with air, limiting the light extraction efficiency. Furthermore, since InP substrates have high thermal resistance, the light output is likely to become saturated when driven with a large current. For these reasons, the structure disclosed in Patent Document 1 was not suitable for realizing an LED element that obtains high light output.

As a method for obtaining a higher optical output than the structure disclosed in Patent Document 1, for example, the structure disclosed in Patent Document 2 can be adopted. That is, a structure realized by bonding a growth substrate on which an epitaxial layer is formed to a conductive support substrate that exhibits high heat dissipation properties and then removing the growth substrate is considered to be effective. However, the light-emitting element described in Patent Document 2 targets a wavelength that is lower than 1000 nm.

Japanese Unexamined Patent Publication No. 4-282875 JP 2012-129357 A

An LED element such as that described in Patent Document 2, i.e., an LED element in which one electrode is disposed above the active layer and the other electrode is disposed below the active layer, and light is emitted by passing a current through the active layer in a direction perpendicular to the surface of the substrate, is sometimes called a "vertical structure."

The present invention aims to realize an infrared LED element with a peak emission wavelength of 1000 nm or more in a vertical structure while improving the light extraction efficiency compared to conventional methods.

The infrared LED element according to the present invention is an infrared LED element having a peak emission wavelength of 1000 nm or more,
A conductive supporting substrate;
A conductive layer formed on the upper layer of the support substrate;
an insulating layer formed on the conductive layer;
a p-type or n-type first semiconductor layer formed on the insulating layer;
an active layer formed on the first semiconductor layer;
a second semiconductor layer formed on the active layer and having a different conductivity type from the first semiconductor layer;
internal electrodes that penetrate the insulating layer at a plurality of positions distributed in a direction parallel to a main surface of the support substrate and electrically connect the first semiconductor layer and the support substrate;
an upper electrode formed on the second semiconductor layer;
The semiconductor device is characterized in that it further comprises an alloy layer formed at the interface between the second semiconductor layer and the upper electrode, which is made of an alloy of a constituent material of the upper electrode and a constituent material of the second semiconductor layer, and has an average film thickness of 150 nm or less.

In order to ensure good electrical connection (ohmic connection) with the semiconductor layer, when forming an electrode (upper electrode) located on the upper layer of the semiconductor layer, an annealing process is performed after forming a film of electrode material on the upper surface of the semiconductor layer. By performing the annealing process, an alloy layer is formed at the interface between the semiconductor layer and the upper electrode.

The metal material used as the electrode material is determined according to the material of the semiconductor layer. This is because different metals can reduce the contact resistance to the semiconductor layer depending on the material of the semiconductor layer. In other words, the type of electrode material is determined by the material of the semiconductor layer, in other words, the emission wavelength. The only semiconductor materials that have been put into practical use in this invention that can realize light-emitting elements with a peak wavelength of 1000 nm or more are InP, GaInAsP, AlGaInAs, and GaInAs-based semiconductors that are lattice-matched to InP substrates.

Conventionally, semiconductor light-emitting elements with an emission wavelength of 1000 nm or more have been developed for use as lasers in optical communications. In the case of laser elements, light is extracted from the end face of the semiconductor layer, so it is not expected that light will be extracted from the main surface of the semiconductor layer (the surface parallel to the main surface of the substrate).

In contrast, when annealing is performed to reduce contact resistance as described above, in the case of a vertically structured infrared LED element, an alloy layer is formed below the main surface of the semiconductor layer that constitutes the light extraction surface.

If the alloy layer were not present, part of the infrared light emitted from the active layer would be incident on the upper electrode. Because the upper electrode is made of a metal material, part of the infrared light incident on the upper electrode would be reflected by the electrode surface. As a result, the reflected light would be returned toward the substrate, and would be reflected again by a layer within the infrared LED element, and extracted from the light extraction surface.

In other words, the presence of the alloy layer absorbs the infrared light emitted from the active layer, causing a decrease in the light extraction efficiency.

On the other hand, if the alloy layer were to be completely eliminated, the contact resistance between the semiconductor layer and the upper electrode would increase, leading to an increase in the forward voltage. Furthermore, the adhesion between the semiconductor layer and the upper electrode would decrease, which could lead to the electrode peeling off during wire bonding. From this perspective, it is difficult to completely eliminate the alloy layer.

As a result of intensive research by the inventors, it was found that when the average film thickness of the alloy layer exceeds 150 nm, the tendency for the light extraction efficiency to decrease is accelerated. In addition, it was found that if the average film thickness of the alloy layer is within 150 nm, a light output comparable to that obtained when the alloy layer is not present can be obtained.

In other words, the infrared LED element described above makes it possible to increase the light extraction efficiency while suppressing the occurrence of two problems: an increase in forward voltage and electrode peeling.

The average thickness of the alloy layer can be determined by setting measurement points every 1 μm evenly within an area of at least 10 μm square when viewed from a direction perpendicular to the main surface of the support substrate, and averaging the thickness of the alloy layer at each measurement point.

The second semiconductor layer may contain InP. The entire second semiconductor layer may be made of InP.

the second semiconductor layer includes a cladding layer located on the active layer side, and a contact layer located above the cladding layer and having at least one of a composition and a dopant concentration different from that of the cladding layer;
The material constituting the contact layer may have a band gap energy higher than the light energy of the peak emission wavelength.

In the case of InP-based materials, materials with relatively small band gap energy such as GaInAsP and GaInAs are more likely to form an ohmic junction than InP layers. This is thought to be because a natural oxide film is more likely to form when the surface has a high In composition. However, even if the thickness of the alloy layer is thin, if the contact layer absorbs the light emitted from the active layer, the light extraction efficiency will decrease. As described above, by forming the contact layer from a material with a band gap energy higher than the light energy of the peak emission wavelength, light absorption in the contact layer is suppressed, ensuring high light extraction efficiency.

From this perspective, it is preferable to form the contact layer from InP, which has a higher dopant concentration than the cladding layer. InP is composed of one type each of group III and V elements, so compositional deviations are unlikely to occur. This has the advantage of suppressing variations between elements during manufacturing, allowing for the stable manufacture of infrared LED elements that exhibit uniform characteristics.

The alloy layer may be made of a material containing Ge.

The second semiconductor layer may have a dopant concentration of 5×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ at a location adjacent to the alloy layer.

In order to realize a low-resistance ohmic contact between the upper electrode and the second semiconductor layer, it is necessary to perform appropriate doping on the second semiconductor layer. If the dopant concentration is less than 5×10 ¹⁷ /cm ³ , the contact resistance between the second semiconductor layer and the upper electrode may increase. In addition, excessive doping leads to deterioration of crystallinity. In particular, when manufacturing the infrared LED element, the active layer is formed after the second semiconductor layer is formed, so the second semiconductor layer serves as a base for forming the active layer. Therefore, from the viewpoint of ensuring high light emission efficiency in the active layer, it is necessary to avoid a situation in which the crystallinity of the second semiconductor layer deteriorates. From this viewpoint, it is preferable that the dopant concentration of the second semiconductor layer is 5×10 ¹⁸ /cm ³ or less.

When viewed in a direction perpendicular to the main surface of the support substrate, the area occupied by the upper electrode may be 20% or less of the area occupied by the second semiconductor layer.

The exposed surface of the second semiconductor layer forms the light extraction surface. In other words, as the area occupied by the upper electrode increases, the area of the light extraction surface decreases accordingly, and the amount of light extracted decreases. With the above configuration, the area of the light extraction surface is secured while light absorption in the alloy layer is suppressed, thereby achieving high light extraction efficiency.

The present invention realizes a vertical infrared LED element with improved light extraction efficiency and a peak emission wavelength of 1000 nm or more.

1 is a cross-sectional view showing a schematic configuration of an embodiment of an infrared LED element of the present invention. 2 is a schematic plan view of the infrared LED element shown in FIG. 1 when viewed in the −Y direction. 2 is an enlarged cross-sectional view of a portion near the upper electrode in FIG. 1 . 1 is a SEM photograph of a cross section of an infrared LED element in the vicinity of an upper electrode. 2 is a cross-sectional view illustrating a step in a manufacturing method of the LED element shown in FIG. 1. 1. FIG. 4 is a cross-sectional view illustrating another step in the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a cross-sectional view illustrating another step in the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a cross-sectional view illustrating another step in the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a cross-sectional view illustrating another step in the manufacturing method of the LED element shown in FIG. 1. FIG. 4 is a cross-sectional view illustrating another step in the manufacturing method of the LED element shown in FIG. 1 is a graph showing the relationship between light output and average film thickness of an alloy layer. 1 is a graph showing the relationship between forward voltage and average film thickness of an alloy layer. FIG. 4 is a cross-sectional view illustrating a configuration of another embodiment of the infrared LED element of the present invention.

Embodiments of the infrared LED element according to the present invention will be described with reference to the drawings. The following drawings are schematic illustrations, and the dimensional ratios in the drawings do not necessarily match the actual dimensional ratios. Furthermore, the dimensional ratios may not match between the drawings.

In this specification, the expression "layer Q2 is formed on layer Q1" is intended to include the case where layer Q2 is formed directly on the surface of layer Q1, as well as the case where layer Q2 is formed on the surface of layer Q1 via a thin film. Note that "thin film" here refers to a layer with a thickness of 20 nm or less, and preferably refers to a layer with a thickness of 10 nm or less.

In this specification, the term "GaInAsP" means a mixed crystal of Ga, In, As, and P, and is a description that simply omits the description of the composition ratio. The same applies to other descriptions such as "AlGaInAs."

Figure 1 is a cross-sectional view showing a schematic structure of an infrared LED element of this embodiment. The infrared LED element 1 shown in Figure 1 has a semiconductor laminate 20 formed on the upper layer of a support substrate 11. Figure 1 corresponds to a schematic cross-sectional view of the infrared LED element 1 cut along the XY plane at a predetermined position. In the following explanation, the X-Y-Z coordinate system shown in Figure 1 will be referred to as appropriate.

In the following description, when a positive or negative direction needs to be distinguished, the direction is described with a positive or negative sign, such as "+X direction" and "-X direction". When a direction is described without distinguishing between positive and negative directions, it is simply described as "X direction". In other words, in this specification, when it is simply described as "X direction", both the "+X direction" and the "-X direction" are included. The same applies to the Y direction and the Z direction. In the following example, it is described that the main surface of the support substrate 11 is parallel to the XZ plane, and light is extracted in the normal direction (Y direction).

In the infrared LED element 1 of this embodiment, infrared light L is generated in the semiconductor laminate 20 (particularly in the active layer 25 described below). More specifically, as shown in FIG. 1, the infrared light L (L1, L2) is extracted in the +Y direction when the active layer 25 is used as a reference. The infrared light L has a peak wavelength of 1000 nm or more. The peak wavelength here corresponds to the wavelength at which the optical output is the highest in the optical spectrum.

[Element structure]
The structure of the infrared LED element 1 will now be described in detail.

(Support substrate 11)
The support substrate 11 is made of, for example, a semiconductor such as Si or Ge, or a metal material such as Cu or CuW. When the support substrate 11 is made of a semiconductor, it may be doped with a high concentration of a dopant so as to exhibit electrical conductivity. As an example, the support substrate 11 is a Si substrate doped with boron (B) at a dopant concentration of 1×10 ¹⁹ /cm ³ or more and having a resistivity of 10 mΩcm or less. As the dopant, for example, phosphorus (P), arsenic (As), antimony (Sb), etc. can be used other than boron (B). From the viewpoint of achieving both high heat dissipation and low manufacturing cost, a Si substrate is preferably used for the support substrate 11.

The thickness of the support substrate 11 (length in the Y direction) is not particularly limited, but is, for example, 50 μm to 500 μm, and preferably 100 μm to 300 μm.

(Conductive layer 16)
1 includes a conductive layer 16 formed on a support substrate 11. In this embodiment, the conductive layer 16 includes a bonding layer 13 and a reflective layer 15 in more detail.

The bonding layer 13 is made of a low melting point solder material, such as Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, Sn, etc. As will be described later with reference to FIG. 4E, this bonding layer 13 is used to bond the growth substrate 3, on whose upper surface the semiconductor laminate 20 is formed, to the support substrate 11. The thickness of the bonding layer 13 is not particularly limited, but is, for example, 0.5 μm to 5.0 μm, and preferably 1.0 μm to 3.0 μm.

The reflective layer 15 has the function of reflecting infrared light L2, which is generated in the active layer 25 and travels toward the support substrate 11 (-Y direction), and directing it in the +Y direction. The reflective layer 15 is made of a conductive material that exhibits high reflectance to infrared light L. The reflectance of the reflective layer 15 to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm to 2000 nm, the reflective layer 15 can be made of a metal material such as Ag, an Ag alloy, Au, Al, or Cu. The material constituting the reflective layer 15 is appropriately selected according to the wavelength of the light generated in the active layer 25.

The thickness of the reflective layer 15 is not particularly limited, but is, for example, 0.1 μm to 2.0 μm, and preferably 0.3 μm to 1.0 μm.

Although not shown in FIG. 1, the conductive layer 16 may further include a barrier layer between the reflective layer 15 and the bonding layer 13 to suppress diffusion of the solder material constituting the bonding layer 13. The material of the barrier layer may be, for example, a material containing Ti, Pt, W, Mo, Ni, etc. As an example, it is composed of a Ti/Pt/Au laminate. The thickness of the barrier layer is not particularly limited, but is, for example, 0.05 μm to 3 μm, and preferably 0.2 μm to 1 μm. The presence of this barrier layer can prevent the material of the bonding layer 13 from diffusing to the reflective layer 15 side, which would reduce the reflectance of the reflective layer 15. The barrier layer may also be provided between the bonding layer 13 and the support substrate 11.

From the viewpoint of improving the light extraction efficiency, it is preferable that the infrared LED element 1 has a reflective layer 15 as shown in FIG. 1, but in the present invention, it is optional whether or not the infrared LED element 1 has a reflective layer 15.

(Insulating layer 17)
The infrared LED element 1 shown in Fig. 1 includes an insulating layer 17 formed on the reflective layer 15. The insulating layer 17 is made of a material that exhibits electrical insulation and has high transparency to infrared light L. The transmittance of the insulating layer 17 to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

When the peak wavelength of the infrared light L is 1000 nm to 2000 nm, materials such as SiO ₂ , SiN, and Al ₂ O ₃ can be used for the insulating layer 17. The material of the insulating layer 17 is appropriately selected depending on the wavelength of the light generated in the active layer 25.

(Semiconductor laminate 20)
The infrared LED element 1 shown in Fig. 1 has a semiconductor laminate 20 formed on an insulating layer 17. The semiconductor laminate 20 is a laminate of multiple semiconductor layers, and includes, for example, a contact layer 21, a first cladding layer 23, an active layer 25, and a second cladding layer 27. As will be described later with reference to Fig. 7, the semiconductor laminate 20 may further include a contact layer 28 on the second cladding layer 27. Each semiconductor layer constituting the semiconductor laminate 20 is made of a material that is lattice-matched with a growth substrate 3 described later and can be epitaxially grown.

<<Contact layer 21, first cladding layer 23>>
In this embodiment, the contact layer 21 is made of, for example, p-type GaInAsP. The thickness of the contact layer 21 is not limited, but is, for example, 10 nm to 1000 nm, and preferably 50 nm to 500 nm. The p-type dopant concentration of the contact layer 21 is preferably 5×10 ¹⁷ /cm ³ to 3×10 ¹⁹ /cm ³ , and more preferably 1×10 ¹⁸ /cm ³ to 2×10 ¹⁹ /cm ³ .

In this embodiment, the first cladding layer 23 is formed on the contact layer 21 and is made of, for example, p-type InP. The thickness of the first cladding layer 23 is not limited, but is, for example, 1000 nm to 10000 nm, and preferably 2000 nm to 5000 nm. The p-type dopant concentration of the first cladding layer 23 at a position away from the active layer 25 is preferably 1×10 ¹⁷ /cm ³ to 3×10 ¹⁸ /cm ³ , and more preferably 5×10 ¹⁷ /cm ³ to 3×10 ¹⁸ /cm ³ .

As the p-type dopant contained in the contact layer 21 and the first cladding layer 23, Zn, Mg, Be, etc. can be used, with Zn or Mg being preferred, and Zn being particularly preferred. In this embodiment, the contact layer 21 and the first cladding layer 23 correspond to the "first semiconductor layer."

<<Active Layer 25>>
In this embodiment, the active layer 25 is a semiconductor layer formed on the first cladding layer 23. The material of the active layer 25 is appropriately selected from materials that can generate light of a target wavelength and can be epitaxially grown in lattice-matched relationship with a growth substrate 3 described later with reference to FIG.

When it is desired to realize an infrared LED element 1 that emits infrared light L with a peak wavelength of 1000 nm to 2000 nm, the active layer 25 may be a single layer structure of GaInAsP, AlGaInAs, or InGaAs, or may be an MQW (Multiple Quantum Well) structure including a well layer made of GaInAsP, AlGaInAs, or InGaAs, and a barrier layer made of GaInAsP, AlGaInAs, InGaAs, or InP that has a larger band gap energy than the well layer.

When the active layer 25 has a single-layer structure, the thickness of the active layer 25 is 50 nm to 2000 nm, and preferably 100 nm to 300 nm. When the active layer 25 has an MQW structure, the active layer 25 is configured by stacking well layers and barrier layers with a thickness of 5 nm to 20 nm in a range of 2 to 50 periods.

The active layer 25 may be doped to n-type or p-type, or may be undoped. If it is doped to n-type, for example, Si can be used as a dopant.

Second Cladding Layer 27
In this embodiment, the second cladding layer 27 is formed on the active layer 25 and is, for example, n-type InP. The thickness of the second cladding layer 27 is not limited, but is, for example, 100 nm to 10,000 nm, and preferably 500 nm to 5,000 nm. The n-type dopant concentration of the second cladding layer 27 is preferably 1×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ , and more preferably 5×10 ¹⁷ /cm ³ to 4×10 ¹⁸ /cm ^3. As the n-type impurity material doped in the second cladding layer 27, Sn, Si, S, Ge, Se, etc. can be used, and Si is particularly preferable. In the infrared LED element 1 of this embodiment, the second cladding layer 27 corresponds to the "second semiconductor layer".

In the example shown in FIG. 1, an uneven portion 27a is formed on the surface on the +Y side of the second cladding layer 27. By forming the uneven portion 27a, the amount of infrared light L (L1, L2) traveling in the +Y direction from the active layer 25 that is reflected toward the active layer 25 by the surface of the second cladding layer 27 is reduced, and the light extraction efficiency is improved. However, in the present invention, it is optional whether or not to provide the uneven portion 27a on the surface of the second cladding layer 27.

The material of the first cladding layer 23 and the second cladding layer 27 is appropriately selected from materials that do not absorb the infrared light L generated in the active layer 25 and that can be epitaxially grown by lattice matching with the growth substrate 3 (see FIG. 4 described later). When an InP substrate is used as the growth substrate 3, the material of the first cladding layer 23 and the second cladding layer 27 can be InP, GaInAsP, AlGaInAs, etc.

In this embodiment, the first semiconductor layer (21, 23) is described as a p-type semiconductor and the second semiconductor layer (second cladding layer 27) is described as an n-type semiconductor, but the conductivity types of the two may be reversed.

(Internal electrode 31)
1 has internal electrodes 31 formed in a plurality of locations within the insulating layer 17, penetrating the insulating layer 17 in the Y direction. The internal electrodes 31 electrically connect the first semiconductor layers (21, 23) and the conductive layer 16. The internal electrodes 31 are provided at a plurality of locations dispersed in a direction parallel to the XZ plane (i.e., a direction parallel to the main surface of the support substrate 11).

The internal electrode 31 is made of a material capable of forming an ohmic connection with the contact layer 21. As an example, the internal electrode 31 is made of AuZn, AuBe, or a laminated structure containing at least Au and Zn (e.g., Au/Zn/Au, etc.). These materials have a lower reflectance for infrared light L than the material that constitutes the reflective layer 15.

When viewed in the Y direction, the arrangement pattern of the internal electrodes 31 may have any shape. However, from the viewpoint of flowing a current uniformly over a wide range in the active layer 25 in a direction parallel to the main surface of the support substrate 11, it is preferable that the internal electrodes 31 are arranged in a dispersed state with a regular shape in the planar direction along the XZ plane.

Figure 2 is an example of a schematic plan view of the infrared LED element 1 when viewed in the Y direction from above the second cladding layer 27. However, in order to make it easier to understand the shape pattern of the internal electrode 31, Figure 2 also illustrates the internal electrode 31. Figure 2 will be described in detail later in the explanation of the upper electrode 40. Note that Figure 2 illustrates a case in which the semiconductor laminate 20 has a rectangular shape when viewed from above.

When the infrared LED element 1 is viewed in the Y direction, the total area of all the internal electrodes 31 is preferably 30% or less, more preferably 20% or less, and particularly preferably 15% or less, of the area in the planar direction of the semiconductor laminate 20 (e.g., the second cladding layer 27). If the total area of the internal electrodes 31 is relatively large, the infrared light L2 traveling from the active layer 25 toward the support substrate 11 (-Y direction) is absorbed by the internal electrodes 31, reducing the extraction efficiency. On the other hand, if the total area of the internal electrodes 31 is too small, the resistance value increases and the forward voltage rises.

(Rear electrode 33)
1 includes a back electrode 33 formed on the surface of the support substrate 11 opposite to the semiconductor laminate 20 (−Y side). The back electrode 33 is in ohmic contact with the support substrate 11. As an example, the back electrode 33 is made of a material such as Ti/Au or Ti/Pt/Au, and may include a plurality of these materials.

(Upper electrode 40)
The infrared LED element 1 shown in Fig. 1 has an upper electrode 40 formed on the upper layer of a semiconductor laminate 20. Typically, a plurality of upper electrodes 40 are formed extending in a predetermined direction.

Figure 2 shows a configuration in which the upper electrode 40 includes a first upper electrode 41 that extends in the X and Z directions along the sides of the semiconductor laminate 20, and a second upper electrode 42 that is formed on the upper surface of the first upper electrode 41 at a specific location and has a larger inner diameter in a top view than the first upper electrode 41. The second upper electrode 42 is provided for the purpose of securing an area for contacting a bonding wire for power supply, and is sometimes called a pad electrode.

The arrangement pattern shape of the first upper electrode 41 is arbitrary, and may be, for example, a lattice shape or a spiral shape. The first upper electrode 41 of the upper electrode 40 is formed over a wide range on the XZ plane while exposing the surface of the semiconductor layer (here, the second cladding layer 27) located in the lower layer. This allows the current flowing in the active layer 25 to be spread in a direction parallel to the XZ plane, and light can be emitted over a wide range in the active layer 25.

The first upper electrode 41 is made of, for example, AuGe/Ni/Au, Au/Ge/Au, Au/Zn/Au, AuZn, AuBe, or a combination of these materials. The second upper electrode 42 is made of, for example, Ti/Au, Ti/Pt/Au, or the like.

The second upper electrode 42 constituting the pad electrode has a circular shape with an inner diameter of about 90 μm to 120 μm, for example, when each side (chip size) of the semiconductor laminate 20 is about 800 μm to 2500 μm. The line width of the first upper electrode 41 is about 10 μm to 30 μm. In a high-output infrared LED element 1 with a chip size exceeding 800 μm, it is preferable to provide the second upper electrode 42 in multiple locations as shown in FIG. 2, from the perspective of injecting a high current.

When viewed in the Y direction, the area occupied by the upper electrodes 40 (first upper electrode 41, second upper electrode 42) is preferably 20% or less of the area occupied by the second cladding layer 27, and more preferably 15% or less. If the area occupied by the upper electrodes 40 is too large, the area of the light extraction surface is reduced, and the light extraction efficiency may decrease. The area occupied by the upper electrodes 40 is preferably 5% or more, and more preferably 8% or more.

(Alloy layer 35)
1 has an alloy layer 35 at the interface between the upper electrode 40 and the second cladding layer 27. The alloy layer 35 is an alloy of the metal material constituting the upper electrode 40 and the semiconductor material constituting the second cladding layer 27.

The alloy layer 35 is mainly present at a position opposite to where the upper electrode 40 is formed (i.e., directly below the upper electrode 40). The thickness of the alloy layer 35 varies slightly depending on the position on the XZ plane, and the average thickness is 150 nm or less, and more preferably the average thickness is 50 nm to 150 nm. The average thickness of the alloy layer 35 can be determined by setting measurement points every 1 μm evenly within a range of 10 μm square or more as viewed in the direction perpendicular to the main surface of the support substrate 11, i.e., the Y direction, and using the average thickness of the alloy layer at each measurement point.

Figure 3A is an enlarged view of the vicinity of the upper electrode 40. Figure 3B is a cross-sectional SEM photograph of the infrared LED element 1 in the vicinity of the upper electrode 40. Note that Figures 3A and 3B show the vicinity of the portion of the upper electrode 40 where the second upper electrode 42 is formed.

In the example shown in Figures 3A and 3B, the upper electrode 40 has a first upper electrode 41 and a second upper electrode 42, and includes an adhesion layer 45 made of, for example, Ti at the position of the second upper electrode 42 closest to the first upper electrode 41. The adhesion layer 45 is provided for the purpose of adhering the second upper electrode 42, which constitutes the pad electrode, to the semiconductor laminate 20 side.

As shown in the SEM photograph in FIG. 3B, the alloy layer 35 is formed at the interface between the upper electrode 40 and the second cladding layer 27, and its thickness varies slightly depending on the location. As described later, the alloy layer 35 is formed by alloying the electrode material and the semiconductor material by a heating process (annealing process) performed after vapor deposition of the electrode material in the process of forming the upper electrode 40 (more specifically, the first upper electrode 41). It is presumed that the thickness of the alloy layer 35 varies slightly depending on the location, as shown in the SEM photograph in FIG. 3B, because the speed of the alloying process due to the heating process varies slightly depending on the location. In the SEM photograph in FIG. 3B, a layer of a different color exists at the boundary between the second upper electrode 42 and the first upper electrode 41, and this layer corresponds to the adhesion layer 45 that constitutes part of the second upper electrode 42 as described above.

In the infrared LED element 1 of this embodiment, the average film thickness of the alloy layer 35 is set to 150 nm or less, thereby improving the light extraction efficiency. This point will be described later with reference to the examples.

[Production method]
An example of a method for manufacturing the above-mentioned infrared LED element 1 will be described with reference to Figures 4A to 4F. Figures 4A to 4F are cross-sectional views of a step in the manufacturing process. The order of the following steps may be changed as appropriate as long as it does not affect the manufacture of the infrared LED element 1.

(Step S1)
4A, a growth substrate 3 made of, for example, InP is transferred into a MOCVD (Metal Organic Chemical Vapor Deposition) device, and a second cladding layer 27, an active layer 25, a first cladding layer 23, and a contact layer 21 are epitaxially grown in sequence on the growth substrate 3 to form a semiconductor laminate 20. In this step S1, the type and flow rate of the source gas, the processing time, the environmental temperature, and the like are appropriately adjusted according to the material and film thickness of the layer to be grown. Examples of materials for each semiconductor layer (21, 23, 25, 27) are as described above.

InP is preferably used as the growth substrate 3. However, when manufacturing an infrared LED element 1 with a peak wavelength of 1070 nm or less, GaAs may be used as the growth substrate 3.

(Step S2)
The epitaxial wafer is removed from the MOCVD apparatus, and a resist mask patterned by photolithography is formed on the surface of the contact layer 21. Then, a material (e.g., AuZn) for forming the internal electrode 31 is deposited using a vacuum deposition apparatus, and the resist mask is peeled off by a lift-off method. Then, an alloying process (annealing process) is performed by heating at 450° C. for 10 minutes, for example, to realize ohmic contact between the contact layer 21 and the internal electrode 31.

Next, the insulating layer 17 made of, for example, _SiO2 is formed by plasma CVD. After that, the insulating layer 17 located above the internal electrodes 31 is removed by photolithography and etching to expose the internal electrodes 31 (see FIG. 4B).

(Step S3)
4C, the reflective layer 15 is formed so as to cover the insulating layer 17 and the internal electrode 31, and then the bonding layer 13a is formed. For example, the reflective layer 15 is formed by depositing, for example, Al/Au to a predetermined thickness using a vacuum deposition device, and then the bonding layer 13a is formed by depositing, for example, Au-Sn to a predetermined thickness. Note that, as described above, a barrier layer may be formed between the reflective layer 15 and the bonding layer 13a by depositing, for example, Ti/Pt/Au to a predetermined thickness.

(Step S4)
4D, a support substrate 11 separate from the growth substrate 3 is prepared, and a bonding layer 13b made of, for example, Au-Sn is formed on the upper surface of the support substrate 11. Although not shown, a metal layer (for example, Ti) for contact may be formed on the surface of the support substrate 11, and the bonding layer 13b may be formed on the metal layer. Also, the above-mentioned barrier layer may be formed before forming the bonding layer 13b.

(Step S5)
4E , the growth substrate 3 and the support substrate 11 are bonded together via the bonding layers 13 (13a, 13b) at a temperature of, for example, 280° C. and a pressure of 1 MPa. By this process, the bonding layer 13a on the growth substrate 3 and the bonding layer 13b on the support substrate 11 are melted and integrated as the bonding layer 13.

(Step S6)
After a resist is applied to the surface on the semiconductor laminate 20 side for protection, the exposed growth substrate 3 is subjected to a grinding/polishing process or a wet etching process using a hydrochloric acid-based etchant, whereby the growth substrate 3 is peeled off and the second cladding layer 27 is exposed (see FIG. 4F ).

(Step S7)
The upper electrode 40 is formed at a predetermined position on the upper surface of the second cladding layer 27. More specifically, the process is carried out in the following manner.

First, photoresist is applied to the upper surface of the second cladding layer 27. Next, a photomask patterned according to the shape of the upper electrode 40 is placed in a predetermined position, and exposure light is irradiated through the photomask. This causes the photoresist to be patterned into the shape of the upper electrode 40, forming a resist mask.

Next, a film of the material that constitutes the upper electrode 40 is formed, for example, using a vacuum deposition apparatus. More specifically, a film of AuGe/Ni/Au or Au/Ge/Au, which is the material of the film that constitutes the first upper electrode 41, is formed. Next, after the photoresist is peeled off, a heat treatment (annealing treatment) is performed, for example, at 450°C for 10 minutes. This forms the first upper electrode 41.

This heat treatment forms an alloy layer 35 at the interface between the first upper electrode 41 and the second cladding layer 27, which is an alloy of the metal material constituting the first upper electrode 41 and the semiconductor material constituting the second cladding layer 27 (see FIG. 3A). Since Al, Ga, In, As, P, etc., which may be considered as semiconductor materials constituting the second cladding layer 27, are not used as the metal material constituting the first upper electrode 41, the presence of the alloy layer 35 can be detected by performing composition analysis using, for example, XRF, etc., on the region including directly below the first upper electrode 41.

Next, the second upper electrode 42 is formed at a predetermined position on the upper surface of the first upper electrode 41. More specifically, the Ti film material constituting the adhesion layer 45 and the Ti/Au, Ti/Pt/Au, etc. film material constituting the second upper electrode 42 are formed using a vacuum deposition device, and then a lift-off process is performed (see Figures 1 and 2).

(Later process)
After step S7, for example, the following steps are executed. Note that the following steps can be appropriately interchanged.

Wet etching is performed on the surface of the second cladding layer 27 where the upper electrode 40 is not formed, forming the uneven portion 27a. Then, mesa etching is performed to separate each element. Specifically, the non-etched areas of the surface of the second cladding layer 27 are masked with a resist patterned by photolithography, and wet etching is performed with a mixture of bromine and methanol. This removes a part of the semiconductor laminate 20 located in the unmasked area (see FIG. 1).

After the thickness of the back side of the support substrate 11 is adjusted, a back electrode 33 is formed on the back side of the support substrate 11. As a specific method for forming the back electrode 33, similar to the upper electrode 40, the back electrode 33 can be formed by depositing a film of the material for forming the back electrode 33 (e.g., Ti/Pt/Au) using a vacuum deposition device and then lifting it off.

The adjustment of the thickness of the back side of the support substrate 11 can be performed as necessary and is not necessarily a required step. The thickness is also appropriately set depending on the application, etc.

Then, the support substrate 11 is diced together to create chips.

Then, bonding wires are attached to the second upper electrodes 42 of each chip.

[Verification 1]
In step S7, a plurality of types of infrared LED element samples #A1 to #A4, and #B1 were manufactured by performing each step under the same conditions except that the heating conditions in the heating step performed when forming the first upper electrode 41 were changed. Sample #B1 is a sample manufactured without carrying out the heat treatment in step S7, and differs from the other samples (#A1 to #A4) in that it does not have an alloy layer 35. A plurality of each of samples #A1 to #A4, and #B1 (approximately 1000 pieces) were manufactured under the same manufacturing conditions.

For each of samples #A1 to #A4, the average thickness of the alloy layer 35 was measured based on the SEM image. The average thickness was determined by averaging the thickness of the alloy layer 35 at multiple measurement points that were evenly spaced every 1 μm within a 15 μm square area of each SEM image. The respective average thicknesses are shown in Table 1 below. Note that for sample #B1, the average thickness is 0 nm, since no alloy layer 35 is present. To be sure, the fact that sample #B1 does not have an alloy layer 35 was also confirmed by the SEM image.

During the wire bonding process, the percentage of samples in which the upper electrode 40 was pulled by the wire and peeled off (peeling rate) was measured. The results are shown in Table 1.

According to Table 1, for sample #B1, in which the alloy layer 35 is not formed, peeling of the upper electrode 4 occurred in 8 of the 1,000 elements. In contrast, peeling of the upper electrode 40 was not confirmed in any of the elements belonging to samples #A1 to #A4, in which the alloy layer 35 is formed. From this result, it can be seen that peeling of the upper electrode 40 during the wire bonding process can be suppressed by performing a heating process when forming the first upper electrode 41 to increase the adhesion between the second cladding layer 27 and the upper electrode 40.

[Verification 2]
The same forward current (20 mA) was supplied to the elements belonging to each sample (#A1 to #A4, #B1) in which peeling of the upper electrode 40 did not occur, and the elements were turned on to measure the relationship between the light output and the average film thickness of the alloy layer 35, and the relationship between the forward voltage and the average film thickness of the alloy layer 35. The results are shown in Figures 5 and 6. The light output shown in Figure 5 was measured using an integrating sphere.

Figure 5 shows that samples #A3 and #A4, in which the average thickness of the alloy layer 35 is 270 nm or more, have a significantly reduced light output compared to samples #A1 and #A2, in which the average thickness is 150 nm or less. It can also be seen that samples #A1 and #A2 have a light output that is almost the same as sample #B1, in which the alloy layer 35 is not formed.

From these results, it is inferred that in the case of sample #A3 and sample #A4, the thickness of the alloy layer 35 present inside is large, so the amount of infrared light L absorbed within the alloy layer 35 is relatively large, resulting in a relative decrease in light output.

On the other hand, according to FIG. 6, samples #A1 and #A2, in which the average thickness of the alloy layer 35 is 150 nm or less, show forward voltages equivalent to samples #A3 and #A4, in which the average thickness of the alloy layer 35 is 270 nm or more. Sample #B1, in which the alloy layer 35 is not provided, has a significantly higher forward voltage than samples #A1 and #A2. From this result, it can be seen that even if the thickness of the alloy layer 35 is made somewhat thin, the effect of reducing the forward voltage can be obtained compared to a configuration in which no alloy layer 35 is provided at all. It can also be seen that the effect of reducing the forward voltage is not significantly increased even if the thickness of the alloy layer 35 is made thicker.

In view of the above results, it can be seen that an infrared LED element 1 having an alloy layer 35 with an average thickness of 150 nm or less can increase light output while simultaneously suppressing peeling of the upper electrode 40 and suppressing an increase in forward voltage. Furthermore, the above verification shows that it is more preferable for the average thickness of the alloy layer 35 to be 50 nm to 150 nm.

[Another embodiment]
7, the infrared LED element 1 may include, on the upper layer of the second cladding layer 27, a contact layer 28 that is doped with a dopant at a higher concentration than the second cladding layer 27. When the second cladding layer 27 is an n-type semiconductor layer as in the above embodiment, the contact layer 28 is also made of an n-type semiconductor layer. In this case, the second cladding layer 27 and the contact layer 28 correspond to the "second semiconductor layer."

As an example, the contact layer 28 is made of n-type InP. The thickness of the contact layer 28 is not limited, but is, for example, 10 nm to 1000 nm, and preferably 50 nm to 500 nm. The n-type dopant concentration of the contact layer 28 is preferably 5×10 ¹⁷ /cm ³ to 1×10 ¹⁹ /cm ³ , and more preferably 1×10 ¹⁸ /cm ³ to 5×10 ¹⁸ /cm ³ .

The infrared LED element 1 shown in FIG. 7 is manufactured in the same manner as described above, except that in step S1, in the epitaxial process described above, the contact layer 28 is formed before the formation of the second cladding layer 27.

1: Infrared LED element 3: Growth substrate 11: Support substrate 13 (13a, 13b): Bonding layer 15: Reflecting layer 16: Conductive layer 17: Insulating layer 20: Semiconductor laminate 21: Contact layer 23: First cladding layer 25: Active layer 27: Second cladding layer 27a: Concave and recessed portion 28: Contact layer 31: Internal electrode 33: Back electrode 35: Alloy layer 40: Upper electrode 41: First upper electrode 42: Second upper electrode 45: Adhesion layer L: Infrared light

Claims (6)

An infrared LED element having a peak emission wavelength of 1000 nm or more,
A conductive supporting substrate;
A conductive layer formed on the upper layer of the support substrate;
an insulating layer formed on the conductive layer;
a p-type or n-type first semiconductor layer formed on the insulating layer;
an active layer formed on the first semiconductor layer;
a second semiconductor layer formed on the active layer and having a different conductivity type from the first semiconductor layer;
internal electrodes that penetrate the insulating layer at a plurality of positions distributed in a direction parallel to a main surface of the support substrate and electrically connect the first semiconductor layer and the support substrate;
an upper electrode formed on the second semiconductor layer;
an alloy layer formed at an interface between the second semiconductor layer and the upper electrode, the alloy layer being made of an alloy of a material constituting the upper electrode and a material constituting the second semiconductor layer, the alloy layer having an average film thickness of 150 nm or less. The infrared LED element of claim 1, characterized in that the second semiconductor layer contains InP. the second semiconductor layer includes a cladding layer located on the active layer side, and a contact layer located above the cladding layer and having at least one of a composition and a dopant concentration different from that of the cladding layer;
3. The infrared LED element according to claim 1, wherein the material of the contact layer has a band gap energy higher than the light energy of the peak emission wavelength. The infrared LED element according to claim 1 or 2, characterized in that the alloy layer is made of a material containing Ge. 3. The infrared LED element according to claim 1, wherein the second semiconductor layer has a dopant concentration of 5×10 ¹⁷ /cm ³ to 5×10 ¹⁸ /cm ³ at a portion adjacent to the alloy layer. The infrared LED element according to claim 1 or 2, characterized in that the area occupied by the upper electrode is 20% or less of the area occupied by the second semiconductor layer when viewed in a direction perpendicular to the main surface of the support substrate.

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