JP7640902B2 - Digital signal processing device and coherent digital signal processing device - Google Patents

Description

The present invention relates to a digital signal processing device and a coherent digital signal processing device.

As demand for data communication increases, optical transmission networks using optical signal modulation technology and optical signal multiplexing technology that enable the transmission of large volumes of traffic are becoming more widespread. In particular, digital coherent technology, which combines coherent detection and digital signal processing technology, has become widely used in ultra-high-speed optical transmission systems with a transmission speed of 200 Gb/s or more per wave. On the other hand, with the spread of large-volume data communication by mobile terminals, as typified by LTE (Long Term Evolution), there is a demand for realizing ultra-high-speed optical transmission of 200 Gb/s at a lower cost, i.e., with a simpler transceiver configuration.

Direct detection, which demodulates data signals based on optical signal intensity information, is a method for achieving ultra-high-speed optical transmission of 200 Gb/s with a simple transceiver configuration. In particular, research is underway into ultra-high-speed optical transmission methods that use 4-level intensity modulation (PAM4: 4-level Pulse Amplitude Modulation), which has higher frequency utilization efficiency than the 2-level intensity modulation method NRZ (Non Return-to-Zero).

In 200 Gb/s-class optical transmission using digital coherent technology, which has been put to practical use as a long-distance transmission technology, polarization multiplexed QPSK modulation (PDM-QPSK) is generally used, with a modulation speed of about 50 Gbaud. On the other hand, when implementing ultra-high-speed optical transmission of 200 Gb/s class using PAM4, which can be realized with the above-mentioned simple transceiver configuration, the modulation speed is about 100 Gbaud, so the signal spectrum occupies a wider frequency range than the PDM-QPSK method. This means that the 200 Gb/s-class PAM4 method is more susceptible to waveform degradation due to filtering caused by the band of electro-optical devices than the PDM-QPSK method.

To solve this problem, a technology has been proposed that improves the tolerance to waveform degradation caused by the bandwidth limitations of electro-optical devices by performing symbol determination using maximum likelihood sequence estimation (MLSE) when performing digital signal processing on the receiving side (Non-Patent Document 1). In this method, all candidate symbol sequences assumed to be transmitted symbol sequences are input to a transmission path simulation filter that performs the same processing on the candidate symbol sequences as in the transmission path, and the likelihood of each candidate symbol sequence is calculated by comparing the output of the transmission path simulation filter with the received symbol sequence. By estimating the sequence with the maximum likelihood as the transmitted symbol sequence, signal demodulation with high demodulation performance is achieved even in a severely bandwidth-limited environment.

D. D. Falconer, et al., ‘Adaptive channel memory truncation for maximum likelihood sequence estimation,’ The Bell System Technical Journal, vol. 52, no. 9, pp. 1541 - 1562 (1973)

However, in MLSE, in principle, all candidate symbol sequences assumed as transmission symbol sequences must be input to the transmission channel simulation filter, and the likelihood of each candidate symbol sequence must be calculated. The length of the candidate symbol sequence is determined by the number of multi-values of the symbol and the number of taps of the transmission channel simulation filter. If the length of the candidate symbol sequence is L, the number of multi-values of the symbol is M, and the number of taps of the transmission channel simulation filter is D, then L can be expressed using M and D as follows:

Therefore, the number of candidate symbol sequences becomes very large when the number of taps D of the transmission channel simulation filter is large. For example, in the case of a PAM4 signal with M=4, in order to use a 15-tap (D=15) transmission channel simulation filter, it is necessary to calculate the likelihoods of L=4 ¹⁶ ≈4×10 ⁹ candidate symbol sequences, which results in a huge amount of calculation.
An object of the present invention is to provide a digital signal processing device capable of reducing the amount of calculation in MLSE.

One aspect of the present invention is a digital signal processing device comprising: a waveform shaping filter unit that performs digital filter processing on received symbols generated by equalizing a received signal and outputs the results of the processing; a candidate symbol generation unit that generates candidate symbols assumed to be transmitted symbols before modulation of the received signal; a transmission path simulation filter unit that performs digital filter processing on the candidate symbols and determined symbols that have previously been determined to be transmitted symbols and outputs the results of the processing; a symbol likelihood calculation unit that calculates the likelihood of a symbol value represented by the received symbol based on the output of the waveform shaping filter unit and the output of the transmission path simulation filter unit; and a symbol determination unit that determines a transmitted symbol based on the likelihood of the symbol value calculated by the symbol likelihood calculation unit.

One aspect of the present invention is a digital signal processing device comprising: a waveform shaping filter section that performs digital filter processing on a received symbol and outputs the result of the processing; a transmission path simulation filter section that performs digital filter processing on a decision symbol, which is an estimate of a past received symbol, and outputs the result of the processing; and a symbol decision section that decides a transmitted symbol by making a hard decision based on a threshold decision on a received symbol estimate calculated based on the output of the waveform shaping filter section and the output of the transmission path simulation filter section.

According to the present invention, the amount of calculations required in MLSE can be reduced.

FIG. 1 is a diagram showing a configuration of an optical signal demodulator 1. 1 is a diagram showing a configuration of a digital signal processing device 4 according to a first embodiment. FIG. 2 illustrates an example of the configuration of a digital equalization unit 10. FIG. 2 is a diagram illustrating an example of the configuration of a waveform shaping filter unit 12. 2 is a diagram illustrating an example of the configuration of a transmission path simulation filter unit 16 according to the first embodiment. FIG. 4 shows experimental results of the digital signal processing device 4 according to the first embodiment. 4 shows experimental results of the digital signal processing device 4 according to the first embodiment. 4 shows experimental results of the digital signal processing device 4 according to the first embodiment. 4 shows experimental results of the digital signal processing device 4 according to the first embodiment. FIG. 11 is a diagram illustrating a transmission path simulation filter unit 16 according to a second embodiment. FIG. 13 is a diagram showing a configuration of a digital signal processing device 4 according to a third embodiment. FIG. 13 is a diagram showing a configuration of a digital signal processing device 4 according to a fourth embodiment. FIG. 2 is a diagram showing a configuration of a coherent digital signal processing device 5.

[Overall configuration]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
1 is a diagram showing the configuration of an optical signal demodulator 1. The optical signal demodulator 1 receives an optical signal from an optical signal modulator (not shown). The optical signal demodulator 1 demodulates the transmitted optical signal to determine the transmitted symbol before being modulated by the optical signal modulator.
The optical signal demodulator 1 includes an optical receiver 2 , an AD converter 3 , and a digital signal processing device 4 .

The optical receiver 2 receives an optical signal and converts the received optical signal into an electrical signal. In a direct detection system, the optical receiver 2 is an optical intensity receiver. The AD converter 3 converts the electrical signal input from the optical receiver 2 into a digital signal. The digital signal processing device 4 performs symbol determination based on the digital signal input from the AD converter 3.

First Embodiment
FIG. 2 is a diagram showing the configuration of a digital signal processing device 4 according to the first embodiment.
The digital signal processing device 4 includes a digital equalizer 10 , a waveform shaping filter 12 , a candidate symbol generator 14 , a transmission path simulation filter 16 , a transition likelihood calculator 18 , a symbol likelihood calculator 20 , and a decision symbol determiner 22 .

The digital equalizer 10 performs digital equalization processing on the digital signal. The digital equalizer 10 is, for example, an FFE (Feed Forward Equalizer). FIG. 3 is a diagram showing an example of the configuration of the digital equalizer 10. The number of taps of the digital equalizer 10 shown in FIG. 3 is two, but is not limited to this. The digital equalizer 10 includes a delayer 102, a multiplier 104, and an adder 106. The delayer 102 stores an input signal and outputs the stored input signal after a certain time. The multiplier 104 multiplies the input signal by a predetermined value. The multiplier 124-i (i is an integer between 1 and 3) multiplies the input signal t _n-i by a tap coefficient b _i . The adder 106 adds two input signals.

Assume that at time n, signal t _n is input to digital equalization unit 10. Assume also that at time n, signal t _n-1 is stored in delay unit 102-1, and signal t _n-2 is stored in delay unit 102-2. Multiplier 104-1 multiplies input t _n by b ₀ and outputs t _n ×b _0. Multiplier 104-2 multiplies input t _{n- 1} by b 1 and outputs t _n-1 ×b _1. Multiplier 104-3 multiplies input t _n-2 by b ₂ and outputs t _n-2 ×b _2. Adder 106-1 adds input t _n ×b ₀ and t _n-1 ×b ₁ , and outputs t _n ×b ₀ +t _n-1 ×b ₁ . Adder 106-2 adds input _tn × _b0 +tn _-1 × _b1 and tn _-2 × _b2 , and outputs _tn × _b0 +tn _-1 × _b1 +tn _-2 × _b2 . Therefore, received symbol _sn output by digital equalization unit 10 is expressed as _sn = _tn × _b0 +tn _-1 × _b1 +tn _-2 × _b2 .

The waveform shaping filter unit 12 performs digital filtering on the received symbol s _i by convolution and outputs a filtered value y _n . The waveform shaping filter unit 12 is, for example, a finite impulse response (FIR) filter. FIG. 4 is a diagram showing an example of the configuration of the waveform shaping filter unit 12. The number of taps of the waveform shaping filter unit 12 shown in FIG. 4 is three, but is not limited to this. The waveform shaping filter unit 12 includes a delay unit 122, a multiplier 124, and an adder 126. The delay unit 122, the multiplier 124, and the adder 126 have the same functions as the delay unit 102, the multiplier 104, and the adder 106 included in the digital equalization unit 10, respectively. The multiplier 124-i (i is an integer between 1 and 4) multiplies the input received symbol s _n-i by a tap coefficient c _i .

The process performed by the waveform shaping filter unit 12 on the input s _i is the same as the process performed by the digital equalization unit 10 on t _i . Therefore, the filtered value y _n output by the waveform shaping filter unit 12 is expressed as y _n = s _n × c ₀ + s _n-1 × c ₁ + s _n-2 × c ₂ + s _n-3 × c ₃ .
Here, if the number of taps is C, _yn is expressed by the following equation.

The candidate symbol generator 14 generates candidate symbols r _n . The candidate symbols r _n are symbols assumed to be transmitted symbols, and in the case of the PAM4 system, for example, the candidate symbol generator 14 generates four candidate symbols r _n (r _n =0, 1, 2, 3).

The transmission channel simulation filter unit 16 performs digital filtering using a convolution operation on the candidate symbol r _n and the decision symbol x _n to output a simulated filter processing value z _n . The decision symbol used by the transmission channel simulation filter unit 16 is a symbol previously determined to be a transmission symbol. The decision symbol will be described in detail later. The transmission channel simulation filter unit 16 is, for example, a finite impulse response (FIR) filter similar to the waveform shaping filter unit 12. FIG. 5 is a diagram showing an example of the configuration of the transmission channel simulation filter unit 16 according to the first embodiment. In the transmission channel simulation filter unit 16 shown in FIG. 5, the number of taps related to the candidate symbol r _n is 1, and the number of taps related to the decision symbol x _n is 2, but is not limited to this. The transmission channel simulation filter unit 16 includes a delay unit 162, a multiplier 164, and an adder 166. The delay unit 162, the multiplier 164, and the adder 166 have the same functions as the delay unit 102, the multiplier 104, and the adder 106 provided in the digital equalization unit 10, respectively, except for the following points.

When delay units 162-1 and 162-3 store input symbols and output the stored input signals after one second, delay unit 162-2 stores input symbols and outputs the stored input signals after two seconds. In other words, delay unit 162-2 delays the signal twice as much as delay units 162-1 and 162-3. Furthermore, multiplier 164-i (i is an integer between 1 and 4) multiplies the input signal by tap coefficient d _i .

At time n, it is assumed that a candidate symbol r _n is input to a delay unit 162-1, and a symbol decision value x _n is input to a delay unit 162-2. Also, at time n, r _n is input to a multiplier 164-1, r _n-1 is input to a multiplier 164-2, x _n-2 is input to a multiplier 164-3, and x _n-3 is input to a multiplier 164-4. Here, the simulated filter processing value z _n output by the transmission path simulation filter unit 16 is expressed as z _n = r _n × d ₀ + r _n-1 × d ₁ + x _n-2 × d ₂ + x _n-3 × d ₃ .

Here, if the number of taps is D and the number of taps related to the candidate symbol r _n is generalized as R (that is, the number of taps related to the decision symbol x _n is D−R), the simulated filter processed value z _n is expressed by the following equation.

Since the number of taps related to the candidate symbol r _n and the number of taps related to the decision symbol x _n are not limited to the above numbers (D=2, R=1), the candidate symbol r _n and the decision symbol used to calculate the simulated filter processing value z _n are also not limited to this. For example, z _n may be calculated using one candidate symbol (only r _n ) or three candidate symbols (r _n , r _n-1 , r n _-2 ). In addition, the candidate symbols used do not have to be consecutive symbols. For example, two symbols r _n and r _n-2 of the candidate symbols may be used to calculate z _n , and r _n-1 may not be used.

The transition likelihood calculation unit 18 calculates the likelihood for each candidate symbol sequence (hereinafter, symbol sequence likelihood) based on the filtered value and the simulated filtered value. Here, the candidate symbol sequence is a combination of candidate symbols used to calculate the simulated filtered value, and is (r _n , r _n-1 ). The symbol sequence likelihood l is calculated, for example, by the following formula:

The symbol sequence likelihood l calculated by the above formula corresponds to the logarithm of the inverse of the likelihood, so the smaller the value, the higher the likelihood. Since _{r n-1} and r _n each take four values and there are 16 (=4 ² ) combinations of r _n-1 and r _n , there are 16 possible values of l.

The symbol likelihood calculation unit 20 calculates the likelihood (symbol value likelihood) for each candidate symbol based on the symbol sequence likelihood. The symbol value likelihood is calculated, for example, by the following formula:

In the above equation, the right-hand side is the minimum value that the equation in parentheses can take when r _n-1 is changed. The symbol value likelihood calculated by the above equation corresponds to the logarithm of the inverse of the likelihood, and therefore the smaller the value, the higher the likelihood. When r _n is fixed and r _n-1 is changed, the symbol likelihood calculation unit 20 calculates, as the symbol value likelihood m at time n, the sum of l calculated by the transition likelihood calculation unit 18 and the symbol value likelihood m calculated by the symbol likelihood calculation unit at time n-1 according to the above equation. Thus, there are four types of symbol value likelihood, the same as the number of values that r _n can take.

The decision symbol determination unit 22 determines a decision symbol x _n based on the symbol value likelihood. The symbol decision value x _n is determined, for example, by the following formula.

In the above equation, the right-hand side is the value of _rn when the equation in parentheses takes a minimum value when _rn is changed. That is, the decision symbol determination unit 22 determines the candidate symbol _rn when the symbol value likelihood at time n takes a minimum value as the decision symbol. In this way, a symbol decision value _xn is determined. The _xn determined by the decision symbol determination unit 22 is input to the transmission path simulation filter unit 16 and used to calculate _zn . In addition, the _xn determined by the decision symbol determination unit 22 is output to the outside as a demodulation result of the optical signal received by the optical signal demodulator 1. That is, the decision symbol determination unit 22 is an example of a symbol decision unit that determines a transmission symbol based on the symbol value likelihood.

<Experimental Results>
6 and 7 show experimental results of the digital signal processing device 4 according to the first embodiment.
The graph shown in FIG. 6 shows the relationship between the received optical power and the bit error rate (BER) under four different conditions. The four different conditions are roughly divided into a "comparative example" and an "embodiment". In the "comparative example", the digital signal processing device 4 includes only the digital equalizer 10, and outputs a signal that has been digitally equalized by the digital equalizer 10 as a demodulation result of the optical signal. In the "embodiment", the digital signal processing device 4 is the same as that of the first embodiment. In the "embodiment", the number of taps C of the waveform shaping filter 12 and the number of taps D of the transmission line simulation filter 16 were both changed to 3, 9, and 16, and an experiment was performed. In the transmission line simulation filter 16 in the "embodiment", the number of taps related to the candidate symbol is 1. In the experiment, the transmission speed per wave is 186 Gb/s, and the PAM4 method is used.

As shown in Figure 6, it can be seen that the BER is reduced by applying the digital signal processing device 4 of the first embodiment.

The graph shown in Figure 7 shows the relationship between the number of taps C of the waveform shaping filter section 12 and the BER. Here, the number of taps D of the transmission path simulation filter section 16 is 9. As shown in Figure 7, it can be seen that the BER increases when C is set to a value less than D (= 9). From the above, it can be seen that in order to reduce the BER, it is desirable for the number of taps of the waveform shaping filter section 12 to be equal to or greater than the number of taps of the transmission path simulation filter section 16.

8 and 9 show experimental results of the digital signal processing device 4 according to the first embodiment.
The experimental results shown in Figures 8 and 9 are different from those shown in Figures 6 and 7 in that the number of taps related to the candidate symbols in the transmission path simulation filter unit 16 is 0. That is, in the transmission path simulation filter unit 16, only r _n is used as the candidate symbol, and x _n-1 to x _n-D+1 are used as the decision symbols. Other than the above conditions, there is no difference between the experiments shown in Figures 8 and 9 and those shown in Figures 6 and 7.

From the experimental results shown in Figures 8 and 9, it can be seen that even when only one candidate symbol is used, the BER is reduced, as in the experimental results shown in Figures 6 and 7, and that it is desirable for the number of taps of the waveform shaping filter section 12 to be greater than or equal to the number of taps of the transmission path simulation filter section 16.

<Action and Effects>
As described above, according to this embodiment, in MLSE, the number of candidate symbols is reduced by using decision symbols, thereby making it possible to reduce the amount of calculation.

The digital equalization unit 10 may update the number of taps. For example, the digital equalization unit 10 updates the number of taps so that the difference between the sequence of received symbols and the signal obtained by hard-judging the sequence of received symbols is minimized. Also, for example, the digital equalization unit 10 updates the number of taps so that the difference between the sequence of received symbols and the sequence of known pilot symbols is minimized.

Furthermore, the tap coefficient c _i of the waveform shaping filter unit 12 and the tap coefficient d _i of the transmission channel simulation filter unit 16 may be updated. c _i and d _i are updated so that the value of l becomes minimum. In other words, c _i and d _i are updated so that the likelihood becomes maximum. The value of l becomes minimum when r _n-1 is x _n-1 and r _n is x _n , so c _i and d _i are updated so that the value of l at this time becomes smaller. For example, c _i and d _i are updated to the values of the following formulas using an LMS (Least Mean Square) algorithm.

That is, the product of μ, E, and s _n-1 is subtracted from c _{i ,} and the product of μ, E, and x _n-1 is added to d _i , thereby updating c _i and d _i .

Here, μ is the step size parameter set in the LMS algorithm. E is the value expressed by the following formula:

In addition, the decision symbol input to the transmission path simulation filter unit 16 may be a pilot symbol.

Although the four symbol values 0, 1, 2, and 3 have been used as examples, this is not limited to this. For example, the four values -1, -1/3, 1/3, and 1 are also acceptable. Furthermore, the symbol values are not limited to four values. For example, in the NRZ format, the symbol values can only have two values.

Second Embodiment
In addition to the functions of the decision symbol determination unit 22 according to the first embodiment, the decision symbol determination unit 22 according to the second embodiment determines the ranking of symbol values based on the likelihood of the symbol values. The symbol values are ranked higher when the probability that the symbol value is a received symbol is higher. The decision symbol determination unit 22 according to the second embodiment determines the first-ranked symbol value x _n (1) by the following formula:

Here, the first-order symbol value x _n (1) is the same as the decision symbol in the first embodiment. Furthermore, the decision symbol determination unit 22 according to the second embodiment determines the second-order symbol value x _n (2) by the following formula:

That is, the second-ranked symbol value x _n (2) is the most likely symbol value excluding x _n (1). A symbol that can take one of the two values x _n (1) and x _n (2) is called a ranked symbol and is represented as r′ _n .

10 is a diagram showing the transmission path simulation filter unit 16 according to the second embodiment. In the transmission path simulation filter unit 16 according to the second embodiment, a ranked symbol _r'n is input to a delay device 162-1. At this time, the simulated filter processing value _zn is expressed as _zn = _rn x _d0 + r'n _-1 x _d1 + _xn-2 x _d2 + _xn-3 x _d3 .

Here, if the number of taps is D and the number of taps related to the ranked symbol r′ _n is 1, then
_zn is expressed by the following formula.

The transition likelihood calculation unit 18 calculates the likelihood l for each candidate symbol sequence using the following formula:

In the first embodiment, r _n-1 takes four values, {0, 1, 2, 3}, whereas in the second embodiment, r' _n-1 takes two values, {x _n (1), x _n (2)}. As a result, whereas the symbol sequence likelihood l was 16 in the first embodiment, the symbol sequence likelihood l is reduced to 8 in the second embodiment. This makes it possible to reduce the amount of calculations compared to the first embodiment.

The symbol likelihood calculation unit 20 calculates the likelihood for each candidate symbol using the following formula:

Since r'n _-1 takes two values, m takes four values. Hereinafter, the method of determining the symbol decision value by the decided symbol decision section 22 in the second embodiment is the same as the method in the first embodiment.

The ranking of the symbol value determined by the judged symbol determination unit 22 is not limited to first and second. For example, the ranking may be determined from first to third. In this case, the ranked symbol _r'n can take three values.

Third embodiment
FIG. 11 is a diagram showing the configuration of a digital signal processing device 4 according to the third embodiment.
In the digital signal processing device 4 according to the third embodiment, the candidate symbol generating section 14 determines a symbol candidate value r _n ′ based on the received symbol s _n output by the digital equalizing section 10 .

The candidate symbol generation unit 14 according to the third embodiment determines, among the symbol values, two values that have a small difference from s _n as r _n '. For example, when the symbol value can have four values, 0, 1, 2, and 3, and the value of s _n is 1.6, the candidate symbol generation unit 14 determines 2 and 1 as r _n '.

r _n takes two values based on s _n , and r _n-1 takes two values based on s n _-1 . Therefore, the symbol sequence likelihood calculated by the transition likelihood calculation unit 18 takes four values. This makes it possible to reduce the amount of calculations compared to the first embodiment.

Fourth embodiment
FIG. 12 is a diagram showing the configuration of a digital signal processing device 4 according to the fourth embodiment.
The digital signal processing device 4 according to the fourth embodiment includes a digital equalization unit 10, a waveform shaping filter unit 12, a transmission path simulation filter unit 16, a transition likelihood calculation unit 18, and a decision symbol determination unit 22. Unlike the digital signal processing device 4 according to the first embodiment, the digital signal processing device 4 according to the fourth embodiment does not include the candidate symbol generation unit 14 and the symbol likelihood calculation unit 20.

In the fourth embodiment, the transmission path simulation filter unit 16 calculates the simulated filter processed value z _n by using only past decision symbols. The simulated filter processed value z _n is calculated by the transmission path simulation filter unit 16 according to the following formula.

Since _zn is based only on the decision symbol _xn, it takes one value. The transition likelihood calculation unit 18 calculates a received symbol estimate p. The calculation method of the received symbol estimate p is the same as the calculation method of the symbol sequence likelihood l, but the received symbol estimate p takes one value. Ideally, the received symbol estimate p is equal to the value related to the received symbol _s0 . The decision symbol determination unit 22 determines the decision symbol xn by performing hard decision based on a threshold decision on the received symbol estimate p. The decision symbol determination unit 22 determines the received symbol estimate p as ₁ if it is equal to or greater than a predetermined threshold for each bit, and as 0 if it is less than the predetermined threshold, and determines the value corresponding to the decision result for each bit as the decision symbol.

This reduces the amount of calculations compared to the first embodiment.

Fifth embodiment
The digital signal processing device 4 according to the fifth embodiment includes an LLR calculation unit 24 in addition to the digital signal processing device 4 according to the first embodiment. The LLR calculation unit 24 calculates a log-likelihood ratio (bit LLR) of each bit corresponding to a decision symbol. The calculated bit LLR is used, for example, for decoding of forward error correction (FEC).
For example, assume that two bits 00, 01, 11, and 10 are assigned to the four values 0, 1, 2, and 3 in the PAM4 format. If the left bit of the two bits is the most significant bit (MSB) and the right bit is the least significant bit (LSB), the bit LLR values for the MSB and LSB are calculated by the following formula.

Here, the values _P0 to _P3 are likelihoods for each symbol value and are expressed by the following formula:

where σ is the noise power. The bit LLR values for the MSB and LSB can also be calculated simply using the following formula:

Also, in the fourth embodiment, when there is only one candidate filter processing value l, the likelihood for each symbol value is calculated using the following formula:

In this case, the bit LLR value can be easily calculated using the following formula:

<Embodiment for Coherent Detection>
FIG. 13 is a diagram showing the configuration of the coherent digital signal processing device 5. The coherent digital signal processing device 5 includes four digital signal processing devices 4. The coherent digital signal processing device 5 is used in coherent detection. At this time, the optical receiver 2 is a coherent receiver. The digital signal processing device 4 receives four digital signals corresponding to the in-phase component (I component) and the quadrature component (Q component) of the X-polarized wave and the Y-polarized wave, respectively. The digital equalizer 10 performs waveform equalization processing on the input digital signal. The waveform equalization processing is, for example, chromatic dispersion compensation, MIMO adaptive equalization, frequency offset compensation, and carrier phase estimation. After the waveform equalization processing is performed by the digital equalizer 10, four received symbols are output from the digital equalizer 10. The four received symbols are input to the digital signal processing device 4, processed in the same manner as in the first embodiment, and a decision symbol is determined.

The digital signal processing device 4 included in the coherent digital signal processing device 5 is not limited to the digital signal processing device 4 according to the first embodiment. For example, the coherent digital signal processing device 5 may include the digital signal processing device 4 according to the second to fifth embodiments described above.

One embodiment of the present invention has been described in detail above with reference to the drawings, but the specific configuration is not limited to that described above, and various design changes, etc. can be made within the scope that does not deviate from the gist of the present invention.

1...optical signal demodulator, 2...optical receiver, 3...AD converter, 4...digital signal processing device, 5...coherent digital signal processing device, 10...digital equalization section, 12...wave shaping filter section, 14...candidate symbol generation section, 16...transmission path simulation filter section, 18...transition likelihood calculation section, 20...symbol likelihood calculation section, 22...decision symbol determination section, 102, 122, 162...delay device, 104, 124, 164...multiplier, 106, 126, 166...adder

Claims (7)

a waveform shaping filter unit that performs digital filtering on received symbols generated by equalizing a received signal and outputs the filtering result;
a candidate symbol generation unit that generates candidate symbols assumed as transmission symbols before modulation of the received signal;
a transmission path simulation filter unit that performs digital filtering on the candidate symbols and decision symbols that have been previously determined to be transmission symbols, and outputs a result of the filtering;
a symbol likelihood calculation unit that calculates a likelihood of a symbol value represented by the received symbol based on an output of the waveform shaping filter unit and an output of the transmission path simulation filter unit;
a symbol determination unit that determines a transmission symbol based on the likelihood of the symbol value calculated by the symbol likelihood calculation unit;
Equipped with
Digital signal processing device. the symbol decision unit determines a symbol rank indicating which symbol value is a received symbol based on the likelihood of the symbol value;
the candidate symbol generation unit generates the candidate symbols based on the symbol rankings.
2. The digital signal processing device according to claim 1. a symbol soft decision unit for determining a symbol candidate value based on the received symbol;
Further equipped with
the candidate symbol generation unit generates the candidate symbols using the symbol candidate values.
2. The digital signal processing device according to claim 1. the waveform shaping filter unit and the transmission path simulation filter unit change tap coefficients so as to increase the likelihood of the symbol value calculated by the symbol likelihood calculation unit;
A digital signal processing device according to any one of claims 1 to 3. The digital signal processing device according to claim 1, wherein the number of taps of the waveform shaping filter section is equal to or greater than the number of taps of the transmission path simulation filter section. an LLR calculation unit that calculates a log likelihood ratio for each bit corresponding to the decision symbol;
2. The digital signal processing device according to claim 1. A digital signal processing apparatus comprising:
A coherent digital signal processing device, wherein the four digital signal processing devices receive received symbols corresponding to an X-polarized I-channel component, an X-polarized Q-channel component, a Y-polarized I-channel component, and a Y-polarized Q-channel component of a received signal, respectively.

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