JP7647262B2 - Image sensor and image pickup device - Google Patents

Description

The present invention relates to an imaging element and an imaging device.

An image sensor including an AD conversion unit is known (for example, see Japanese Patent Application Laid-Open No. 2003-233633). Conventionally, noise caused by heat generated in the AD conversion unit has been a problem.
Patent Document 1: JP2013-51674A

In a first aspect of the present invention, an imaging element includes a first substrate on which a first pixel block having pixels and a second pixel block adjacent to the first pixel block are arranged, a first circuit block that converts signals output from pixels in the first pixel block into digital signals, and a second circuit block that converts signals output from pixels in the second pixel block into digital signals, and is laminated on the first substrate, and the distance between the first circuit block and the second circuit block is different from the distance between the first pixel block and the second pixel block.

In a second aspect of the present invention, an imaging element includes a first pixel block having pixels, a first substrate on which the first pixel block and the second pixel block are arranged, a first circuit block that converts signals output from pixels in the first pixel block into digital signals, and a second circuit block that converts signals output from pixels in the second pixel block into digital signals, and is laminated on the first substrate, where the first pixel block and the second pixel block are adjacent to each other, and the first circuit block and the second circuit block are not adjacent to each other.

In a third aspect of the present invention, an imaging element includes a first substrate on which a plurality of pixel blocks each having pixels is arranged two-dimensionally, and a second substrate on which a plurality of circuit blocks are arranged, stacked on the first substrate, each of which converts a signal output by at least one of the plurality of pixel blocks into a digital signal, and the arrangement of the plurality of pixel blocks is different from the arrangement of the plurality of circuit blocks corresponding to each of the plurality of pixel blocks.

In a second aspect of the present invention, an imaging device is provided that includes the imaging element.

Note that the above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions.

FIG. 4 is a diagram showing an overview of an image sensor 400 according to the present embodiment. An example of a specific configuration of the pixel unit 110 will be described. 2 shows an example of a circuit configuration of a pixel 112. An example of a more specific configuration of the processing circuit section 210 will be described. 2 illustrates a schematic diagram of the connection relationship between a pixel block 120 and a processing block 220. FIG. 4 is a schematic diagram showing the relationship between brightness of a subject and heat generation. 2A and 2B are schematic diagrams showing other connection relationships between the pixel block 120 and the processing block 220. Another connection relationship between the pixel block 120 and the processing block 222 is shown diagrammatically. Another connection relationship between the pixel block 120 and the processing block 222 is shown diagrammatically. 2 illustrates a schematic diagram of the connection relationship between a pixel block 120 and a processing block 220. FIG. 2 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

In this specification, the X-axis and Y-axis are mutually orthogonal, and the Z-axis is orthogonal to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the image sensor 400. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction is described as a "row" and the arrangement in the Y-axis direction as a "column," but the matrix direction is not limited to this. In addition, the Z-axis direction is the optical axis direction in which light from the subject enters.

Figure 1 is a diagram showing an overview of an image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 includes a first substrate 100 and a second substrate 200. As shown in Figure 1, the first substrate 100 is laminated on the second substrate 200.

The first substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light. The first substrate 100 is sometimes called a pixel chip.

The second substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. The second substrate 200 is sometimes referred to as a signal processing chip.

The processing circuit unit 210 receives the pixel signals output from the first substrate 100. The processing circuit unit 210 processes the input pixel signals. For example, the processing circuit unit 210 performs a process of converting an analog signal into a digital signal. Specifically, the processing circuit unit 210 performs a process of converting the input pixel signals into a digital signal. The processing circuit unit 210 may perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (correlated double sampling).

The processing circuit unit 210 in this example is disposed in a position facing the pixel unit 110 on the second substrate 200. That is, the processing circuit unit 210 is disposed so as to at least partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output a control signal to the pixel unit 110 for controlling the driving of the pixel unit 110.

The peripheral circuit section 230 controls the driving of the processing circuit section 210. The peripheral circuit section 230 is arranged around the processing circuit section 210 on the second substrate 200. The peripheral circuit section 230 may also be electrically connected to the first substrate 100 and control the driving of the pixel section 110.

In addition to the first substrate 100 and the second substrate 200, the imaging element 400 may have a third substrate stacked on the second substrate 200. For example, the third substrate is a memory chip that performs image processing according to the signal output by the second substrate 200. The structure of the imaging element 400 may be either a back-illuminated type or a front-illuminated type. An example of a back-illuminated type will be described below.

Figure 2 shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of the pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

The pixel section 110 has a number of pixel blocks 120 arranged two-dimensionally along the row and column directions. In this example, the pixel section 110 has M×N pixel blocks 120 (M and N are natural numbers). In this example, the case is illustrated where M is equal to N, but M and N may be different.

The pixel block 120 has at least one pixel 112. In this example, the pixel block 120 has m×n pixels 112 (m and n are natural numbers). For example, the pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, the case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has multiple pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of the pixel block 120 is connected to a common control line so that the pixels 112 are set to the same exposure time. In one example, n pixels 112 arranged in the row direction are connected by a common control line.

On the other hand, the exposure times may be different between the multiple pixel blocks 120. That is, the pixels 112 in a pixel block 120 may have the same exposure time, but the pixels 112 in the other pixel blocks 120 may have different exposure times. For example, when the pixels 112 in a pixel block 120 are connected in the row direction by a common control line, the pixels 112 in the other pixel blocks 120 are commonly connected by different control lines.

In this embodiment, one pixel block 120 is arranged for one processing block 220. The connection relationship between the pixel block 120 and the processing block 220 will be described later.

The pixels 112 have a photoelectric conversion function that converts light into an electric charge. The pixels 112 accumulate the electric charge that is generated by photoelectric conversion. The m pixels 112 are arranged in a line in the column direction and connected to a common signal line 122. The m pixels 112 are arranged in n columns in the row direction in the pixel block 120.

In other words, the pixel block 120 is a collection of multiple pixels 112 connected by a common control line. The pixel block 120 can also be said to be the smallest unit of a circuit for multiple pixels 112 for which the same exposure time is set.

Figure 3 shows an example of the circuit configuration of pixel 112. Pixel 112 includes photoelectric conversion unit 104, transfer unit 123, reset unit 126, and pixel output unit 127. Pixel output unit 127 includes amplifier unit 128 and selection unit 129. In this example, transfer unit 123, reset unit 126, amplifier unit 128, and selection unit 129 are described as N-channel FETs, but the type of transistor is not limited to this.

The photoelectric conversion unit 104 has a photoelectric conversion function that converts light into an electric charge. The photoelectric conversion unit 104 accumulates the electric charge that has been photoelectrically converted. The photoelectric conversion unit 104 is, for example, a photodiode.

The transfer unit 123 transfers the charge accumulated in the photoelectric conversion unit 104 to the storage unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charge of the photoelectric conversion unit 104. In other words, the transfer unit 123 serves as a gate, the photoelectric conversion unit 104 serves as a source, and the storage unit 125 serves as a drain, forming a so-called transfer transistor. The gate terminal of the transfer unit 123 is connected to a local transfer control line for each pixel block 120, and a control signal φTX1 is input thereto.

The charge from the photoelectric conversion unit 104 is transferred to the accumulation unit 125 by the transfer unit 123. The accumulation unit 125 is an example of a floating diffusion (FD).

The reset unit 126 discharges the charge in the storage unit 125 to a power supply line to which a predetermined power supply voltage VDD is supplied. The gate terminal of the reset unit 126 is connected to a global reset control line that spans multiple pixel blocks 120, and a reset control signal φRST is input.

The pixel output unit 127 outputs a signal based on the potential of the storage unit 125 to the signal line 122. The pixel output unit 127 has an amplifier unit 128 and a selection unit 129. The amplifier unit 128 has a gate terminal connected to the storage unit 125, a drain terminal connected to a power supply wiring that supplies a power supply voltage VDD, and a source terminal connected to the drain terminal of the selection unit 129.

The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the selection unit 129 electrically connects the pixel 112 and the signal line 122, a pixel signal is output from the pixel 112 to the signal line 122. The gate terminal of the selection unit 129 is connected to a global selection control line across multiple pixel blocks 120 for inputting a selection control signal φSEL. The source terminal of the selection unit 129 is connected to the load current source 121.

The load current source 121 supplies a current to the signal line 122. The load current source 121 may be provided on the first substrate 100 or on the second substrate 200.

Hereinafter, the charge stored in the photoelectric conversion unit 104, the charge transferred to the storage unit 125, and/or the signal based on the potential of the storage unit 125 may be referred to as a pixel signal.

In other words, the pixel 112 includes at least one photoelectric conversion unit 104 and a pixel output unit 127 as a readout unit that reads out an image signal from the at least one photoelectric conversion unit 104 to a signal line 122. The pixel 112 can be said to be the smallest unit of a circuit that outputs a pixel signal that constitutes an image to the signal line 122.

Figure 4 shows an example of a more specific configuration of the processing circuit unit 210. In this example, an enlarged view of the processing circuit unit 210 and the processing block 220 provided in the processing circuit unit 210 is shown.

The processing circuit unit 210 has processing blocks 220 arranged in rows and columns. In this example, the processing circuit unit 210 has M×N processing blocks 220.

In this embodiment, the processing block 220 and the pixel block 120 are arranged in an overlapping position when viewed from the optical axis direction, but the processing block 220 and the pixel block 120 arranged in an overlapping position are not necessarily connected. In this case, the areas of the processing block 220 and the pixel block 120 may be approximately the same, including the margin between adjacent blocks.

The processing block 220 controls the driving of the pixel block 120 to which it is electrically connected. The processing block 220 and the pixel block 120 are sometimes referred to as being electrically connected to each other. For example, the processing block 220 controls the exposure time of the corresponding pixel block 120. The processing block 220 also has a processing circuit such as an AD converter, and processes the signal output by the corresponding pixel block 120. In one example, the processing block 220 converts the analog pixel signal output from the corresponding pixel block 120 into a digital signal. The processing block 220 in this example includes an exposure control unit 10, a pixel driving unit 20, a joining unit 30, a signal conversion unit 40, and a signal output unit 50.

The exposure control unit 10 controls the exposure of the multiple pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixels 112. In one example, the exposure control unit 10 adjusts at least one of the start timing or end timing of the exposure to control the exposure time for each pixel block 120.

The pixel driving unit 20 is electrically connected to the multiple pixels 112. The pixel driving unit 20 selects and drives an arbitrary pixel 112 from the multiple pixels 112 based on a signal from the exposure control unit 10. The image sensor 400 can set the exposure time for each pixel block 120 according to the intensity of the incident light, thereby expanding the dynamic range.

The bonding unit 30 bonds the first substrate 100 and the second substrate 200. The bonding unit 30 inputs the pixel signals input from the first substrate 100 to the signal conversion unit 40. The bonding units 30 are provided corresponding to the n pixels 112 arranged in the row direction, and input the pixel signals to the signal conversion unit 40 for each column.

The signal conversion unit 40 converts the analog signal output by the pixel unit 110 into a digital signal. In this example, the signal conversion unit 40 converts the analog pixel signal into a digital signal. The signal conversion unit 40 sequentially converts the analog signals from m pixels 112 arranged in the column direction into digital signals. The signal conversion unit 40 has n AD converters 42 arranged in the row direction. Each of the AD converters 42 converts analog signals from the pixels 112 in the corresponding column of the corresponding pixel block 120 into digital signals in parallel. This can also be said to be a so-called column ADC method for one pixel block 120.

The signal output unit 50 receives the digital signal from the signal conversion unit 40. In one example, the signal output unit 50 temporarily stores the digital signal. The signal output unit 50 may have a latch circuit for storing the digital signal.

Instead of providing one processing block 220 for one pixel block 120, one processing block 220 may be provided for N pixel blocks 120 (N is a natural number equal to or greater than 2). The N pixel blocks 120 corresponding to one processing block may be referred to as a pixel block group. For example, two pixel blocks 120 arranged side by side in the column direction may be treated as one pixel block group, and one processing block 220 may be provided for each pixel block 120. In this case, the processing block 220 may control the exposure time for each pixel block 120.

In addition, the processing block 220 is electrically connected to at least one pixel block 120, and can be said to be the smallest unit of a circuit that processes pixel signals of the at least one pixel block 120. The processing circuit unit 210 can also be said to be composed of a group of processing blocks 220.

Figure 5 shows a schematic diagram of the connection relationship between the pixel block 120 and the processing block 220. For ease of explanation, Figure 5 shows 4x4 blocks in the pixel section 110 and the processing circuit section 210, and each block is represented in order in the XY directions, such as "1-1" and "1-2."

In the example shown in FIG. 5, the columns with "1" in the X direction, i.e., pixel blocks "1-1", "1-2", "1-3", and "1-4", are connected by connection wiring 250 to processing blocks "1-1", "1-2", "1-3", and "1-4" that overlap in the Z direction, which is the stacking direction. Note that there are n connection wirings 250, which is the number of columns of pixel blocks 120, but only one is shown in the figure as a representative. The connection wiring 250 extends in approximately the Z direction across the boundary surface 102 between the pixel section 110 and the processing circuit section 210.

On the other hand, the columns with "2" in the X direction, i.e. pixel blocks "2-1", "2-2", "2-3" and "2-4", are not connected to the processing blocks "2-1", "2-2", "2-3" and "2-4" that overlap in the Z direction, which is the stacking direction. Instead, pixel block "2-1" is connected to processing block "2-3" that does not overlap in the Z direction. Also, pixel block "2-2" is connected to processing block "2-4" that does not overlap in the Z direction, pixel block "2-3" is connected to processing block "2-1" that does not overlap in the Z direction, and pixel block "2-4" is connected to processing block "2-2" that does not overlap in the Z direction.

The pixel block "2-1" and the processing block "2-3" are electrically connected by a connection wiring 252 that extends in the Z direction across the boundary surface 102 between the pixel section 110 and the processing circuit section 210, and a connection wiring 253 that is connected to the connection wiring 252 and extends within the XY plane of the processing circuit section 210. The other pixel blocks and processing blocks in the column "2" in the X direction are similarly electrically connected by the connection wiring 252, 253.

The connection wirings 252 and 253 are shown as one representative wiring, similar to the connection wiring 250. Furthermore, the connection wiring 253 extending in the XY plane may be provided on the pixel section 110 side, or may be provided on both the pixel section 110 and the processing circuit section 210.

The connection relationship between the pixel blocks and processing blocks in the column with the X direction being "3" is the same as that of the column with the X direction being "1". Furthermore, the connection relationship between the pixel blocks and processing blocks in the column with the X direction being "4" is the same as that of the column with the X direction being "2". In addition, throughout the pixel unit 110 and the processing circuit unit 210, the connection relationship between the pixel blocks and processing blocks with the X direction being "1" and the connection relationship between the pixel blocks and processing blocks with the X direction being "2" are treated as one unit, and the connection relationships are repeatedly applied in the X and Y directions. Note that some of the repetitions may have different connection relationships.

In the connection relationship between the pixel blocks and the processing blocks shown in FIG. 5, for example, pixel blocks "1-1" and "2-1" are adjacent in the X direction, but the processing blocks "1-1" and "2-3" connected to them are not adjacent in the X direction. Therefore, the connection relationship in FIG. 5 can be said to be an example in which the layout relationship of the multiple pixel blocks is different from the layout relationship of the multiple circuit blocks corresponding to each of the multiple pixel blocks.

In addition, in FIG. 5, when one of the pixel blocks that are connected and overlap with the processing block in the Z direction is focused on, one of the pixel blocks adjacent to that pixel block is connected to a processing block that does not overlap in the Z direction. For example, when one of the pixel blocks adjacent to pixel block "1-1" that is connected and overlaps with the processing block in the Z direction is focused on, pixel block "2-1" is connected to processing block "2-3" that does not overlap in the Z direction.

Figure 6 is a schematic diagram showing the relationship between the brightness of a subject and heat generation. Figure 6 shows the connection relationship in Figure 5 on the XY plane.

For example, let's say that light from a bright subject is incident across pixel blocks "1-1," "1-2," "2-1," and "2-2." In addition, subjects often span adjacent pixel blocks like this.

For example, when using a method for expanding the dynamic range in which pixel signals are read out by changing the exposure time or the number of times pixel signals are output for each pixel block, pixel signals from a pixel block where a bright subject is incident may be read out to the processing block more frequently than from other pixel blocks so that the pixels in that pixel block do not become saturated. In this case, in the processing block where readout is frequent, processing such as AD conversion is performed more frequently, resulting in more heat being generated.

According to the embodiment of FIG. 6, the processing blocks "1-1", "1-2", "2-3", and "2-4" are connected to the pixel blocks "1-1", "1-2", "2-1", and "2-2". Therefore, the processing blocks "1-1", "1-2", "2-3", and "2-4" generate a large amount of heat. Here, the processing blocks "1-1" and "1-2" are not adjacent to the processing blocks "2-3" and "2-4" in either the X or Y direction. Therefore, the areas with high heat generation are dispersed overall. This makes it possible to suppress noise in pixel signals caused by heat being transferred to the pixel blocks by concentrating the areas with high heat generation.

Figure 7 shows another schematic diagram of the connection between the pixel block 120 and the processing block 220. In Figure 7, the same components as in Figure 5 are given the same reference numbers and will not be described. Figure 7 is also simplified like Figure 5.

In the example shown in FIG. 7, pixel block "1-1" is connected to processing block "1-1" which overlaps in the Z direction, which is the stacking direction, and processing block "1-3" which does not overlap in the Z direction. In this case, some of the pixels 112 in pixel block "1-1" are connected to processing block "1-1" by connection wiring 255 and connection wiring 256 connected thereto and extending mainly in the Z direction. Meanwhile, some of the other pixels 112 in pixel block "1-1" are connected to processing block "1-3" by connection wiring 255 and connection wiring 257 connected thereto and extending in the X and Y directions as well.

In this case, since the processing block 220 is a column ADC type, it is preferable that the above-mentioned some pixels 112 and the other some pixels 112 are arranged by column. From the viewpoint of dispersing heat, it is also preferable that the number of pixels in the some pixels and the number of pixels in the other some pixels are the same or nearly the same. For example, the pixels 112 in the odd columns of pixel block "1-1" may be connected to processing block "1-1", and the pixels 112 in the even columns of pixel block "1-1" may be connected to processing block "1-3".

In this case, in the figure, n connection wirings 255, n/2 connection wirings 256, and n/2 connection wirings 257 are each shown as one representative. Note that all or part of the connection wirings 257 may be arranged on the pixel section 110 side, as in the case of FIG. 5.

Similarly, pixel block "1-2" is connected to processing block "1-2" which overlaps in the Z direction, which is the stacking direction, and processing block "1-4" which does not overlap in the Z direction. Furthermore, pixel block "1-3" is connected to processing block "1-3" which overlaps in the Z direction, which is the stacking direction, and pixel block "1-1" which does not overlap in the Z direction. Furthermore, pixel block "1-4" is connected to processing block "1-4" which overlaps in the Z direction, which is the stacking direction, and pixel block "1-2" which does not overlap in the Z direction.

In the example shown in FIG. 7, if we look at one processing block, that processing block is connected to two pixel blocks. For example, processing block "1-1" is connected to pixel blocks "1-1" and "1-3". In this case, some of the multiple AD converters 42 in processing block "1-1" are connected to one pixel block "1-1", and some of the other AD converters 42 are connected to the other pixel block "1-3". This allows parallel processing similar to that when pixel blocks and processing blocks are connected one-to-one.

In FIG. 7, throughout the pixel section 110 and the processing circuit section 210, the connection relationships between the pixel blocks "1" to "4" in the Y direction and the processing blocks are treated as one unit, and the connection relationships are repeatedly applied in the X and Y directions. Note that some of the repetitions may have different connection relationships.

The connection relationship between the pixel blocks and processing blocks shown in Figure 7 is such that, for example, pixel block "1-1" overlaps with processing block "1-1" but does not overlap with processing block "1-3," yet is connected to both. Therefore, the connection relationship in Figure 7 can be said to be an example in which the layout relationship of multiple pixel blocks differs from the layout relationship of multiple circuit blocks corresponding to each of the multiple pixel blocks.

In the example of Figure 7, for example, let us say that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, pixel block "1-1" is connected to two processing blocks "1-1" and "1-3", so the heat generated is distributed to these two processing blocks. Furthermore, because these two processing blocks are not adjacent to each other, the area with high heat generation is further distributed.

In addition, looking at the four pixel blocks "1-1", "1-2", "2-1" and "2-2" as a whole, they are connected to eight processing blocks "1-1", "1-2", "1-3", "1-4", "2-1", "2-2", "2-3" and "2-4", and the processing frequency of each processing block is half the frequency of reading out a single pixel block. Therefore, the areas that generate a lot of heat are dispersed overall. This makes it possible to suppress noise in the pixel signal caused by heat being transferred to the pixel blocks by concentrating the areas that generate a lot of heat.

Figure 8 shows a schematic diagram of another connection relationship between the pixel block 120 and the processing block 222. In Figure 8, the same components as those in Figures 5 to 7 are given the same reference numbers and will not be described. Figure 8 is also simplified like Figure 5.

In the example of FIG. 8, two pixel blocks, consisting of the pixel section 110 and the processing circuit section 212 as a whole, are connected to one processing block as one pixel block group. For example, two pixel blocks "1-1" and "1-2" are connected to one processing block "1-1, 2" by a connection wiring 250. In this case, each of the processing blocks 222 has 2n AD converters 42.

Furthermore, pixel blocks "1-1" and "1-2" are connected to processing block "1-1,2" which overlaps in the Z direction, and pixel blocks "1-3" and "1-4" are also connected to processing block "1-3,4" which overlaps in the Z direction. On the other hand, pixel blocks "2-1" and "2-2" are connected to processing block "2-3,4" which does not overlap in the Z direction by connection wiring 252 and 253, and pixel blocks "2-3" and "2-4" are also connected to processing block "2-1,2" which does not overlap in the Z direction.

In FIG. 8, throughout the pixel section 110 and the processing circuit section 210, the pixel blocks in the X direction are numbered from "1" to "4" and the Y direction is numbered from "1" to "2", i.e., the connection relationship between the pixel block group and the processing block is treated as one unit, and the connection relationship is applied repeatedly in the X and Y directions. Note that some of the repetitions may have different connection relationships.

In the connection relationship between the pixel blocks and processing blocks shown in FIG. 8, for example, pixel block "1-1" overlaps with processing block "1-1, 2," but pixel block "2-1" does not overlap with processing block "2-3, 4." Therefore, the connection relationship in FIG. 8 can be said to be an example in which the layout relationship of multiple pixel blocks differs from the layout relationship of multiple circuit blocks corresponding to each of the multiple pixel blocks.

In the example of Figure 8, for example, let us say that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, due to the above connection relationship, the processing frequency is high for processing blocks "1-1, 2" and "2-3, 4". As these two processing blocks are not adjacent to each other, the area with high heat generation is dispersed. This makes it possible to suppress noise in the pixel signal caused by heat being transferred to the pixel block side due to the concentration of the area with high heat generation.

Figure 9 shows another schematic diagram of the connection between the pixel block 120 and the processing block 222. In Figure 9, the same components as those in Figures 5 to 8 are given the same reference numerals and will not be described. Figure 8 is also simplified in the same way as Figure 5.

In the example of FIG. 9, two pixel blocks in the pixel section 110 and the processing circuit section 212 as a whole are connected to two processing blocks as one pixel block group. For example, two pixel blocks "1-1" and "1-2" are connected to two processing blocks "1-1,2" and "1-3,4" by connection wiring 255, 256, and 257.

In this case, each of the processing blocks 222 has 2n AD converters 42. Furthermore, some of the pixels 112 of the two pixel blocks "1-1" and "1-2" are connected to one processing block "1-1,2", and some of the pixels 112 are connected to the other processing block "1-3,4". For example, the pixels 112 in the odd columns of both pixel blocks "1-1" and "1-2" may be connected to one processing block "1-1,2", and the pixels 112 in the even columns of both pixel blocks "1-1" and "1-2" may be connected to the other processing block "1-3,4".

In FIG. 9, throughout the pixel section 110 and the processing circuit section 210, the connection relationships between the pixel blocks "1" to "4" in the X direction and the processing blocks are treated as one unit, and the connection relationships are repeatedly applied in the XY directions. Note that some of the repetitions may have different connection relationships.

The connection relationship between the pixel blocks and processing blocks shown in Figure 9 is such that, for example, pixel block "1-1" overlaps with processing block "1-1,2" but does not overlap with processing block "1-3,4." Therefore, the connection relationship in Figure 9 can be said to be an example in which the layout relationship of multiple pixel blocks differs from the layout relationship of multiple circuit blocks corresponding to each of the multiple pixel blocks.

In the example of Figure 9, for example, assume that light from a bright subject is incident across pixel blocks "1-1", "1-2", "2-1" and "2-2". In this case, due to the above connection relationship, the heat is distributed to four processing blocks with twice the area. Furthermore, the processing frequency in these four processing blocks is half the readout frequency of one pixel block group. Therefore, the areas with high heat generation as a whole are distributed. This makes it possible to reduce noise in the pixel signal caused by heat being transferred to the pixel blocks by concentrating the areas with high heat generation.

Figure 10 shows a schematic diagram of the connection between the pixel block 120 and the processing block 220. In Figure 10, the same components as those in Figure 6 are given the same reference numbers and will not be described.

In FIG. 10, pixel block "1-1" is electrically connected to processing block "1-1." Pixel block "2-1" is electrically connected to processing block "2-3."

Here, the distance L1 between pixel block "1-1" and pixel block "2-1" is different from the distance L2 between the corresponding processing block "1-1" and processing block "2-3". Specifically, the distance L1 is shorter than the distance L2. Here, the distance may be the distance between representative positions in each block, and for example, the representative position may be the geometric center of gravity (also called the center) of each block. Also, if each block is rectangular, it may be one of the corners.

For ease of explanation, the connection relationships between pixel blocks "1-1" and "2-1" and processing blocks "1-1" and "2-3" in FIG. 10 are the same as those in FIG. 6. However, the connection relationships are not limited to those in FIG. 6, and in this embodiment, it is sufficient that the pixel blocks are connected so that the distance between a pixel block of interest and another pixel block is different from the distance between the two corresponding processing blocks.

In addition, in the above distance relationship, the pixel block of interest and the other pixel blocks do not have to be adjacent to each other. Furthermore, if there is at least one pair of a pixel block and a processing block in which the distance between the pixel block of interest and the other pixel block is different from the distance between the two corresponding processing blocks, there may be a pair in which the distance between the other two pixel blocks is the same as the distance between the corresponding processing blocks.

In any of the above embodiments, the pixel 112 may be provided with a discharge section. The discharge section discharges the charge accumulated in the photoelectric conversion section 104 to a power supply wiring to which the power supply voltage VDD is supplied. As another example, the transfer section 123 may be omitted. In that case, the storage section 125 does not function as a floating diffusion. The storage section 125 and the pixel output section 127 may be shared with other pixels. The pixel 112 may be composed of multiple photoelectric conversion sections 104 and transfer sections 123.

Furthermore, in any of the above embodiments, the processing block 220 may not be provided with an exposure control unit 10 and a pixel driving unit 20, and reading may be performed mainly for each processing block 220, and conversion may be performed by the signal conversion unit 40. In this case, the exposure time of the pixels 112 is controlled not for each pixel block 120, but for the entire pixel unit 110.

Fig. 11 is a block diagram showing an example of the configuration of an imaging device 500 according to an embodiment. The imaging device 500 includes an imaging element 400, a system control unit 501, a driving unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a driving unit 514, and a photographing lens 520.

The photographing lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a group of multiple optical lenses, and focuses the subject light beam from the scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. Note that in FIG. 11, the photographing lens 520 is represented by a virtual single lens placed near the pupil.

The driving unit 514 drives the photographing lens 520. In one example, the driving unit 514 moves the optical lens group of the photographing lens 520 to change the focus position. The driving unit 514 may also drive an iris diaphragm in the photographing lens 520 to control the amount of subject light entering the image sensor 400.

The drive unit 502 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 400 according to instructions from the system control unit 501. The operation unit 508 also accepts instructions from the photographer using a release button, etc.

The image sensor 400 passes the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 generates image data that has been subjected to various image processes using the work memory 504 as a workspace. For example, when generating image data in a JPEG file format, a color video signal is generated from the signal obtained in the Bayer array, and then compression processing is performed. The generated image data is recorded in the recording unit 505 and converted into a display signal that is displayed on the display unit 506 for a preset time.

The photometry unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences that generate image data. The photometry unit 503 includes an AE sensor with, for example, about one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each area of the scene.

The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The photometry unit 503 may also be shared by the image sensor 400. The calculation unit 512 also executes various calculations for operating the image capture device 500. The drive unit 502 may be partly or entirely mounted on the image sensor 400. A part of the system control unit 501 may be mounted on the image sensor 400.

The present invention has been described above using an embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiment. It is clear from the claims that forms incorporating such modifications or improvements can also be included in the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before" or "prior to," and it should be noted that the processes may be performed in any order, unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is necessary to perform the processes in this order.

10 Exposure control unit, 20 Pixel driving unit, 30 Joint unit, 40 Signal conversion unit, 42 AD converter, 50 Signal output unit, 100 First substrate, 102 Boundary surface, 104 Photoelectric conversion unit, 110 Pixel unit, 112 Pixel, 120 Pixel block, 121 Load current source, 122 Signal line, 123 Transfer unit, 125 Storage unit, 126 Reset unit, 127 Pixel output unit, 128 Amplification unit, 129 Selection unit, 200 Second substrate, 210, 212 Processing circuit unit, 220, 222 Processing block, 250, 252, 253, 255, 256, 257 Connection wiring, 400 Image sensor, 500 Image pickup device, 501 System control unit, 502 Driving unit, 503 Photometric unit, 504 Work memory, 505 Recording unit, 506 Display unit, 508 Operation unit, 511 Image processing unit, 512 Calculation unit, 514 Drive unit, 520 Shooting lens

Claims (20)

a first substrate on which pixel blocks are arranged in the row and column directions, the pixel blocks including a first photoelectric conversion unit that converts light into electric charges and a second photoelectric conversion unit that converts light into electric charges and is arranged in the row direction alongside the first photoelectric conversion unit;
a second substrate , which is a substrate stacked on the first substrate, and in which processing blocks each including a plurality of conversion units for converting an analog signal into a digital signal are arranged side by side in the row direction and the column direction ;
Equipped with
the processing block includes a first processing block arranged at a position overlapping a first pixel block among the pixel blocks in a stacking direction in which the first substrate and the second substrate are stacked,
the first processing block includes a first conversion unit that converts a signal based on charges converted by the first photoelectric conversion unit of a second pixel block that is disposed at a position different from the first pixel block among the pixel blocks into a digital signal, and a second conversion unit that converts a signal based on charges converted by the second photoelectric conversion unit of the second pixel block into a digital signal;
Image sensor. 2. The imaging device according to claim 1,
the first processing block is disposed at a position not overlapping with the second pixel block in the stacking direction.
Image sensor. 3. The imaging device according to claim 1,
the processing block includes a second processing block disposed at a position overlapping with the second pixel block in the stacking direction;
the second processing block includes a third conversion unit that converts a signal based on the charge converted by the first photoelectric conversion unit of the first pixel block into a digital signal, and a fourth conversion unit that converts a signal based on the charge converted by the second photoelectric conversion unit of the first pixel block into a digital signal.
Image sensor. 4. The imaging device according to claim 3,
the second processing block is disposed at a position not overlapping with the first pixel block in the stacking direction.
Image sensor. 5. The imaging device according to claim 1,
the second pixel block is arranged alongside the first pixel block in the column direction;
Image sensor. 6. The imaging device according to claim 5,
the second pixel block is disposed adjacent to the first pixel block in the column direction.
Image sensor. 3. The imaging device according to claim 1,
the processing block includes a second processing block arranged at a position overlapping a third pixel block arranged at a position different from that of the second pixel block in the stacking direction, among the pixel blocks;
the second processing block includes a third conversion unit that converts a signal based on the charge converted by the first photoelectric conversion unit of the third pixel block into a digital signal, and a fourth conversion unit that converts a signal based on the charge converted by the second photoelectric conversion unit of the third pixel block into a digital signal.
Image sensor. 8. The imaging device according to claim 7,
the second processing block is disposed at a position not overlapping with the first pixel block in the stacking direction.
Image sensor. 9. The imaging device according to claim 7,
the third pixel block is arranged alongside the first pixel block in the column direction;
Image sensor. 10. The imaging device according to claim 9,
the third pixel block is disposed adjacent to the first pixel block in the column direction.
Image sensor. The imaging device according to any one of claims 1 to 10,
the first processing block includes a first exposure control unit that controls an accumulation time for accumulating the electric charge converted by the first photoelectric conversion unit of the first pixel block and an accumulation time for accumulating the electric charge converted by the second photoelectric conversion unit of the first pixel block.
Image sensor. The imaging device according to claim 11,
the first pixel block includes a first transfer unit that transfers charges converted by the first photoelectric conversion unit of the first pixel block, and a second transfer unit that transfers charges converted by the second photoelectric conversion unit of the first pixel block,
the first exposure control unit controls a timing at which the first transfer unit transfers electric charges from the first photoelectric conversion unit of the first pixel block and a timing at which the second transfer unit transfers electric charges from the second photoelectric conversion unit of the first pixel block.
Image sensor. The imaging device according to any one of claims 1 to 10,
the first processing block includes a first exposure control unit that controls an exposure time of the first pixel block;
Image sensor. The imaging device according to claim 13,
the first exposure control unit controls a timing to start exposure of the first pixel block;
Image sensor. 15. The imaging device according to claim 13,
the first exposure control unit controls a timing to end exposure of the first pixel block;
Image sensor. The imaging device according to any one of claims 1 to 15,
An imaging element comprising a third substrate that is stacked on the first substrate and performs image processing on a signal output from the second substrate. The imaging device according to any one of claims 1 to 16,
The second conversion unit is arranged next to the first conversion unit in the row direction.
Image sensor. An imaging device comprising the imaging element according to claim 1 . 20. The imaging device according to claim 18,
an imaging device comprising a drive unit that drives a photographing lens that emits light to the imaging element; 20. The imaging device according to claim 18 or 19,
An imaging device comprising a generation unit electrically connected to the imaging element and configured to generate image data.

Images