JP7649248B2 - Printed wiring board and method for manufacturing printed wiring board - Google Patents

Description

The present disclosure relates to a printed wiring board having a cavity and a method for manufacturing a printed wiring board.

In recent years, with the increasing integration and density of boards and wiring, there are cases where large cavities are created in multilayer boards and electronic components are mounted therein.

JP 2016-122728 A

The printed wiring board of the present disclosure has a multilayer substrate. The multilayer substrate has a core substrate having a first surface and a second surface, a first build-up layer located on the first surface of the core substrate, and a second build-up layer located on the second surface of the core substrate. The multilayer substrate also has a cavity, a first conductor layer, and a second conductor layer. The cavity penetrates the first build-up layer and the core substrate, and the bottom surface is the surface of the second build-up layer, the first conductor layer is located on the bottom surface of the cavity, and the second conductor layer is located within the second build-up layer and overlaps at least a portion of the periphery of the bottom surface of the cavity in a planar perspective.

The method for manufacturing a printed wiring board of the present disclosure includes a first step of preparing a core substrate having a first surface and a second surface, the second step of performing pattern plating on the seed layer provided on the core substrate to form a first conductor layer, a third step of removing a portion of the seed layer from the surface of the seed layer including the first conductor layer of the core substrate such that the seed layer remains in the central portion of the core substrate, which is an area where a cavity is to be formed, and a fourth step of forming a first build-up layer having a first insulating resin layer on the first surface of the core substrate. and a fourth step of forming a second buildup layer having a second insulating resin layer on the second surface of the core substrate. A fifth step of pattern plating the surface of the second buildup layer to form a second conductor layer at a position overlapping at least a portion of the periphery of the bottom surface of the cavity formed in a planar perspective. A sixth step of processing the core substrate from the side of the first buildup layer to penetrate the first buildup layer and the core substrate and form the cavity whose bottom surface is the surface of the second buildup layer.

1 is a cross-sectional view illustrating a configuration of a printed wiring board according to an embodiment. 2 is a cross-sectional view taken along line II-II of FIG. 1. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 4A to 4C are cross-sectional views illustrating a method for manufacturing a printed wiring board according to an embodiment. 1 is a cross-sectional view illustrating an effect of a printed wiring board according to an embodiment. 1 is a cross-sectional view illustrating an effect of a printed wiring board according to an embodiment.

Hereinafter, an embodiment will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of a printed wiring board according to one disclosed embodiment. The printed wiring board shown in FIG. 1 is an example.

The printed wiring board shown as an embodiment has a multilayer substrate 54 as shown below. The multilayer substrate 54 has a core substrate 51, a first buildup layer 61, and a second buildup layer 62. The core substrate 51 has a first surface 51a and a second surface 51b. The first buildup layer 61 and the second buildup layer 62 are laminated on the core substrate 51. The first buildup layer 61 has an insulating resin layer 61a and an insulating resin layer 61b. The second buildup layer 62 has an insulating resin layer 62a and an insulating resin layer 62b.

The first buildup layer 61 is arranged to face the first surface 51a of the core substrate 51. The second buildup layer 62 is arranged to face the second surface 51b of the core substrate 51. The multilayer substrate 54 also has a cavity 20, a first conductor layer 17, and a second conductor layer 12a.

The cavity 20 is open in the multilayer substrate 54 from the first buildup layer 61 side to the core substrate 51. The cavity 20 is provided so that the surface 62aa of the second buildup layer 62 becomes the bottom surface 79.

The first conductor layer 17 is arranged so as to be exposed on the bottom surface 79 of the cavity 20. The second conductor layer 12a is provided on the surface 62ab of the insulating resin layer 62a opposite the core substrate 51.

The second conductor layer 12a is located within the second build-up layer 62. Also, when the multilayer substrate 54 is viewed from above, the second conductor layer 12a is located so as to overlap at least a portion of the peripheral portion 79t of the bottom surface 79 of the cavity 20. In other words, when the multilayer substrate 54 is viewed from above, the second conductor layer 12a is provided at a position corresponding to the peripheral portion 79t of the bottom surface 79 of the cavity 20. With this configuration, even if a cavity 20 with a large volume is provided in the printed wiring board, the printed wiring board can be made less likely to bend.

When a cavity 20 having a large volume and a thin bottom side is formed in the multilayer substrate 54, it is prone to bending at the bottom side 79. The mechanical strength can be increased by inserting a metal member into the peripheral portion 79t of the bottom side 79 of the cavity 20, which is prone to bending. This is due to the high elasticity of the metal member. In this case, the second conductor layer 12a is positioned in a lower layer, separated from the first conductor layer 17 and seed layer 12 exposed at the bottom side 79 of the cavity 20 by a distance of about the thickness of the insulating resin layer 62a.

When the multilayer substrate 54 is viewed in plan, the first conductor layer 17 is located at the center of the bottom surface 79 of the cavity 20, and the second conductor layer 12a is located at the peripheral portion 79t of the bottom surface 79 of the cavity 20. The first conductor layer 17 and the second conductor layer 12a are arranged so as to be separated by about one insulating resin layer in the thickness (stacking) direction of the multilayer substrate 54.

This makes it possible to make the multilayer substrate 54 less likely to bend even when the volume of the cavity 20 is large and the insulating resin layer (62a, 62b) below the cavity 20 is thin. If the second conductor layer 12a were arranged so as to be exposed on the bottom surface 79 of the cavity 20, there is a concern that the multilayer substrate 54 would be more likely to bend and that it would be difficult to ensure electrical insulation between the first conductor layer 17 originally arranged within the cavity 20.

The multilayer substrate 54 will now be described in detail. As shown in FIG. 1, the printed wiring board of this embodiment has a multilayer substrate 54. The multilayer substrate 54 has a core substrate 51, a first buildup layer 61, and a second buildup layer 62.

The core substrate 51 is, for example, a substrate having a seed layer 12 on both sides of a base material 11. The base material 11 is a sheet-shaped molded body made of insulating resin. A conductor layer 16 forming an electrical circuit is formed on one side (top surface) of the core substrate 51.

A conductor layer 17 forming an electrical circuit is formed on the other surface (lower surface) of the core substrate 51. The core substrate 51 has a via 15 connecting the conductor layer 16 and the conductor layer 17.

That is, the multilayer substrate 54 has conductor layers 16 and 17, and a via 15. The via 15 penetrates the insulating resin layer 11 in the thickness direction. The via 15 is disposed between the conductor layers 16 and 17. The conductor layer 16 is disposed so that a portion of it overlaps the seed layer 12 formed on one surface (upper surface) of the substrate 11. The conductor layer 17 is disposed so that a portion of it overlaps the seed layer 12 formed on the other surface (lower surface) of the substrate 11.

The first buildup layer 61 is disposed on the upper surface of the core substrate 51 and has an insulating resin layer 61a and a conductor layer as described below. In the example shown in FIG. 1, the first buildup layer 61 has an insulating resin layer 61a having one surface (lower surface) in contact with the core substrate 51, and an insulating resin layer 61b having one surface (lower surface) in contact with the other surface (upper surface) of the insulating resin layer 61a.

A conductive layer forming an electrical circuit is formed on the upper surface of the insulating resin layer 61a. The insulating resin layer 61a has vias 15 that connect the conductor layer formed on its upper surface to the conductor layer 16 formed on the upper surface of the core substrate 51. The vias 15 are formed so as to penetrate the insulating resin layer 61a in the thickness direction.

A conductor layer 63 is formed on the other surface (top surface) of the insulating resin layer 61b. The insulating resin layer 61b has a via 15 that connects the conductor layer 63 formed on its top surface to the conductor layer formed on the top surface of the insulating resin layer 61a. The via 15 is formed so as to penetrate the insulating resin layer 61b in the thickness direction.

That is, the vias 15 are provided in each of the two first build-up layers 61 arranged on the upper surface side of the core substrate 15.

The second buildup layer 62 is disposed on the other surface (lower surface) of the core substrate 51, and has an insulating resin layer 62a and a conductor layer as described below. In the example shown in FIG. 1, the second buildup layer 62 has an insulating resin layer 62a, one surface (upper surface) of which contacts the core substrate 51, and an insulating resin layer 62b, one surface (upper surface) of which contacts the other surface (lower surface) of the insulating resin layer 62a. Hereinafter, the insulating resin layer 62a may be referred to as the first insulating resin layer 62a. Similarly, the insulating resin layer 62b may be referred to as the second insulating resin layer 62b.

A first conductor layer 17 forming an electric circuit is formed on the upper surface of the insulating resin layer 62a. A conductive layer forming an electric circuit is formed on the other surface (lower surface) of the insulating resin layer 62a. The insulating resin layer 62a has a via 15 that connects the first conductor layer 17 formed on the upper surface and the conductive layer formed on the lower surface. The via 15 is formed so as to penetrate the insulating resin layer 62a in the thickness direction. The via 15 is also formed so as to overlap the first conductor layer 17 in the insulating resin layer 62a in the direction parallel to the surface.

A conductor layer 64 is formed on the other surface (lower surface) of the insulating resin layer 62b. The insulating resin layer 62b has a via 15 that connects the conductor layer 64 formed on the lower surface and the conductive layer formed on the lower surface of the insulating resin layer 62a. That is, the insulating resin layer 62b located at the bottom layer of the multilayer substrate 54 has a via 15. The via 15 is formed so as to penetrate the insulating resin layer 62b in the thickness direction.

1, the via 15 provided in the insulating resin layer 62a and the via 15 provided in the insulating resin layer 62b are in an overlapping state. In the example shown in FIG. 1, the via 15 formed in the second buildup layer 62 is formed within the cavity forming region 65 and directly below the cavity 20. The insulating resin layer 62a and the insulating resin layer 62b are in an overlapping state.

To repeat, the multilayer substrate 54 has a cavity 20. The cavity 20 penetrates the first buildup layer 61 and the core substrate 51 from the conductor layer 63 side of the multilayer substrate 54. In other words, the cavity 20 forms a space whose bottom surface is the upper surface of the second buildup layer 62. The cavity 20 opens to occupy a partial area (cavity formation area 65) on the formation surface of the conductor layer 63 of the multilayer substrate 54.

The cavity 20 has a concave cross section. In the cavity 20, the insulating resin surface (bottom surface 79) of a portion of the second buildup layer 62 and the first conductor layer 17 formed on the upper surface of the second buildup layer 62 are exposed as bottom surfaces (in a flat state) of equal height. In other words, the first conductor layer 17 in the cavity 20 is arranged so as to be exposed on the surface of the insulating resin layer 62a that forms the bottom surface of the cavity 20.

In addition, the first conductor layer 17 in the cavity 20 is partially embedded in the insulating resin layer 62a. At the bottom of the cavity 20, it is preferable that the surface 79 (bottom surface 79) on the insulating resin layer 62a and the first conductor layer 17 are disposed so as to be substantially flush with each other. The word "substantially" is used because the first conductor layer 17 is exposed by etching, which may result in slight unevenness (steps) of 2 μm to 3 μm. A portion of the first conductor layer 17 formed on the bottom of the cavity 20 functions as a connection pad for connecting to electronic components.

The multilayer substrate 54 has, around the cavity 20, in addition to the aforementioned conductor layer 16, first conductor layer 17, and via 15, a seed layer 12a (hereinafter referred to as the second conductor layer 12a).

The second buildup layer 62 has a second conductor layer 12a at a position corresponding to the cavity forming region 65 at approximately the center in the thickness direction. The second conductor layer 12a is formed at a position corresponding to at least the side wall surface in the depth direction of the cavity 20. That is, the second conductor layer 12a is located in a portion where the side wall surface (20a in FIG. 1) of the cavity 20 is extended toward the first insulating resin layer 62a and the second insulating resin layer 62b. The position of the second conductor layer 12a when viewed in the thickness direction of the multilayer substrate 54 is the position where the side wall surface 20a of the cavity 20 is suspended toward the first insulating resin layer 62a in the second buildup layer 62 arranged on the lower layer side of the core substrate 51.

The planar position of the second conductor layer 12a in the multilayer substrate 54 is a central position directly below the wall surface 20a of the cavity 20. The position of the wall surface 20a of the cavity 20 and the position hanging down from the position of the wall surface 20a of the cavity 20 toward the first insulating resin layer 62a can also be referred to as the contour portion of the cavity 20. It is preferable that the second conductor layer 12a is disposed directly below the contour portion of the cavity 20.

The second conductor layer 12a can be formed, for example, between the insulating resin layer 62a and the insulating resin layer 62b (on the joint surface). The second conductor layer 12a may be in a state where it is not connected to other conductor layers and conductive layers. In other words, the second conductor layer 12a may be electrically isolated from other conductor layers and conductive layers.

The conductor layers 63 and 64 are connected to each other via through holes 10 that penetrate the first buildup layer 61, the core substrate 51, and the second buildup layer 62 in areas other than the cavity formation area 65. Note that conductor layers 73 and 74 (see FIG. 14) and solder resists 71 and 72 (see FIG. 13) may be formed above and below the through holes 10 in a later process as necessary. The solder resists 71 and 72 are formed on the surfaces of the top and/or bottom layers of the multilayer substrate 54. The conductor layers 73 and 74 are surrounded by an insulating coating of the solder resists 71 and 72 to function as connection pads.

Although conductor layer 16 and conductor layer 17 are electrically the same, the conductor layer formed integrally with via 15 is referred to as conductor layer 16, and the conductor layer laminated on seed layer 12, described later, is referred to as first conductor layer 17.

Thus, the printed wiring board of the embodiment is provided with a cavity forming region 65 of a multilayer substrate 54 in which a first buildup layer 61 is laminated on the upper surface (first surface) of a core substrate 51 as a substrate having an insulating resin layer 11 and a second buildup layer 62 is laminated on the lower surface (second surface) of the core substrate 51, the cavity 20 being formed by countersinking from above the first buildup layer 61 through the core substrate 51 and using a surface 79 of the insulating resin layer 62a of the second buildup layer 62 as a bottom surface, and a conductor layer 17 having a surface at the same height as the surface 79 of the insulating resin layer 62a of the second buildup layer 62 and embedded in the insulating resin layer 62a of the second buildup layer 62 so that the surface forms part of the bottom surface of the cavity 20.

In the example shown in Figure 1, a seed layer 12 is formed in advance on the underside of the core substrate 51 in an area including the cavity formation region 65, and the insulating resin layer 11 of the core substrate 51 is removed by the recess processing during cavity formation, leaving only the conductor layer 17.

The printed wiring board of the embodiment has a second conductor layer 12a in the second buildup layer 62 arranged on the lower layer side of the cavity 20. In this printed wiring board (multilayer substrate 54), the cavity 20 penetrates from the first buildup layer 61 to the core substrate 51 and is formed to reach a range exceeding 1/2 of the thickness of the multilayer substrate 54, particularly to a range exceeding 3/5. The cavity 20 is formed to a deep position in the thickness direction of the multilayer substrate 54. Since the cavity 20 is formed to a deep position in the thickness direction of the multilayer substrate 54, the multilayer substrate 54 is easily bent around the cavity 20. In other words, it is easier to bend compared to a printed wiring board in which the cavity 20 is formed to a position 1/2 or less in the thickness direction of the multilayer substrate 54.

In the printed wiring board of the embodiment, even the portion of the core substrate 51 located in the center of the thickness direction of the multilayer substrate 54 has been removed. In other words, the core substrate 51 member, which normally has glass cloth, is not present where the cavity 20 is formed. As such, because the core substrate 51 has been partially removed, the mechanical strength of this printed wiring board may be weakened.

When this printed wiring board is used, for example, as a connector for electrical connection, a socket or the like is inserted into the cavity 20. Normally, when a connector is inserted into the cavity 20, the printed wiring board is prone to deformation.

However, in the printed wiring board of the embodiment, the second conductor layer 12a is provided below the wall surface 20a of the cavity 20, so that the printed wiring board is less likely to bend even at the position where the cavity 20 exists. In this printed wiring board, even if a cavity 20 is formed penetrating the core substrate 51, it is possible to increase the mechanical strength of the second build-up layer 62 located on the bottom side of the cavity 20.

In this case, the second conductor layer 12a may be formed to extend from the contour of the cavity 20. The second conductor layer 12a is preferably arranged to straddle the cavity 20 side and the outside of the cavity 20 with the hanging position of the wall surface 20a of the cavity 20 at the center.

The second conductor layer 12a may have a strip shape. Here, strip shape refers to a shape that is elongated with a predetermined width. In the case of the second conductor layer 12a, the predetermined width refers to a region that spreads in both directions from the center when the wall surface 20a of the cavity 20 is the center. The spread region is a range in which an insulating portion is provided between the other adjacent conductors (the conductor layer including the via 15 in FIG. 1). A specific predetermined width can be set to be 5 μm or more and 500 μm or less.

As shown in Fig. 2, the second conductor layer 12a may be arranged to go around the vicinity of the position where the bottom surface 79 and the wall surface 20a of the cavity 20 provided in the multilayer substrate 54 intersect. Fig. 2 is a diagram showing a plan view of the interface between the insulating resin layer 62a and the insulating resin layer 62b, and shows a state in which the second conductor layer 12a is arranged in a band shape to go around the peripheral portion 79t of the cavity 20. In other words, when the second conductor layer 12a is arranged in the second build-up layer 62 in a ring shape, the multilayer substrate 54 can be made even more difficult to bend.

The cavity 20 is a cross-sectional concave portion formed by drilling and/or laser processing a portion of a predetermined layer of the multilayer substrate 54 (a cavity forming region 65 (see FIG. 7) including the range of the seed layer 12 formed on the core substrate 51 and the shielding conductor prohibited area at the boundary between the cavity portion and the non-cavity portion where the seed layer 12 is not formed) to a predetermined depth (a position near the seed layer 12 from which the center of the thickness of the core substrate 51 or above has been removed), removing the remaining portion by laser processing to expose the seed layer 12, and then removing the seed layer 12 by flash etching. "Above the center of the thickness" refers to a depth that is at least half the thickness of the core substrate 51 and does not reach the seed layer 12.

That is, the cavity 20 has a cavity bottom (bottom surface) in which the seed layer 12 formed on the lower surface of the core substrate 51 is exposed by countersinking the cavity forming region 65 with an area capable of accommodating electronic components, and then the exposed seed layer 12 is removed by flash etching to expose the insulating resin layer 62a and the conductor layer 17 thereunder in a substantially flat manner. In addition, in the above-mentioned cavity forming region 65, directly below the boundary between the cavity portion and the non-cavity portion where the seed layer 12 is not formed, a second conductor layer 12a is formed in a layer lower than the bottom surface of the cavity 20 (between the insulating resin layer 62a and the insulating resin layer 62b). This second conductor layer 12a spreads from directly below the bottom surface of the cavity 20 to the periphery. In addition, in this embodiment, the second conductor layer 12a spreads in a strip shape around and inwardly from directly below the cavity contour portion of the bottom surface of the cavity 20. The second conductor layer 12a is made of copper having a thickness of, for example, 12 μm or more, and is made up of a dummy pattern or a ground layer, a power supply layer, or the like.

The electronic component housed in the cavity 20 is, for example, a bare chip (an unpackaged IC without terminals) and has an electrode on the bottom for connection to the multilayer substrate 54. The electrode on the bottom of the electronic component may be connected to the surface of the conductor layer 17 exposed flatly on the bottom of the cavity as a component mounting land, or may be connected via a metal plating layer 80 (see FIG. 14) formed by plating the conductor layer 17. In this case, the metal plating layer 80 is formed by stacking plating layers such as nickel plating and gold plating.

The conductor layers 63 and 64 are formed on the surface of the multilayer substrate 54 (the core substrate 51 and the first and second build-up layers 61 and 62 above and below it), and are formed as part of the circuit wiring (conductor layer 63a) by subsequent etching. The conductor layers 63 and 64 are copper solid patterns, formed by, for example, copper plating (about 15 μm thick) on copper foil (about 9 μm thick).

Vias 15 are connected to the ends (direction along the surface) of conductor layers 63 and 64. Vias 15 provide interlayer connections between conductors (conductor layers 16, 17, 63, 64, etc.) provided on any layer of multilayer substrate 54.

The core substrate 51 is made by processing an insulating resin layer 11 (see Figure 3-7) having seed layers 12 formed on the top and bottom surfaces to form vias 15.

Examples of insulating resins that form the insulating resin layer 11 include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenolic resin, polytetrafluoroethylene (PTFE) resin, silicon resin, polybutadiene resin, polyester resin, melamine resin, urea resin, polyphenylene sulfide (PPS) resin, polyphenylene oxide (PPO) resin, etc. Two or more of these resins may be mixed.

Vias 15 are formed by filling via hole pilot holes 14 (see FIG. 4) with metal plating through a plating process. Vias 15 connect conductors (conductor layers 63, 64, 16, 17, etc.) provided on each layer (including inner and outer layers) of multilayer board 54 (see FIG. 8). In FIG. 8, it can be seen that conductor layer 63 on the upper surface is connected to conductor layer 17 through via 15, and conductor layer 64 on the lower surface is connected to conductor layer 17 through via 15.

The seed layer 12 is, for example, copper with a thickness of 1 μm to 10 μm (1 μm or more and 10 μm or less), and is arranged with a portion remaining under the conductor layer 17. There are no particular limitations on the seed layer 12 as long as it is electrically connected and can shield the laser, but for example, thin copper foil or electroless copper plating is used. Thin copper foil, which has a dense metal composition, is more suitable.

The core substrate 51 is formed by forming the upper and lower surfaces of the insulating resin layer 11 using a method such as modified semi-additive process (M-SAP) or semi-additive process (SAP), and exposing the connection pads provided in a portion of the seed layer 12 and the conductor layer 17 (the central part of the lower surface of the core substrate 51 in Figure 5) that will become the circuit wiring while protecting them from flash etching with an etching resist.

The printed wiring board of the present disclosure can basically be obtained by going through the first to sixth steps described above. Below, the manufacturing method of the printed wiring board of the embodiment will be described with reference to Figures 3 to 15.

As shown in Figure 3, the core substrate base material 11A is formed by laminating a seed layer 12 (e.g., a conductive metal foil such as thin copper foil) on the upper surface (first surface 11a) and lower surface (second surface 11b) of a base material 11 made of insulating resin. In this case, the thickness of the seed layer 12 is preferably, for example, about 1 µm to 10 µm. Alternatively, the core substrate base material 11A may have a seed layer 12 on at least the lower surface of the upper and lower surfaces of the base material 11.

Next, as shown in Figure 4, laser processing is performed on the core substrate base material 11A to form via hole pilot holes 14.

When the via hole pilot hole 14 is formed by laser processing, a thin resin film may remain at the bottom of the via hole pilot hole 14. In this case, a desmear process is performed. In the desmear process, the resin is swelled with a strong alkali, and then an oxidizing agent (e.g., chromic acid, a permanganate aqueous solution, etc.) is used to decompose and remove the resin.

In addition, the resin film may be removed by, for example, wet blasting with an abrasive or plasma treatment. Furthermore, the inner wall surface of the via hole pilot hole 14 may be roughened for plating. Examples of roughening include wet processes using an oxidizing agent (e.g., chromic acid, permanganate aqueous solution, etc.) and dry processes such as plasma treatment and ashing treatment.

(Pattern plating process)
5, this process is a process of forming a conductor layer 16, a first conductor layer 17, and vias 15 by pattern plating on a partial region of a seed layer 12 provided on the upper and lower surfaces of an insulating resin substrate 11 and on via hole pilot holes 14. Specifically, a dry film 13 (plating resist) is attached onto the seed layer 12 by lamination, and then exposed to light and developed to remove the dry film 13 from the areas where it is desired to form circuit parts such as the conductor layer 16 and vias 15 on the upper surface and the first conductor layer 17, which is a conductive circuit on the lower surface.

Next, a pattern plating process is performed on the via hole pilot holes 14 for forming the circuit section of the insulating resin substrate 11 from which a portion of the dry film 13 has been removed, and on the seed layer 12 surrounding the via hole pilot holes 14, to form a conductor layer 16 on the upper surface of the insulating resin substrate 11, vias 15 inside the substrate 11, and a conductive layer (including the seed layer 12 and the first conductor layer 17) on the lower surface of the substrate 11.

Here, the pattern plating may be copper plating alone or copper plating combined with nickel plating. The combination of copper plating and nickel plating is used because there is a concern that when the seed layer 12 is removed in a later process, the pattern plated parts other than the seed layer 12 may also be slightly etched. The nickel plating functions as a barrier against the removal of the seed layer 12. Nickel plating and copper plating are performed continuously. In this case, the thickness of the nickel plating should be 2 μm or more.

This nickel plating process is sometimes called "barrier plating." When the plating film formed in this process also serves as a plating film for surface treatment of component mounting, successive plating of nickel, gold, nickel, and copper may be performed. In this case, too, the thickness of the nickel plating should be 2 μm or more for the first plating and 3 μm or more for the second plating, and the gold plating depends on the component mounting method, but in the case of wire bonding, it is recommended that it be 0.3 μm or more.

The correction of circuit width is no different from that of conventional M-SAP or semi-additive methods, just by correcting it to about 6 μm thicker than the design value before exposure.

(Dry film peeling process)
Next, after pattern plating, the remaining dry film 13 is peeled off to expose the seed layer 12.

(Processing of cavity forming area)
Next, as shown in Fig. 6, a dry film 18 (photosensitive etching resist) is laminated on the seed layer 12 and the first conductor layer 17 on the lower surface (second surface 11b) of the substrate 11. After this, exposure and development are performed, and the dry film 18 is left in the cavity forming region 65 (excluding the shielding conductor prohibited area at the boundary between the cavity portion and the non-cavity portion) and the dry film 18 is removed from other portions. Parts of the exposed seed layer 12 that are not covered by the dry film 18 and are not required as conductive circuits are removed by flash etching. After this, the dry film 18 is removed from the surfaces of the seed layer 12 and the first conductor layer 17.

That is, in this process, the dry film 18 is attached to the cavity formation region 65 within the area where the seed layer 12 is formed on the surface (second surface 11b in this case) of the substrate 11, and then the seed layer 12 outside the dry film 18 is removed by flash etching. After that, the dry film 18 on the seed layer 12 is peeled off. In this case, the seed layer 12 formed on the upper surface (first surface 11a) of the substrate 11 is also removed.

In this way, the core substrate 51 shown in Figure 7 is completed. A conductor layer 16 is formed on the upper surface (first surface 11a) of the base material 11 of this core substrate 51 as part of a circuit electrically connected to the via 15. In addition, the seed layer 12 remains in the cavity formation region 65 (excluding the no-shielding-conductor area at the boundary between the cavity portion and the non-cavity portion) on the lower surface (second surface 11b) of the core substrate 51. The portion of the seed layer 12 within the cavity formation region 65 serves as a laser receiver (shielding member) during laser processing, which will be described later.

In addition, a first conductor layer 17 is formed as a conductive circuit on the lower surface of the substrate 11. In this example, the circuit is formed using M-SAP as an example, but the circuit (in this case, the first conductor layer 17) can also be formed using SAP that uses electroless copper plating as a seed layer.

(Build-up layer formation process)
In this step, build-up is performed an arbitrary number of times on at least the lower layer (lower surface) of the upper layer (upper surface) and lower layer (lower surface) of the core substrate base material 11A that will become the core substrate 51, to produce the laminated substrate 54A. That is, in this step, the first build-up layer 61 and the second build-up layer 62 are formed on the core substrate base material 11A that will become the core substrate 51, while leaving the seed layer 12 partially in the cavity formation region 65. This forms the laminated substrate 54A in which a part of the seed layer 12 is embedded between the internal core substrate 51 (insulating resin substrate) and the second build-up layer 62 (lower structure).

Here, a conventional method may be used as the build-up process for forming the first build-up layer 61 and the second build-up layer 62. For example, a method may be used in which an insulating resin layer 61a is first attached to the core substrate base material 11A that will become the core substrate 51, and then via holes are formed using a laser. After this, a plating process is performed on the surface of the insulating resin layer 61a including the via holes, to form the vias 15 and the conductor layer 17. When the first build-up layer 61 is to be multi-layered as shown in FIG. 7, the same process is repeated.

For circuit formation of the first buildup layer 61 and the second buildup layer 62, not only the subtractive method in which conductors unnecessary for the circuit are removed by etching, but also M-SAP, SAP, etc. can be applied as in the case of the core substrate 51. For laminating the first and second buildup layers 61, 62, techniques such as multi-stage pressing or resin lamination are used.

In this example, insulating resin layer 61a, insulating resin layer 61b, and conductor layer 17 (first conductor layer 17) are formed on the upper first buildup layer 61. A conductor layer 63 connected to via 15 is formed on the upper surface of the first buildup layer 61, which is the uppermost layer (surface layer). When forming the conductor layer 63 on the upper surface of the uppermost layer (insulating resin layer 61b) of the multilayer substrate 54, the range of cavity formation region 65 is removed. This is to facilitate countersinking in the cavity formation process described below.

The second build-up layer 62 has an insulating resin layer 62a, an insulating resin layer 62b, and a conductor layer 17. A via 15 is formed within a cavity forming region 65 in the insulating resin layer 62a directly below the core substrate base material 11A that becomes the core substrate 51. The via 15 is connected to the first conductor layer 17 of the core substrate 51 at the top and to the via 15 of the insulating resin layer 62b at the bottom. The first conductor layer 17 is formed on the left and right undersides of the insulating resin layer 62a and the insulating resin layer 62b. A through hole 10 is formed through the first conductor layer 17 to connect the first conductor layer 17 of the other layers, the conductor layer 63 of the top layer, and the conductor layer 64 of the bottom layer.

Furthermore, in the cavity forming region 65, directly below the boundary between the cavity portion and the non-cavity portion (at a position corresponding to the cavity forming region 65 and its boundary), the aforementioned second conductor layer 12a is formed one layer below the bottom surface of the cavity 20 (between the insulating resin layer 62a and the insulating resin layer 62b). This second conductor layer 12a serves as a laser receiver (shielding member) during the laser processing described below, and prevents the laser from penetrating into the lower layer. Any method may be used to form this second conductor layer 12a, and may be a subtractive method, M-SAP, semi-additive method, or the like.

(Cavity forming process)
9, in this step, a drill is directed from the side of the first buildup layer 61 of the laminated substrate 54A toward the seed layer 12 left on the core substrate 51. In other words, a cavity forming region 65 previously provided in the laminated substrate 54A is processed as if it were carved out with a drill.

In this case, there are two steps: a step (sinking process 1) of penetrating the first build-up layer 61 by inserting a drill into the cavity formation region 65 in the stacking direction (thickness direction), and partially removing the insulating resin layer 61a and the insulating resin layer 61b while leaving a part of the base material 11 on the seed layer 12 inside the core substrate 51 to form the cavity 20; and a step (sinking process 2) of removing the insulating resin 68 remaining in the cavity 20 by laser processing, using the seed layer 12 and the second conductor layer 12a, one layer below, as shielding members for the laser light, to expose the seed layer 12 at the bottom of the cavity 20.

(Counterboring 1 (Drilling))
In this process, a recess is formed (cutting process using a combination of drilling and laser processing is also possible) from above the laminated substrate 54A, penetrating through the first build-up layer 61 in the cavity formation region 65 to the substrate 11 in the core substrate substrate 11A, and most of the insulating resin is removed except for a part of the substrate 11 on the seed layer 12 on the underside of the core substrate substrate 11A, to form a cavity 20.

Specifically, as shown in FIG. 9, a drill 66 having a sensor at the bit tip is placed at one end of the cavity formation region 65 (e.g., the left end as viewed in the figure), and drilled down to a position just before the seed layer 12 on the surface of the core board base material 11A (a position just before reaching the bottom of the cavity 20), and the drill 66 is moved from that position in the lateral direction A to remove the insulating resin layer 11 with the drill 66.

In this example, a portion of the substrate 11 is left on the bottom of the cavity 20, but if the drilling precision is high, it may be drilled right up to the surface of the seed layer 12.

The reason why the recessing process is performed in two stages, including drilling and not just laser processing as described below, is that a seed layer 12, etc. is used as a receiving conductor (shielding member) for the laser in the laser processing described below, and the insulating resin 68, which is the remaining part of the substrate 11, is removed.

(Counterboring 2 (Laser processing))
In this step, as shown in Fig. 10, a laser beam is applied from above the opening of the cavity 20 in the direction of arrow B to remove the insulating resin 68 left on the bottom of the cavity 20 by the drilling process in Fig. 8. A processing laser such as a carbon dioxide laser ( _CO2 laser) or a YAG laser can be used for the laser processing.

With conventional technology, if the laser ablation conditions are not appropriate, there is a problem that the laser can penetrate to the lower layer in the no-shielding-conductor area at the boundary between the cavity and non-cavity sections, potentially damaging the substrate.

In the method for manufacturing a printed wiring board disclosed herein, the seed layer 12 and the second conductor layer 12a, which is one layer below, are used as shielding members for laser light, and the remaining portion of the upper layer portion left at the bottom of the cavity 20 is removed by laser processing, exposing the flat surface of the seed layer 12 at the bottom of the cavity 20, as shown in Figure 11. At this time, by using the second conductor layer 12a as a shielding member for laser light, even when the conditions for laser irradiation are not appropriate, it is possible to prevent the laser from penetrating into the lower layer and damaging the substrate (in this case, the insulating resin layer 62a) in the shielding conductor prohibited area at the boundary between the cavity portion and the non-cavity portion.

When the insulating resin 68 at the bottom of the cavity 20 is processed by laser processing, a thin resin film (fine resin debris) may remain in that area. To remove such remaining fine resin debris, the area carbonized by the laser is cleaned. For this purpose, a water washing process such as high-pressure water washing or a desmear process using plasma processing or permanganate processing is performed. These processes may be performed twice or three times.

Desmearing is a process in which the resin is swelled with a strong alkali and then decomposed and removed using an oxidizing agent (e.g., chromic acid, aqueous permanganate solution, etc.). The resin film may also be removed by wet blasting with an abrasive or by plasma treatment. When performing plasma treatment, masking with a dry film may be performed to protect the surface substrate.

When performing the desmear process, in order to protect the outermost layer substrate and the outermost layer circuit, the process may be reversed and the cavity 20 may be formed before the outermost layer circuit is formed. In that case, in order to protect the cavity 20, it is necessary to protect it with a dry film or the like. Electrodeposition resist (ED, etc.) may also be used.

The second conductor layer 12a used as a laser light receiving conductor (laser light shielding member) can improve the rigidity of the multilayer substrate 54, which is reduced by the absence of an upper structure due to the cavity 20. In this case, the second conductor layer 12a is sufficient to be provided only on the cavity outline as a laser light shielding member, but if it is placed on the entire bottom surface of the cavity, the rigidity can be further strengthened. Furthermore, the plate thickness of the cavity portion, which is prone to variation when only wiring is used, can be stabilized. When the second conductor layer 12a is placed only on the cavity outline, the laser irradiation diameter and interlayer positional deviation are taken into consideration, and the second conductor layer 12a is placed 200 μm wide outward from the end of the seed layer 12 as a reference, so that the laser can be sufficiently shielded.

In addition, because the seed layer 12 penetrates the substrate 11, if multiple circuits are to be extended from the first conductor layer 17 outside the cavity, the multiple circuits will short out at the seed layer 12. However, by forming the seed layer 12 slightly narrower than the cavity 20, the seed layer 12 will not penetrate the substrate 11, and multiple circuits can be extended outside the cavity.

The copper foil (barrier layer) of the seed layer 12 at the bottom of the cavity 20 can be of various types, such as profile-free foil, low-profile foil, or standard foil.

16 and 17, the effect of forming the second conductor layer 12a will be described. FIG. 16 is a diagram showing an outline of the cavity 20, and FIG. 17 is an enlarged view of the periphery of the contour of the cavity 20 shown by the dashed line A in FIG. 16. The second conductor layer 12a is disposed on the lower surface of the insulating resin layer 62a, and as described above, it functions as a shielding member for the laser light L. In this case, in this embodiment, the insulating resin layer 62a may be processed so that the vicinity of its surface is locally affected by the laser light.

When the second conductor layer 12a is provided on the insulating resin layer 62a below the contour of the cavity 20, the upper side of the second conductor layer 12a is slightly hollowed out when the contour is processed with laser light. This results in a smaller volume than when the second conductor layer 12a is not provided.

The shape of the hollowed-out portion is such that there is a step on the wall surface 20a side of the cavity 20 (62aL in the figure), but the opposite side, the inside of the cavity 20 (symbol 62aR), has a shape that is perpendicular to the surface (bottom surface 79) of the insulating resin layer 62a.

When the solder resist R is formed on the bottom surface 79 side of the cavity 20, it is possible to prevent the solder resist R from creeping up the wall surface 20a, and at the same time, the solder resist can be formed with a uniform thickness on the bottom surface of the cavity 20. This is because the wall surface 20a side (62aL) of the cavity 20 is stepped, making it easy for the solder resist to creep up, but the inner side (62aR) is a vertical surface, making it difficult for the solder resist to creep up.

At the intersection X between the inner side 62aR of the hollowed-out portion and the bottom surface 79, the solder resist can be made to have the same thickness as other portions of the bottom surface 79. That is, in Fig. 17, the thickness _tC1 of the solder resist at the corner of the hollowed-out portion and the thickness _t79 of the solder resist on the bottom surface 79 can be made the same. Here, "the same" means that the relationship roughly satisfies the following formula.
t _C1 - _{t 79} ≦1μm

In this embodiment, the cavity 20 is formed after the outermost circuit is formed, but if the cavity 20 is subjected to a desmear treatment such as permanganate treatment after the laser treatment, the cavity 20 may be formed before the outermost circuit is formed in order to protect the surface substrate and prevent deterioration of the circuit peel strength. In addition, if the outermost circuit is formed by pattern plating such as M-SAP, the process can be combined with the seed layer removal process described below to reduce the number of processes.

(Seed layer removal process)
In this process, as shown in FIG. 12, the seed layer 12 exposed at the bottom of the cavity 20 is removed by flash etching to expose the surface 79 of the insulating resin layer 62a of the second build-up layer 62 and the surface of the conductor layer 17 embedded in the insulating resin.

In more detail, in this process, the seed layer 12 (copper foil), which is a barrier layer, is removed by flash etching the bottom of the cavity forming region 65. In this way, the multilayer substrate 54 is obtained. The surface (bottom surface 79) of the insulating resin layer 62a under the core substrate 51 and the first conductor layer 17, whose surface is exposed at the same height (position) as the bottom surface 79 and embedded in the insulating resin layer 62a, form part of the bottom surface 79 of the cavity 20. In this way, the first conductor layer 17 exposed flatly on the bottom surface of the cavity 20 functions as a component mounting land, making it possible to connect the circuit wiring in this multilayer substrate 54 and the electronic components housed in the cavity 20.

If it is not desired to reduce the thickness of the outermost conductor layer by flash etching, this can be done after the solder resist. Alternatively, masking with a dry film can be done after the solder resist, and the areas to be etched can be selected arbitrarily.

In the previous section, we explained that there is a concern that the pattern plating portion may also be slightly etched in addition to the seed layer, but the amount of etching is about 2 μm, and since the flash etching solution has the property of etching uniformly in the vertical direction, there is no adverse effect on the conductor thickness.

If nickel plating is used as a barrier plating, the nickel must also be etched. Nickel removers such as the NH-1860 series (manufactured by MEC Co., Ltd.) are suitable for etching nickel.

For wire bonding applications where gold plating is applied under nickel barrier plating, it is in principle possible to use ferric chloride and cupric chloride solutions, which are typical etching solutions for the subtractive method, as they do not dissolve gold. However, they are unsuitable because they have a strong penetrating power into the interface and will penetrate into the interface between the gold plating and the insulating material, causing side etching that dissolves the nickel and copper plating below the gold plating.

(Outer layer circuit formation process)
In this process, the conductor layer 64 of the second buildup layer 62 at the bottom of the multilayer substrate 54 formed as shown in Fig. 12 is etched to remove a portion of the conductor layer 64a as a circuit as shown in Fig. 13. Also, the conductor layer 63 of the first buildup layer 61 at the top of the substrate is etched to remove a portion of the conductor layer 63a as a circuit wiring or wiring pattern. The outer layer circuit may be formed by a subtractive method using an electrodeposited resist as an etching resist, which has excellent conformability to the wall surfaces of recesses and through holes. The electrodeposited resist is an etching resist that utilizes the properties of electrodeposition coating.

(Solder resist process)
In this process, the first and second buildup layers 61, 62 shown in Fig. 13 are coated with an insulating film including parts of the conductor layers 63a, 64a, and solder resists 71, 72 are formed as shown in Fig. 14. The solder resist may be of a dry film type or a liquid type.

(Electronic component mounting location forming process)
The steps after this are performed when a step is required for the component mounting land. In this step, as shown in Fig. 15, plating is applied to the conductor layer 17 exposed at the bottom of the cavity 20 to form a metal plating layer 80, and a connection pad, which is a component mounting land with a step from the bottom surface, is formed.

A circuit pattern may also be formed by plating the conductor layer 63a of the first build-up layer 61 on the upper part of the multilayer board 54. In this case, if the through-hole 10 is filled with resin or metal, the upper and lower parts of the through-hole 10 that do not have the solder resist 71 are also plated, so that conductor layers 73 and 74 are also formed here.

If necessary, a process for mounting electronic components may be added as follows. In this process, an electronic component is accommodated in cavity 20, and electrodes provided on the bottom of the electronic component are brought into contact with metal plating layer 80 (connection pads) to connect the circuits to each other. Note that if electronic components are not mounted here but are instead mounted elsewhere, the processes following the electronic component mounting process are not necessary.

Thus, the core substrate base material 11A for forming the printed wiring board of this embodiment has an insulating resin base material 11 having a first surface (upper surface) 11a and a second surface (lower surface) 11b opposite the first surface (upper surface) 11a. A seed layer 12 is formed on the second surface (lower surface) 11b of the insulating resin base material 11. A first conductor layer 17 is formed by pattern plating in a partial area of the seed layer 12. The core substrate 51 has an insulating resin base material 11, a seed layer 12, and a first conductor layer 17. A second build-up layer 62 built up with insulating resin is formed on at least the lower surface of the core substrate 51, forming a multi-layer substrate (laminated substrate 54A). A cavity 20 is formed by processing the laminated substrate 54 such that a portion of the core substrate 51 (cavity forming region 65) is recessed from the side of the first buildup layer 61 so that the seed layer 12 of the second surface (lower surface) 51b of the core substrate 51 is exposed at the bottom. When the seed layer 12 exposed at the bottom of the cavity 20 is removed by flash etching, the surface (bottom surface 79) of the insulating resin layer 62a of the second buildup layer 62 located below the core substrate 51 remains. The first conductor layer 17 is embedded in the bottom surface 79 so that the top surface is aligned almost flush. With this configuration, the circuit connection between the electronic component accommodated in the cavity 20 and the substrate side can be made at the bottom of the electronic component.

In this way, by forming the first conductor layer 17, which is almost flush with the bottom surface 79 of the cavity 20, as a connection pad (component mounting land) and connecting it to an electrode at the bottom of the electronic component, the peel strength of the component mounting land as a wiring pattern at the bottom of the cavity 20 can be improved.

The examples of the manufacturing procedures for printed wiring boards in each of the above embodiments are merely examples, and it is possible to vary the processing steps in various ways by interchanging the processing steps, adding new processing steps, and deleting some processing steps.

Although an embodiment of the present invention has been described, this embodiment is shown by way of example only, and the invention can be embodied in a variety of other forms, and components can be omitted, substituted, or modified without departing from the spirit and scope of the invention.

10...through hole, 11...insulating resin substrate, 12...seed layer, 12a...second conductor layer, 13, 18...dry film, 14...via hole pilot hole, 15...via, 16, 63, 64...conductor layer, 17...first conductor layer, 20...cavity, 51...core substrate, 54...multilayer substrate, 61, 62...build-up layer, 61a, 61b, 62a, 62b...insulating resin layer, 66...drill, 68...insulating resin, 71, 72...solder resist, 79...bottom surface, 80...metal plating layer.

Claims (2)

A first step of preparing a core substrate having a first surface and a second surface, the second surface being provided with a seed layer;
a second step of forming a first conductor layer by pattern plating the seed layer provided on the core substrate;
a third step of removing a portion of the seed layer on a surface of the seed layer including the first conductor layer of the core substrate such that the seed layer remains in a central portion of the core substrate, which is a region in which a cavity is to be formed;
a fourth step of forming a first buildup layer having a first insulating resin layer on the first surface of the core substrate and forming a second buildup layer having a second insulating resin layer on the second surface of the core substrate;
a fifth step of pattern-plating the surface of the second buildup layer with nickel, gold, nickel, and copper in that order to form a second conductor layer at a position that overlaps at least a portion of a periphery of a bottom surface of the cavity to be formed in a plan view;
a sixth step of forming the cavity, the bottom surface of which is a surface of the second buildup layer, by using the seed layer and the second conductor layer as a shielding member for a laser beam when penetrating the first buildup layer and the core substrate by laser processing from the first buildup layer side of the core substrate;
A method for manufacturing a printed wiring board comprising the steps of: The method for manufacturing a printed wiring board according to claim 1 , wherein the second conductor layer is formed so as to go around a peripheral portion of the bottom surface of the cavity.

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