JP7649611B2 - Highly transparent semiconductor/metal interface - Google Patents

Description

The present disclosure relates to semiconductor devices, and more particularly to techniques for promoting highly transparent semiconductor/metal interfaces.

The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description presented later. In one or more embodiments described herein, a device, system, method, computer-implemented method, apparatus, or computer program product, or combination thereof, that can promote a highly transparent semiconductor/metal interface is described.

According to one embodiment, the method may include forming a silicon-on-insulator (SOI) over the wafer. The method may further include depositing a metal on the SOI. The method may further include forming a structure by dry etching the metal and dry etching the SOI. The method may further include forming a template over the structure. The method may further include etching a portion of the SOI for removal under the metal. The method may further include growing a semiconductor where the portion of the SOI was removed.

According to another embodiment, the method can include forming a template structure comprising a metal element and a silicon element by etching away a portion of the silicon element for removal. The method can further include creating an interface between the metal element and the semiconductor by growing a semiconductor where the portion of the silicon element was removed.

According to another embodiment, the method can include forming a cavity structure including a first sidewall comprising a metal element and a second sidewall comprising a silicon element. The method can further include growing a semiconductor in the cavity structure using the silicon element as a nucleation seed to form an interface between the metal element and the semiconductor.

1A-1D are cross-sectional views of example and non-limiting devices that can facilitate a highly transparent semiconductor/metal interface according to one or more embodiments described herein. 2 is a cross-sectional view of the example and non-limiting device of FIG. 1 after removing a portion of the metal layer and the silicon layer according to one or more embodiments described herein. 3 is a cross-sectional view of the example and non-limiting device of FIG. 2 after removing another portion of the metal layer according to one or more embodiments described herein. 4 is a cross-sectional view of the exemplary and non-limiting device of FIG. 3 after forming a dielectric layer over the device of FIG. 3 according to one or more embodiments described herein. 5 is a cross-sectional view of the example and non-limiting device of FIG. 4 after etching a portion of the silicon layer to remove the underlying metal layer in accordance with one or more embodiments described herein. FIG. 6 is a cross-sectional view of the example and non-limiting device of FIG. 5 after a portion of the silicon layer has been removed and a semiconductor has been grown thereon, according to one or more embodiments described herein. 5 is an exemplary and non-limiting top-down scanning electron microscope (SEM) micrograph showing the device of FIG. 4 according to one or more embodiments described herein. 7 is an exemplary and non-limiting top-down SEM micrograph showing the device of FIG. 6 according to one or more embodiments described herein. 1 is an exemplary and non-limiting top-down SEM micrograph showing indium arsenide (InAs) nanowires grown within a partially superconducting template according to one or more embodiments described herein. 1 is an exemplary and non-limiting top-down SEM micrograph showing an InAs nanowire grown entirely within a superconducting template according to one or more embodiments described herein. 11 is an exemplary and non-limiting transmission electron microscope (TEM) cross-sectional view of the fully superconducting template of FIG. 10 along line AA, according to one or more embodiments described herein. 12 is an exemplary and non-limiting close-up view of a highly transparent semiconductor/metal interface within the cross-sectional view of FIG. 11, according to one or more embodiments described herein. 12 is an exemplary and non-limiting enlarged view of a portion of a semiconductor device in the cross-sectional view of FIG. 11 according to one or more embodiments described herein. 12 is an exemplary and non-limiting graph showing the results of an energy dispersive x-ray analysis (EDX) scan of the highly transparent semiconductor/metal interface shown in FIG. 11 according to one or more embodiments described herein. 1 is an exemplary and non-limiting top-down SEM micrograph showing a device with a highly transparent semiconductor/metal interface according to one or more embodiments described herein. 1 is an example and non-limiting graph showing differential conductance as a function of back gate bias voltage according to one or more embodiments described herein. 1 is an example and non-limiting linear scale graph showing differential conductance versus split gate bias voltage and source-drain bias voltage in accordance with one or more embodiments described herein. 1 is an example and non-limiting logarithmic scale graph showing differential conductance versus split gate bias voltage and source-drain bias voltage in accordance with one or more embodiments described herein. 1 is an exemplary and non-limiting graph illustrating differential conductance as a function of source-drain bias voltage at a split gate bias voltage of about −1.1 volts according to one or more embodiments described herein. 1 is an exemplary and non-limiting graph illustrating differential conductance as a function of source-drain bias voltage at a split gate bias voltage of approximately −3.375 volts in accordance with one or more embodiments described herein. 1 is an exemplary and non-limiting graph illustrating differential conductance as a function of source-drain bias voltage at a split gate bias voltage of about −3.75 volts according to one or more embodiments described herein. 22 is an example and non-limiting logarithmic scale graph of FIG. 18 recording the split gate bias voltages of FIGS. 19-21 according to one or more embodiments described herein. 1 is an example and non-limiting linear scale graph showing differential conductance versus side gate bias voltage and source-drain bias voltage according to one or more embodiments described herein. 1 is an exemplary and non-limiting graph illustrating differential conductance as a function of source-drain bias voltage at a side gate bias voltage of about −2.6 volts according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface achieved with a metal overlying a semiconductor according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface achieved with a metal overlying a semiconductor according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface achieved with a metal overlying a semiconductor according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface achieved with a metal overlying a semiconductor according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface achieved with a metal overlying a semiconductor according to one or more embodiments described herein. 1A-1C are cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces realized with device structures patterned in a self-aligned manner according to one or more embodiments described herein. 1A-1D are cross-sectional views of example and non-limiting devices that can facilitate a highly transparent semiconductor/metal interface according to one or more embodiments described herein. FIG. 46 is a cross-sectional view of the example and non-limiting device of FIG. 45 after etching the metal and silicon of the device of FIG. 45 according to one or more embodiments described herein. 47 is a cross-sectional view of the example and non-limiting device of FIG. 46 after etching the metal of the device of FIG. 46 according to one or more embodiments described herein. FIG. 48 is a cross-sectional view of the example and non-limiting device of FIG. 47 after forming a dielectric over the metal and silicon of the device of FIG. 47 in accordance with one or more embodiments described herein. FIG. 49 is a cross-sectional view of the example and non-limiting device of FIG. 48 after etching a portion of the silicon to remove under metal of the device of FIG. 48 in accordance with one or more embodiments described herein. FIG. 50 is a cross-sectional view of the example and non-limiting device of FIG. 49 after a semiconductor has been grown where a portion of the silicon has been removed from the device of FIG. 49 according to one or more embodiments described herein. 49 is an exemplary and non-limiting top-down scanning electron microscope (SEM) micrograph showing the device of FIG. 48 according to one or more embodiments described herein. 50 is an exemplary and non-limiting top-down scanning electron microscope (SEM) micrograph showing the device of FIG. 49 according to one or more embodiments described herein. 51 is an exemplary and non-limiting top-down scanning electron microscope (SEM) micrograph showing the device of FIG. 50 according to one or more embodiments described herein. FIG. 51 is an exemplary and non-limiting cross-sectional view of the device of FIG. 50 according to one or more embodiments described herein. FIG. 55 is an exemplary and non-limiting close-up view of a highly transparent semiconductor/metal interface within the cross-sectional view of FIG. 54, according to one or more embodiments described herein. 1 is a flow diagram of an example and non-limiting method that can promote a highly transparent semiconductor/metal interface according to one or more embodiments described herein. 4 is a flow diagram of another exemplary and non-limiting method that can promote a highly transparent semiconductor/metal interface according to one or more embodiments described herein. 4 is a flow diagram of another exemplary and non-limiting method that can promote a highly transparent semiconductor/metal interface according to one or more embodiments described herein. FIG. 1 is a block diagram of an example and non-limiting operating environment in which one or more embodiments described herein may be facilitated.

The following detailed description is illustrative only and is not intended to limit the embodiments or the application and/or uses of the embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections or in the Detailed Description section.

One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that in various instances, one or more embodiments may be practiced without these specific details.

FIGS. 1-6 illustrate an exemplary and non-limiting multi-step fabrication sequence that may be performed to fabricate one or more embodiments of the present disclosure described herein and/or illustrated in the figures. For example, the non-limiting multi-step fabrication sequence illustrated in FIGS. 1-6 may be performed to fabricate device 1510 with a highly transparent semiconductor/metal interface as shown in scanning electron microscope (SEM) micrograph 1500 in FIG. 15.

1 illustrates a cross-sectional view of an exemplary and non-limiting device 100 that can facilitate a highly transparent semiconductor/metal interface according to one or more embodiments described herein. As shown in FIG. 1, the device 100 can include a substrate 110. The substrate 110 can include any material having semiconducting properties, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), germanium (Ge) alloys, and the like. In one embodiment, the substrate 110 can include a layered semiconductor, including, but not limited to, silicon/silicon germanium (Si/SiGe), silicon/silicon carbide (Si/SiC), and the like.

The device 100 may further comprise a dielectric layer 120 formed over the substrate 110. The dielectric layer 120 may comprise any material having dielectric properties, such as, but not limited to, _silicon dioxide ( _SiO2 ), silicon nitride ( _Si3N4 ), hafnium oxide ( _HfO2 ), _aluminum oxide ( _Al2O3 ), and other materials having dielectric properties. In an embodiment, the dielectric layer 120 may be a buried oxide (BOX) layer. In an embodiment, the BOX layer may be thermally grown or obtained by ion implantation. In an embodiment, the dielectric layer 120 may be grown or formed by atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), tetraethyl orthosilicate (TEOS), or the like. In an embodiment, the dielectric layer 120 may comprise any combination of a BOX layer grown or formed by ALD, PECVD, TEOS, or the like, and one or more dielectric layers. The dielectric layer 120 may include a thickness (eg, height) of about 150 nm.

The device 100 may further comprise a silicon layer 130 formed over the dielectric layer 120. The silicon layer 130 may comprise a silicon-on-insulator (SOI) layer, a polycrystalline silicon layer, or a combination thereof. In one embodiment, the silicon layer 130 may comprise a thickness (e.g., height) ranging from about 30 nm to about 70 nm. In one embodiment, the substrate 110, the dielectric layer 120, and the silicon layer 130 form an SOI wafer.

The device 100 may further comprise a metal layer 140 formed over the silicon layer 130. The metal layer 140 may comprise titanium nitride (TiN), a non-superconductor, a superconductor, a ferromagnetic metal, or a combination thereof. In one embodiment, the metal layer 140 may be grown or formed over the silicon layer 130 by physical vapor deposition (PVD). In one embodiment, a _SiO2 layer is grown or formed on the silicon layer 130 prior to forming the metal layer 140 over the silicon layer 130. In one embodiment, the surface of the silicon layer 130 is cleaned prior to forming the metal layer 140 using a piranha solution, an oxygen plasma ( _O2 plasma), or a combination thereof. The metal layer 140 may comprise a thickness (e.g., height) of about 25 nm.

FIG. 2 illustrates a cross-sectional view of the exemplary and non-limiting device 100 of FIG. 1 after removing a portion of the metal layer 140 and the silicon layer 130 according to one or more embodiments described herein. The device 200 may include an exemplary and non-limiting alternative embodiment of the device 100 after removing a portion of the metal layer 140 and the silicon layer 130 to form the structure 210. In one embodiment, a layer may be referred to as an element after removing a portion of the layer. For example, the silicon layer 130 may be referred to as the silicon element 130 after removing a portion of the silicon layer 130 to form the structure 210. As another example, the metal layer 140 may be referred to as the metal element 140 after removing a portion of the metal layer 140 to form the structure 210. In one embodiment, the metal layer 140 and the portion of the silicon layer 130 may be removed from the device 100 using a dry etch. In one embodiment, the dry etch may be performed using an inductively coupled plasma (ICP) with hydrogen bromide (HBr). In one embodiment, removing portions of the metal layer 140 and silicon layer 130 from the device 100 may include electron beam lithography (EBL) patterning using hydrogen silsesquioxane (HSQ) as a negative resist.

In one embodiment, the HSQ resist may be removed from the device 200 using dilute hydrofluoric acid (dHF). In one embodiment, an adhesion layer may be formed on the device 200 by using ALD to deposit _SiO2 over the device 200. In one embodiment, the adhesion layer may have a thickness (e.g., height) of about 5 nm. In one embodiment, the dielectric layer 120 acts as an etch stop layer during removal of the metal layer 140 and the portion of the silicon layer 130 from the device 100. In one embodiment, the metal layer 140 and the portion of the silicon layer 130 are removed from the device 100 in separate steps to form the device 200. In one embodiment, the metal layer 140 and the portion of the silicon layer 130 are removed from the device 100 in a single step to form the device 200. In one embodiment, the removal of the metal layer 140 and the portion of the silicon layer 130 from the device 100 in a single step forms a self-aligned structure.

3 illustrates a cross-sectional view of the example and non-limiting device of FIG. 2 after removing a portion of the metal layer 140 from the structure 210 of the device 200 according to one or more embodiments described herein. The device 300 may include example and non-limiting alternative embodiments of the device 200 after removing a portion of the metal layer 140 from the structure 210 to form the structure 310. In an embodiment, the portion of the metal layer 140 may be removed from the structure 210 using a selective etch. In an embodiment, the portion of the metal layer 140 may be removed from the structure 210 by etching the portion of the metal layer 140 in a solution of H ₂ O/H ₂ O ₂ /NH ₄ OH 5:2:1 at 65 degrees Celsius (° C.). In an embodiment, removing the portion of the metal layer 140 from the structure 210 may include EBL patterning using a chemically semi-amplified resist (CSAR) as a positive resist. In one embodiment, the SiO ₂ adhesion layer may be removed from the device 300 by etching the SiO ₂ adhesion layer with buffered hydrofluoric acid (BHF).

4 illustrates a cross-sectional view of the exemplary and non-limiting device of FIG. 3 after forming a dielectric layer over device 300 according to one or more embodiments described herein. Device 400 can include exemplary and non-limiting alternative embodiments of device 300 formed by growing or forming a dielectric layer 410 over device 300. Dielectric layer 410 can include any material having dielectric properties, such as, but not limited to, silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), and other materials having dielectric properties. In one embodiment, dielectric layer 410 can comprise a thickness (e.g., height) of about 40 nm. In one embodiment, dielectric layer 410 can be formed on device 300 by using ALD to deposit SiO ₂ over device 300. In one embodiment, the CSAR layer can be removed from device 300 prior to forming dielectric layer 410 over device 300. In one embodiment, the dielectric layer 410 acts as a template for the growth of the semiconductor. In one embodiment, the dielectric layer 410 forms a template over the structure 310. In one embodiment, the template determines the geometry of the semiconductor.

FIG. 5 illustrates a cross-sectional view of the exemplary and non-limiting device of FIG. 4 after etching a portion 520 of the silicon layer 130 for removal beneath the metal layer 140, according to one or more embodiments described herein. The device 500 may include an exemplary and non-limiting alternative embodiment of the device 400 formed by etching a portion 520 of the silicon layer 130 from the structure 310 to form a structure 510. In one embodiment, the structure 510 is a template structure. In one embodiment, the template structure further comprises a dielectric layer 410. In one embodiment, the portion 520 of the silicon layer 130 is etched for removal using tetramethyl ammonium hydroxide (TMAH), xenon difluoride (XeF ₂ ) gas, or hot hydrochloric acid (HCl) vapor. In one embodiment, the portion 520 of the silicon layer 130 is etched for removal using 2% TMAH at 80° C. In one embodiment, the silicon layer 130 is exposed using a hydrofluoric acid etch prior to etching the portion 520 of the silicon layer 130 for removal. In one embodiment, the remaining portions of silicon layer 130 that remain after etching portion 520 may provide nucleation seeds that may initiate the growth of a semiconductor (eg, semiconductor 620 in FIG. 6).

In one embodiment, etching the portion 520 of the silicon layer 130 for removal can include EBL patterning using CSAR as a positive resist. In one embodiment, the portion 520 of the silicon layer 130 can be locally exposed prior to removal by creating an opening in a template that the dielectric layer 410 forms over the structure 310 using EBL patterning. In one embodiment, the portion 520 of the silicon layer 130 can be locally exposed prior to removal by locally etching one or more holes in a template that the dielectric layer 410 forms over the structure 310 using a dry etch (e.g., reactive ion etch (RIE), such as an etch performed using ARCHHF ₃ as an etchant gas), a wet etch (e.g., BHF etch, etc.), or a combination thereof. In one embodiment, the metal layer 140 can be protected while the portion 520 of the silicon layer 130 is etched for removal by an adhesion layer comprising SiO ₂ overlying the metal layer 140. In one embodiment, the adhesion layer can include a thickness (e.g., height) of about 5 nm.

6 illustrates a cross-sectional view of the exemplary and non-limiting device of FIG. 5 after growing semiconductor 620 where portion 520 of silicon layer 130 has been removed, according to one or more embodiments described herein. Device 600 may include exemplary and non-limiting alternative embodiments of device 500 formed by growing semiconductor 620 where portion 520 of silicon layer 130 has been removed from structure 510 to form structure 610. In one embodiment, semiconductor 620 is grown by metalorganic chemical vapor deposition (MOCVD) or metalorganic chemical vapor phase epitaxy (MOVPE). In one embodiment, semiconductor 620 includes indium arsenide (InAs). In one embodiment, semiconductor 620 is a III-V semiconductor. In one embodiment, a highly permeable interface between metal layer 140 and semiconductor 620 is formed in situ during the growth of semiconductor 620. In one embodiment, a dHF wet etch is performed prior to growing semiconductor 620 to remove native SiO2 from nucleation seeds provided by remaining portions of silicon layer 130 in structure 510, or to expose features of metal layer 140 in structure 510, or both. In one embodiment, growing semiconductor 620 includes adjusting growth conditions for the aspect ratio of the template structure, the crystal growth direction, the segment shape of metal layer 140 in structure 510, or a combination thereof.

Figure 7 shows an exemplary and non-limiting top-down scanning electron microscope (SEM) micrograph 700 illustrating a device comprising device 400 of Figure 4 according to one or more embodiments described herein. In SEM micrograph 700, a portion of metal layer 140 overlying silicon layer 130 has been selectively removed.

Figure 8 shows an exemplary and non-limiting top-down SEM micrograph 800 illustrating the device 600 of Figure 6 according to one or more embodiments described herein. In the SEM micrograph 800, the semiconductor 620 is grown where a portion of the silicon layer 130 has been etched away to remove the underlying metal layer 140. Figure 8 shows that a highly transparent interface between the metal layer 140 and the semiconductor 620 is formed in situ during the growth of the semiconductor 620.

9 shows an exemplary and non-limiting top-down SEM micrograph 900 illustrating InAs nanowires grown within a partially superconducting template 910 according to one or more embodiments described herein. The SEM micrograph 900 shows that the InAs nanowires are not obscured by a metal layer (e.g., TiN) in a first portion 920 of the template 910. The SEM micrograph 900 further shows that the InAs nanowires are completely obscured by a metal layer in a second portion 930 of the template 910.

Figure 10 shows an exemplary and non-limiting top-down SEM micrograph 1000 showing an InAs nanowire 1010 grown entirely within a superconducting template according to one or more embodiments described herein. The SEM micrograph 1000 shows that the InAs nanowire is completely obscured by a metal layer (e.g., TiN) in a portion 1020 of the template 1010.

11-13 show exemplary and non-limiting transmission electron microscope (TEM) cross-sectional views of the fully superconducting template 1010 of FIG. 10 along line A-A, according to one or more embodiments described herein. FIG. 11 shows a view 1100 illustrating a highly transparent interface between a metal layer 1110 (e.g., TiN) and a semiconductor 1120 (e.g., InAs) formed in situ during growth of the semiconductor 1120. FIG. 12 shows an enlarged view 1200 illustrating a region 1130 of the highly transparent interface between the metal layer 1110 and the semiconductor 1120 of FIG. 11. The brightness of layers 1110 and 1120 are reversed in FIG. 12 relative to their respective brightness in FIG. 11 because different TEM detectors were used to capture FIGS. 11 and 12. FIG. 13 shows an enlarged view 1300 illustrating a region 1210 of the semiconductor 1120 of FIG. 12. As shown by FIG. 13, the semiconductor 1120 can include a single crystal structure that does not have grain boundaries.

14 illustrates an exemplary and non-limiting graph 1400 showing the results of an energy dispersive x-ray analysis (EDX) scan of the highly transparent semiconductor/metal interface shown in FIG. 11 according to one or more embodiments described herein. Each curve in graph 1400 plots counts of a given element versus depth within the interface. Curve 1410 illustrates nitrogen (N), curve 1420 illustrates titanium (Ti), curve 1430 illustrates arsenic (As), and curve 1440 illustrates indium (In). As illustrated by FIG. 14, TiN dominates the interface within region 1450 of graph 1400, whereas InAs dominates the interface within region 1460 of graph 1400.

Figure 15 shows an exemplary and non-limiting top-down SEM micrograph 1500 illustrating a device 1510 with a highly transparent semiconductor/metal interface according to one or more embodiments described herein. The device 1510 can include a highly transparent semiconductor/non-superconductor interface between the semiconductor and the non-superconductor at contact 1520. The device 1510 can further include a highly transparent semiconductor/superconductor interface between the semiconductor and the superconductor at contact 1530.

16-24 show example and non-limiting charts illustrating electrical characteristics of the semiconductor/superconductor interface at the contact 1530 of the device 1510 according to one or more embodiments described herein. FIG. 16 shows the results of tuning the back gate of the device 1510 at a temperature of 14 Kelvin (K) by varying V _BG while holding the split gate bias voltage (V _QPC ) and the side gate bias voltage (V _SG ) constant at 0V. In particular, FIG. 16 shows an example and non-limiting graph 1600 showing differential conductance as a function of the back gate bias voltage (V _BG ). As shown by the vertical dotted line in FIG. 16, the back gate bias voltage of the device 1510 can be set to −15V to be in the tunneling regime and to cool the temperature of the device 1510 to a reference temperature.

17-22 show the results of split gate conditioning of device 1510 at a temperature of 20 millikelvin (mK) while V _SG is held constant at 0V. FIG. 17 shows an example and non-limiting linear scale graph 1700 of differential conductance versus V _QPC and source-drain bias voltage (V _SD ). FIG. 18 shows an example and non-limiting logarithmic scale graph 1800 of differential conductance versus V _QPC and V _SD . FIG. 19 shows an example and non-limiting graph 1900 of differential conductance as a function of V _SD at a V _QPC of about −1.1 volts, which corresponds to the solid line across the V _QPC axis of graph 2200 shown by FIG. 22. In particular, graph 1900 shows the Andreev-enhanced conductance due to the semiconductor/superconductor interface at contact 1530 of device 1510.

FIG. 20 shows an exemplary and non-limiting graph 2000 illustrating differential conductance as a function of V _SD at a V _QPC of about −3.375 volts, which corresponds to the dotted line across the V _QPC axis of graph 2200 shown by FIG. 22. In particular, graph 2000 illustrates the emergence of sub-gap states at the semiconductor/superconductor interface at contact 1530 of device 1510. FIG. 21 shows an exemplary and non-limiting graph 2100 illustrating differential conductance as a function of V _SD at a V _QPC of about −3.75 volts, which corresponds to the dotted line across the V _QPC axis of graph 2200 shown by FIG. 22. In particular, graph 2100 illustrates spectroscopy of the superconducting gap at the semiconductor/superconductor interface at contact 1530 of device 1510. FIG. 22 illustrates an example and non-limiting logarithmic scale graph 2200 showing differential conductance versus V _QPC and V _SD in accordance with one or more embodiments described herein.

23-24 show the results of side gate tuning of device 1510. FIG. 23 shows an example and non-limiting linear scale graph 2300 showing differential conductance versus V _SG and V _SD in accordance with one or more embodiments described herein. FIG. 24 shows an example and non-limiting graph 2400 showing differential conductance as a function of V _SD at a V _SG of about −2.6 volts, which corresponds to the solid line across the V _SG axis of graph 2300 shown by FIG.

25-44 show cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface according to one or more embodiments described herein. 25-44 show that embodiments of the present disclosure can implement devices with a highly transparent semiconductor/metal interface in various configurations. Each device shown in 25-44 includes a semiconductor grown where a portion of the silicon layer (e.g., portion 520 of FIG. 5) has been removed. Device 2500 of FIG. 25 can include an example and non-limiting alternative embodiment of device 600 of FIG. 6 that features continuous stripes of metal layer 140. In one embodiment, device 2500 can be formed by omitting the removal of a portion of metal layer 140 from structure 210 shown in FIG. 3. In this embodiment, structure 2510 can be formed by growing semiconductor 620 from where a portion of silicon layer 130 has been removed.

Device 2600 of FIG. 26 may include an example and non-limiting alternative embodiment of device 600 of FIG. 6 after removing a portion of metal layer 140 from structure 610 to form structure 2610. In one embodiment, a portion of metal layer 140 may be removed from structure 210 using a selective etch. In one embodiment, a portion of metal layer 140 may be removed from structure 610 by etching a portion of metal layer 140 in a solution of _{H2O / H2O2} / _NH4OH 5:2:1 at 65° C. In one embodiment, removing a portion of metal layer 140 from structure 610 may include EBL patterning using CSAR as a positive resist.

Device 2700 of Figure 27 may include an example and non-limiting alternative embodiment of device 2500 of Figure 25 that features interrupted segments of metal layer 140. Device 2700 may be formed by removing a portion of metal layer 140 from structure 2510 to form structure 2710. In one embodiment, the portion of metal layer 140 may be removed from structure 2510 by etching the portion of metal layer 140 in a solution of _H2O / _H2O2 / _{NH4OH 5} :2:1 at 65°C. In one embodiment, removing the portion of metal layer 140 from structure 2510 may include EBL patterning using CSAR as a positive resist.

28-38 show cross-sectional views of example and non-limiting devices having highly transparent semiconductor/metal interfaces achieved using multiple metals with different characteristics according to one or more embodiments described herein. Each metal layer shown in FIGS. 28-38 interfaces with a semiconductor grown where a portion of a silicon layer (e.g., portion 520 in FIG. 5) has been removed. Each interface in FIGS. 28-38 is formed in situ during the growth of the semiconductor.

FIG. 28 illustrates an example and non-limiting device 2800 that includes a metal layer 2810 having different properties than the metal layer 140 described above with respect to FIGS. 1-6. For example, if the metal layer 140 includes TiN, the metal layer 2810 may include a non-superconductor. As another example, if the metal layer 140 includes a ferromagnetic metal, the metal layer 2810 may include a superconductor. As another example, if the metal layer 140 includes a non-superconductor, the metal layer 2810 may include a ferromagnetic metal. In an embodiment, the metal layer 2810 may include TiN, a non-superconductor, a superconductor, a ferromagnetic metal, or a combination thereof. The device 2900 of FIG. 29 may include an example and non-limiting alternative embodiment of the device 2800 of FIG. 28 that is formed by removing one or more portions of the metal layer 2810 from the device 2800 to form the structure 2910. FIG. 30 illustrates an example and non-limiting device 3000 formed by growing semiconductor 620 between metal layer 2810 and metal layer 140 overlying metal layer 2810. Device 3100 of FIG. 31 can include example and non-limiting alternative embodiments of device 3000 of FIG. 30 that remove one or more portions of metal layer 2810 from device 3000 to form structure 3110.

32 illustrates an exemplary and non-limiting device 3200 that includes a metal layer 3210 having different properties than the metal layer 140 described above with respect to FIGS. 1-6. For example, if the metal layer 140 includes a first ferromagnetic metal (e.g., nickel (Ni)), the metal layer 3210 can include a second ferromagnetic metal (e.g., cobalt (Co)). As another example, if the metal layer 140 includes a first non-superconductor (e.g., phosphorus bronze), the metal layer 3210 can include a second non-superconductor (e.g., cupro-nickel). As another example, if the metal layer 140 includes a first superconductor (e.g., TiN), the metal layer 3210 can include a second superconductor (e.g., niobium titanium (NbTi)).

33 illustrates an exemplary and non-limiting device 3300 formed by growing semiconductor 620 between metal layer 3210, metal layer 140, and metal layer 2810 underlying both metal layer 3210 and metal layer 140. FIG. 34 illustrates an exemplary and non-limiting device 3400 formed by growing semiconductor 620 between metal layer 3210, metal layer 140, and metal layer 2810. Device 3400 can include a cavity structure defined by metal layer 3210, metal layer 140, metal layer 2810, and a silicon layer (not shown) underlying metal layer 2810. In one embodiment, metal layer 3210, metal layer 2810, metal layer 140, and silicon layer each provide a sidewall of the cavity structure. FIG. 35 illustrates an exemplary and non-limiting device 3500 formed by growing semiconductor 620 between metal layer 3210, metal layer 140, and metal layer 2810. In device 3500, semiconductor 620 is grown over metal layer 2810. FIG. 36 illustrates an exemplary and non-limiting device 3600 formed by growing semiconductor 620 between metal layer 3210, metal layer 140, and metal layer 2810. Device 3600 can include a cavity structure defined by metal layer 3210, metal layer 140, metal layer 2810, and a silicon layer (not shown) underlying metal layer 2810. In one embodiment, metal layer 3210, metal layer 2810, metal layer 140, and silicon layer each provide a sidewall of the cavity structure.

FIG. 37 illustrates an exemplary and non-limiting device 3700 comprising a metal layer 3710 having properties different from both the metal layer 2810 described above with respect to FIGS. 28-36 and the metal layer 140 described above with respect to FIGS. 1-6. For example, if the metal layer 140 comprises a superconductor and the metal layer 2810 comprises a first ferromagnetic metal (e.g., nickel (Ni)), the metal layer 3710 can comprise a second ferromagnetic metal (e.g., cobalt (Co)). As another example, if the metal layer 140 comprises a ferromagnetic metal and the metal layer 2810 comprises a first non-superconductor (e.g., phosphorus bronze), the metal layer 3710 can comprise a second non-superconductor (e.g., cupro-nickel). As another example, if metal layer 140 comprises a non-superconductor and metal layer 2810 comprises a first superconductor (e.g., TiN), metal layer 3710 may comprise a second superconductor (e.g., niobium titanium (NbTi)). Device 3700 may comprise a cavity structure defined by metal layer 3210, metal layer 140, metal layer 2810, metal layer 3710, and a silicon layer (not shown) underlying metal layer 3710. In one embodiment, metal layer 3710, metal layer 3210, metal layer 2810, metal layer 140, and silicon layer each provide a sidewall of the cavity structure.

38 illustrates an exemplary and non-limiting device 3800 formed by growing semiconductor 620 between metal layer 3710, metal layer 3210, metal layer 140, and metal layer 2810. Device 3800 can include a cavity structure defined by metal layer 3710, metal layer 3210, metal layer 140, metal layer 2810, and a silicon layer (not shown) underlying metal layer 2810. In one embodiment, metal layer 3710, metal layer 3210, metal layer 2810, metal layer 140, and silicon layer each provide a sidewall of the cavity structure.

39-43 show cross-sectional views of example and non-limiting devices having a highly transparent semiconductor/metal interface realized with a metal overlying the semiconductor according to one or more embodiments described herein. FIG. 39 shows an example and non-limiting device 3900 formed by growing a semiconductor 620 beneath a metal layer 140. The device 3900 can include a cavity structure defined by the metal layer 140 and a silicon layer (not shown) underlying the metal layer 140. In one embodiment, the metal layer 140 and the silicon layer each provide a sidewall of the cavity structure. FIG. 40 shows an example and non-limiting device 4000 formed by growing a semiconductor 620 between the metal layer 140 and the metal layer 2810. The device 4000 can include a cavity structure defined by the metal layer 140, the metal layer 2810, and a silicon layer (not shown) underlying the metal layer 140. In one embodiment, metal layer 140, metal layer 2810, and silicon layer each provide a sidewall of the cavity structure.

41 illustrates an exemplary and non-limiting device 4100 formed by growing a semiconductor 620 between metal layer 140 and metal layer 2810. The device 4100 can include a cavity structure defined by metal layer 140, metal layer 2810, and a silicon layer (not shown) underlying metal layer 2810. In one embodiment, metal layer 140, metal layer 2810, and a silicon layer each provide a sidewall of the cavity structure. FIG. 42 illustrates an exemplary and non-limiting device 4200 formed by growing a semiconductor 620 between metal layer 140 and metal layer 2810. The device 4200 can include a cavity structure defined by metal layer 140, metal layer 2810, and a silicon layer (not shown) underlying metal layer 140. In one embodiment, metal layer 140, metal layer 2810, and a silicon layer each provide a sidewall of the cavity structure. FIG. 43 illustrates an exemplary and non-limiting device 4300 formed by growing semiconductor 620 between metal layer 140, metal layer 2810, and metal layer 3710. Device 4300 can include a cavity structure defined by metal layer 140, metal layer 2810, metal layer 3710, and a silicon layer (not shown) underlying metal layer 3710. In one embodiment, metal layer 140, metal layer 2810, metal layer 3710, and silicon layer each provide a sidewall of the cavity structure.

44 illustrates a cross-sectional view of an example and non-limiting device 4400 with a highly transparent semiconductor/metal interface realized with a structure patterned in a self-aligned manner according to one or more embodiments described herein. The device 4400 may comprise an example and non-limiting alternative embodiment of the device 100 after removing portions of the metal layer 140 and the silicon layer 130 in a single step to form structures 4410, 4420, and 4430. As illustrated by FIG. 44, the structure 4420 may comprise a semiconductor 620 grown where the portion of the silicon layer 130 was removed. In an embodiment, one or more of the structures 4410-4430 may comprise a gate structure. For example, the structure 4420 may comprise a back gate. As another example, the structure 4410 and/or the structure 4430 may comprise a split gate electrode. As another example, the structure 4410 and/or the structure 4430 may comprise a side gate electrode.

The semiconductor nanowires shown in the embodiments of the present disclosure can be grown inside lateral cavities. This mechanism has been termed template-assisted selective epitaxy (TASE) since the cavities can act as templates to guide the semiconductor during growth. The template determines the geometry of the embedded semiconductor structures and can play an essential role in the fabrication of devices with highly transparent semiconductor/metal interfaces. TASE semiconductor growth dynamics can be realized in vertical and lateral _SiO2 templates. The embodiments disclosed herein can extend the capabilities of the TASE technique by incorporating superconducting TiN segments into the template to facilitate hybrid superconductor/semiconductor devices. This approach is termed hybrid TASE. An example hybrid TASE process flow overview is shown in Figures 45-50.

The fabrication of the hybrid template may be based on an 8 inch (20.32 cm) SOI wafer that may feature a BOX layer 4520 with a thin single crystal SOI layer 4530 on top. As shown by the example of FIG. 45, the SOI wafer may comprise a thin Si layer (e.g., SOI layer) 4530 separated from a Si substrate 4510 by a buried SiO2 layer (e.g., BOX layer 4520) and may be metallized with a 25 nm thick film of TiN 4540 to form the device 4500 of FIG. 45. The BOX layer 4520 may be 150 nm thick for all devices shown here. The thickness of the SOI layer 4530 may range from 40 nm to 70 nm.

The (110) orientation of the SOI layer used in this process flow may differ from the (001) orientation of the SOI layer that is commonly used to achieve lateral TASE semiconductor growth. Due to the lower symmetry of the (110) SOI layer used, the exemplary process flow can incorporate III-V nanostructures laterally in the <001>, <110>, and <111> directions on a single chip by taking advantage of the different growth dynamics in each direction. The SOI wafer can be metallized by sputtering a 25 nm thick layer of TiN 4540. The SOI/TiN bi-layer nanowires can be patterned by dry etching of the unprotected TiN and SOI regions in a single step to form the device 4600 of FIG. 46. This can encourage the TiN and SOI structures to be self-aligned. The self-aligned nanowire bi-layer structure can be patterned into the TiN 4540 and SOI layer 4530 as shown in FIG. 46. In FIG. 46, the nanowires terminate in a square. As shown in FIG. 47, the TiN4540 can be selectively etched with respect to this square.

In a selective etching step, the TiN layer 4540 can be partially removed at one end of the wire to form the device 4700 of FIG. 47. The structure can be masked in a conformal 40 nm thick template _SiO2 layer 4810 which can be locally etched in the areas where the TiN layer 4540 was selectively removed before forming the device 4800 of FIG. 48. This is shown in the top view SEM micrograph 5100 of FIG. 51 showing the device 4800. Selective etching of the SOI nanowire structure creates a hollow cavity 4910 with _SiO2 and TiN sidewalls. Selective etching of the Si wire creates a cavity formed by the template SiO2 and TiN stripes. A segment of Si remains at the end of the cavity. The length of the cavity can be determined by the etch time chosen such that a segment of Si remains at the end of the cavity to form the device 4900 of FIG. 49. This is shown in the top-down SEM micrograph 5200 of Figure 52, which shows device 4900. The Si segments can act as seeds for epitaxial growth of InAs nanowires, as shown in Figure 50.

In a final step, InAs nanowires 5010 can be grown inside the template structure by MOVPE to form the device 5000 of FIG. 50. This is shown in the top-down SEM micrograph 5300 of FIG. 53 showing the device 5000. Residual Si segments in the template can act as nucleation seeds from which the InAs growth begins. For the InAs growth, the V/III material ratio can be adjusted so that the nanowire radially fills the template, thereby creating an interface between the InAs semiconductor and the TiN superconductor. Thus, the height of the nanowire can be determined by the thickness of the SOI layer 4530 (e.g., 40 nm to 70 nm), and the width of the lithographically defined template (e.g., 40 nm to 100 nm) can be set to the width of the nanowire. The length of the nanowire can typically be 1 μm and can be adjusted by the Si etching and InAs growth time. Due to different diffusion mechanisms of the precursor species trimethylindium (TMIn) and tertbutylarsine (TBA) inside the template, the effective V/III ratio at the growth front may depend on the aspect ratio of the empty cavity 4910. Since the effective aspect ratio may change during growth, not only may the effective V/III ratio change as a function of the nanowire length, but also the growth rates of the {110} and {111}B facets. The nanowire InAs may exhibit distinct {111}B facets as it approaches the end of the template.

The following disclosure describes in more detail the fabrication of templates with incorporated TiN segments. In one embodiment, the wafer may be cleaned in concentrated piranha (sulfuric acid and hydrogen peroxide 2:1), followed by a rinse in ultrapure water and cleaning in a 600 watt (W) oxygen plasma. In one embodiment, a 3 nm SiO2 layer may be deposited by ALD in an oxygen plasma ambient to add a thin SiO2 layer on top of the native SiO2 formed by the etching step. A 25 nm thick layer of TiN may be deposited on the wafer by DC reactive magnetron sputtering, as shown in FIG. 45.

The Si/TiNbi-layer nanostructures can be patterned by inductively coupled HBr plasma etching. For this, a 50 nm thick mask of hydrogen silsesquioxane (HSQ) negative resist can be defined using electron beam lithography at 100 kV. After etching of both the Si and TiN layers, the HSQ mask can be removed in dilute hydrofluoric acid. The Si/TiN wires that can be patterned in this manner are approximately 2 μm long and have widths ranging from 40 nm to 100 nm. This lithographically defined width can correspond to the minimum width of the InAs nanowires grown at a later stage. The Si/TiN wires can end in a square as shown in FIG. 46.

The Si/TiN wires can be encapsulated in a 5 nm _SiO2 layer deposited by oxygen plasma ALD to ensure adhesion of an 80 nm AR-P6200.04 positive resist layer. Electron beam lithography can be used to pattern squares at one end of the wires. As shown in Figure 47, the ALD grown _SiO2 layer can be etched in buffered hydrofluoric acid (BHF) and the TiN squares can be selectively removed in a wet etch solution of _H2O , _H2O2 , and _NH4OH (5: ₂ :1) at 65°C.

The resist can be removed using an organic solvent and a 40 nm layer of SiO2 can be grown using oxygen plasma ALD. This _SiO2 layer can guide the growth of the III-V structures and is called the SiO2 template. To reduce the etch rate of the SiO2 template, the device can be annealed at 600° C. for 30 seconds. Using electron beam lithography on an 80 nm layer of AR-P6200.04 positive resist, openings can be defined in the areas where the TiN was previously etched. The openings can be transferred to the _SiO2 template using reactive ion etching in an Ar/ _CHF3 atmosphere and BHF etching. In this way, the Si squares at the ends of each wire can be exposed. In one embodiment, the exposed areas should not overlap the TiN stripes on top of the sacrificial Si wires so that the TiN features remain protected by the template _SiO2 . This situation is shown in FIG. 48. The exposed Si squares can help to selectively etch the sacrificial Si structures and create the cavities formed by the template _SiO2 and TiN. The etching can be carried out in a 2% tetramethylammonium hydroxide (TMAH) solution at 80°C. The length of the cavities can be determined by the etching time which can be chosen such that the Si segments remain, as shown in Fig. 49. Due to the anisotropy of the etching, these Si segments exhibit typical {111} facets, as shown in Fig. 52. They are oriented perpendicular to the (110) wafer surface.

The following disclosure details an example of InAs semiconductor growth inside the template cavities. Prior to MOVPE semiconductor growth, the template can be immersed in dilute hydrofluoric acid (DHF). This etch can serve two purposes, as it removes the SiO2 protective layer under the embedded TiN regions, and etches the native SiO2 from the Si{111} seed facet while creating a hydrogen-terminated facet. At the same time, the dimensions of the inner template can increase slightly during the DHF immersion. This effect can be seen in Figure 54, where the InAs nanowires are about 20 nm wider than the TiN regions.

After etching in DHF, the chips may be transferred into a MOVPE growth reactor where they may be annealed at 600° C. under a flow of TBA. H ₂ may be used as a carrier gas and InAs growth may be initiated when TMIn is introduced into the reactor. InAs growth may be carried out at a pressure of 60 Torr (8 kPa) at a temperature of 550° C. or 600° C. and a V/III ratio between 70 and 150. Examples of typical growth times range from 40 to 60 minutes. The length of the nanowires thus grown may depend not only on the growth conditions in the reactor, but also, in particular, on the aspect ratio and crystal orientation of the template and the area of exposed TiN present in the cavity. The aspect ratio of the template may be determined by the SOI thickness, the lithographically defined width of the template, and the Si backetch length. InAs nanowires grown inside a template with a low aspect ratio (e.g., where the cavity cross-sectional area may be about 90 nm x 120 nm and the cavity length is 1 μm) may have a higher growth rate compared to wires in a high aspect template on the same chip. A typical device with a high aspect ratio may feature a cross-sectional area of 50 nm x 50 nm, and a length of over 1 μm. As the effective length of the cavity decreases during growth, an acceleration of the growth rate may be observed as the growth front approaches the template opening.

The following disclosure details the contacts and gates of an example device. After InAs growth, a bilayer of PMMA669.04 (300 nm) and AR-P672.03 (100 nm) resists may be spun and the device contacts may be patterned using e-beam lithography. After resist development in methyl isobutyl ketone (MIBK) and isopropanol (IPA) with a ratio of 1:2, the SiO2 template may be locally etched with BHF in the contact areas and the exposed InAs regions may then be passivated by immersion in a 2% ammonium sulfide solution before evaporation of Ti (10 nm) and Au (150 nm). After lift-off in dimethyl sulfoxide (DMSO), a single layer of AR-P672.03 (100 nm) may be spun and the gate structures may be patterned by e-beam lithography. The resist may be developed in MIBK:IPA (1:2), layers of Ti (5 nm) and Au (20 nm) may be evaporated, and lift-off may be performed in DMSO. A Si handle wafer may be used as an additional backgate. It may be contacted by etching the native SiO2 in BHF and evaporating Ti (5 nm) and Pt (40 nm). During this step, the devices on the chip may be protected by a 6.2 μm thick layer of photoresist.

54-56 show exemplary and non-limiting TEM cross-sectional views of device 5000 of FIG. 50 along line B-B, according to one or more embodiments described herein. FIG. 54 shows a diagram 5400 illustrating a highly transparent interface between metal layer 5410 (e.g., TiN) and semiconductor 5420 (e.g., InAs) formed in situ during growth of semiconductor 5420. FIG. 55 shows an enlarged view 5500 illustrating region 5430 of the highly transparent interface between metal layer 5410 and semiconductor 5420 of FIG. 54. FIG. 56 shows an enlarged view 5600 illustrating region 5440 of semiconductor 5420 of FIG. 54. As shown by FIG. 56, semiconductor 5420 may include a single crystal structure without grain boundaries.

FIGS. 54-55 show exemplary and non-limiting TEM cross-sectional views of device 5000 of FIG. 50 taken from the view of line 5310 shown in FIG. 53. FIG. 54 shows a view 5400 showing the highly permeable interface between metal layer 4540 and semiconductor 5010 from the view of line 5310. FIG. 55 shows an enlarged view 5500 showing the region 5410 of the highly permeable interface between metal layer 4540 and semiconductor 5010 of FIG. 54.

56 illustrates a flow diagram of an exemplary and non-limiting method 5600 that can promote a highly transparent semiconductor/metal interface according to one or more embodiments described herein. Repeated descriptions of elements used in other embodiments described herein are omitted for brevity. At 5610, the method 5600 can include forming an SOI (e.g., silicon layer 130 of FIG. 1) over the wafer. At 5620, the method 5600 can include depositing a metal (e.g., metal layer 140 of FIG. 1) on the SOI. At 5630, the method 5600 can include dry etching the metal and forming a structure (e.g., structure 210 of FIG. 2) by dry etching the SOI. At 5640, the method 5600 can include forming a template over the structure. At 5650, the method 5600 can include etching a portion of the SOI (e.g., portion 520 of FIG. 5) for removal of the metal underneath. At 5660, the method 5600 can include growing a semiconductor (e.g., semiconductor 620 of FIG. 6) where the portion of the SOI was removed.

In one embodiment, the metal comprises TiN, a superconductor, a non-superconductor, a ferromagnetic metal, or a combination thereof. In one embodiment, the template determines the geometry of the semiconductor. In one embodiment, growing the semiconductor is performed using MOVPE. In one embodiment, the interface between the metal and the semiconductor is formed in situ during growth of the semiconductor. In one embodiment, the method 5600 further comprises exposing the SOI using a hydrofluoric acid etch before etching the portion of the SOI for removal. In one embodiment, the method 5600 further comprises depositing a dielectric on the SOI before depositing the metal.

57 illustrates a flow diagram of another exemplary and non-limiting method that can promote a highly transparent semiconductor/metal interface according to one or more embodiments described herein. Repeated descriptions of elements used in other embodiments described herein are omitted for brevity. At 5710, the method 5700 can include forming a template structure comprising a metal element (e.g., metal layer 140 of structure 510 of FIG. 5) and a silicon element (e.g., silicon layer 130 of structure 510) by etching a portion of the silicon element (e.g., portion 520) for removal. At 5720, the method 5700 can include creating an interface between the metal element and the semiconductor (e.g., semiconductor 620 of FIG. 6) by growing a semiconductor where the portion of the silicon element was removed.

In one embodiment, the silicon elements include silicon-on-insulator, polycrystalline silicon, or a combination thereof. In one embodiment, the remaining portions of the silicon elements (e.g., silicon layer 130 of structure 610 of FIG. 6) remaining after etching provide nucleation seeds to initiate semiconductor growth. In one embodiment, the semiconductor is a III-V semiconductor. In one embodiment, the template structure further comprises a dielectric layer (e.g., dielectric layer 410 of FIG. 5) overlying the metal elements and the silicon elements. In one embodiment, the silicon elements include a (110) crystal orientation. In one embodiment, the template structure is formed on a silicon wafer. In one embodiment, the method 5700 can further include dry etching the metal layer and the silicon layer in a single step to self-align the metal elements and the silicon elements.

58 illustrates a flow diagram of another exemplary and non-limiting method that can promote a highly transparent semiconductor/metal interface according to one or more embodiments described herein. Repeated descriptions of elements used in other embodiments described herein are omitted for brevity. At 5810, the method 5800 can include forming a cavity structure including a first sidewall comprising a metal element (e.g., metal layer 140 of structure 510 of FIG. 5) and a second sidewall comprising a silicon element (e.g., silicon layer 130 of structure 510). At 5820, the method 5800 can include growing a semiconductor (e.g., semiconductor 620 of FIG. 6) in the cavity structure using the silicon element as a nucleation seed to form an interface between the metal element and the semiconductor.

In one embodiment, the cavity structure overlies a silicon-on-insulator wafer. In one embodiment, forming the cavity structure includes etching a portion of the silicon element (e.g., portion 520 of FIG. 5) for removal. In one embodiment, the length of the cavity structure corresponds to the etching time used to form the cavity structure. In one embodiment, the height of the semiconductor is determined by the thickness of the dielectric layer overlying the cavity structure. In one embodiment, the growth of the semiconductor is guided by one or more geometric shapes of the cavity structure.

To provide context for various aspects of the presently disclosed subject matter, FIG. 59 and the following discussion provide a general description of a suitable environment in which various aspects of the presently disclosed subject matter may be implemented. FIG. 59 illustrates that a suitable operating environment 5900 for implementing various aspects of the present disclosure may also include a computer 5912. The computer 5912 may also include a processing unit 5914, a system memory 5916, and a system bus 5918. The system bus 5918 couples system components, including but not limited to the system memory 5916, to the processing unit 5914. The processing unit 5914 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 5914. The system bus 5918 may be any of several types of bus structures including a memory bus or memory controller, a bus for peripherals or external bus, or a local bus using any of the various available bus architectures, or combinations thereof, including but not limited to Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1094), and Small Computer Systems Interface (SCSI). The system memory 5916 may also include volatile memory 5920 and non-volatile memory 5922. The Basic Input/Output System (BIOS), containing the basic routines for transferring information between elements within the computer 5912, such as during start-up, is stored in the non-volatile memory 5922. By way of example and not limitation, the non-volatile memory 5922 may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). The volatile memory 5920 may also include random access memory (RAM) that acts as external cache memory. By way of example and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), Direct Rambus RAM (DRRAM), Direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM.

The computer 5912 may also include removable/non-removable, volatile/non-volatile computer storage media. FIG. 59 shows, for example, disk storage 5924. Disk storage 5924 may include, but is not limited to, devices such as magnetic disk drives, floppy (R) disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 5924 may also include storage media, separately or in combination with other storage media, including, but not limited to, optical disk drives such as compact disk ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewriteable drives (CD-RW drives), or digital versatile disk ROM drives (DVD-ROM). To facilitate connection of disk storage 5924 to the system bus 5918, a removable/non-removable interface, such as interface 5926, is typically used. Fig. 59 also illustrates that software acts as an interface between a user and the basic computer resources described in suitable operating environment 5900. Such software may include, for example, an operating system 5928. The operating system 5928, which may be stored on disk storage 5924, acts to control and allocate resources of the computer 5912. System applications 5930 take advantage of the management of resources by the operating system 5928 through, for example, program modules 5932 and program data 5934 stored either in system memory 5916 or on disk storage 5924. It is to be understood that the present disclosure may be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer 5912 through an input device 5936. The input devices 5936 include, but are not limited to, pointing devices such as a mouse, trackball, or stylus, touch pads, keyboards, microphones, joysticks, game pads, satellite dishes, scanners, TV tuner cards, digital cameras, digital video cameras, web cameras, and the like. These and other input devices connect to the processing unit 5914 through the system bus 5918 via interface ports 5938. Interface ports 5938 include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). The output device(s) 5940 use some of the same types of ports as the input device(s) 5936. Thus, for example, a USB port may be used to provide input to the computer 5912 as well as to output information from the computer 5912 to the output device(s) 5940. An output adapter 5942 is provided to illustrate the presence of some output device(s) 5940 such as monitors, speakers, and printers, among other output devices 5940 that require special adapters. Output adapters 5942 include, by way of example and not limitation, video cards and sound cards that provide a means of connection between the output device 5940 and the system bus 5918. It may be noted that other devices, such as a remote computer 5944, and/or systems of devices, provide both input and output capabilities.

The computer 5912 can operate in a networked environment using logical connections to one or more remote computers, such as the remote computer 5944. The remote computer 5944 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer device, or other common network node, and typically includes many of the elements or elements described above in connection with the computer 5912. For simplicity, only one memory storage device 5946 is shown with the remote computer 5944. The remote computer 5944 is logically connected to the computer 5912 through a network interface 5948, which is then physically connected via a communication connection 5950. The network interface 5948 encompasses wired communication networks such as local area networks (LANs), wide area networks (WANs), cellular networks, or wireless communication networks, or both. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereof, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection 5950 refers to the hardware/software used to connect network interface 5948 to system bus 5918. Although communications connection 5950 is shown inside computer 5912 for clarity of illustration, communications connection 5950 can also be external to computer 5912. The hardware/software for connecting to network interface 5948 can include internal and external technologies such as modems, including ordinary telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards, for illustrative purposes only.

The present invention may be a system, method, apparatus, or computer program product, or a combination thereof, at any possible level of technical detail integration. The computer program product may include one (or more) computer readable storage medium having computer readable program instructions for causing a processor to execute aspects of the present invention. The computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may include portable computer diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs, or flash memories), static random access memories (SRAMs), portable compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves with instructions recorded therein, and any suitable combinations thereof. As used herein, computer-readable storage media should not be construed as being, per se, ephemeral signals such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted through wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing device/processing device or to an external computer or storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing device/processing device receives the computer-readable program instructions from the network and routes the computer-readable program instructions to the computer-readable storage medium within each computing device/processing device for storage. The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages including object oriented programming languages such as Smalltalk®, C++, and procedural programming languages such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the invention, an electronic circuit, including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, may be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine, such that the instructions executed by the processor of the computer or other programmable data processing apparatus create means for performing the functions/operations specified in one or more blocks of the flowcharts and/or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium and capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored includes a product including instructions for performing aspects of the functions/operations specified in one or more blocks of the flowcharts and/or block diagrams. The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational operations to generate a computer-implemented process such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions/operations specified in one or more blocks of the flowcharts and/or block diagrams.

The flowchart diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart diagrams or block diagrams may represent a module, segment, or part of an instruction that includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may be performed out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, depending on the functionality involved, or in some cases the blocks may be executed in the reverse order. It should also be noted that each block in the block diagrams and/or flowchart diagrams, and combinations of blocks in the block diagrams and/or flowchart diagrams, may be implemented by a dedicated hardware-based system that executes the specified functions or operations, or a combination of dedicated hardware and computer instructions.

Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one or more computers, or both, those skilled in the art will recognize that the disclosure can also be implemented or may be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types or both. Those skilled in the art will also appreciate that the computer-implemented methods of the present invention can be implemented with other computer system configurations, including single or multi-processor computer systems, mini-computing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be implemented in a distributed computing environment in which tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure may be implemented on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, the computer-executable components may be executed from a memory that may include or be comprised of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Additionally, one or more embodiments described herein may execute the code of the computer-executable components in a distributed manner, e.g., with multiple processors that are combined or cooperate to execute the code from one or more distributed memory units. As used herein, the term "memory" may encompass a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

As used in this application, terms such as "component," "system," "platform," "interface," and the like, can refer to or include a computer-related or machine-related entity that includes one or more specific functionalities, or both. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. By way of example, both an application running on a server and the server can be a component. One or more components can reside within a process or a thread of execution, or both, and a component can be localized on one computer or distributed among two or more computers, or both. In another example, each component can execute from various computer-readable media having various data structures stored thereon. A component may communicate with local and/or remote processes according to signals, etc., having one or more data packets (e.g., data from one component communicating with another component in a local or distributed system, or communicating with other systems via signals over a network such as the Internet). As another example, a component may be a device having a particular functionality provided by mechanical parts operated by electrical or electronic circuits operated by software or firmware applications executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware applications. As yet another example, a component may be a device providing a particular functionality through electronic components without mechanical parts, where the electronic components may include a processor or other means for executing software or firmware that provides at least a portion of the functionality of the electronic components. In one aspect, a component may emulate an electronic component via a virtual machine, for example in a cloud computing system.

In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, "X employs A or B" is satisfied in any of the foregoing examples if X employs A, X employs B, or X employs both A and B. Also, as used in this specification and the accompanying drawings, the articles "a" and "an" should generally be construed to mean "one or more" unless otherwise specified or clear from the context to cover the singular form. As used herein, the terms "example" and/or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and/or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

As used herein, the term "processor" may refer to substantially any computing processing device or device, including, but not limited to, a single-core processor, a single processor with software multithreading, a multi-core processor, a multi-core processor with software multithreading, a multi-core processor with hardware multithreading, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or improve the performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component that relate to the operation and functionality of a component are utilized to refer to a "memory component," an entity embodied in a memory, or a component that comprises a memory. It should be understood that the memory and/or memory components described herein can be either volatile or non-volatile memory, or can include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory may include, for example, RAM that may act as external cache memory. By way of example and not limitation, RAM may include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), etc. Memory is available in many forms, such as SDRAM, Enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), Direct Rambus RAM (DRRAM), Direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to, these and any other suitable types of memory.

The foregoing includes merely examples of systems and computer-implemented methods. Of course, in order to describe this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, and one of ordinary skill in the art may recognize that many further combinations and permutations of the present invention are possible. Furthermore, to the extent that terms such as "including," "having," "possessing," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when "comprising" is used as a transitional term in a claim.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with Government support under 140D6318C0028 awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention.

The description of various embodiments has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims (19)

forming a silicon-on-insulator (SOI) layer over the wafer;
depositing a metal on the SOI;
forming a structure by dry etching a portion of the metal to form a metal element and dry etching a portion of the SOI to form a SOI element ;
forming a template over the structure;
forming a cavity structure by etching a portion of the SOI element to remove the metal underneath;
and growing a semiconductor where a portion of the SOI element has been removed , using the remaining portion of the SOI element as a nucleation seed . The method of claim 1, wherein the metal comprises TiN, a superconductor, a non-superconductor, a ferromagnetic metal, or a combination thereof. 3. The method of claim 1 or 2, further comprising: exposing the SOI using a hydrofluoric acid etch prior to etching the portion of the SOI for removal. The method of any one of claims 1 to 3, wherein the template determines the geometric shape of the semiconductor. The method of any one of claims 1 to 4, wherein growing the semiconductor is performed using metalorganic vapor phase epitaxy (MOVPE). The method of any one of claims 1 to 5, wherein the interface between the metal and the semiconductor is formed in situ during the growth of the semiconductor. The method of claim 1 , further comprising: depositing a dielectric on the SOI prior to depositing the metal. forming a silicon-on-insulator (SOI) layer over the wafer;
depositing a metal on the SOI;
forming a template structure comprising a metal element and a silicon element by dry etching to remove the metal and a portion of the SOI , the template structure including a template covering the metal element and the silicon element;
and creating an interface between the metal element and the semiconductor where the portion of the silicon element was removed by growing a semiconductor using the remaining portion of the silicon element as a nucleation seed . The method of claim 8, wherein the silicon element comprises silicon-on-insulator, polycrystalline silicon, or a combination thereof. The method according to claim 8 or 9 , wherein the semiconductor is a III-V semiconductor. The method of claim 8 , wherein the template structure further comprises a dielectric layer overlying the metal elements and the silicon elements. 12. The method of claim 8 , further comprising: dry etching the metal layer and the silicon layer in a single step to self-align the metal elements and the silicon elements. 13. The method of claim 8, wherein an exposed surface of a remaining portion of the silicon element after the portion of the silicon element is removed comprises a (110) crystal orientation. 14. The method of any of claims 8 to 13 , wherein the template structure is formed on a silicon wafer. forming a cavity structure including a first sidewall comprising a first metal element, a second sidewall opposite the first sidewall and comprising a second metal element, and a third sidewall between the first sidewall and the second sidewall and comprising a silicon -on-insulator (SOI) element , wherein forming the cavity structure includes etching a portion of the SOI element for removal;
growing the semiconductor within the cavity structure using the SOI element as a nucleation seed to form interfaces between the first and second metal elements and a semiconductor. The method of claim 15 , wherein the cavity structure overlies a silicon-on-insulator wafer. 17. The method of claim 15 or 16 , wherein the length of the cavity structure corresponds to an etching time used to form the cavity structure. 18. The method of claim 15 , wherein the semiconductor height is determined by the thickness of the SOI element . 19. The method of any of claims 15 to 18 , wherein the semiconductor growth is guided by one or more geometries of the cavity structure.

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