JP7689343B2 - CONTROL DEVICE, QUANTUM COMPUTER, CONTROL METHOD, AND PROGRAM - Google Patents

Description

The present invention relates to quantum error correction in quantum computers.

Quantum computers are expected to use the principles of quantum mechanics to significantly speed up the time required to solve problems such as prime factorization and quantum chemistry calculations compared to conventional computers. For this reason, their development is being actively pursued around the world.

Quantum bits, the basic elements that make up quantum computers, are prone to errors, so to perform quantum computations on a practical scale, a quantum error correction mechanism is required to detect and correct errors that occur during execution. In quantum error correction, information is represented as logical quantum bits using multiple quantum bits using quantum error correcting codes, and calculations are performed while detecting and correcting errors.

Fu, Xiang, et al. "A heterogeneous quantum computer architecture." Proceedings of the ACM International Conference on Computing Frontiers. 2016.

The mechanism of quantum error correction is based on the premise that errors occur independently in each quantum bit. However, in recent years, it has been experimentally observed that when cosmic rays are incident on a chip on which quantum bits are integrated, the error rate of quantum bits over a wide range increases significantly for a long period of time. Errors with this nature are called burst errors.

Although the frequency with which cosmic rays strike a chip is low, they are almost certain to occur during long-term calculations, so error correction using surface codes, for example, may not function as expected. Note that burst errors like those described above can also occur due to external factors other than cosmic rays.

The present invention has been made in consideration of the above points, and aims to provide a technique for reducing the effects of burst errors in quantum computers.

According to the disclosed technology, there is provided a control device that controls a quantum processor having a plurality of quantum bits that constitute a quantum error correcting code, the control device comprising:
an anomaly detection unit that detects an area where an anomaly has occurred in a quantum bit in the quantum processor based on a syndrome value periodically acquired from the quantum processor; and
A control device is provided that includes at least one of a code extension unit that modifies a quantum error correcting code to increase the code distance of a logical quantum bit in the region when an abnormality is detected by the anomaly detection unit, and a re-execution unit that, when an abnormality is detected by the anomaly detection unit, goes back in time and re-executes an estimate of an error in the quantum bit using information from the region.

The disclosed technology provides a technique for reducing the effects of burst errors in a quantum computer.

1 is a configuration diagram of a quantum computer according to an embodiment of the present invention. FIG. 1 is a diagram for explaining a quantum error correction process. FIG. 1 is a diagram for explaining a burst error caused by cosmic rays. FIG. 2 is a detailed configuration diagram of a quantum computer according to an embodiment of the present invention. FIG. 11 is a schematic diagram for explaining a processing procedure. FIG. 2 is a diagram showing a schematic diagram of coordinates on a three-dimensional grid that are targets for matching; FIG. 2 is a diagram illustrating an example of a hardware configuration of a control device.

The following describes an embodiment of the present invention (the present embodiment) with reference to the drawings. The embodiment described below is merely an example, and the embodiment to which the present invention is applied is not limited to the following embodiment. In the following description, references are represented by numbers, such as [2], and the names of the documents corresponding to the numbers are listed at the end of the specification.

(Overall equipment configuration)
1 shows an example of the overall configuration of a quantum computer 300 according to the present embodiment. The "quantum computer" may also be called a "quantum computer" or a "quantum computing device." This quantum computer 300 makes it possible to perform quantum computation while mitigating the effects of burst errors caused by cosmic rays or the like.

As shown in FIG. 1, the quantum computer 300 includes a control device 100 and a quantum processor 200. The control device 100 performs error-tolerant quantum computation by transmitting a control signal to the quantum processor 200 and acquiring a computation result (measurement result) from the quantum processor 200. The control device 100 can be realized by a classical computer.

The quantum processor 200 has multiple quantum bits that constitute a quantum two-level system. There are no particular limitations on the physical system for realizing the quantum bits, and any physical system may be used. For example, superconducting circuits, ion traps, photons, quantum dots, etc. may be used as physical systems.

In this embodiment, a surface code, which is a type of topological code, is formed by a plurality of quantum bits in the quantum processor 200. Therefore, the plurality of quantum bits in the quantum processor 200 are arranged in a lattice pattern on a two-dimensional plane, which will hereinafter be referred to as a qubit plane. However, using a surface code as a quantum error correcting code is just one example, and a quantum error correcting code other than a surface code may also be used.

Figure 1 shows the main functional parts of the control device 100, namely, an anomaly detection part 301, a code extension part 302, and a re-execution part 303. The anomaly detection part 301 detects an area where an anomaly has occurred in the quantum bit in the quantum processor based on a syndrome value periodically acquired from the quantum processor 200. When an anomaly is detected by the anomaly detection part 301, the code extension part 302 modifies the quantum error correction code so as to increase the code distance of the logical quantum bit in the area. When an anomaly detection part 301 detects an anomaly, the re-execution part 302 goes back in time and re-executes the estimation of the quantum bit error using information on the area. More specific functional configurations of the anomaly detection part 301, the code extension part 302, and the re-execution part 303 will be described later.

(Basic quantum error correction processing)
Here, we will explain the basic quantum error correction process. As mentioned above, quantum bits, which are the basic elements that make up a quantum computer, are prone to errors, and a quantum error correction mechanism that detects and corrects errors that occur during execution is required to perform quantum calculations on a practical scale. In quantum error correction, information is expressed as a logical quantum bit using multiple quantum bits using a quantum error correction code, and calculations are performed while detecting and correcting errors.

A typical flow of quantum error correction will be described with reference to Figure 2. A in Figure 2 shows a qubit plane, which is a chip on which qubits are integrated. As shown in Figure 1, the qubits integrated in the qubit plane are divided into square blocks. Each block constitutes one logical qubit.

As shown in Figure 2B, each block is composed of quantum bits arranged in a grid. A code realized by arranging data quantum bits (black circles) for storing data in each block and ancillary quantum bits for detecting errors that occur in the data quantum bits is called a surface code [2], and is said to be the closest to being realized.

In Figure 2B, the shaded boxes (diamonds) represent ancillary qubits. Also shown in Figure 2B are unused data qubits (open circles) and unused ancillary qubits, which can be used for code extension. Figure 1B also shows the case where the code distance is d.

In surface codes, periodic parity checks can be performed using auxiliary error-detecting quantum bits, allowing indirect information about errors occurring in the quantum bits to be obtained.

When error detection is performed using an auxiliary quantum bit with a surface code, information regarding the parity of one bit of error is obtained for each auxiliary quantum bit, and arranging these gives a two-dimensional bit map that indicates whether the number of errors that have occurred in the data quantum bits surrounding the auxiliary quantum bit is even or odd. The value obtained here is called the syndrome value. The value that indicates whether the number of errors is even or odd can also be called the parity. A bit with a syndrome value of 1 (odd) is called an active bit.

Syndrome value measurements (stabilizer measurements) are repeated over a certain cycle. This cycle is called the code cycle. The syndrome values of one code cycle are considered as one layer, and by stacking the syndrome values of each code cycle, three-dimensional lattice data is obtained, as shown in Figure 2D. This data corresponds to the data in the syndrome buffer, which will be described later. Each node in Figure 2D corresponds to one syndrome value.

Here, the shaded ancillary quantum bit shown in E gives the even/odd error for bit flipping, and the shaded ancillary quantum bit shown in F gives the even/odd error for phase flipping. The subsequent processing is common to both and the same processing is performed in parallel, so we will only describe the information obtained from the shaded ancillary quantum bit shown in F.

To correct the errors that occur, the errors must be estimated from the syndrome values. This task is called decoding. When the errors that occur in each quantum bit are independent, it is known that decoding the surface code can be reduced to the following task:

As mentioned above, the bitmap of syndrome values arranged in time series becomes a three-dimensional grid (or graph) as shown in Figure 2D. Consider pairing the points (black dots) in this grid where the syndrome values are odd (active), or pairing black dots with grid boundaries. It is known that the edges that form the path when pairing have a one-to-one correspondence with the error that occurred. From this, the task of estimating the most likely error corresponds to pairing with the shortest edge length, and this problem coincides with the problem called minimum weight perfect matching. In other words, here, when pairing points (black dots) where the syndrome values are odd (active), or pairing black dots with grid boundaries, pairing is performed so that the total length (weight) of the paired path is minimized.

Various methods have been proposed to solve minimum weight perfect matching quickly while correcting errors [3]. During the calculation, the incoming syndrome values are sequentially decoded by the control device, and the errors are estimated with a delay equal to the time it takes to decode them. The estimated errors are written into a table called the Pauli frame. When the logical quantum bit is measured, the feedback of the estimated errors is used to correct the measurement result. The above mechanism makes it possible to realize quantum error correction.

As mentioned above, when cosmic rays hit a chip on which quantum bits are integrated, a burst error occurs in which the error rate of quantum bits over a wide area increases significantly for a long period of time. Although the frequency with which cosmic rays hit a chip is not high, they are almost certain to occur during calculations carried out over a long period of time, which raised concerns that error correction using surface codes would not function with the expected performance.

Figure 3 is a schematic diagram showing the effects of cosmic rays. In the right-hand diagram of Figure 3, the area where the error rate increases during a certain period at a certain position on a two-dimensional plane is shown shaded as an anomalous region.

In this embodiment, we will explain a technology that significantly reduces the impact of burst errors compared to conventional technology, without significantly affecting the performance of a quantum computer, by modifying the quantum error correction mechanism in the architecture of conventional quantum computers.

(Details of device configuration)
Fig. 4 shows a detailed configuration diagram of a quantum computer 300 according to this embodiment. The configuration shown in Fig. 4 is a typical computer architecture that realizes a fault-tolerant quantum computer, to which the proposed technology according to the present invention is incorporated. In particular, the part enclosed in the dotted line frame is an element added in this proposal. However, with the addition of the part enclosed in the dotted line frame, the other elements also perform operations that are not performed by fault-tolerant quantum computers of existing technology.

As shown in FIG. 4, the quantum computer 300 according to this embodiment has a host CPU 110, a quantum-classical interface 120, classical control units 130, and a quantum bit plane 200.

The control device 100 in the configuration shown in FIG. 1 corresponds to the "host CPU 110 + quantum-classical interface 120 + classical control unit 130" in FIG. 4. The "host CPU 110 + quantum-classical interface 120 + classical control unit 130", that is, the control device 100, may be realized by one computer (and program), may be realized by multiple computers (and programs), may be realized by dedicated hardware and a computer (and program), or may be realized only by dedicated hardware.

For example, the internal mechanisms of the classical control unit 130 may be implemented using software (i.e., by having a computer execute a program), or some or all of the internal mechanisms may be implemented using dedicated hardware.

The quantum-classical interface 120 has an AD converter 121 and a DA converter 122.

The classical control unit 130 includes a measurement result extraction unit 131, a classical register 132, a syndrome extraction unit 133, a syndrome buffer 134, a decoding unit 135, a Pauli frame 136, an anomaly detection unit 137, an active node counter 138, a matching buffer 139, an expansion queue 144, an instruction history buffer 145, an instruction buffer 140, a stabilizer map 141, a stabilizer assignment unit 142, and an instruction decoder 143. The instruction decoder 143 also functions as a scheduler, and may be referred to as an instruction decoder/schedule unit 143.

(Overview of Operation of the Quantum Computer 300)
In the error-tolerant quantum computation performed by the quantum computer 300, the quantum bits are integrated in the quantum bit plane 200 and are externally controlled. During the computation, the control device 100 continuously detects whether any errors have occurred in the quantum bits. The time required to perform an "operation to perform error detection once for all quantum bits" is called one code cycle.

Every other code cycle, the control device 100 obtains a syndrome value to determine what type of error has occurred and where in the quantum bit. If no errors occur in the quantum bit, the syndrome value will be all 0, but if an error occurs, the statistics will change according to the probability of that error.

In this embodiment, the control device 100 includes an anomaly detection unit 137. The anomaly detection unit 137 continuously monitors statistical information on syndrome values, and when a certain condition is met for a certain quantum bit (a specific quantum bit), it determines that the quantum bit is in an abnormal state with a larger error than normal. The anomaly detection unit 137 may also be called an anomaly detection unit.

If the anomaly detection unit 137 determines that a particular quantum bit is in an abnormal state, i.e., that a burst error has occurred, the anomaly detection unit 137 adds an instruction to the instruction buffer 140 to restore the reliability of the encoded logical quantum bit that uses the abnormal quantum bit. The anomaly detection unit 137 also notifies the error estimation unit not to trust the abnormal quantum bit when estimating the location of the error.

In the quantum computer 300 of this embodiment, the core mechanism for solving the problem of reducing the effects of burst errors is as follows.

(1) A mechanism that processes syndrome value information and detects abnormalities from statistical changes (function of the anomaly detection unit 137).

(2) A mechanism (such as the expansion buffer 144 and instructions stored therein) that transforms the code so that the logical error rate of the logical quantum bit including the quantum bit in which the burst error occurred falls within an acceptable range.

(3) A mechanism for more reliable estimation of error information using information that a particular quantum bit is in an abnormal state (a new function of the decoding unit 135).

(Description of the operation of each part 1)
The operation of each part of the quantum computer 300 shown in Fig. 4 will be described in detail below. First, in "Description of the Operation of Each Part 1", the mechanism that constitutes a standard fault-tolerant quantum computer will be described. This standard mechanism is a slightly modified design similar to the design in reference [4].

<Host CPU 110>
The host CPU 110 is a processor that performs normal computer processing to communicate with the quantum processor. It sequentially sends instructions to be executed by the quantum processor to the instruction decode unit 143, and receives the results of quantum computation as classical bit data from the classical register 132.

<Instruction Decode Unit 143>
The instruction decode unit 143 decodes an instruction sent from the host CPU 110, queries the stabilizer allocation unit 142 as to whether the instruction is executable, and adds the data to the instruction buffer 140 based on appropriate scheduling. Depending on the instruction, data in the classical register 132 may be used to determine whether the instruction is executable. In addition, the executed instruction is notified to the Pauli frame 136.

<Instruction Buffer 140>
The instruction buffer 140 may be called an instruction queue. The instruction buffer 140 is a data queue (data buffer) that holds an instruction set sent from the instruction decoder 143. An instruction is executed, and when the execution is completed, the instruction is deleted from the queue.

<Stabilizer allocation unit 142>
The qubits arranged in the qubit plane 200 are stabilized in a predetermined manner during the calculation. The stabilizer allocation unit 142 manages how each qubit is stabilized. The operation of the qubits encoded with the error-correcting code based on the instruction stored in the instruction buffer 140 can be indirectly performed by changing the stabilization method. This method is called code deformation [5] or lattice surgery [6] because the instruction is performed by deforming or patching the code arranged in a lattice shape. The stabilizer allocation unit 142 periodically sends a control signal to the qubit plane 200 to stabilize the qubits in a predetermined manner.

<Stabilizer Map 141>
The stabilizer map 141 is a table for holding information indicating how the stabilizer allocation unit 142 is currently stabilizing the quantum bits on the quantum bit plane 200 .

<DA converter 122>
The DA converter 122 is a mechanism that converts the control signal sent from the stabilizer allocation unit 142 from a digital signal to an analog signal and transmits the analog signal to the quantum bit plane 200, thereby enabling control of the quantum bits on the quantum bit plane 200, which is an analog element.

<Quantum Bit Plane 200>
The quantum bit plane 200 is a chip on which an array of integrated quantum bits is arranged. The quantum bit plane 200 is typically assumed to have quantum bits arranged in a two-dimensional lattice. However, the scope of application of the technology according to the present invention is not limited to a specific graph structure such as a two-dimensional lattice.

<AD converter 121>
The AD converter 121 is a unit that reads the reflected wave of the analog control signal sent to the quantum bit plane 200 and converts it into a digital signal. The data to be converted into a digital signal are a signal intended to read the encoded logical quantum bit and an error detection signal that indicates whether an error has occurred in the stabilized quantum bit. The former is sent to the measurement result extraction unit 131, and the latter is sent to the syndrome extraction unit 133.

<Measurement result extraction unit 131>
The measurement result extraction unit 131 processes the signal sent by the AD converter 121 for the purpose of reading out the logical quantum bit, and calculates the measurement result of the logical quantum bit. However, the calculated data has not yet been error-corrected and is unreliable. This calculated unreliable data is sent to the classical register 132, and the data is corrected by the Pauli frame 136.

<Syndrome Extraction Unit 133>
The syndrome extraction unit 133 is a unit that processes the error detection signal received from the AD converter 121 and calculates information called a syndrome value, which is data for estimating what kind of error has occurred. The calculated syndrome value is stored in a syndrome buffer 134 (which may be called a syndrome queue).

<Syndrome Buffer 134>
The syndrome buffer 134 is a unit that holds the syndrome values received from the syndrome extraction unit 133. When a syndrome value becomes unnecessary, the syndrome value is deleted from the buffer (queue).

<Decoding Unit 135>
The decoding unit 135 is a unit that decodes information indicating what kind of error has occurred in the quantum bit from the syndrome value held in the syndrome buffer 134. The decoded information on the position and time of the error is sent to the Pauli frame 136.

<Pauli Frame 136>
The Pauli frame 136 is a unit that compiles information on what errors have accumulated in the quantum bits in the quantum bit plane 200 at a certain point in time, based on information sent from the decode unit 135. The Pauli frame 136 uses this information to correct errors in the “measurement results of logical quantum bits whose errors have not been corrected” stored in the classical register 132 by the measurement result extraction unit 131.

<Classical Register 132>
The classical register 132 is a unit that holds the measurement results of the logical quantum bits (classical bits of 0 and 1). The measurement results of the logical quantum bits with no error correction are first stored by the measurement result extraction unit 131, and then when the information in the Pauli frame 136 is updated, the errors are corrected by the Pauli frame 136. The error-corrected measurement data is sent to the host CPU 110, and is also used by the instruction decoder 135 to schedule instructions.

(Explanation of operation of each part 2)
Next, as an explanation 2 of the operation of each part, we will explain the mechanism that was not present in the architecture of conventional error-correcting quantum computers and that was newly added in the technology of the present invention, as well as the changes in other mechanisms resulting from the incorporation of this mechanism.

<Anomaly detection unit 143>
The anomaly detection unit 143 acquires the oldest code cycle data and the newest code cycle data from the syndrome buffer 139 (which may be called a syndrome queue) each time a syndrome value is added to the syndrome buffer 134. Based on the acquired data, the anomaly detection unit 143 updates the statistical information of the syndrome values stored in the active node counter 138, and checks whether an anomaly has occurred in the quantum bits arranged in the quantum bit plane 200. If no anomaly has occurred, nothing is done. If an anomaly has occurred, the anomaly detection unit 143 notifies the decoding unit 135 and the extension buffer 144 (which may be called an extension queue) of the position information of the quantum bit where the anomaly has occurred.

Active Node Counter 138
The active node counter 138 is a small data table that the anomaly detection unit 143 uses to collect statistical information on past syndrome values.

<Expansion Buffer 144>
The extension buffer 144 is a buffer (queue) that accumulates instructions for storing instructions to deal with an abnormality when an abnormality occurs in a quantum bit. When the extension buffer 144 receives the position of the quantum bit where an abnormality occurs from the anomaly detection unit 137, the extension buffer 144 adds an instruction to increase the encoding level and temporarily make the data more robust so that the information of the encoded logical quantum bit at that position is not damaged. The instruction addition may be performed by the extension buffer 144 itself, or may be performed by the anomaly detection unit 137 to the extension buffer 144.

The extension buffer 144 and the stabilizer allocation unit 142 that executes the instructions stored in the extension buffer 144 may be collectively referred to as the code extension unit.

<Stabilizer allocation unit 142>
In the conventional technology, the stabilizer allocation unit 142 refers to and executes only the instructions in the instruction buffer 140, but in this embodiment, it takes precedence over this and executes the instructions in the extension buffer 144. Note that the anomaly detection unit 137 may store the above-mentioned extension instructions in the instruction buffer 140, and the stabilizer allocation unit 142 may execute the extension instructions with priority.

<Decoding Unit 143>
In the conventional technology, the decoding unit 143 simply receives data from the syndrome buffer 134 and sequentially performs decoding. In contrast, in the present embodiment, when the decoding unit 143 is notified by the anomaly detection unit 137 that a quantum bit is abnormal, the decoding unit 143 inquires of the Pauli frame 136 whether it is possible to rewind (which may also be expressed as rolling back, falling back, going back to the past, etc.) the estimation result that was previously sent.

If rewinding is not possible, no rewinding is performed. If rewinding is possible, the previous estimation is rewinded to just before the code cycle in which the quantum bit becomes abnormal, and the estimation of the error information is rerun. When the estimation of the error information is performed at this time, the type of abnormality of the quantum bit at the notified position is known, such as a high error rate, so that decoding with higher performance than before the rerun can be performed. In addition, in order to rewind the Pauli frame 136 described below, the estimation results are stored in the matching buffer 139 (which may be called a matching queue) as needed.

The function in the decoding unit 143 that re-executes error estimation may be called a re-execution unit.

<Matching Buffer 139>
The matching buffer 139 is a data queue that stores information indicating where and what type of error occurred at each time, as estimated by the decoding unit 135. When rewinding occurs, the maximum rewind time is fixed, so data that is no longer needed after that time has passed is deleted from the buffer.

<Instruction History Buffer 145>
The instruction history buffer 145 is a data queue that temporarily buffers and holds data sent from the instruction decoder 143. The data in the instruction history buffer 145 is used for rewinding the Pauli frame 136, which will be described later.

<Pauli Frame 136>
When the Pauli frame 136 receives an inquiry from the decode unit 135 as to whether or not rewinding is possible, it checks whether or not the previously corrected information is still unused with respect to the classical register 132. If it is unused, it is determined that rewinding is possible, and if it has been used, it is determined that rewinding is not possible.

If rewinding is possible, all error corrections to the classical register 132 after the rewind time are canceled. In addition, the Pauli frame 136 rewinds the contents of the Pauli frame 136 using data from the instruction history buffer 145 and the matching buffer 139.

(Explanation of the core operation for solving the problem)
The above-mentioned core operations (1) to (3) for solving the problem will be described in more detail below. Before that, an overview of the processing procedure will be described with reference to Fig. 5. Fig. 5 is a diagram showing the state of the quantum bit plane 200 and the manner in which syndrome values are repeatedly acquired from the quantum bit plane 200 and stored in the syndrome buffer 134, with the horizontal axis representing time, which progresses to the right.

In S1 (step 1), the quantum bit plane 200 is exposed to cosmic rays, and an abnormal state caused by the cosmic rays continues for the period shown as C _anomaly .

In S2, the anomaly detection unit 137 determines that an anomaly has occurred (the quantum bit has been affected by a burst error) based on the syndrome values stored in the syndrome buffer 134.

In S3, the stabilizer allocation unit 142 uses the instructions stored in the extension buffer 144 to modify the code so that the logical error rate of the logical quantum bit falls within an acceptable range. This modification continues for the period indicated by T.

In S4, the decoding unit 135 falls back on the error information estimate and estimates error information with higher reliability. In other words, the error information calculated from the time of fallback to the time of anomaly detection (more specifically, immediately before the code cycle in which the quantum bit becomes abnormal) is not used, and the error information is calculated again from the time of rewinding, taking into account the area in which the anomaly occurred.

5 indicates that the fallback is performed up to d cycles before the start of the abnormality occurrence.C _latency in FIG. 5 indicates the period from the start of the abnormality occurrence to the detection of the abnormality.

The above points (1) to (3) are explained in more detail below.

(1) A mechanism that processes syndrome value information and detects abnormalities from statistical changes (the operating mechanism of the anomaly detection unit 137).

The following describes one method of determining from the syndrome value at which position and space (time) a burst error is occurring as the operation of the anomaly detection unit 137, but this method is only one example, and the operation of the anomaly detection unit 137 is not limited to the following operation. Any method may be used as long as it can detect from the syndrome value the position and space (position and time) at which a burst error is occurring.

In a typical noise model, the syndrome values become an independent series by taking out the syndrome values every other value in time. Taking out the syndrome values every other value in time means, specifically, taking the syndrome value for each code cycle. Therefore, the frequency at which the syndrome value is 1 (active) over multiple code cycles is tallied, and if this frequency exceeds a certain percentage, it is determined that a burst error has occurred at the position where the frequency exceeds a certain amount.

For example, the time (time length) of a number of code cycles is defined as C _window . Also, assume that the syndrome value obtained in the t-th code cycle is m (m-bit length). The anomaly detection unit 137 compares the number of active bits (bits with a syndrome value of 1) at each bit position in the period from "t-C _window " to t with a threshold value, and obtains a comparison result for each of the m bit positions. If the number of active bits (bits with a syndrome value of 1) is greater than the threshold value, it can be determined that an anomaly has occurred at the position of the quantum bit corresponding to that bit position. By performing such a determination for each code cycle, it is possible to determine the area (position and time) where an anomaly (burst error) has occurred.

The time when the burst error occurred is calculated taking into account the delay from the time when the abnormality was detected to the time when the abnormality was detected. In the example of Fig. 5, it can be estimated that the burst error started to occur at a time before the C _latency from the time of S2.

(2) A mechanism (extension buffer 144 and instructions stored therein) that transforms the code so that the logical error rate of the logical quantum bit, including the quantum bit in which the burst error occurred, falls within an acceptable range.

In the surface code assumed in this embodiment, a framework called code deformation is used to use many quantum bits without changing the encoded information, but it is possible to transform it into a code that is more robust to errors. Therefore, code deformation is applied to the logical quantum bits including the quantum bit in which the burst error occurred, and the code is temporarily updated to a code that is more robust to errors using more quantum bits. After a sufficient amount of time has passed and the quantum bits have recovered to a normal state, the code is restored to the original code using the code deformation method. The schematic diagram in Figure 5 shows that the code is temporarily updated to a code that is more robust to errors using more quantum bits for the period indicated by T.

(3) A mechanism for more reliable estimation of error information using information that a particular quantum bit is in an abnormal state (a new function of the decoding unit 135).

As mentioned above, it is known that the operation of estimating the most likely location and time of an error from the information in the syndrome buffer 134 can be performed approximately using a graph problem called the minimum weight perfect matching problem, in which the coordinates are the location and time at which the syndrome was detected [2].

Therefore, even if a burst error occurs, a similar method can be used by adjusting the graph weights. However, simply changing the weights will lengthen the processing time in the decoding unit 135, significantly affecting the overall speed of the computer. Therefore, in this proposal, we propose the following high-speed method that can be used in the case of localized errors such as burst errors.

An example of the operation of the decoding unit 135 using this technique will be described with reference to FIG. 6. FIG. 6 is a schematic diagram showing coordinates on a three-dimensional grid that are the targets of matching performed by the decoding unit 135. FIG. 6 lists paths that need to be searched when pairing two nodes.

In Figure 6, the black points (black circles) represent the points to be matched. Each black point must be matched to another black point or to the left or right walls of the 3D grid (the shaded areas in Figure 6). As mentioned before, matching is computed as a minimum weight perfect matching problem.

The cost of matching depends on the number of squares (edges) that can be moved up, down, left, right, forward, and backward on the three-dimensional grid. One edge of a square connects two nodes (qubits).

Figure 6 shows matching between a node and a boundary (wall), and matching between two nodes. In Figure 6, the shaded boxes indicate areas where burst errors occur. In these areas, the weighting is reduced when moving one square (one side) on the three-dimensional grid. This means that the area can be passed through at a lower cost when matching.

At this time, the decoding unit 135 sequentially matches each individual black point with the left or right wall or another black point that is closest in distance on the grid. At this time, the decoding unit 135 calculates the distance from the specified black point to the left or right wall or another black point as the Manhattan distance, which can be calculated in constant time if there is no burst error. If there is an area where a burst error has occurred, the weight of the square (edge) movement in that area is made smaller than the weight of the movement outside that area to calculate the distance.

As shown in Figure 6, even if there are areas with locally low weights due to burst errors, if the number of burst errors is at most one or two, the lines connecting the black dots shown in Figure 6 or the lines connecting the black dots with the left and right walls are all possible patterns of paths with the shortest distances, and since the number of such paths is a constant, the decoding unit 135 can quickly indicate where each black dot should be matched by calculating and comparing all distances.

In Figure 6, paths 1, 2, and 5 are candidates for the shortest path that does not pass through the abnormal region, and paths 3, 4, and 6 are candidates for the shortest path that passes through the abnormal region. In this way, all possible paths for the solution are enumerated to find the result with the shortest total distance.

(Example of hardware configuration of control device 100)
The control device 100 can be realized, for example, by causing a computer to execute a program. This computer may be a physical computer or a virtual machine on the cloud.

That is, the control device 100 can be realized by executing a program corresponding to the processing performed by the control device 100 using hardware resources such as a CPU and memory built into the computer. The above program can be recorded on a computer-readable recording medium (such as a portable memory) and stored or distributed. The above program can also be provided via a network such as the Internet or email.

Figure 7 is a diagram showing an example of the hardware configuration of the computer. The computer in Figure 7 has a drive device 1000, an auxiliary storage device 1002, a memory device 1003, a CPU 1004, an interface device 1005, a display device 1006, an input device 1007, an output device 1008, etc., all of which are interconnected by a bus BS.

The program that realizes the processing on the computer is provided by a recording medium 1001, such as a CD-ROM or a memory card. When the recording medium 1001 storing the program is set in the drive device 1000, the program is installed from the recording medium 1001 via the drive device 1000 into the auxiliary storage device 1002. However, the program does not necessarily have to be installed from the recording medium 1001, but may be downloaded from another computer via a network. The auxiliary storage device 1002 stores the installed program as well as necessary files, data, etc.

When an instruction to start a program is received, the memory device 1003 reads out and stores the program from the auxiliary storage device 1002. The CPU 1004 realizes functions related to the control device 100 in accordance with the program stored in the memory device 1003. The interface device 1005 is used as an interface for connecting to a network or a quantum processor, etc. The display device 1006 displays a GUI (Graphical User Interface) or the like according to a program. The input device 1007 is composed of a keyboard and mouse, buttons, a touch panel, etc., and is used to input various operational instructions. The output device 1008 outputs the results of calculations.

(Effects of the embodiment)
As described above, the anomaly detection technique according to the present embodiment can dynamically protect the error correction mechanism that is normally exposed to cosmic rays for a long time. There are two protection procedures: a method of temporarily increasing the code distance of the logical quantum bit affected by the burst error, and a method of re-executing the error estimation taking into account the effect of the burst error. By combining these, it is possible to significantly reduce the error rate of the logical quantum bit that increases due to the effect of the burst error.

When an abnormality is detected, significant effects can be achieved by using both a method of temporarily increasing the code distance of a logical quantum bit affected by a burst error and a method of re-estimating the error taking into account the effects of the burst error. However, it is also possible to use only one of the methods of temporarily increasing the code distance of a logical quantum bit affected by a burst error and re-estimating the error taking into account the effects of the burst error.

(Additional Note)
The following supplementary items are further disclosed regarding the above-described embodiment.
(Additional note 1)
A control device that controls a quantum processor having a plurality of quantum bits that configure a quantum error correcting code,
Memory,
at least one processor coupled to the memory;
Including,
The processor,
detecting a region in which an anomaly has occurred in a quantum bit in the quantum processor based on syndrome values periodically acquired from the quantum processor;
a control device that executes at least one of a process of modifying a quantum error correcting code so as to increase the code distance of a logical quantum bit in the region when the abnormality is detected, and a process of going back in time and re-estimating an error in the quantum bit using information from the region when the abnormality is detected.
(Additional note 2)
The control device according to claim 1, wherein the processor determines that an abnormality has occurred at a position corresponding to a syndrome value when the number of syndrome values having a predetermined value in a certain period of time is greater than a threshold value.
(Additional note 3)
The control device according to claim 1, wherein the processor restores the quantum error correcting code to the code before the transformation after the quantum bit has recovered to a normal state.
(Additional note 4)
The control device described in Appendix 1, wherein the processor, in order to estimate a quantum bit error, makes the weight of the edge in the region smaller than the weight of the edge in a portion other than the region when searching for a match between a node having a predetermined value and another node having a predetermined value as a solution to a minimum weight perfect matching problem in a three-dimensional graph consisting of a plurality of nodes and edges corresponding to syndrome values over a plurality of periods.
(Additional note 5)
5. A quantum computer comprising the control device according to claim 1 and the quantum processor.
(Additional note 6)
A control method performed by a computer used as a control device for controlling a quantum processor having a plurality of quantum bits constituting a quantum error correcting code, comprising:
detecting a region in which an anomaly has occurred in a quantum bit in the quantum processor based on syndrome values periodically acquired from the quantum processor;
a control method for performing at least one of the following processes: when the abnormality is detected, a process of modifying a quantum error correcting code so as to increase the code distance of a logical quantum bit in the region; and when the abnormality is detected, a process of going back in time and re-estimating an error in the quantum bit using information from the region.
(Supplementary Note 7)
A non-transitory storage medium storing a program for causing a computer to function as each unit in the control device according to any one of claims 1 to 4.

Although the present embodiment has been described above, the present invention is not limited to such a specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.
[References]
[2] Fowler, Austin G., et al. "Surface codes: Towards practical large-scale quantum computation." Physical Review A 86.3 (2012): 032324.
[3] Holmes, Adam, et al. "NISQ+: Boosting quantum computing power by approximating quantum error correction." 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2020.
[4] Fu, Xiang, et al. "A heterogeneous quantum computer architecture." Proceedings of the ACM International Conference on Computing Frontiers. 2016.
[5] Bombin, H., & Martin-Delgado, MA (2009). "Quantum measurements and gates by code deformation". Journal of Physics A: Mathematical and Theoretical, 42(9), 095302.
[6] Horsman, C., Fowler, AG, Devitt, S., & Van Meter, R. (2012).
"Surface code quantum computing by lattice surgery". New Journal of Physics, 14(12), 123011.

100 Control device 110 Host CPU
120 Quantum-classical interface 121 AD converter 122 DA converter 130 Classical control unit 131 Measurement result extraction unit 132 Classical register 133 Syndrome extraction unit 134 Syndrome buffer 135 Decode unit 136 Pauli frame 137 Anomaly detection unit 138 Active node counter 139 Matching buffer 140 Instruction buffer 141 Stabilizer map 142 Stabilizer allocation unit 143 Instruction decoding unit 144 Extension buffer 145 Instruction history buffer 200 Quantum processor, quantum bit plane 300 Quantum computer 301 Anomaly detection unit 302 Code extension unit 303 Re-execution unit 1000 Drive device 1001 Recording medium 1002 Auxiliary storage device 1003 Memory device 1004 CPU
1005 Interface device 1006 Display device 1007 Input device 1008 Output device

Claims (7)

A control device that controls a quantum processor having a plurality of quantum bits that configure a quantum error correcting code,
an anomaly detection unit that detects an area where an anomaly has occurred in a quantum bit in the quantum processor based on a syndrome value periodically acquired from the quantum processor; and
a code extension unit that modifies a quantum error correcting code to increase a code distance of a logical quantum bit in the region when an abnormality is detected by the anomaly detection unit, and a re-execution unit that, when an abnormality is detected by the anomaly detection unit, goes back in time and re-executes an estimate of an error in the quantum bit using information of the region. The control device according to claim 1 , wherein the anomaly detection unit determines that an anomaly has occurred at a position corresponding to a syndrome value when the number of syndrome values having a predetermined value in a certain period is greater than a threshold value. The control device according to claim 1 , wherein the code extension unit restores the quantum error correcting code to the code before the transformation after the quantum bit has recovered to a normal state. 2. The control device according to claim 1, wherein the re-execution unit, in order to estimate quantum bit errors, makes the weight of the edge in the region smaller than the weight of the edge in a portion other than the region when searching for a matching between a node having a predetermined value and another node having a predetermined value as a solution to a minimum weight perfect matching problem in a three-dimensional graph consisting of a plurality of nodes and edges corresponding to syndrome values over a plurality of periods. A quantum computer comprising the control device according to any one of claims 1 to 4 and the quantum processor. A control method performed by a control device that controls a quantum processor having a plurality of quantum bits that constitute a quantum error correcting code, comprising:
detecting a region in which an anomaly has occurred in a quantum bit in the quantum processor based on syndrome values periodically acquired from the quantum processor;
a control method for performing at least one of the following processes: when the abnormality is detected, a process of modifying a quantum error correcting code so as to increase the code distance of a logical quantum bit in the region; and when the abnormality is detected, a process of going back in time and re-estimating an error in the quantum bit using information from the region. A program for causing a computer to function as each part of a control device according to any one of claims 1 to 4.

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