JP7695538B2 - Board and mounting board - Google Patents

Description

The present invention relates to a substrate and a mounting substrate.

For example, Japanese Patent Application Laid-Open No. 2016-18846 (Patent Document 1) describes a semiconductor package. The semiconductor package described in Patent Document 1 is a QFN (Quad Flat Non-leaded) package. A central electrode and multiple peripheral electrodes are exposed from the back surface of the semiconductor package in Patent Document 1. The central electrode is located in the center of the back surface. The peripheral electrodes are located around the central electrode.

JP 2016-18846 A

The semiconductor package described in Patent Document 1 is mounted on a substrate. The substrate has, for example, a base material, a conductor pattern, and a solder resist. The conductor pattern is disposed on the main surface of the base material and has a central pad, multiple peripheral pads, and wiring. The peripheral pads are located around the central pad. The wiring connects the outer periphery of the central pad to the peripheral pads. The solder resist is disposed on the main surface of the substrate so as to cover the conductor pattern. The solder resist has a first opening that exposes the central pad and multiple second openings that expose the peripheral pads.

The semiconductor package described in Patent Document 1 is mounted on a substrate by bonding the central electrode to the central pad with a solder alloy and bonding the peripheral electrodes to the peripheral pads with a solder alloy.

The first opening may be located outside the outer periphery of the central pad in a plan view. In other words, the connection between the wiring and the outer periphery of the central pad is exposed from the first opening. As a result, when the solder alloy is melted to join the central electrode and the central pad, some of the molten solder alloy may become a solder ball at the connection between the wiring and the outer periphery of the central pad. The solder ball may cause a short circuit between adjacent peripheral pads.

The present invention has been made in consideration of the problems of the conventional technology as described above. More specifically, the present invention provides a substrate and a mounting substrate that can suppress the occurrence of solder balls at the connection between the wiring and the central pad.

The substrate of the present invention comprises a base material having a main surface, a conductor pattern disposed on the main surface and having a central pad portion, peripheral pad portions surrounding the central pad portion, and wiring connecting the outer periphery of the central pad portion to the peripheral pad portion, and a solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening exposing the central pad portion and a second opening exposing the peripheral pad portion. The solder resist covers the connection portion of the wiring with the central pad portion.

In the above substrate, the first opening may be located inside the outer periphery of the central pad portion in a plan view.

The above-mentioned substrate may further include an annular wall disposed on the solder resist. The annular wall may be disposed outside the first opening and inside the peripheral pad portion in a plan view. The annular wall may be formed of a resin material different from the solder resist. In the above-mentioned substrate, the annular wall may be formed of a resin ink that is colored a different color from the solder resist. In the above-mentioned substrate, the thickness of the conductor pattern may be greater than the thickness of the solder resist.

The mounting board of the present invention comprises a substrate, a semiconductor package having a back surface, and a solder alloy. The substrate is the substrate described above. The semiconductor package has, on the back surface, a central electrode facing the central pad portion, and a peripheral electrode surrounding the central electrode and facing the peripheral pad portion. The solder alloy bonds the central electrode to the central pad portion, and also bonds the peripheral electrode to the peripheral pad portion. In the mounting board described above, the semiconductor package may be a QFN package.

The substrate and mounting board of the present invention can suppress the occurrence of solder balls at the connection between the wiring and the central pad.

FIG. 2 is a plan view of the substrate 100. 2 is a cross-sectional view taken along line II-II in FIG. 2 is a cross-sectional view of a mounting substrate 200. FIG. FIG. 2 is a bottom view of the semiconductor package 300. FIG. 2 is a plan view of the substrate 100A. FIG. 1 is a plan view of a substrate 100B. 7 is a cross-sectional view taken along line VII-VII in FIG. 6. FIG. 1 is a plan view of a substrate 100C.

Details of the embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts will be given the same reference symbols, and redundant explanations will not be repeated.

First Embodiment
A substrate according to a first embodiment will be described. In the following, the substrate according to the first embodiment will be referred to as a substrate 100.

<Configuration of Substrate 100>
The structure of the substrate 100 will be described below.

Figure 1 is a plan view of the substrate 100. Figure 2 is a cross-sectional view taken along line II-II in Figure 1. As shown in Figures 1 and 2, the substrate 100 has a base material 10, a conductor pattern 20, and a solder resist 30.

The substrate 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are end surfaces in the thickness direction of the substrate 10. The second main surface 10b is the opposite surface to the first main surface 10a. The substrate 10 is made of an electrically insulating material. The substrate 10 is made of, for example, glass epoxy. However, the electrically insulating material used for the substrate 10 is not limited to this.

The conductor pattern 20 is disposed on the first main surface 10a. The conductor pattern 20 is formed of an electrically conductive material. The conductor pattern 20 is formed of, for example, copper. However, the electrically conductive material used for the conductor pattern 20 is not limited to this.

The conductor pattern 20 has a central pad 21 and a plurality of peripheral pads 22. The central pad 21 is, for example, rectangular in plan view. More specifically, the central pad 21 is square in plan view. The peripheral pads 22 are arranged around the central pad 21. The peripheral pads 22 are, for example, rectangular in plan view. More specifically, the peripheral pads 22 are rectangular in plan view. The peripheral pads 22 are arranged at a distance from the outer periphery (outer periphery 21a) of the central pad 21. The short side of the peripheral pad 22 in plan view faces the outer periphery 21a with a gap therebetween. The plurality of peripheral pads 22 facing one side of the outer periphery 21a are lined up in a row along the direction of that one side.

Some of the multiple peripheral pads 22 (referred to as peripheral pads 22a) are connected to the outer periphery 21a by wiring 23.

A through hole 10c is formed in the substrate 10. The through hole 10c penetrates the substrate 10 in the thickness direction. The through hole 10c is formed at a position overlapping the central pad 21 in a plan view. A conductor layer 24 is disposed on the inner wall surface of the through hole 10c. The conductor layer 24 is connected to the central pad 21. The conductor layer 24 is also disposed on the second main surface 10b around the through hole 10c. The conductor layer 24 is formed of an electrically conductive material (e.g., copper).

The solder resist 30 is disposed on the first main surface 10a so as to cover the conductor pattern 20. The solder resist 30 is also disposed on the second main surface 10b. The solder resist 30 covers the conductor pattern (not shown) disposed on the second main surface 10b. The solder resist 30 is formed of an electrically insulating material. The solder resist 30 is formed of, for example, an epoxy resin. However, the electrically insulating material used for the solder resist 30 is not limited to this. The solder resist 30 may be colored.

The solder resist 30 has a first opening 31 and a number of second openings 32. The first opening 31 and the second opening 32 penetrate the solder resist 30 in the thickness direction. The central pad 21 is exposed from the first opening 31. The peripheral pads 22 are exposed from the second openings 32.

The first opening 31 is rectangular in plan view. More specifically, the first opening 31 is square in plan view. The first opening 31 is located inside the outer periphery 21a in plan view. From another perspective, the outer periphery of the central pad 21 and the connection between the outer periphery 21a and the wiring 23 are covered with the solder resist 30.

The second opening 32 is rectangular in plan view. More specifically, the second opening 32 is rectangular in plan view.

The thickness of the conductor pattern 20 is thickness T1. The thickness of the solder resist 30 is thickness T2. It is preferable that thickness T1 is greater than thickness T2.

<Configuration of mounting substrate 200>
The configuration of the mounting board 200 will be described below.

Figure 3 is a cross-sectional view of the mounting board 200. As shown in Figure 3, the mounting board 200 has a substrate 100 and a semiconductor package 300.

The semiconductor package 300 is, for example, a QFN package. However, the semiconductor package 300 is not limited to this. The semiconductor package 300 may be, for example, an LGA (Lead Grid Array) package. The semiconductor package 300 has a lead frame 310, a semiconductor chip 320, bonding wires 330, and a sealing resin 340.

The lead frame 310 has a die pad portion 311 and a plurality of lead portions 312. The plurality of lead portions 312 are arranged around the die pad portion 311. The lead frame 310 is formed of an electrically conductive material. The lead frame 310 is formed of, for example, a copper alloy. However, the electrically conductive material used for the lead frame 310 is not limited to this.

The semiconductor chip 320 has a surface 320a and a back surface 320b. The surface 320a and the back surface 320b are end faces in the thickness direction of the semiconductor chip 320. The back surface 320b is the opposite surface to the surface 320a. The semiconductor chip 320 is disposed on the die pad portion 311. More specifically, the back surface 320b is connected to the die pad portion 311 by a solder alloy (not shown), a conductive adhesive (not shown), or the like. Although not shown, a bonding pad is formed on the surface 320a.

The bonding wire 330 is connected at one end to a bonding pad of the semiconductor chip 320, and at the other end to the lead portion 312. The bonding wire 330 is made of an electrically conductive material such as gold or copper. The sealing resin 340 seals the lead frame 310, the semiconductor chip 320, and the bonding wire 330. The sealing resin 340 is made of, for example, an epoxy resin. However, the resin material used for the sealing resin 340 is not limited to this.

The semiconductor package 300 has a front surface 300a and a back surface 300b. The front surface 300a and the back surface 300b are end surfaces in the thickness direction of the semiconductor package 300. FIG. 4 is a bottom view of the semiconductor package 300. As shown in FIG. 4, the die pad portion 311 and the lead portion 312 are exposed from the sealing resin 340 on the back surface 300b. The die pad portion 311 and the lead portion 312 exposed from the sealing resin 340 on the back surface 300b respectively become the central electrode 300c and the peripheral electrode 300d of the semiconductor package 300. The peripheral electrode 300d is arranged around the central electrode 300c.

As shown in FIG. 3, the semiconductor package 300 is mounted on the substrate 100. More specifically, the solder alloy 210 joins the central pad 21 to the central electrode 300c and also joins the peripheral pad 22 to the peripheral electrode 300d. The solder alloy 210 is made of, for example, a tin alloy.

When mounting the semiconductor package 300 on the substrate 100, first, cream solder is applied onto the central pad 21 and the peripheral pads 22. Cream solder is a paste in which an organic solvent, flux, and particles of solder alloy 210 are mixed. The cream solder is applied, for example, near the four corners of the central pad 21 exposed from the first opening 31 in a plan view.

Secondly, the semiconductor package 300 is mounted on the substrate 100. At this time, the central pad 21 faces the central electrode 300c with the cream solder interposed therebetween, and the peripheral pad 22 faces the peripheral electrode 300d with the cream solder interposed therebetween. By mounting the semiconductor package 300 on the substrate 100, the cream solder applied on the central pad 21 is spread out.

Thirdly, the substrate 100 on which the semiconductor package 300 is mounted is placed in a reflow furnace. This causes the solder alloy 210 to melt and spread between the central pad 21 and the central electrode 300c and between the peripheral pad 22 and the peripheral electrode 300d, forming a bond between the central pad 21 and the central electrode 300c and a bond between the peripheral pad 22 and the peripheral electrode 300d. As a result, the semiconductor package 300 is mounted on the substrate 100, forming the mounting substrate 200.

The gas generated when the flux and organic solvent evaporate from the solder paste is discharged through the through hole 10c. In other words, the through hole 10c is a gas vent hole during reflow.

<Effects of the Substrate 100>
The effects of the substrate 100 will be described below in comparison with a substrate according to a comparative example. The substrate according to the comparative example is referred to as substrate 100A.

Figure 5 is a plan view of the substrate 100A. As shown in Figure 5, the substrate 100A has a base material 10 (not shown in Figure 5), a conductor pattern 20, and a solder resist 30. In the substrate 100A, the conductor pattern 20 has a central pad 21, a plurality of peripheral pads 22, and wiring 23. In these respects, the configuration of the substrate 100A is common to the configuration of the substrate 100.

In the substrate 100A, the first opening 31 is located outside the outer peripheral edge 21a in a plan view. As a result, the connection between the outer peripheral edge 21a and the wiring 23 is exposed from the first opening 31. In other words, the connection between the outer peripheral edge 21a and the wiring 23 is not covered by the solder resist 30. In these respects, the configuration of the substrate 100A differs from the configuration of the substrate 100.

When the semiconductor package 300 is mounted on the substrate 100A, the cream solder applied on the central pad 21 is spread and spreads over the connection between the outer periphery 21a and the wiring 23. In the substrate 100A, the heat of the molten solder alloy 210 on the connection between the outer periphery 21a and the wiring 23 is also dissipated from the peripheral pad 22 via the wiring 23. Therefore, the molten solder alloy 210 on the connection between the outer periphery 21a and the wiring 23 is more likely to solidify than the molten solder alloy 210 on the central pad 21. As a result, the solidified solder alloy 210 on the connection between the outer periphery 21a and the wiring 23 is separated from the unsolidified solder alloy 210 on the central pad 21, and becomes a solder ball.

On the other hand, in the substrate 100, the connection between the outer peripheral edge 21a and the wiring 23 is covered with solder resist 30, so unlike the substrate 100A, solder balls are less likely to occur.

In addition, when the semiconductor package 300 is mounted on the substrate 100A, the cream solder applied to the central pad 21 spreads onto the solder resist 30 around the first opening 31. The molten solder alloy 210 on the solder resist 30 tends to flow toward the central pad 21 because the interfacial energy at the interface with the solder resist 30 is greater than the interfacial energy at the interface with the central pad 21.

However, when thickness T1 is greater than thickness T2, there is a step between the solder resist 30 around the first opening 31 and the central pad 21, in which the solder resist 30 side is lower, and the molten solder alloy 210 on the solder resist 30 around the first opening 31 cannot overcome the step and may become a solder ball.

On the other hand, in the substrate 100, the solder resist 30 and the central pad 21 overlap around the first opening 31. As a result, there is a step between the solder resist 30 around the first opening 31 and the central pad 21 exposed from the first opening 31, where the solder resist 30 side is higher. Therefore, in the substrate 100, the molten solder alloy 210 on the solder resist 30 around the first opening 31 can easily flow toward the central pad 21 side exposed from the first opening 31, making it difficult for solder balls to occur.

Second Embodiment
A substrate according to the second embodiment will be described. In the following, the substrate according to the second embodiment will be referred to as substrate 100B. Here, differences from substrate 100 will be mainly described, and overlapping descriptions will not be repeated.

<Configuration of substrate 100B>
The configuration of the substrate 100B will be described below.

Figure 6 is a plan view of the substrate 100B. Figure 7 is a cross-sectional view taken along line VII-VII in Figure 6. As shown in Figures 6 and 7, the substrate 100B has a base material 10, a conductor pattern 20, and a solder resist 30. In this respect, the configuration of the substrate 100B is common to that of the substrate 100. The substrate 100B further has an annular wall 40. In this respect, the configuration of the substrate 100B is different from that of the substrate 100.

The annular wall 40 is annular in plan view. More specifically, the annular wall 40 is rectangular annular in plan view. The annular wall 40 is disposed outside the first opening 31 and inside the peripheral pad 22 in plan view. The annular wall 40 is disposed on the solder resist 30.

The annular wall 40 is formed from a resin material different from that of the solder resist 30. The annular wall 40 is formed from, for example, a resin ink. The resin ink is, for example, silk ink. This resin ink is preferably colored a different color from that of the solder resist 30. For example, when the solder resist 30 is colored green, the annular wall 40 is formed from a resin ink that is colored white.

Although not shown, letters are written on the solder resist 30 with the same resin ink as that used for the annular wall 40. These letters indicate, for example, information required when mounting components on the board 100B and information regarding handling of the board 100B.

<Effects of the substrate 100B>
The effects of the substrate 100B will be described below.

In the substrate 100B, the annular wall 40 is disposed outside the first opening 31 and inside the peripheral pads 22. Therefore, even if a solder ball occurs, the solder ball is prevented from moving between two adjacent peripheral pads 22 and causing a short circuit between these two peripheral pads 22.

In addition, in the manufacturing process of the substrate 100B, characters for displaying various information are written on the solder resist 30 using a resin ink that is colored a different color than the solder resist 30. In the substrate 100B, the annular wall 40 is formed using the same resin ink as that used to write the characters, so that the annular wall 40 can be formed within this process, and there is no need to add a new process to form the annular wall 40.

Third Embodiment
A substrate according to a third embodiment will be described. In the following, the substrate according to the third embodiment will be referred to as substrate 100C. Here, differences from substrate 100B will be mainly described, and overlapping descriptions will not be repeated.

<Configuration of Substrate 100C>
The configuration of the substrate 100C will be described below.

Figure 8 is a plan view of substrate 100C. As shown in Figure 8, substrate 100C has a base material 10 (not shown in Figure 8), a conductor pattern 20, a solder resist 30, and an annular wall 40. In this respect, the configuration of substrate 100C is the same as that of substrate 100B. In substrate 100C, first opening 31 is located outside outer periphery 21a in plan view. That is, in substrate 100C, the connection portion between outer periphery 21a and wiring 23 is not covered by solder resist 30. In this respect, the configuration of substrate 100C is different from that of substrate 100B.

<Effects of the substrate 100C>
In the substrate 100C, the connection between the outer peripheral edge 21a and the wiring 23 is not covered with the solder resist 30, and therefore solder balls may occur on the connection between the outer peripheral edge 21a and the wiring 23. However, in the substrate 100C, the annular wall 40 is disposed outside the first opening 31 and inside the peripheral pad 22, and therefore the generated solder balls are prevented from moving between two adjacent peripheral pads 22 and causing a short circuit between these two peripheral pads 22.

Although the embodiment of the present invention has been described above, the above-mentioned embodiment can be modified in various ways. Furthermore, the scope of the present invention is not limited to the above-mentioned embodiment. The scope of the present invention is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

10 Base material, 10a First main surface, 10b Second main surface, 10c Through hole, 20 Conductor pattern, 21 Central pad, 21a Outer periphery, 22, 22a Peripheral pad, 23 Wiring, 24 Conductor layer, 30 Solder resist, 31 First opening, 32 Second opening, 40 Annular wall, 100, 100A, 100B, 100C Substrate, 200 Mounting substrate, 210 Solder alloy, 300 Semiconductor package, 300a Surface, 300b Back surface, 300c Central electrode, 300d Peripheral electrode, 310 Lead frame, 311 Die pad portion, 312 Lead portion, 320 Semiconductor chip, 320a Surface, 320b Back surface, 330 Bonding wire, 340 Sealing resin, T1, T2 Thickness.

Claims (7)

A substrate having a main surface;
a conductor pattern disposed on the main surface and including a central pad portion, peripheral pad portions around the central pad portion, and wiring connecting an outer periphery of the central pad portion to the peripheral pad portion;
a solder resist disposed on the main surface so as to cover the conductor pattern, the solder resist having a first opening exposing the central pad portion and a second opening exposing the peripheral pad portion;
The solder resist covers a connection portion of the wiring with the central pad portion. The substrate according to claim 1, wherein the first opening is located inside the outer periphery of the central pad portion in a plan view. a circular wall disposed on the solder resist;
the annular wall is disposed on the outer side of the first opening and on the inner side of the peripheral pad portion in a plan view,
The substrate according to claim 1 , wherein the annular wall is formed of a resin material different from that of the solder resist. The substrate according to claim 3, wherein the annular wall is formed from a resin ink that is colored a different color than the solder resist. The substrate according to any one of claims 1 to 4, wherein the thickness of the conductor pattern is greater than the thickness of the solder resist. The substrate according to any one of claims 1 to 5,
a semiconductor package having a back surface;
a solder alloy;
the semiconductor package has, on the back surface, a central electrode facing the central pad portion, and a peripheral electrode surrounding the central electrode and facing the peripheral pad portion;
The solder alloy joins the central electrode and the central pad portion, and also joins the peripheral electrode and the peripheral pad portion. The mounting board according to claim 6 , wherein the semiconductor package is a QFN package.

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